1 /** 2 * \file 3 * 4 * \brief Instance description for XDMAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_XDMAC_INSTANCE_H_ 32 #define _SAMV71_XDMAC_INSTANCE_H_ 33 34 /* ========== Register definition for XDMAC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_XDMAC_CIE0 (0x40078050) /**< (XDMAC) Channel Interrupt Enable Register 0 */ 38 #define REG_XDMAC_CID0 (0x40078054) /**< (XDMAC) Channel Interrupt Disable Register 0 */ 39 #define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register 0 */ 40 #define REG_XDMAC_CIS0 (0x4007805C) /**< (XDMAC) Channel Interrupt Status Register 0 */ 41 #define REG_XDMAC_CSA0 (0x40078060) /**< (XDMAC) Channel Source Address Register 0 */ 42 #define REG_XDMAC_CDA0 (0x40078064) /**< (XDMAC) Channel Destination Address Register 0 */ 43 #define REG_XDMAC_CNDA0 (0x40078068) /**< (XDMAC) Channel Next Descriptor Address Register 0 */ 44 #define REG_XDMAC_CNDC0 (0x4007806C) /**< (XDMAC) Channel Next Descriptor Control Register 0 */ 45 #define REG_XDMAC_CUBC0 (0x40078070) /**< (XDMAC) Channel Microblock Control Register 0 */ 46 #define REG_XDMAC_CBC0 (0x40078074) /**< (XDMAC) Channel Block Control Register 0 */ 47 #define REG_XDMAC_CC0 (0x40078078) /**< (XDMAC) Channel Configuration Register 0 */ 48 #define REG_XDMAC_CDS_MSP0 (0x4007807C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */ 49 #define REG_XDMAC_CSUS0 (0x40078080) /**< (XDMAC) Channel Source Microblock Stride 0 */ 50 #define REG_XDMAC_CDUS0 (0x40078084) /**< (XDMAC) Channel Destination Microblock Stride 0 */ 51 #define REG_XDMAC_CIE1 (0x40078090) /**< (XDMAC) Channel Interrupt Enable Register 1 */ 52 #define REG_XDMAC_CID1 (0x40078094) /**< (XDMAC) Channel Interrupt Disable Register 1 */ 53 #define REG_XDMAC_CIM1 (0x40078098) /**< (XDMAC) Channel Interrupt Mask Register 1 */ 54 #define REG_XDMAC_CIS1 (0x4007809C) /**< (XDMAC) Channel Interrupt Status Register 1 */ 55 #define REG_XDMAC_CSA1 (0x400780A0) /**< (XDMAC) Channel Source Address Register 1 */ 56 #define REG_XDMAC_CDA1 (0x400780A4) /**< (XDMAC) Channel Destination Address Register 1 */ 57 #define REG_XDMAC_CNDA1 (0x400780A8) /**< (XDMAC) Channel Next Descriptor Address Register 1 */ 58 #define REG_XDMAC_CNDC1 (0x400780AC) /**< (XDMAC) Channel Next Descriptor Control Register 1 */ 59 #define REG_XDMAC_CUBC1 (0x400780B0) /**< (XDMAC) Channel Microblock Control Register 1 */ 60 #define REG_XDMAC_CBC1 (0x400780B4) /**< (XDMAC) Channel Block Control Register 1 */ 61 #define REG_XDMAC_CC1 (0x400780B8) /**< (XDMAC) Channel Configuration Register 1 */ 62 #define REG_XDMAC_CDS_MSP1 (0x400780BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */ 63 #define REG_XDMAC_CSUS1 (0x400780C0) /**< (XDMAC) Channel Source Microblock Stride 1 */ 64 #define REG_XDMAC_CDUS1 (0x400780C4) /**< (XDMAC) Channel Destination Microblock Stride 1 */ 65 #define REG_XDMAC_CIE2 (0x400780D0) /**< (XDMAC) Channel Interrupt Enable Register 2 */ 66 #define REG_XDMAC_CID2 (0x400780D4) /**< (XDMAC) Channel Interrupt Disable Register 2 */ 67 #define REG_XDMAC_CIM2 (0x400780D8) /**< (XDMAC) Channel Interrupt Mask Register 2 */ 68 #define REG_XDMAC_CIS2 (0x400780DC) /**< (XDMAC) Channel Interrupt Status Register 2 */ 69 #define REG_XDMAC_CSA2 (0x400780E0) /**< (XDMAC) Channel Source Address Register 2 */ 70 #define REG_XDMAC_CDA2 (0x400780E4) /**< (XDMAC) Channel Destination Address Register 2 */ 71 #define REG_XDMAC_CNDA2 (0x400780E8) /**< (XDMAC) Channel Next Descriptor Address Register 2 */ 72 #define REG_XDMAC_CNDC2 (0x400780EC) /**< (XDMAC) Channel Next Descriptor Control Register 2 */ 73 #define REG_XDMAC_CUBC2 (0x400780F0) /**< (XDMAC) Channel Microblock Control Register 2 */ 74 #define REG_XDMAC_CBC2 (0x400780F4) /**< (XDMAC) Channel Block Control Register 2 */ 75 #define REG_XDMAC_CC2 (0x400780F8) /**< (XDMAC) Channel Configuration Register 2 */ 76 #define REG_XDMAC_CDS_MSP2 (0x400780FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */ 77 #define REG_XDMAC_CSUS2 (0x40078100) /**< (XDMAC) Channel Source Microblock Stride 2 */ 78 #define REG_XDMAC_CDUS2 (0x40078104) /**< (XDMAC) Channel Destination Microblock Stride 2 */ 79 #define REG_XDMAC_CIE3 (0x40078110) /**< (XDMAC) Channel Interrupt Enable Register 3 */ 80 #define REG_XDMAC_CID3 (0x40078114) /**< (XDMAC) Channel Interrupt Disable Register 3 */ 81 #define REG_XDMAC_CIM3 (0x40078118) /**< (XDMAC) Channel Interrupt Mask Register 3 */ 82 #define REG_XDMAC_CIS3 (0x4007811C) /**< (XDMAC) Channel Interrupt Status Register 3 */ 83 #define REG_XDMAC_CSA3 (0x40078120) /**< (XDMAC) Channel Source Address Register 3 */ 84 #define REG_XDMAC_CDA3 (0x40078124) /**< (XDMAC) Channel Destination Address Register 3 */ 85 #define REG_XDMAC_CNDA3 (0x40078128) /**< (XDMAC) Channel Next Descriptor Address Register 3 */ 86 #define REG_XDMAC_CNDC3 (0x4007812C) /**< (XDMAC) Channel Next Descriptor Control Register 3 */ 87 #define REG_XDMAC_CUBC3 (0x40078130) /**< (XDMAC) Channel Microblock Control Register 3 */ 88 #define REG_XDMAC_CBC3 (0x40078134) /**< (XDMAC) Channel Block Control Register 3 */ 89 #define REG_XDMAC_CC3 (0x40078138) /**< (XDMAC) Channel Configuration Register 3 */ 90 #define REG_XDMAC_CDS_MSP3 (0x4007813C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */ 91 #define REG_XDMAC_CSUS3 (0x40078140) /**< (XDMAC) Channel Source Microblock Stride 3 */ 92 #define REG_XDMAC_CDUS3 (0x40078144) /**< (XDMAC) Channel Destination Microblock Stride 3 */ 93 #define REG_XDMAC_CIE4 (0x40078150) /**< (XDMAC) Channel Interrupt Enable Register 4 */ 94 #define REG_XDMAC_CID4 (0x40078154) /**< (XDMAC) Channel Interrupt Disable Register 4 */ 95 #define REG_XDMAC_CIM4 (0x40078158) /**< (XDMAC) Channel Interrupt Mask Register 4 */ 96 #define REG_XDMAC_CIS4 (0x4007815C) /**< (XDMAC) Channel Interrupt Status Register 4 */ 97 #define REG_XDMAC_CSA4 (0x40078160) /**< (XDMAC) Channel Source Address Register 4 */ 98 #define REG_XDMAC_CDA4 (0x40078164) /**< (XDMAC) Channel Destination Address Register 4 */ 99 #define REG_XDMAC_CNDA4 (0x40078168) /**< (XDMAC) Channel Next Descriptor Address Register 4 */ 100 #define REG_XDMAC_CNDC4 (0x4007816C) /**< (XDMAC) Channel Next Descriptor Control Register 4 */ 101 #define REG_XDMAC_CUBC4 (0x40078170) /**< (XDMAC) Channel Microblock Control Register 4 */ 102 #define REG_XDMAC_CBC4 (0x40078174) /**< (XDMAC) Channel Block Control Register 4 */ 103 #define REG_XDMAC_CC4 (0x40078178) /**< (XDMAC) Channel Configuration Register 4 */ 104 #define REG_XDMAC_CDS_MSP4 (0x4007817C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */ 105 #define REG_XDMAC_CSUS4 (0x40078180) /**< (XDMAC) Channel Source Microblock Stride 4 */ 106 #define REG_XDMAC_CDUS4 (0x40078184) /**< (XDMAC) Channel Destination Microblock Stride 4 */ 107 #define REG_XDMAC_CIE5 (0x40078190) /**< (XDMAC) Channel Interrupt Enable Register 5 */ 108 #define REG_XDMAC_CID5 (0x40078194) /**< (XDMAC) Channel Interrupt Disable Register 5 */ 109 #define REG_XDMAC_CIM5 (0x40078198) /**< (XDMAC) Channel Interrupt Mask Register 5 */ 110 #define REG_XDMAC_CIS5 (0x4007819C) /**< (XDMAC) Channel Interrupt Status Register 5 */ 111 #define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register 5 */ 112 #define REG_XDMAC_CDA5 (0x400781A4) /**< (XDMAC) Channel Destination Address Register 5 */ 113 #define REG_XDMAC_CNDA5 (0x400781A8) /**< (XDMAC) Channel Next Descriptor Address Register 5 */ 114 #define REG_XDMAC_CNDC5 (0x400781AC) /**< (XDMAC) Channel Next Descriptor Control Register 5 */ 115 #define REG_XDMAC_CUBC5 (0x400781B0) /**< (XDMAC) Channel Microblock Control Register 5 */ 116 #define REG_XDMAC_CBC5 (0x400781B4) /**< (XDMAC) Channel Block Control Register 5 */ 117 #define REG_XDMAC_CC5 (0x400781B8) /**< (XDMAC) Channel Configuration Register 5 */ 118 #define REG_XDMAC_CDS_MSP5 (0x400781BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */ 119 #define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride 5 */ 120 #define REG_XDMAC_CDUS5 (0x400781C4) /**< (XDMAC) Channel Destination Microblock Stride 5 */ 121 #define REG_XDMAC_CIE6 (0x400781D0) /**< (XDMAC) Channel Interrupt Enable Register 6 */ 122 #define REG_XDMAC_CID6 (0x400781D4) /**< (XDMAC) Channel Interrupt Disable Register 6 */ 123 #define REG_XDMAC_CIM6 (0x400781D8) /**< (XDMAC) Channel Interrupt Mask Register 6 */ 124 #define REG_XDMAC_CIS6 (0x400781DC) /**< (XDMAC) Channel Interrupt Status Register 6 */ 125 #define REG_XDMAC_CSA6 (0x400781E0) /**< (XDMAC) Channel Source Address Register 6 */ 126 #define REG_XDMAC_CDA6 (0x400781E4) /**< (XDMAC) Channel Destination Address Register 6 */ 127 #define REG_XDMAC_CNDA6 (0x400781E8) /**< (XDMAC) Channel Next Descriptor Address Register 6 */ 128 #define REG_XDMAC_CNDC6 (0x400781EC) /**< (XDMAC) Channel Next Descriptor Control Register 6 */ 129 #define REG_XDMAC_CUBC6 (0x400781F0) /**< (XDMAC) Channel Microblock Control Register 6 */ 130 #define REG_XDMAC_CBC6 (0x400781F4) /**< (XDMAC) Channel Block Control Register 6 */ 131 #define REG_XDMAC_CC6 (0x400781F8) /**< (XDMAC) Channel Configuration Register 6 */ 132 #define REG_XDMAC_CDS_MSP6 (0x400781FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */ 133 #define REG_XDMAC_CSUS6 (0x40078200) /**< (XDMAC) Channel Source Microblock Stride 6 */ 134 #define REG_XDMAC_CDUS6 (0x40078204) /**< (XDMAC) Channel Destination Microblock Stride 6 */ 135 #define REG_XDMAC_CIE7 (0x40078210) /**< (XDMAC) Channel Interrupt Enable Register 7 */ 136 #define REG_XDMAC_CID7 (0x40078214) /**< (XDMAC) Channel Interrupt Disable Register 7 */ 137 #define REG_XDMAC_CIM7 (0x40078218) /**< (XDMAC) Channel Interrupt Mask Register 7 */ 138 #define REG_XDMAC_CIS7 (0x4007821C) /**< (XDMAC) Channel Interrupt Status Register 7 */ 139 #define REG_XDMAC_CSA7 (0x40078220) /**< (XDMAC) Channel Source Address Register 7 */ 140 #define REG_XDMAC_CDA7 (0x40078224) /**< (XDMAC) Channel Destination Address Register 7 */ 141 #define REG_XDMAC_CNDA7 (0x40078228) /**< (XDMAC) Channel Next Descriptor Address Register 7 */ 142 #define REG_XDMAC_CNDC7 (0x4007822C) /**< (XDMAC) Channel Next Descriptor Control Register 7 */ 143 #define REG_XDMAC_CUBC7 (0x40078230) /**< (XDMAC) Channel Microblock Control Register 7 */ 144 #define REG_XDMAC_CBC7 (0x40078234) /**< (XDMAC) Channel Block Control Register 7 */ 145 #define REG_XDMAC_CC7 (0x40078238) /**< (XDMAC) Channel Configuration Register 7 */ 146 #define REG_XDMAC_CDS_MSP7 (0x4007823C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */ 147 #define REG_XDMAC_CSUS7 (0x40078240) /**< (XDMAC) Channel Source Microblock Stride 7 */ 148 #define REG_XDMAC_CDUS7 (0x40078244) /**< (XDMAC) Channel Destination Microblock Stride 7 */ 149 #define REG_XDMAC_CIE8 (0x40078250) /**< (XDMAC) Channel Interrupt Enable Register 8 */ 150 #define REG_XDMAC_CID8 (0x40078254) /**< (XDMAC) Channel Interrupt Disable Register 8 */ 151 #define REG_XDMAC_CIM8 (0x40078258) /**< (XDMAC) Channel Interrupt Mask Register 8 */ 152 #define REG_XDMAC_CIS8 (0x4007825C) /**< (XDMAC) Channel Interrupt Status Register 8 */ 153 #define REG_XDMAC_CSA8 (0x40078260) /**< (XDMAC) Channel Source Address Register 8 */ 154 #define REG_XDMAC_CDA8 (0x40078264) /**< (XDMAC) Channel Destination Address Register 8 */ 155 #define REG_XDMAC_CNDA8 (0x40078268) /**< (XDMAC) Channel Next Descriptor Address Register 8 */ 156 #define REG_XDMAC_CNDC8 (0x4007826C) /**< (XDMAC) Channel Next Descriptor Control Register 8 */ 157 #define REG_XDMAC_CUBC8 (0x40078270) /**< (XDMAC) Channel Microblock Control Register 8 */ 158 #define REG_XDMAC_CBC8 (0x40078274) /**< (XDMAC) Channel Block Control Register 8 */ 159 #define REG_XDMAC_CC8 (0x40078278) /**< (XDMAC) Channel Configuration Register 8 */ 160 #define REG_XDMAC_CDS_MSP8 (0x4007827C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */ 161 #define REG_XDMAC_CSUS8 (0x40078280) /**< (XDMAC) Channel Source Microblock Stride 8 */ 162 #define REG_XDMAC_CDUS8 (0x40078284) /**< (XDMAC) Channel Destination Microblock Stride 8 */ 163 #define REG_XDMAC_CIE9 (0x40078290) /**< (XDMAC) Channel Interrupt Enable Register 9 */ 164 #define REG_XDMAC_CID9 (0x40078294) /**< (XDMAC) Channel Interrupt Disable Register 9 */ 165 #define REG_XDMAC_CIM9 (0x40078298) /**< (XDMAC) Channel Interrupt Mask Register 9 */ 166 #define REG_XDMAC_CIS9 (0x4007829C) /**< (XDMAC) Channel Interrupt Status Register 9 */ 167 #define REG_XDMAC_CSA9 (0x400782A0) /**< (XDMAC) Channel Source Address Register 9 */ 168 #define REG_XDMAC_CDA9 (0x400782A4) /**< (XDMAC) Channel Destination Address Register 9 */ 169 #define REG_XDMAC_CNDA9 (0x400782A8) /**< (XDMAC) Channel Next Descriptor Address Register 9 */ 170 #define REG_XDMAC_CNDC9 (0x400782AC) /**< (XDMAC) Channel Next Descriptor Control Register 9 */ 171 #define REG_XDMAC_CUBC9 (0x400782B0) /**< (XDMAC) Channel Microblock Control Register 9 */ 172 #define REG_XDMAC_CBC9 (0x400782B4) /**< (XDMAC) Channel Block Control Register 9 */ 173 #define REG_XDMAC_CC9 (0x400782B8) /**< (XDMAC) Channel Configuration Register 9 */ 174 #define REG_XDMAC_CDS_MSP9 (0x400782BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */ 175 #define REG_XDMAC_CSUS9 (0x400782C0) /**< (XDMAC) Channel Source Microblock Stride 9 */ 176 #define REG_XDMAC_CDUS9 (0x400782C4) /**< (XDMAC) Channel Destination Microblock Stride 9 */ 177 #define REG_XDMAC_CIE10 (0x400782D0) /**< (XDMAC) Channel Interrupt Enable Register 10 */ 178 #define REG_XDMAC_CID10 (0x400782D4) /**< (XDMAC) Channel Interrupt Disable Register 10 */ 179 #define REG_XDMAC_CIM10 (0x400782D8) /**< (XDMAC) Channel Interrupt Mask Register 10 */ 180 #define REG_XDMAC_CIS10 (0x400782DC) /**< (XDMAC) Channel Interrupt Status Register 10 */ 181 #define REG_XDMAC_CSA10 (0x400782E0) /**< (XDMAC) Channel Source Address Register 10 */ 182 #define REG_XDMAC_CDA10 (0x400782E4) /**< (XDMAC) Channel Destination Address Register 10 */ 183 #define REG_XDMAC_CNDA10 (0x400782E8) /**< (XDMAC) Channel Next Descriptor Address Register 10 */ 184 #define REG_XDMAC_CNDC10 (0x400782EC) /**< (XDMAC) Channel Next Descriptor Control Register 10 */ 185 #define REG_XDMAC_CUBC10 (0x400782F0) /**< (XDMAC) Channel Microblock Control Register 10 */ 186 #define REG_XDMAC_CBC10 (0x400782F4) /**< (XDMAC) Channel Block Control Register 10 */ 187 #define REG_XDMAC_CC10 (0x400782F8) /**< (XDMAC) Channel Configuration Register 10 */ 188 #define REG_XDMAC_CDS_MSP10 (0x400782FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */ 189 #define REG_XDMAC_CSUS10 (0x40078300) /**< (XDMAC) Channel Source Microblock Stride 10 */ 190 #define REG_XDMAC_CDUS10 (0x40078304) /**< (XDMAC) Channel Destination Microblock Stride 10 */ 191 #define REG_XDMAC_CIE11 (0x40078310) /**< (XDMAC) Channel Interrupt Enable Register 11 */ 192 #define REG_XDMAC_CID11 (0x40078314) /**< (XDMAC) Channel Interrupt Disable Register 11 */ 193 #define REG_XDMAC_CIM11 (0x40078318) /**< (XDMAC) Channel Interrupt Mask Register 11 */ 194 #define REG_XDMAC_CIS11 (0x4007831C) /**< (XDMAC) Channel Interrupt Status Register 11 */ 195 #define REG_XDMAC_CSA11 (0x40078320) /**< (XDMAC) Channel Source Address Register 11 */ 196 #define REG_XDMAC_CDA11 (0x40078324) /**< (XDMAC) Channel Destination Address Register 11 */ 197 #define REG_XDMAC_CNDA11 (0x40078328) /**< (XDMAC) Channel Next Descriptor Address Register 11 */ 198 #define REG_XDMAC_CNDC11 (0x4007832C) /**< (XDMAC) Channel Next Descriptor Control Register 11 */ 199 #define REG_XDMAC_CUBC11 (0x40078330) /**< (XDMAC) Channel Microblock Control Register 11 */ 200 #define REG_XDMAC_CBC11 (0x40078334) /**< (XDMAC) Channel Block Control Register 11 */ 201 #define REG_XDMAC_CC11 (0x40078338) /**< (XDMAC) Channel Configuration Register 11 */ 202 #define REG_XDMAC_CDS_MSP11 (0x4007833C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */ 203 #define REG_XDMAC_CSUS11 (0x40078340) /**< (XDMAC) Channel Source Microblock Stride 11 */ 204 #define REG_XDMAC_CDUS11 (0x40078344) /**< (XDMAC) Channel Destination Microblock Stride 11 */ 205 #define REG_XDMAC_CIE12 (0x40078350) /**< (XDMAC) Channel Interrupt Enable Register 12 */ 206 #define REG_XDMAC_CID12 (0x40078354) /**< (XDMAC) Channel Interrupt Disable Register 12 */ 207 #define REG_XDMAC_CIM12 (0x40078358) /**< (XDMAC) Channel Interrupt Mask Register 12 */ 208 #define REG_XDMAC_CIS12 (0x4007835C) /**< (XDMAC) Channel Interrupt Status Register 12 */ 209 #define REG_XDMAC_CSA12 (0x40078360) /**< (XDMAC) Channel Source Address Register 12 */ 210 #define REG_XDMAC_CDA12 (0x40078364) /**< (XDMAC) Channel Destination Address Register 12 */ 211 #define REG_XDMAC_CNDA12 (0x40078368) /**< (XDMAC) Channel Next Descriptor Address Register 12 */ 212 #define REG_XDMAC_CNDC12 (0x4007836C) /**< (XDMAC) Channel Next Descriptor Control Register 12 */ 213 #define REG_XDMAC_CUBC12 (0x40078370) /**< (XDMAC) Channel Microblock Control Register 12 */ 214 #define REG_XDMAC_CBC12 (0x40078374) /**< (XDMAC) Channel Block Control Register 12 */ 215 #define REG_XDMAC_CC12 (0x40078378) /**< (XDMAC) Channel Configuration Register 12 */ 216 #define REG_XDMAC_CDS_MSP12 (0x4007837C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */ 217 #define REG_XDMAC_CSUS12 (0x40078380) /**< (XDMAC) Channel Source Microblock Stride 12 */ 218 #define REG_XDMAC_CDUS12 (0x40078384) /**< (XDMAC) Channel Destination Microblock Stride 12 */ 219 #define REG_XDMAC_CIE13 (0x40078390) /**< (XDMAC) Channel Interrupt Enable Register 13 */ 220 #define REG_XDMAC_CID13 (0x40078394) /**< (XDMAC) Channel Interrupt Disable Register 13 */ 221 #define REG_XDMAC_CIM13 (0x40078398) /**< (XDMAC) Channel Interrupt Mask Register 13 */ 222 #define REG_XDMAC_CIS13 (0x4007839C) /**< (XDMAC) Channel Interrupt Status Register 13 */ 223 #define REG_XDMAC_CSA13 (0x400783A0) /**< (XDMAC) Channel Source Address Register 13 */ 224 #define REG_XDMAC_CDA13 (0x400783A4) /**< (XDMAC) Channel Destination Address Register 13 */ 225 #define REG_XDMAC_CNDA13 (0x400783A8) /**< (XDMAC) Channel Next Descriptor Address Register 13 */ 226 #define REG_XDMAC_CNDC13 (0x400783AC) /**< (XDMAC) Channel Next Descriptor Control Register 13 */ 227 #define REG_XDMAC_CUBC13 (0x400783B0) /**< (XDMAC) Channel Microblock Control Register 13 */ 228 #define REG_XDMAC_CBC13 (0x400783B4) /**< (XDMAC) Channel Block Control Register 13 */ 229 #define REG_XDMAC_CC13 (0x400783B8) /**< (XDMAC) Channel Configuration Register 13 */ 230 #define REG_XDMAC_CDS_MSP13 (0x400783BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */ 231 #define REG_XDMAC_CSUS13 (0x400783C0) /**< (XDMAC) Channel Source Microblock Stride 13 */ 232 #define REG_XDMAC_CDUS13 (0x400783C4) /**< (XDMAC) Channel Destination Microblock Stride 13 */ 233 #define REG_XDMAC_CIE14 (0x400783D0) /**< (XDMAC) Channel Interrupt Enable Register 14 */ 234 #define REG_XDMAC_CID14 (0x400783D4) /**< (XDMAC) Channel Interrupt Disable Register 14 */ 235 #define REG_XDMAC_CIM14 (0x400783D8) /**< (XDMAC) Channel Interrupt Mask Register 14 */ 236 #define REG_XDMAC_CIS14 (0x400783DC) /**< (XDMAC) Channel Interrupt Status Register 14 */ 237 #define REG_XDMAC_CSA14 (0x400783E0) /**< (XDMAC) Channel Source Address Register 14 */ 238 #define REG_XDMAC_CDA14 (0x400783E4) /**< (XDMAC) Channel Destination Address Register 14 */ 239 #define REG_XDMAC_CNDA14 (0x400783E8) /**< (XDMAC) Channel Next Descriptor Address Register 14 */ 240 #define REG_XDMAC_CNDC14 (0x400783EC) /**< (XDMAC) Channel Next Descriptor Control Register 14 */ 241 #define REG_XDMAC_CUBC14 (0x400783F0) /**< (XDMAC) Channel Microblock Control Register 14 */ 242 #define REG_XDMAC_CBC14 (0x400783F4) /**< (XDMAC) Channel Block Control Register 14 */ 243 #define REG_XDMAC_CC14 (0x400783F8) /**< (XDMAC) Channel Configuration Register 14 */ 244 #define REG_XDMAC_CDS_MSP14 (0x400783FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */ 245 #define REG_XDMAC_CSUS14 (0x40078400) /**< (XDMAC) Channel Source Microblock Stride 14 */ 246 #define REG_XDMAC_CDUS14 (0x40078404) /**< (XDMAC) Channel Destination Microblock Stride 14 */ 247 #define REG_XDMAC_CIE15 (0x40078410) /**< (XDMAC) Channel Interrupt Enable Register 15 */ 248 #define REG_XDMAC_CID15 (0x40078414) /**< (XDMAC) Channel Interrupt Disable Register 15 */ 249 #define REG_XDMAC_CIM15 (0x40078418) /**< (XDMAC) Channel Interrupt Mask Register 15 */ 250 #define REG_XDMAC_CIS15 (0x4007841C) /**< (XDMAC) Channel Interrupt Status Register 15 */ 251 #define REG_XDMAC_CSA15 (0x40078420) /**< (XDMAC) Channel Source Address Register 15 */ 252 #define REG_XDMAC_CDA15 (0x40078424) /**< (XDMAC) Channel Destination Address Register 15 */ 253 #define REG_XDMAC_CNDA15 (0x40078428) /**< (XDMAC) Channel Next Descriptor Address Register 15 */ 254 #define REG_XDMAC_CNDC15 (0x4007842C) /**< (XDMAC) Channel Next Descriptor Control Register 15 */ 255 #define REG_XDMAC_CUBC15 (0x40078430) /**< (XDMAC) Channel Microblock Control Register 15 */ 256 #define REG_XDMAC_CBC15 (0x40078434) /**< (XDMAC) Channel Block Control Register 15 */ 257 #define REG_XDMAC_CC15 (0x40078438) /**< (XDMAC) Channel Configuration Register 15 */ 258 #define REG_XDMAC_CDS_MSP15 (0x4007843C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */ 259 #define REG_XDMAC_CSUS15 (0x40078440) /**< (XDMAC) Channel Source Microblock Stride 15 */ 260 #define REG_XDMAC_CDUS15 (0x40078444) /**< (XDMAC) Channel Destination Microblock Stride 15 */ 261 #define REG_XDMAC_CIE16 (0x40078450) /**< (XDMAC) Channel Interrupt Enable Register 16 */ 262 #define REG_XDMAC_CID16 (0x40078454) /**< (XDMAC) Channel Interrupt Disable Register 16 */ 263 #define REG_XDMAC_CIM16 (0x40078458) /**< (XDMAC) Channel Interrupt Mask Register 16 */ 264 #define REG_XDMAC_CIS16 (0x4007845C) /**< (XDMAC) Channel Interrupt Status Register 16 */ 265 #define REG_XDMAC_CSA16 (0x40078460) /**< (XDMAC) Channel Source Address Register 16 */ 266 #define REG_XDMAC_CDA16 (0x40078464) /**< (XDMAC) Channel Destination Address Register 16 */ 267 #define REG_XDMAC_CNDA16 (0x40078468) /**< (XDMAC) Channel Next Descriptor Address Register 16 */ 268 #define REG_XDMAC_CNDC16 (0x4007846C) /**< (XDMAC) Channel Next Descriptor Control Register 16 */ 269 #define REG_XDMAC_CUBC16 (0x40078470) /**< (XDMAC) Channel Microblock Control Register 16 */ 270 #define REG_XDMAC_CBC16 (0x40078474) /**< (XDMAC) Channel Block Control Register 16 */ 271 #define REG_XDMAC_CC16 (0x40078478) /**< (XDMAC) Channel Configuration Register 16 */ 272 #define REG_XDMAC_CDS_MSP16 (0x4007847C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */ 273 #define REG_XDMAC_CSUS16 (0x40078480) /**< (XDMAC) Channel Source Microblock Stride 16 */ 274 #define REG_XDMAC_CDUS16 (0x40078484) /**< (XDMAC) Channel Destination Microblock Stride 16 */ 275 #define REG_XDMAC_CIE17 (0x40078490) /**< (XDMAC) Channel Interrupt Enable Register 17 */ 276 #define REG_XDMAC_CID17 (0x40078494) /**< (XDMAC) Channel Interrupt Disable Register 17 */ 277 #define REG_XDMAC_CIM17 (0x40078498) /**< (XDMAC) Channel Interrupt Mask Register 17 */ 278 #define REG_XDMAC_CIS17 (0x4007849C) /**< (XDMAC) Channel Interrupt Status Register 17 */ 279 #define REG_XDMAC_CSA17 (0x400784A0) /**< (XDMAC) Channel Source Address Register 17 */ 280 #define REG_XDMAC_CDA17 (0x400784A4) /**< (XDMAC) Channel Destination Address Register 17 */ 281 #define REG_XDMAC_CNDA17 (0x400784A8) /**< (XDMAC) Channel Next Descriptor Address Register 17 */ 282 #define REG_XDMAC_CNDC17 (0x400784AC) /**< (XDMAC) Channel Next Descriptor Control Register 17 */ 283 #define REG_XDMAC_CUBC17 (0x400784B0) /**< (XDMAC) Channel Microblock Control Register 17 */ 284 #define REG_XDMAC_CBC17 (0x400784B4) /**< (XDMAC) Channel Block Control Register 17 */ 285 #define REG_XDMAC_CC17 (0x400784B8) /**< (XDMAC) Channel Configuration Register 17 */ 286 #define REG_XDMAC_CDS_MSP17 (0x400784BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */ 287 #define REG_XDMAC_CSUS17 (0x400784C0) /**< (XDMAC) Channel Source Microblock Stride 17 */ 288 #define REG_XDMAC_CDUS17 (0x400784C4) /**< (XDMAC) Channel Destination Microblock Stride 17 */ 289 #define REG_XDMAC_CIE18 (0x400784D0) /**< (XDMAC) Channel Interrupt Enable Register 18 */ 290 #define REG_XDMAC_CID18 (0x400784D4) /**< (XDMAC) Channel Interrupt Disable Register 18 */ 291 #define REG_XDMAC_CIM18 (0x400784D8) /**< (XDMAC) Channel Interrupt Mask Register 18 */ 292 #define REG_XDMAC_CIS18 (0x400784DC) /**< (XDMAC) Channel Interrupt Status Register 18 */ 293 #define REG_XDMAC_CSA18 (0x400784E0) /**< (XDMAC) Channel Source Address Register 18 */ 294 #define REG_XDMAC_CDA18 (0x400784E4) /**< (XDMAC) Channel Destination Address Register 18 */ 295 #define REG_XDMAC_CNDA18 (0x400784E8) /**< (XDMAC) Channel Next Descriptor Address Register 18 */ 296 #define REG_XDMAC_CNDC18 (0x400784EC) /**< (XDMAC) Channel Next Descriptor Control Register 18 */ 297 #define REG_XDMAC_CUBC18 (0x400784F0) /**< (XDMAC) Channel Microblock Control Register 18 */ 298 #define REG_XDMAC_CBC18 (0x400784F4) /**< (XDMAC) Channel Block Control Register 18 */ 299 #define REG_XDMAC_CC18 (0x400784F8) /**< (XDMAC) Channel Configuration Register 18 */ 300 #define REG_XDMAC_CDS_MSP18 (0x400784FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */ 301 #define REG_XDMAC_CSUS18 (0x40078500) /**< (XDMAC) Channel Source Microblock Stride 18 */ 302 #define REG_XDMAC_CDUS18 (0x40078504) /**< (XDMAC) Channel Destination Microblock Stride 18 */ 303 #define REG_XDMAC_CIE19 (0x40078510) /**< (XDMAC) Channel Interrupt Enable Register 19 */ 304 #define REG_XDMAC_CID19 (0x40078514) /**< (XDMAC) Channel Interrupt Disable Register 19 */ 305 #define REG_XDMAC_CIM19 (0x40078518) /**< (XDMAC) Channel Interrupt Mask Register 19 */ 306 #define REG_XDMAC_CIS19 (0x4007851C) /**< (XDMAC) Channel Interrupt Status Register 19 */ 307 #define REG_XDMAC_CSA19 (0x40078520) /**< (XDMAC) Channel Source Address Register 19 */ 308 #define REG_XDMAC_CDA19 (0x40078524) /**< (XDMAC) Channel Destination Address Register 19 */ 309 #define REG_XDMAC_CNDA19 (0x40078528) /**< (XDMAC) Channel Next Descriptor Address Register 19 */ 310 #define REG_XDMAC_CNDC19 (0x4007852C) /**< (XDMAC) Channel Next Descriptor Control Register 19 */ 311 #define REG_XDMAC_CUBC19 (0x40078530) /**< (XDMAC) Channel Microblock Control Register 19 */ 312 #define REG_XDMAC_CBC19 (0x40078534) /**< (XDMAC) Channel Block Control Register 19 */ 313 #define REG_XDMAC_CC19 (0x40078538) /**< (XDMAC) Channel Configuration Register 19 */ 314 #define REG_XDMAC_CDS_MSP19 (0x4007853C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */ 315 #define REG_XDMAC_CSUS19 (0x40078540) /**< (XDMAC) Channel Source Microblock Stride 19 */ 316 #define REG_XDMAC_CDUS19 (0x40078544) /**< (XDMAC) Channel Destination Microblock Stride 19 */ 317 #define REG_XDMAC_CIE20 (0x40078550) /**< (XDMAC) Channel Interrupt Enable Register 20 */ 318 #define REG_XDMAC_CID20 (0x40078554) /**< (XDMAC) Channel Interrupt Disable Register 20 */ 319 #define REG_XDMAC_CIM20 (0x40078558) /**< (XDMAC) Channel Interrupt Mask Register 20 */ 320 #define REG_XDMAC_CIS20 (0x4007855C) /**< (XDMAC) Channel Interrupt Status Register 20 */ 321 #define REG_XDMAC_CSA20 (0x40078560) /**< (XDMAC) Channel Source Address Register 20 */ 322 #define REG_XDMAC_CDA20 (0x40078564) /**< (XDMAC) Channel Destination Address Register 20 */ 323 #define REG_XDMAC_CNDA20 (0x40078568) /**< (XDMAC) Channel Next Descriptor Address Register 20 */ 324 #define REG_XDMAC_CNDC20 (0x4007856C) /**< (XDMAC) Channel Next Descriptor Control Register 20 */ 325 #define REG_XDMAC_CUBC20 (0x40078570) /**< (XDMAC) Channel Microblock Control Register 20 */ 326 #define REG_XDMAC_CBC20 (0x40078574) /**< (XDMAC) Channel Block Control Register 20 */ 327 #define REG_XDMAC_CC20 (0x40078578) /**< (XDMAC) Channel Configuration Register 20 */ 328 #define REG_XDMAC_CDS_MSP20 (0x4007857C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */ 329 #define REG_XDMAC_CSUS20 (0x40078580) /**< (XDMAC) Channel Source Microblock Stride 20 */ 330 #define REG_XDMAC_CDUS20 (0x40078584) /**< (XDMAC) Channel Destination Microblock Stride 20 */ 331 #define REG_XDMAC_CIE21 (0x40078590) /**< (XDMAC) Channel Interrupt Enable Register 21 */ 332 #define REG_XDMAC_CID21 (0x40078594) /**< (XDMAC) Channel Interrupt Disable Register 21 */ 333 #define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register 21 */ 334 #define REG_XDMAC_CIS21 (0x4007859C) /**< (XDMAC) Channel Interrupt Status Register 21 */ 335 #define REG_XDMAC_CSA21 (0x400785A0) /**< (XDMAC) Channel Source Address Register 21 */ 336 #define REG_XDMAC_CDA21 (0x400785A4) /**< (XDMAC) Channel Destination Address Register 21 */ 337 #define REG_XDMAC_CNDA21 (0x400785A8) /**< (XDMAC) Channel Next Descriptor Address Register 21 */ 338 #define REG_XDMAC_CNDC21 (0x400785AC) /**< (XDMAC) Channel Next Descriptor Control Register 21 */ 339 #define REG_XDMAC_CUBC21 (0x400785B0) /**< (XDMAC) Channel Microblock Control Register 21 */ 340 #define REG_XDMAC_CBC21 (0x400785B4) /**< (XDMAC) Channel Block Control Register 21 */ 341 #define REG_XDMAC_CC21 (0x400785B8) /**< (XDMAC) Channel Configuration Register 21 */ 342 #define REG_XDMAC_CDS_MSP21 (0x400785BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */ 343 #define REG_XDMAC_CSUS21 (0x400785C0) /**< (XDMAC) Channel Source Microblock Stride 21 */ 344 #define REG_XDMAC_CDUS21 (0x400785C4) /**< (XDMAC) Channel Destination Microblock Stride 21 */ 345 #define REG_XDMAC_CIE22 (0x400785D0) /**< (XDMAC) Channel Interrupt Enable Register 22 */ 346 #define REG_XDMAC_CID22 (0x400785D4) /**< (XDMAC) Channel Interrupt Disable Register 22 */ 347 #define REG_XDMAC_CIM22 (0x400785D8) /**< (XDMAC) Channel Interrupt Mask Register 22 */ 348 #define REG_XDMAC_CIS22 (0x400785DC) /**< (XDMAC) Channel Interrupt Status Register 22 */ 349 #define REG_XDMAC_CSA22 (0x400785E0) /**< (XDMAC) Channel Source Address Register 22 */ 350 #define REG_XDMAC_CDA22 (0x400785E4) /**< (XDMAC) Channel Destination Address Register 22 */ 351 #define REG_XDMAC_CNDA22 (0x400785E8) /**< (XDMAC) Channel Next Descriptor Address Register 22 */ 352 #define REG_XDMAC_CNDC22 (0x400785EC) /**< (XDMAC) Channel Next Descriptor Control Register 22 */ 353 #define REG_XDMAC_CUBC22 (0x400785F0) /**< (XDMAC) Channel Microblock Control Register 22 */ 354 #define REG_XDMAC_CBC22 (0x400785F4) /**< (XDMAC) Channel Block Control Register 22 */ 355 #define REG_XDMAC_CC22 (0x400785F8) /**< (XDMAC) Channel Configuration Register 22 */ 356 #define REG_XDMAC_CDS_MSP22 (0x400785FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */ 357 #define REG_XDMAC_CSUS22 (0x40078600) /**< (XDMAC) Channel Source Microblock Stride 22 */ 358 #define REG_XDMAC_CDUS22 (0x40078604) /**< (XDMAC) Channel Destination Microblock Stride 22 */ 359 #define REG_XDMAC_CIE23 (0x40078610) /**< (XDMAC) Channel Interrupt Enable Register 23 */ 360 #define REG_XDMAC_CID23 (0x40078614) /**< (XDMAC) Channel Interrupt Disable Register 23 */ 361 #define REG_XDMAC_CIM23 (0x40078618) /**< (XDMAC) Channel Interrupt Mask Register 23 */ 362 #define REG_XDMAC_CIS23 (0x4007861C) /**< (XDMAC) Channel Interrupt Status Register 23 */ 363 #define REG_XDMAC_CSA23 (0x40078620) /**< (XDMAC) Channel Source Address Register 23 */ 364 #define REG_XDMAC_CDA23 (0x40078624) /**< (XDMAC) Channel Destination Address Register 23 */ 365 #define REG_XDMAC_CNDA23 (0x40078628) /**< (XDMAC) Channel Next Descriptor Address Register 23 */ 366 #define REG_XDMAC_CNDC23 (0x4007862C) /**< (XDMAC) Channel Next Descriptor Control Register 23 */ 367 #define REG_XDMAC_CUBC23 (0x40078630) /**< (XDMAC) Channel Microblock Control Register 23 */ 368 #define REG_XDMAC_CBC23 (0x40078634) /**< (XDMAC) Channel Block Control Register 23 */ 369 #define REG_XDMAC_CC23 (0x40078638) /**< (XDMAC) Channel Configuration Register 23 */ 370 #define REG_XDMAC_CDS_MSP23 (0x4007863C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */ 371 #define REG_XDMAC_CSUS23 (0x40078640) /**< (XDMAC) Channel Source Microblock Stride 23 */ 372 #define REG_XDMAC_CDUS23 (0x40078644) /**< (XDMAC) Channel Destination Microblock Stride 23 */ 373 #define REG_XDMAC_GTYPE (0x40078000) /**< (XDMAC) Global Type Register */ 374 #define REG_XDMAC_GCFG (0x40078004) /**< (XDMAC) Global Configuration Register */ 375 #define REG_XDMAC_GWAC (0x40078008) /**< (XDMAC) Global Weighted Arbiter Configuration Register */ 376 #define REG_XDMAC_GIE (0x4007800C) /**< (XDMAC) Global Interrupt Enable Register */ 377 #define REG_XDMAC_GID (0x40078010) /**< (XDMAC) Global Interrupt Disable Register */ 378 #define REG_XDMAC_GIM (0x40078014) /**< (XDMAC) Global Interrupt Mask Register */ 379 #define REG_XDMAC_GIS (0x40078018) /**< (XDMAC) Global Interrupt Status Register */ 380 #define REG_XDMAC_GE (0x4007801C) /**< (XDMAC) Global Channel Enable Register */ 381 #define REG_XDMAC_GD (0x40078020) /**< (XDMAC) Global Channel Disable Register */ 382 #define REG_XDMAC_GS (0x40078024) /**< (XDMAC) Global Channel Status Register */ 383 #define REG_XDMAC_GRS (0x40078028) /**< (XDMAC) Global Channel Read Suspend Register */ 384 #define REG_XDMAC_GWS (0x4007802C) /**< (XDMAC) Global Channel Write Suspend Register */ 385 #define REG_XDMAC_GRWS (0x40078030) /**< (XDMAC) Global Channel Read Write Suspend Register */ 386 #define REG_XDMAC_GRWR (0x40078034) /**< (XDMAC) Global Channel Read Write Resume Register */ 387 #define REG_XDMAC_GSWR (0x40078038) /**< (XDMAC) Global Channel Software Request Register */ 388 #define REG_XDMAC_GSWS (0x4007803C) /**< (XDMAC) Global Channel Software Request Status Register */ 389 #define REG_XDMAC_GSWF (0x40078040) /**< (XDMAC) Global Channel Software Flush Request Register */ 390 391 #else 392 393 #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< (XDMAC) Channel Interrupt Enable Register 0 */ 394 #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< (XDMAC) Channel Interrupt Disable Register 0 */ 395 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask Register 0 */ 396 #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< (XDMAC) Channel Interrupt Status Register 0 */ 397 #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< (XDMAC) Channel Source Address Register 0 */ 398 #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< (XDMAC) Channel Destination Address Register 0 */ 399 #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< (XDMAC) Channel Next Descriptor Address Register 0 */ 400 #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< (XDMAC) Channel Next Descriptor Control Register 0 */ 401 #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< (XDMAC) Channel Microblock Control Register 0 */ 402 #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< (XDMAC) Channel Block Control Register 0 */ 403 #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< (XDMAC) Channel Configuration Register 0 */ 404 #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */ 405 #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< (XDMAC) Channel Source Microblock Stride 0 */ 406 #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< (XDMAC) Channel Destination Microblock Stride 0 */ 407 #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< (XDMAC) Channel Interrupt Enable Register 1 */ 408 #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< (XDMAC) Channel Interrupt Disable Register 1 */ 409 #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< (XDMAC) Channel Interrupt Mask Register 1 */ 410 #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< (XDMAC) Channel Interrupt Status Register 1 */ 411 #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< (XDMAC) Channel Source Address Register 1 */ 412 #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< (XDMAC) Channel Destination Address Register 1 */ 413 #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< (XDMAC) Channel Next Descriptor Address Register 1 */ 414 #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< (XDMAC) Channel Next Descriptor Control Register 1 */ 415 #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< (XDMAC) Channel Microblock Control Register 1 */ 416 #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< (XDMAC) Channel Block Control Register 1 */ 417 #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< (XDMAC) Channel Configuration Register 1 */ 418 #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */ 419 #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< (XDMAC) Channel Source Microblock Stride 1 */ 420 #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< (XDMAC) Channel Destination Microblock Stride 1 */ 421 #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< (XDMAC) Channel Interrupt Enable Register 2 */ 422 #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< (XDMAC) Channel Interrupt Disable Register 2 */ 423 #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< (XDMAC) Channel Interrupt Mask Register 2 */ 424 #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< (XDMAC) Channel Interrupt Status Register 2 */ 425 #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< (XDMAC) Channel Source Address Register 2 */ 426 #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< (XDMAC) Channel Destination Address Register 2 */ 427 #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< (XDMAC) Channel Next Descriptor Address Register 2 */ 428 #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< (XDMAC) Channel Next Descriptor Control Register 2 */ 429 #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< (XDMAC) Channel Microblock Control Register 2 */ 430 #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< (XDMAC) Channel Block Control Register 2 */ 431 #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< (XDMAC) Channel Configuration Register 2 */ 432 #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */ 433 #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< (XDMAC) Channel Source Microblock Stride 2 */ 434 #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< (XDMAC) Channel Destination Microblock Stride 2 */ 435 #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< (XDMAC) Channel Interrupt Enable Register 3 */ 436 #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< (XDMAC) Channel Interrupt Disable Register 3 */ 437 #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< (XDMAC) Channel Interrupt Mask Register 3 */ 438 #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< (XDMAC) Channel Interrupt Status Register 3 */ 439 #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< (XDMAC) Channel Source Address Register 3 */ 440 #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< (XDMAC) Channel Destination Address Register 3 */ 441 #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< (XDMAC) Channel Next Descriptor Address Register 3 */ 442 #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< (XDMAC) Channel Next Descriptor Control Register 3 */ 443 #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< (XDMAC) Channel Microblock Control Register 3 */ 444 #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< (XDMAC) Channel Block Control Register 3 */ 445 #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< (XDMAC) Channel Configuration Register 3 */ 446 #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */ 447 #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< (XDMAC) Channel Source Microblock Stride 3 */ 448 #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< (XDMAC) Channel Destination Microblock Stride 3 */ 449 #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< (XDMAC) Channel Interrupt Enable Register 4 */ 450 #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< (XDMAC) Channel Interrupt Disable Register 4 */ 451 #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< (XDMAC) Channel Interrupt Mask Register 4 */ 452 #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< (XDMAC) Channel Interrupt Status Register 4 */ 453 #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< (XDMAC) Channel Source Address Register 4 */ 454 #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< (XDMAC) Channel Destination Address Register 4 */ 455 #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< (XDMAC) Channel Next Descriptor Address Register 4 */ 456 #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< (XDMAC) Channel Next Descriptor Control Register 4 */ 457 #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< (XDMAC) Channel Microblock Control Register 4 */ 458 #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< (XDMAC) Channel Block Control Register 4 */ 459 #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< (XDMAC) Channel Configuration Register 4 */ 460 #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */ 461 #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< (XDMAC) Channel Source Microblock Stride 4 */ 462 #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< (XDMAC) Channel Destination Microblock Stride 4 */ 463 #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< (XDMAC) Channel Interrupt Enable Register 5 */ 464 #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< (XDMAC) Channel Interrupt Disable Register 5 */ 465 #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< (XDMAC) Channel Interrupt Mask Register 5 */ 466 #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< (XDMAC) Channel Interrupt Status Register 5 */ 467 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address Register 5 */ 468 #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< (XDMAC) Channel Destination Address Register 5 */ 469 #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< (XDMAC) Channel Next Descriptor Address Register 5 */ 470 #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< (XDMAC) Channel Next Descriptor Control Register 5 */ 471 #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< (XDMAC) Channel Microblock Control Register 5 */ 472 #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< (XDMAC) Channel Block Control Register 5 */ 473 #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< (XDMAC) Channel Configuration Register 5 */ 474 #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */ 475 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblock Stride 5 */ 476 #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< (XDMAC) Channel Destination Microblock Stride 5 */ 477 #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< (XDMAC) Channel Interrupt Enable Register 6 */ 478 #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< (XDMAC) Channel Interrupt Disable Register 6 */ 479 #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< (XDMAC) Channel Interrupt Mask Register 6 */ 480 #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< (XDMAC) Channel Interrupt Status Register 6 */ 481 #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< (XDMAC) Channel Source Address Register 6 */ 482 #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< (XDMAC) Channel Destination Address Register 6 */ 483 #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< (XDMAC) Channel Next Descriptor Address Register 6 */ 484 #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< (XDMAC) Channel Next Descriptor Control Register 6 */ 485 #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< (XDMAC) Channel Microblock Control Register 6 */ 486 #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< (XDMAC) Channel Block Control Register 6 */ 487 #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< (XDMAC) Channel Configuration Register 6 */ 488 #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */ 489 #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< (XDMAC) Channel Source Microblock Stride 6 */ 490 #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< (XDMAC) Channel Destination Microblock Stride 6 */ 491 #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< (XDMAC) Channel Interrupt Enable Register 7 */ 492 #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< (XDMAC) Channel Interrupt Disable Register 7 */ 493 #define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< (XDMAC) Channel Interrupt Mask Register 7 */ 494 #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< (XDMAC) Channel Interrupt Status Register 7 */ 495 #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< (XDMAC) Channel Source Address Register 7 */ 496 #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< (XDMAC) Channel Destination Address Register 7 */ 497 #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< (XDMAC) Channel Next Descriptor Address Register 7 */ 498 #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< (XDMAC) Channel Next Descriptor Control Register 7 */ 499 #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< (XDMAC) Channel Microblock Control Register 7 */ 500 #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< (XDMAC) Channel Block Control Register 7 */ 501 #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< (XDMAC) Channel Configuration Register 7 */ 502 #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */ 503 #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< (XDMAC) Channel Source Microblock Stride 7 */ 504 #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< (XDMAC) Channel Destination Microblock Stride 7 */ 505 #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< (XDMAC) Channel Interrupt Enable Register 8 */ 506 #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< (XDMAC) Channel Interrupt Disable Register 8 */ 507 #define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< (XDMAC) Channel Interrupt Mask Register 8 */ 508 #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< (XDMAC) Channel Interrupt Status Register 8 */ 509 #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< (XDMAC) Channel Source Address Register 8 */ 510 #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< (XDMAC) Channel Destination Address Register 8 */ 511 #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< (XDMAC) Channel Next Descriptor Address Register 8 */ 512 #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< (XDMAC) Channel Next Descriptor Control Register 8 */ 513 #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< (XDMAC) Channel Microblock Control Register 8 */ 514 #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< (XDMAC) Channel Block Control Register 8 */ 515 #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< (XDMAC) Channel Configuration Register 8 */ 516 #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */ 517 #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< (XDMAC) Channel Source Microblock Stride 8 */ 518 #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< (XDMAC) Channel Destination Microblock Stride 8 */ 519 #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< (XDMAC) Channel Interrupt Enable Register 9 */ 520 #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< (XDMAC) Channel Interrupt Disable Register 9 */ 521 #define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< (XDMAC) Channel Interrupt Mask Register 9 */ 522 #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< (XDMAC) Channel Interrupt Status Register 9 */ 523 #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< (XDMAC) Channel Source Address Register 9 */ 524 #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< (XDMAC) Channel Destination Address Register 9 */ 525 #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< (XDMAC) Channel Next Descriptor Address Register 9 */ 526 #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< (XDMAC) Channel Next Descriptor Control Register 9 */ 527 #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< (XDMAC) Channel Microblock Control Register 9 */ 528 #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< (XDMAC) Channel Block Control Register 9 */ 529 #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< (XDMAC) Channel Configuration Register 9 */ 530 #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */ 531 #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< (XDMAC) Channel Source Microblock Stride 9 */ 532 #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< (XDMAC) Channel Destination Microblock Stride 9 */ 533 #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< (XDMAC) Channel Interrupt Enable Register 10 */ 534 #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< (XDMAC) Channel Interrupt Disable Register 10 */ 535 #define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< (XDMAC) Channel Interrupt Mask Register 10 */ 536 #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< (XDMAC) Channel Interrupt Status Register 10 */ 537 #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< (XDMAC) Channel Source Address Register 10 */ 538 #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< (XDMAC) Channel Destination Address Register 10 */ 539 #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< (XDMAC) Channel Next Descriptor Address Register 10 */ 540 #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< (XDMAC) Channel Next Descriptor Control Register 10 */ 541 #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< (XDMAC) Channel Microblock Control Register 10 */ 542 #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< (XDMAC) Channel Block Control Register 10 */ 543 #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< (XDMAC) Channel Configuration Register 10 */ 544 #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */ 545 #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< (XDMAC) Channel Source Microblock Stride 10 */ 546 #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< (XDMAC) Channel Destination Microblock Stride 10 */ 547 #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< (XDMAC) Channel Interrupt Enable Register 11 */ 548 #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< (XDMAC) Channel Interrupt Disable Register 11 */ 549 #define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< (XDMAC) Channel Interrupt Mask Register 11 */ 550 #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< (XDMAC) Channel Interrupt Status Register 11 */ 551 #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< (XDMAC) Channel Source Address Register 11 */ 552 #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< (XDMAC) Channel Destination Address Register 11 */ 553 #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< (XDMAC) Channel Next Descriptor Address Register 11 */ 554 #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< (XDMAC) Channel Next Descriptor Control Register 11 */ 555 #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< (XDMAC) Channel Microblock Control Register 11 */ 556 #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< (XDMAC) Channel Block Control Register 11 */ 557 #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< (XDMAC) Channel Configuration Register 11 */ 558 #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */ 559 #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< (XDMAC) Channel Source Microblock Stride 11 */ 560 #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< (XDMAC) Channel Destination Microblock Stride 11 */ 561 #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< (XDMAC) Channel Interrupt Enable Register 12 */ 562 #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< (XDMAC) Channel Interrupt Disable Register 12 */ 563 #define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< (XDMAC) Channel Interrupt Mask Register 12 */ 564 #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< (XDMAC) Channel Interrupt Status Register 12 */ 565 #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< (XDMAC) Channel Source Address Register 12 */ 566 #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< (XDMAC) Channel Destination Address Register 12 */ 567 #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< (XDMAC) Channel Next Descriptor Address Register 12 */ 568 #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< (XDMAC) Channel Next Descriptor Control Register 12 */ 569 #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< (XDMAC) Channel Microblock Control Register 12 */ 570 #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< (XDMAC) Channel Block Control Register 12 */ 571 #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< (XDMAC) Channel Configuration Register 12 */ 572 #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */ 573 #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< (XDMAC) Channel Source Microblock Stride 12 */ 574 #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< (XDMAC) Channel Destination Microblock Stride 12 */ 575 #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< (XDMAC) Channel Interrupt Enable Register 13 */ 576 #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< (XDMAC) Channel Interrupt Disable Register 13 */ 577 #define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< (XDMAC) Channel Interrupt Mask Register 13 */ 578 #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< (XDMAC) Channel Interrupt Status Register 13 */ 579 #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< (XDMAC) Channel Source Address Register 13 */ 580 #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< (XDMAC) Channel Destination Address Register 13 */ 581 #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< (XDMAC) Channel Next Descriptor Address Register 13 */ 582 #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< (XDMAC) Channel Next Descriptor Control Register 13 */ 583 #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< (XDMAC) Channel Microblock Control Register 13 */ 584 #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< (XDMAC) Channel Block Control Register 13 */ 585 #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< (XDMAC) Channel Configuration Register 13 */ 586 #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */ 587 #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< (XDMAC) Channel Source Microblock Stride 13 */ 588 #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< (XDMAC) Channel Destination Microblock Stride 13 */ 589 #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< (XDMAC) Channel Interrupt Enable Register 14 */ 590 #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< (XDMAC) Channel Interrupt Disable Register 14 */ 591 #define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< (XDMAC) Channel Interrupt Mask Register 14 */ 592 #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< (XDMAC) Channel Interrupt Status Register 14 */ 593 #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< (XDMAC) Channel Source Address Register 14 */ 594 #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< (XDMAC) Channel Destination Address Register 14 */ 595 #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< (XDMAC) Channel Next Descriptor Address Register 14 */ 596 #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< (XDMAC) Channel Next Descriptor Control Register 14 */ 597 #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< (XDMAC) Channel Microblock Control Register 14 */ 598 #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< (XDMAC) Channel Block Control Register 14 */ 599 #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< (XDMAC) Channel Configuration Register 14 */ 600 #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */ 601 #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< (XDMAC) Channel Source Microblock Stride 14 */ 602 #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< (XDMAC) Channel Destination Microblock Stride 14 */ 603 #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< (XDMAC) Channel Interrupt Enable Register 15 */ 604 #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< (XDMAC) Channel Interrupt Disable Register 15 */ 605 #define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< (XDMAC) Channel Interrupt Mask Register 15 */ 606 #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< (XDMAC) Channel Interrupt Status Register 15 */ 607 #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< (XDMAC) Channel Source Address Register 15 */ 608 #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< (XDMAC) Channel Destination Address Register 15 */ 609 #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< (XDMAC) Channel Next Descriptor Address Register 15 */ 610 #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< (XDMAC) Channel Next Descriptor Control Register 15 */ 611 #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< (XDMAC) Channel Microblock Control Register 15 */ 612 #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< (XDMAC) Channel Block Control Register 15 */ 613 #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< (XDMAC) Channel Configuration Register 15 */ 614 #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */ 615 #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< (XDMAC) Channel Source Microblock Stride 15 */ 616 #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< (XDMAC) Channel Destination Microblock Stride 15 */ 617 #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< (XDMAC) Channel Interrupt Enable Register 16 */ 618 #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< (XDMAC) Channel Interrupt Disable Register 16 */ 619 #define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< (XDMAC) Channel Interrupt Mask Register 16 */ 620 #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< (XDMAC) Channel Interrupt Status Register 16 */ 621 #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< (XDMAC) Channel Source Address Register 16 */ 622 #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< (XDMAC) Channel Destination Address Register 16 */ 623 #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< (XDMAC) Channel Next Descriptor Address Register 16 */ 624 #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< (XDMAC) Channel Next Descriptor Control Register 16 */ 625 #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< (XDMAC) Channel Microblock Control Register 16 */ 626 #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< (XDMAC) Channel Block Control Register 16 */ 627 #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< (XDMAC) Channel Configuration Register 16 */ 628 #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */ 629 #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< (XDMAC) Channel Source Microblock Stride 16 */ 630 #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< (XDMAC) Channel Destination Microblock Stride 16 */ 631 #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< (XDMAC) Channel Interrupt Enable Register 17 */ 632 #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< (XDMAC) Channel Interrupt Disable Register 17 */ 633 #define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< (XDMAC) Channel Interrupt Mask Register 17 */ 634 #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< (XDMAC) Channel Interrupt Status Register 17 */ 635 #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< (XDMAC) Channel Source Address Register 17 */ 636 #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< (XDMAC) Channel Destination Address Register 17 */ 637 #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< (XDMAC) Channel Next Descriptor Address Register 17 */ 638 #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< (XDMAC) Channel Next Descriptor Control Register 17 */ 639 #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< (XDMAC) Channel Microblock Control Register 17 */ 640 #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< (XDMAC) Channel Block Control Register 17 */ 641 #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< (XDMAC) Channel Configuration Register 17 */ 642 #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */ 643 #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< (XDMAC) Channel Source Microblock Stride 17 */ 644 #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< (XDMAC) Channel Destination Microblock Stride 17 */ 645 #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< (XDMAC) Channel Interrupt Enable Register 18 */ 646 #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< (XDMAC) Channel Interrupt Disable Register 18 */ 647 #define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< (XDMAC) Channel Interrupt Mask Register 18 */ 648 #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< (XDMAC) Channel Interrupt Status Register 18 */ 649 #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< (XDMAC) Channel Source Address Register 18 */ 650 #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< (XDMAC) Channel Destination Address Register 18 */ 651 #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< (XDMAC) Channel Next Descriptor Address Register 18 */ 652 #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< (XDMAC) Channel Next Descriptor Control Register 18 */ 653 #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< (XDMAC) Channel Microblock Control Register 18 */ 654 #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< (XDMAC) Channel Block Control Register 18 */ 655 #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< (XDMAC) Channel Configuration Register 18 */ 656 #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */ 657 #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< (XDMAC) Channel Source Microblock Stride 18 */ 658 #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< (XDMAC) Channel Destination Microblock Stride 18 */ 659 #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< (XDMAC) Channel Interrupt Enable Register 19 */ 660 #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< (XDMAC) Channel Interrupt Disable Register 19 */ 661 #define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< (XDMAC) Channel Interrupt Mask Register 19 */ 662 #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< (XDMAC) Channel Interrupt Status Register 19 */ 663 #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< (XDMAC) Channel Source Address Register 19 */ 664 #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< (XDMAC) Channel Destination Address Register 19 */ 665 #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< (XDMAC) Channel Next Descriptor Address Register 19 */ 666 #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< (XDMAC) Channel Next Descriptor Control Register 19 */ 667 #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< (XDMAC) Channel Microblock Control Register 19 */ 668 #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< (XDMAC) Channel Block Control Register 19 */ 669 #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< (XDMAC) Channel Configuration Register 19 */ 670 #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */ 671 #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< (XDMAC) Channel Source Microblock Stride 19 */ 672 #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< (XDMAC) Channel Destination Microblock Stride 19 */ 673 #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< (XDMAC) Channel Interrupt Enable Register 20 */ 674 #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< (XDMAC) Channel Interrupt Disable Register 20 */ 675 #define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< (XDMAC) Channel Interrupt Mask Register 20 */ 676 #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< (XDMAC) Channel Interrupt Status Register 20 */ 677 #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< (XDMAC) Channel Source Address Register 20 */ 678 #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< (XDMAC) Channel Destination Address Register 20 */ 679 #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< (XDMAC) Channel Next Descriptor Address Register 20 */ 680 #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< (XDMAC) Channel Next Descriptor Control Register 20 */ 681 #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< (XDMAC) Channel Microblock Control Register 20 */ 682 #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< (XDMAC) Channel Block Control Register 20 */ 683 #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< (XDMAC) Channel Configuration Register 20 */ 684 #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */ 685 #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< (XDMAC) Channel Source Microblock Stride 20 */ 686 #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< (XDMAC) Channel Destination Microblock Stride 20 */ 687 #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< (XDMAC) Channel Interrupt Enable Register 21 */ 688 #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< (XDMAC) Channel Interrupt Disable Register 21 */ 689 #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask Register 21 */ 690 #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< (XDMAC) Channel Interrupt Status Register 21 */ 691 #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< (XDMAC) Channel Source Address Register 21 */ 692 #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< (XDMAC) Channel Destination Address Register 21 */ 693 #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< (XDMAC) Channel Next Descriptor Address Register 21 */ 694 #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< (XDMAC) Channel Next Descriptor Control Register 21 */ 695 #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< (XDMAC) Channel Microblock Control Register 21 */ 696 #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< (XDMAC) Channel Block Control Register 21 */ 697 #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< (XDMAC) Channel Configuration Register 21 */ 698 #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */ 699 #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< (XDMAC) Channel Source Microblock Stride 21 */ 700 #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< (XDMAC) Channel Destination Microblock Stride 21 */ 701 #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< (XDMAC) Channel Interrupt Enable Register 22 */ 702 #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< (XDMAC) Channel Interrupt Disable Register 22 */ 703 #define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< (XDMAC) Channel Interrupt Mask Register 22 */ 704 #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< (XDMAC) Channel Interrupt Status Register 22 */ 705 #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< (XDMAC) Channel Source Address Register 22 */ 706 #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< (XDMAC) Channel Destination Address Register 22 */ 707 #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< (XDMAC) Channel Next Descriptor Address Register 22 */ 708 #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< (XDMAC) Channel Next Descriptor Control Register 22 */ 709 #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< (XDMAC) Channel Microblock Control Register 22 */ 710 #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< (XDMAC) Channel Block Control Register 22 */ 711 #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< (XDMAC) Channel Configuration Register 22 */ 712 #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */ 713 #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< (XDMAC) Channel Source Microblock Stride 22 */ 714 #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< (XDMAC) Channel Destination Microblock Stride 22 */ 715 #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< (XDMAC) Channel Interrupt Enable Register 23 */ 716 #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< (XDMAC) Channel Interrupt Disable Register 23 */ 717 #define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< (XDMAC) Channel Interrupt Mask Register 23 */ 718 #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< (XDMAC) Channel Interrupt Status Register 23 */ 719 #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< (XDMAC) Channel Source Address Register 23 */ 720 #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< (XDMAC) Channel Destination Address Register 23 */ 721 #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< (XDMAC) Channel Next Descriptor Address Register 23 */ 722 #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< (XDMAC) Channel Next Descriptor Control Register 23 */ 723 #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< (XDMAC) Channel Microblock Control Register 23 */ 724 #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< (XDMAC) Channel Block Control Register 23 */ 725 #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< (XDMAC) Channel Configuration Register 23 */ 726 #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */ 727 #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< (XDMAC) Channel Source Microblock Stride 23 */ 728 #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< (XDMAC) Channel Destination Microblock Stride 23 */ 729 #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< (XDMAC) Global Type Register */ 730 #define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< (XDMAC) Global Configuration Register */ 731 #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< (XDMAC) Global Weighted Arbiter Configuration Register */ 732 #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< (XDMAC) Global Interrupt Enable Register */ 733 #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< (XDMAC) Global Interrupt Disable Register */ 734 #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< (XDMAC) Global Interrupt Mask Register */ 735 #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< (XDMAC) Global Interrupt Status Register */ 736 #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< (XDMAC) Global Channel Enable Register */ 737 #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< (XDMAC) Global Channel Disable Register */ 738 #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< (XDMAC) Global Channel Status Register */ 739 #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< (XDMAC) Global Channel Read Suspend Register */ 740 #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< (XDMAC) Global Channel Write Suspend Register */ 741 #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< (XDMAC) Global Channel Read Write Suspend Register */ 742 #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< (XDMAC) Global Channel Read Write Resume Register */ 743 #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< (XDMAC) Global Channel Software Request Register */ 744 #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< (XDMAC) Global Channel Software Request Status Register */ 745 #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< (XDMAC) Global Channel Software Flush Request Register */ 746 747 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 748 749 /* ========== Instance Parameter definitions for XDMAC peripheral ========== */ 750 #define XDMAC_INSTANCE_ID 58 751 #define XDMAC_CLOCK_ID 58 752 753 #endif /* _SAMV71_XDMAC_INSTANCE_ */ 754
