1 /** 2 * \file 3 * 4 * \brief Instance description for USART1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_USART1_INSTANCE_H_ 32 #define _SAMV71_USART1_INSTANCE_H_ 33 34 /* ========== Register definition for USART1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_USART1_US_CR (0x40028000) /**< (USART1) Control Register */ 38 #define REG_USART1_US_MR (0x40028004) /**< (USART1) Mode Register */ 39 #define REG_USART1_US_IER (0x40028008) /**< (USART1) Interrupt Enable Register */ 40 #define REG_USART1_US_IDR (0x4002800C) /**< (USART1) Interrupt Disable Register */ 41 #define REG_USART1_US_IMR (0x40028010) /**< (USART1) Interrupt Mask Register */ 42 #define REG_USART1_US_CSR (0x40028014) /**< (USART1) Channel Status Register */ 43 #define REG_USART1_US_RHR (0x40028018) /**< (USART1) Receive Holding Register */ 44 #define REG_USART1_US_THR (0x4002801C) /**< (USART1) Transmit Holding Register */ 45 #define REG_USART1_US_BRGR (0x40028020) /**< (USART1) Baud Rate Generator Register */ 46 #define REG_USART1_US_RTOR (0x40028024) /**< (USART1) Receiver Timeout Register */ 47 #define REG_USART1_US_TTGR (0x40028028) /**< (USART1) Transmitter Timeguard Register */ 48 #define REG_USART1_US_FIDI (0x40028040) /**< (USART1) FI DI Ratio Register */ 49 #define REG_USART1_US_NER (0x40028044) /**< (USART1) Number of Errors Register */ 50 #define REG_USART1_US_IF (0x4002804C) /**< (USART1) IrDA Filter Register */ 51 #define REG_USART1_US_MAN (0x40028050) /**< (USART1) Manchester Configuration Register */ 52 #define REG_USART1_US_LINMR (0x40028054) /**< (USART1) LIN Mode Register */ 53 #define REG_USART1_US_LINIR (0x40028058) /**< (USART1) LIN Identifier Register */ 54 #define REG_USART1_US_LINBRR (0x4002805C) /**< (USART1) LIN Baud Rate Register */ 55 #define REG_USART1_US_LONMR (0x40028060) /**< (USART1) LON Mode Register */ 56 #define REG_USART1_US_LONPR (0x40028064) /**< (USART1) LON Preamble Register */ 57 #define REG_USART1_US_LONDL (0x40028068) /**< (USART1) LON Data Length Register */ 58 #define REG_USART1_US_LONL2HDR (0x4002806C) /**< (USART1) LON L2HDR Register */ 59 #define REG_USART1_US_LONBL (0x40028070) /**< (USART1) LON Backlog Register */ 60 #define REG_USART1_US_LONB1TX (0x40028074) /**< (USART1) LON Beta1 Tx Register */ 61 #define REG_USART1_US_LONB1RX (0x40028078) /**< (USART1) LON Beta1 Rx Register */ 62 #define REG_USART1_US_LONPRIO (0x4002807C) /**< (USART1) LON Priority Register */ 63 #define REG_USART1_US_IDTTX (0x40028080) /**< (USART1) LON IDT Tx Register */ 64 #define REG_USART1_US_IDTRX (0x40028084) /**< (USART1) LON IDT Rx Register */ 65 #define REG_USART1_US_ICDIFF (0x40028088) /**< (USART1) IC DIFF Register */ 66 #define REG_USART1_US_WPMR (0x400280E4) /**< (USART1) Write Protection Mode Register */ 67 #define REG_USART1_US_WPSR (0x400280E8) /**< (USART1) Write Protection Status Register */ 68 69 #else 70 71 #define REG_USART1_US_CR (*(__O uint32_t*)0x40028000U) /**< (USART1) Control Register */ 72 #define REG_USART1_US_MR (*(__IO uint32_t*)0x40028004U) /**< (USART1) Mode Register */ 73 #define REG_USART1_US_IER (*(__O uint32_t*)0x40028008U) /**< (USART1) Interrupt Enable Register */ 74 #define REG_USART1_US_IDR (*(__O uint32_t*)0x4002800CU) /**< (USART1) Interrupt Disable Register */ 75 #define REG_USART1_US_IMR (*(__I uint32_t*)0x40028010U) /**< (USART1) Interrupt Mask Register */ 76 #define REG_USART1_US_CSR (*(__I uint32_t*)0x40028014U) /**< (USART1) Channel Status Register */ 77 #define REG_USART1_US_RHR (*(__I uint32_t*)0x40028018U) /**< (USART1) Receive Holding Register */ 78 #define REG_USART1_US_THR (*(__O uint32_t*)0x4002801CU) /**< (USART1) Transmit Holding Register */ 79 #define REG_USART1_US_BRGR (*(__IO uint32_t*)0x40028020U) /**< (USART1) Baud Rate Generator Register */ 80 #define REG_USART1_US_RTOR (*(__IO uint32_t*)0x40028024U) /**< (USART1) Receiver Timeout Register */ 81 #define REG_USART1_US_TTGR (*(__IO uint32_t*)0x40028028U) /**< (USART1) Transmitter Timeguard Register */ 82 #define REG_USART1_US_FIDI (*(__IO uint32_t*)0x40028040U) /**< (USART1) FI DI Ratio Register */ 83 #define REG_USART1_US_NER (*(__I uint32_t*)0x40028044U) /**< (USART1) Number of Errors Register */ 84 #define REG_USART1_US_IF (*(__IO uint32_t*)0x4002804CU) /**< (USART1) IrDA Filter Register */ 85 #define REG_USART1_US_MAN (*(__IO uint32_t*)0x40028050U) /**< (USART1) Manchester Configuration Register */ 86 #define REG_USART1_US_LINMR (*(__IO uint32_t*)0x40028054U) /**< (USART1) LIN Mode Register */ 87 #define REG_USART1_US_LINIR (*(__IO uint32_t*)0x40028058U) /**< (USART1) LIN Identifier Register */ 88 #define REG_USART1_US_LINBRR (*(__I uint32_t*)0x4002805CU) /**< (USART1) LIN Baud Rate Register */ 89 #define REG_USART1_US_LONMR (*(__IO uint32_t*)0x40028060U) /**< (USART1) LON Mode Register */ 90 #define REG_USART1_US_LONPR (*(__IO uint32_t*)0x40028064U) /**< (USART1) LON Preamble Register */ 91 #define REG_USART1_US_LONDL (*(__IO uint32_t*)0x40028068U) /**< (USART1) LON Data Length Register */ 92 #define REG_USART1_US_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< (USART1) LON L2HDR Register */ 93 #define REG_USART1_US_LONBL (*(__I uint32_t*)0x40028070U) /**< (USART1) LON Backlog Register */ 94 #define REG_USART1_US_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< (USART1) LON Beta1 Tx Register */ 95 #define REG_USART1_US_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< (USART1) LON Beta1 Rx Register */ 96 #define REG_USART1_US_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< (USART1) LON Priority Register */ 97 #define REG_USART1_US_IDTTX (*(__IO uint32_t*)0x40028080U) /**< (USART1) LON IDT Tx Register */ 98 #define REG_USART1_US_IDTRX (*(__IO uint32_t*)0x40028084U) /**< (USART1) LON IDT Rx Register */ 99 #define REG_USART1_US_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< (USART1) IC DIFF Register */ 100 #define REG_USART1_US_WPMR (*(__IO uint32_t*)0x400280E4U) /**< (USART1) Write Protection Mode Register */ 101 #define REG_USART1_US_WPSR (*(__I uint32_t*)0x400280E8U) /**< (USART1) Write Protection Status Register */ 102 103 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 /* ========== Instance Parameter definitions for USART1 peripheral ========== */ 106 #define USART1_DMAC_ID_RX 10 107 #define USART1_DMAC_ID_TX 9 108 #define USART1_INSTANCE_ID 14 109 #define USART1_CLOCK_ID 14 110 #define USART1_USCLKS_MCK 0 /* MCK */ 111 #define USART1_USCLKS_DIV 1 /* MCK/8 */ 112 #define USART1_USCLKS_PCK 2 /* PCK4 */ 113 #define USART1_USCLKS_SCK 3 /* SCK */ 114 115 #endif /* _SAMV71_USART1_INSTANCE_ */ 116
