1 /** 2 * \file 3 * 4 * \brief Instance description for UART4 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_UART4_INSTANCE_H_ 32 #define _SAMV71_UART4_INSTANCE_H_ 33 34 /* ========== Register definition for UART4 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_UART4_CR (0x400E1E00) /**< (UART4) Control Register */ 38 #define REG_UART4_MR (0x400E1E04) /**< (UART4) Mode Register */ 39 #define REG_UART4_IER (0x400E1E08) /**< (UART4) Interrupt Enable Register */ 40 #define REG_UART4_IDR (0x400E1E0C) /**< (UART4) Interrupt Disable Register */ 41 #define REG_UART4_IMR (0x400E1E10) /**< (UART4) Interrupt Mask Register */ 42 #define REG_UART4_SR (0x400E1E14) /**< (UART4) Status Register */ 43 #define REG_UART4_RHR (0x400E1E18) /**< (UART4) Receive Holding Register */ 44 #define REG_UART4_THR (0x400E1E1C) /**< (UART4) Transmit Holding Register */ 45 #define REG_UART4_BRGR (0x400E1E20) /**< (UART4) Baud Rate Generator Register */ 46 #define REG_UART4_CMPR (0x400E1E24) /**< (UART4) Comparison Register */ 47 #define REG_UART4_WPMR (0x400E1EE4) /**< (UART4) Write Protection Mode Register */ 48 49 #else 50 51 #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< (UART4) Control Register */ 52 #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< (UART4) Mode Register */ 53 #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< (UART4) Interrupt Enable Register */ 54 #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< (UART4) Interrupt Disable Register */ 55 #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< (UART4) Interrupt Mask Register */ 56 #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< (UART4) Status Register */ 57 #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< (UART4) Receive Holding Register */ 58 #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< (UART4) Transmit Holding Register */ 59 #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< (UART4) Baud Rate Generator Register */ 60 #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< (UART4) Comparison Register */ 61 #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< (UART4) Write Protection Mode Register */ 62 63 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 /* ========== Instance Parameter definitions for UART4 peripheral ========== */ 66 #define UART4_DMAC_ID_RX 29 67 #define UART4_DMAC_ID_TX 28 68 #define UART4_INSTANCE_ID 46 69 #define UART4_CLOCK_ID 46 70 #define UART4_BRSRCCK_PERIPH_CLK 0 /* MCK */ 71 #define UART4_BRSRCCK_PMC_PCK 0 /* PCK4 */ 72 73 #endif /* _SAMV71_UART4_INSTANCE_ */ 74
