1 /** 2 * \file 3 * 4 * \brief Instance description for SDRAMC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_SDRAMC_INSTANCE_H_ 32 #define _SAMV71_SDRAMC_INSTANCE_H_ 33 34 /* ========== Register definition for SDRAMC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SDRAMC_MR (0x40084000) /**< (SDRAMC) SDRAMC Mode Register */ 38 #define REG_SDRAMC_TR (0x40084004) /**< (SDRAMC) SDRAMC Refresh Timer Register */ 39 #define REG_SDRAMC_CR (0x40084008) /**< (SDRAMC) SDRAMC Configuration Register */ 40 #define REG_SDRAMC_LPR (0x40084010) /**< (SDRAMC) SDRAMC Low Power Register */ 41 #define REG_SDRAMC_IER (0x40084014) /**< (SDRAMC) SDRAMC Interrupt Enable Register */ 42 #define REG_SDRAMC_IDR (0x40084018) /**< (SDRAMC) SDRAMC Interrupt Disable Register */ 43 #define REG_SDRAMC_IMR (0x4008401C) /**< (SDRAMC) SDRAMC Interrupt Mask Register */ 44 #define REG_SDRAMC_ISR (0x40084020) /**< (SDRAMC) SDRAMC Interrupt Status Register */ 45 #define REG_SDRAMC_MDR (0x40084024) /**< (SDRAMC) SDRAMC Memory Device Register */ 46 #define REG_SDRAMC_CFR1 (0x40084028) /**< (SDRAMC) SDRAMC Configuration Register 1 */ 47 #define REG_SDRAMC_OCMS (0x4008402C) /**< (SDRAMC) SDRAMC OCMS Register */ 48 #define REG_SDRAMC_OCMS_KEY1 (0x40084030) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */ 49 #define REG_SDRAMC_OCMS_KEY2 (0x40084034) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */ 50 51 #else 52 53 #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< (SDRAMC) SDRAMC Mode Register */ 54 #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< (SDRAMC) SDRAMC Refresh Timer Register */ 55 #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< (SDRAMC) SDRAMC Configuration Register */ 56 #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< (SDRAMC) SDRAMC Low Power Register */ 57 #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< (SDRAMC) SDRAMC Interrupt Enable Register */ 58 #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< (SDRAMC) SDRAMC Interrupt Disable Register */ 59 #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< (SDRAMC) SDRAMC Interrupt Mask Register */ 60 #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< (SDRAMC) SDRAMC Interrupt Status Register */ 61 #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< (SDRAMC) SDRAMC Memory Device Register */ 62 #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< (SDRAMC) SDRAMC Configuration Register 1 */ 63 #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< (SDRAMC) SDRAMC OCMS Register */ 64 #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */ 65 #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */ 66 67 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* ========== Instance Parameter definitions for SDRAMC peripheral ========== */ 70 #define SDRAMC_INSTANCE_ID 62 71 #define SDRAMC_CLOCK_ID 62 72 73 #endif /* _SAMV71_SDRAMC_INSTANCE_ */ 74
