1 /** 2 * \file 3 * 4 * \brief Instance description for RTC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_RTC_INSTANCE_H_ 32 #define _SAMV71_RTC_INSTANCE_H_ 33 34 /* ========== Register definition for RTC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_RTC_CR (0x400E1860) /**< (RTC) Control Register */ 38 #define REG_RTC_MR (0x400E1864) /**< (RTC) Mode Register */ 39 #define REG_RTC_TIMR (0x400E1868) /**< (RTC) Time Register */ 40 #define REG_RTC_CALR (0x400E186C) /**< (RTC) Calendar Register */ 41 #define REG_RTC_TIMALR (0x400E1870) /**< (RTC) Time Alarm Register */ 42 #define REG_RTC_CALALR (0x400E1874) /**< (RTC) Calendar Alarm Register */ 43 #define REG_RTC_SR (0x400E1878) /**< (RTC) Status Register */ 44 #define REG_RTC_SCCR (0x400E187C) /**< (RTC) Status Clear Command Register */ 45 #define REG_RTC_IER (0x400E1880) /**< (RTC) Interrupt Enable Register */ 46 #define REG_RTC_IDR (0x400E1884) /**< (RTC) Interrupt Disable Register */ 47 #define REG_RTC_IMR (0x400E1888) /**< (RTC) Interrupt Mask Register */ 48 #define REG_RTC_VER (0x400E188C) /**< (RTC) Valid Entry Register */ 49 #define REG_RTC_WPMR (0x400E18E4) /**< (RTC) Write Protect Mode Register */ 50 51 #else 52 53 #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< (RTC) Control Register */ 54 #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< (RTC) Mode Register */ 55 #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< (RTC) Time Register */ 56 #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< (RTC) Calendar Register */ 57 #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< (RTC) Time Alarm Register */ 58 #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< (RTC) Calendar Alarm Register */ 59 #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< (RTC) Status Register */ 60 #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< (RTC) Status Clear Command Register */ 61 #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< (RTC) Interrupt Enable Register */ 62 #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< (RTC) Interrupt Disable Register */ 63 #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< (RTC) Interrupt Mask Register */ 64 #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< (RTC) Valid Entry Register */ 65 #define REG_RTC_WPMR (*(__O uint32_t*)0x400E18E4U) /**< (RTC) Write Protect Mode Register */ 66 67 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* ========== Instance Parameter definitions for RTC peripheral ========== */ 70 #define RTC_INSTANCE_ID 2 71 72 #endif /* _SAMV71_RTC_INSTANCE_ */ 73
