1 /** 2 * \file 3 * 4 * \brief Instance description for MLB 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_MLB_INSTANCE_H_ 32 #define _SAMV71_MLB_INSTANCE_H_ 33 34 /* ========== Register definition for MLB peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_MLB_MLBC0 (0x40068000) /**< (MLB) MediaLB Control 0 Register */ 38 #define REG_MLB_MS0 (0x4006800C) /**< (MLB) MediaLB Channel Status 0 Register */ 39 #define REG_MLB_MS1 (0x40068014) /**< (MLB) MediaLB Channel Status1 Register */ 40 #define REG_MLB_MSS (0x40068020) /**< (MLB) MediaLB System Status Register */ 41 #define REG_MLB_MSD (0x40068024) /**< (MLB) MediaLB System Data Register */ 42 #define REG_MLB_MIEN (0x4006802C) /**< (MLB) MediaLB Interrupt Enable Register */ 43 #define REG_MLB_MLBC1 (0x4006803C) /**< (MLB) MediaLB Control 1 Register */ 44 #define REG_MLB_HCTL (0x40068080) /**< (MLB) HBI Control Register */ 45 #define REG_MLB_HCMR (0x40068088) /**< (MLB) HBI Channel Mask 0 Register 0 */ 46 #define REG_MLB_HCMR0 (0x40068088) /**< (MLB) HBI Channel Mask 0 Register 0 */ 47 #define REG_MLB_HCMR1 (0x4006808C) /**< (MLB) HBI Channel Mask 0 Register 1 */ 48 #define REG_MLB_HCER (0x40068090) /**< (MLB) HBI Channel Error 0 Register 0 */ 49 #define REG_MLB_HCER0 (0x40068090) /**< (MLB) HBI Channel Error 0 Register 0 */ 50 #define REG_MLB_HCER1 (0x40068094) /**< (MLB) HBI Channel Error 0 Register 1 */ 51 #define REG_MLB_HCBR (0x40068098) /**< (MLB) HBI Channel Busy 0 Register 0 */ 52 #define REG_MLB_HCBR0 (0x40068098) /**< (MLB) HBI Channel Busy 0 Register 0 */ 53 #define REG_MLB_HCBR1 (0x4006809C) /**< (MLB) HBI Channel Busy 0 Register 1 */ 54 #define REG_MLB_MDAT (0x400680C0) /**< (MLB) MIF Data 0 Register 0 */ 55 #define REG_MLB_MDAT0 (0x400680C0) /**< (MLB) MIF Data 0 Register 0 */ 56 #define REG_MLB_MDAT1 (0x400680C4) /**< (MLB) MIF Data 0 Register 1 */ 57 #define REG_MLB_MDAT2 (0x400680C8) /**< (MLB) MIF Data 0 Register 2 */ 58 #define REG_MLB_MDAT3 (0x400680CC) /**< (MLB) MIF Data 0 Register 3 */ 59 #define REG_MLB_MDWE (0x400680D0) /**< (MLB) MIF Data Write Enable 0 Register 0 */ 60 #define REG_MLB_MDWE0 (0x400680D0) /**< (MLB) MIF Data Write Enable 0 Register 0 */ 61 #define REG_MLB_MDWE1 (0x400680D4) /**< (MLB) MIF Data Write Enable 0 Register 1 */ 62 #define REG_MLB_MDWE2 (0x400680D8) /**< (MLB) MIF Data Write Enable 0 Register 2 */ 63 #define REG_MLB_MDWE3 (0x400680DC) /**< (MLB) MIF Data Write Enable 0 Register 3 */ 64 #define REG_MLB_MCTL (0x400680E0) /**< (MLB) MIF Control Register */ 65 #define REG_MLB_MADR (0x400680E4) /**< (MLB) MIF Address Register */ 66 #define REG_MLB_ACTL (0x400683C0) /**< (MLB) AHB Control Register */ 67 #define REG_MLB_ACSR (0x400683D0) /**< (MLB) AHB Channel Status 0 Register 0 */ 68 #define REG_MLB_ACSR0 (0x400683D0) /**< (MLB) AHB Channel Status 0 Register 0 */ 69 #define REG_MLB_ACSR1 (0x400683D4) /**< (MLB) AHB Channel Status 0 Register 1 */ 70 #define REG_MLB_ACMR (0x400683D8) /**< (MLB) AHB Channel Mask 0 Register 0 */ 71 #define REG_MLB_ACMR0 (0x400683D8) /**< (MLB) AHB Channel Mask 0 Register 0 */ 72 #define REG_MLB_ACMR1 (0x400683DC) /**< (MLB) AHB Channel Mask 0 Register 1 */ 73 74 #else 75 76 #define REG_MLB_MLBC0 (*(__IO uint32_t*)0x40068000U) /**< (MLB) MediaLB Control 0 Register */ 77 #define REG_MLB_MS0 (*(__IO uint32_t*)0x4006800CU) /**< (MLB) MediaLB Channel Status 0 Register */ 78 #define REG_MLB_MS1 (*(__IO uint32_t*)0x40068014U) /**< (MLB) MediaLB Channel Status1 Register */ 79 #define REG_MLB_MSS (*(__IO uint32_t*)0x40068020U) /**< (MLB) MediaLB System Status Register */ 80 #define REG_MLB_MSD (*(__I uint32_t*)0x40068024U) /**< (MLB) MediaLB System Data Register */ 81 #define REG_MLB_MIEN (*(__IO uint32_t*)0x4006802CU) /**< (MLB) MediaLB Interrupt Enable Register */ 82 #define REG_MLB_MLBC1 (*(__IO uint32_t*)0x4006803CU) /**< (MLB) MediaLB Control 1 Register */ 83 #define REG_MLB_HCTL (*(__IO uint32_t*)0x40068080U) /**< (MLB) HBI Control Register */ 84 #define REG_MLB_HCMR (*(__IO uint32_t*)0x40068088U) /**< (MLB) HBI Channel Mask 0 Register 0 */ 85 #define REG_MLB_HCMR0 (*(__IO uint32_t*)0x40068088U) /**< (MLB) HBI Channel Mask 0 Register 0 */ 86 #define REG_MLB_HCMR1 (*(__IO uint32_t*)0x4006808CU) /**< (MLB) HBI Channel Mask 0 Register 1 */ 87 #define REG_MLB_HCER (*(__I uint32_t*)0x40068090U) /**< (MLB) HBI Channel Error 0 Register 0 */ 88 #define REG_MLB_HCER0 (*(__I uint32_t*)0x40068090U) /**< (MLB) HBI Channel Error 0 Register 0 */ 89 #define REG_MLB_HCER1 (*(__I uint32_t*)0x40068094U) /**< (MLB) HBI Channel Error 0 Register 1 */ 90 #define REG_MLB_HCBR (*(__I uint32_t*)0x40068098U) /**< (MLB) HBI Channel Busy 0 Register 0 */ 91 #define REG_MLB_HCBR0 (*(__I uint32_t*)0x40068098U) /**< (MLB) HBI Channel Busy 0 Register 0 */ 92 #define REG_MLB_HCBR1 (*(__I uint32_t*)0x4006809CU) /**< (MLB) HBI Channel Busy 0 Register 1 */ 93 #define REG_MLB_MDAT (*(__IO uint32_t*)0x400680C0U) /**< (MLB) MIF Data 0 Register 0 */ 94 #define REG_MLB_MDAT0 (*(__IO uint32_t*)0x400680C0U) /**< (MLB) MIF Data 0 Register 0 */ 95 #define REG_MLB_MDAT1 (*(__IO uint32_t*)0x400680C4U) /**< (MLB) MIF Data 0 Register 1 */ 96 #define REG_MLB_MDAT2 (*(__IO uint32_t*)0x400680C8U) /**< (MLB) MIF Data 0 Register 2 */ 97 #define REG_MLB_MDAT3 (*(__IO uint32_t*)0x400680CCU) /**< (MLB) MIF Data 0 Register 3 */ 98 #define REG_MLB_MDWE (*(__IO uint32_t*)0x400680D0U) /**< (MLB) MIF Data Write Enable 0 Register 0 */ 99 #define REG_MLB_MDWE0 (*(__IO uint32_t*)0x400680D0U) /**< (MLB) MIF Data Write Enable 0 Register 0 */ 100 #define REG_MLB_MDWE1 (*(__IO uint32_t*)0x400680D4U) /**< (MLB) MIF Data Write Enable 0 Register 1 */ 101 #define REG_MLB_MDWE2 (*(__IO uint32_t*)0x400680D8U) /**< (MLB) MIF Data Write Enable 0 Register 2 */ 102 #define REG_MLB_MDWE3 (*(__IO uint32_t*)0x400680DCU) /**< (MLB) MIF Data Write Enable 0 Register 3 */ 103 #define REG_MLB_MCTL (*(__IO uint32_t*)0x400680E0U) /**< (MLB) MIF Control Register */ 104 #define REG_MLB_MADR (*(__IO uint32_t*)0x400680E4U) /**< (MLB) MIF Address Register */ 105 #define REG_MLB_ACTL (*(__IO uint32_t*)0x400683C0U) /**< (MLB) AHB Control Register */ 106 #define REG_MLB_ACSR (*(__IO uint32_t*)0x400683D0U) /**< (MLB) AHB Channel Status 0 Register 0 */ 107 #define REG_MLB_ACSR0 (*(__IO uint32_t*)0x400683D0U) /**< (MLB) AHB Channel Status 0 Register 0 */ 108 #define REG_MLB_ACSR1 (*(__IO uint32_t*)0x400683D4U) /**< (MLB) AHB Channel Status 0 Register 1 */ 109 #define REG_MLB_ACMR (*(__IO uint32_t*)0x400683D8U) /**< (MLB) AHB Channel Mask 0 Register 0 */ 110 #define REG_MLB_ACMR0 (*(__IO uint32_t*)0x400683D8U) /**< (MLB) AHB Channel Mask 0 Register 0 */ 111 #define REG_MLB_ACMR1 (*(__IO uint32_t*)0x400683DCU) /**< (MLB) AHB Channel Mask 0 Register 1 */ 112 113 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 /* ========== Instance Parameter definitions for MLB peripheral ========== */ 116 #define MLB_INSTANCE_ID 53 117 #define MLB_CLOCK_ID 53 118 119 #endif /* _SAMV71_MLB_INSTANCE_ */ 120
