1 /** 2 * \file 3 * 4 * \brief Instance description for MCAN1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_MCAN1_INSTANCE_H_ 32 #define _SAMV71_MCAN1_INSTANCE_H_ 33 34 /* ========== Register definition for MCAN1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_MCAN1_CREL (0x40034000) /**< (MCAN1) Core Release Register */ 38 #define REG_MCAN1_ENDN (0x40034004) /**< (MCAN1) Endian Register */ 39 #define REG_MCAN1_CUST (0x40034008) /**< (MCAN1) Customer Register */ 40 #define REG_MCAN1_DBTP (0x4003400C) /**< (MCAN1) Data Bit Timing and Prescaler Register */ 41 #define REG_MCAN1_TEST (0x40034010) /**< (MCAN1) Test Register */ 42 #define REG_MCAN1_RWD (0x40034014) /**< (MCAN1) RAM Watchdog Register */ 43 #define REG_MCAN1_CCCR (0x40034018) /**< (MCAN1) CC Control Register */ 44 #define REG_MCAN1_NBTP (0x4003401C) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */ 45 #define REG_MCAN1_TSCC (0x40034020) /**< (MCAN1) Timestamp Counter Configuration Register */ 46 #define REG_MCAN1_TSCV (0x40034024) /**< (MCAN1) Timestamp Counter Value Register */ 47 #define REG_MCAN1_TOCC (0x40034028) /**< (MCAN1) Timeout Counter Configuration Register */ 48 #define REG_MCAN1_TOCV (0x4003402C) /**< (MCAN1) Timeout Counter Value Register */ 49 #define REG_MCAN1_ECR (0x40034040) /**< (MCAN1) Error Counter Register */ 50 #define REG_MCAN1_PSR (0x40034044) /**< (MCAN1) Protocol Status Register */ 51 #define REG_MCAN1_TDCR (0x40034048) /**< (MCAN1) Transmit Delay Compensation Register */ 52 #define REG_MCAN1_IR (0x40034050) /**< (MCAN1) Interrupt Register */ 53 #define REG_MCAN1_IE (0x40034054) /**< (MCAN1) Interrupt Enable Register */ 54 #define REG_MCAN1_ILS (0x40034058) /**< (MCAN1) Interrupt Line Select Register */ 55 #define REG_MCAN1_ILE (0x4003405C) /**< (MCAN1) Interrupt Line Enable Register */ 56 #define REG_MCAN1_GFC (0x40034080) /**< (MCAN1) Global Filter Configuration Register */ 57 #define REG_MCAN1_SIDFC (0x40034084) /**< (MCAN1) Standard ID Filter Configuration Register */ 58 #define REG_MCAN1_XIDFC (0x40034088) /**< (MCAN1) Extended ID Filter Configuration Register */ 59 #define REG_MCAN1_XIDAM (0x40034090) /**< (MCAN1) Extended ID AND Mask Register */ 60 #define REG_MCAN1_HPMS (0x40034094) /**< (MCAN1) High Priority Message Status Register */ 61 #define REG_MCAN1_NDAT1 (0x40034098) /**< (MCAN1) New Data 1 Register */ 62 #define REG_MCAN1_NDAT2 (0x4003409C) /**< (MCAN1) New Data 2 Register */ 63 #define REG_MCAN1_RXF0C (0x400340A0) /**< (MCAN1) Receive FIFO 0 Configuration Register */ 64 #define REG_MCAN1_RXF0S (0x400340A4) /**< (MCAN1) Receive FIFO 0 Status Register */ 65 #define REG_MCAN1_RXF0A (0x400340A8) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */ 66 #define REG_MCAN1_RXBC (0x400340AC) /**< (MCAN1) Receive Rx Buffer Configuration Register */ 67 #define REG_MCAN1_RXF1C (0x400340B0) /**< (MCAN1) Receive FIFO 1 Configuration Register */ 68 #define REG_MCAN1_RXF1S (0x400340B4) /**< (MCAN1) Receive FIFO 1 Status Register */ 69 #define REG_MCAN1_RXF1A (0x400340B8) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */ 70 #define REG_MCAN1_RXESC (0x400340BC) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 71 #define REG_MCAN1_TXBC (0x400340C0) /**< (MCAN1) Transmit Buffer Configuration Register */ 72 #define REG_MCAN1_TXFQS (0x400340C4) /**< (MCAN1) Transmit FIFO/Queue Status Register */ 73 #define REG_MCAN1_TXESC (0x400340C8) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */ 74 #define REG_MCAN1_TXBRP (0x400340CC) /**< (MCAN1) Transmit Buffer Request Pending Register */ 75 #define REG_MCAN1_TXBAR (0x400340D0) /**< (MCAN1) Transmit Buffer Add Request Register */ 76 #define REG_MCAN1_TXBCR (0x400340D4) /**< (MCAN1) Transmit Buffer Cancellation Request Register */ 77 #define REG_MCAN1_TXBTO (0x400340D8) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */ 78 #define REG_MCAN1_TXBCF (0x400340DC) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */ 79 #define REG_MCAN1_TXBTIE (0x400340E0) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 80 #define REG_MCAN1_TXBCIE (0x400340E4) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 81 #define REG_MCAN1_TXEFC (0x400340F0) /**< (MCAN1) Transmit Event FIFO Configuration Register */ 82 #define REG_MCAN1_TXEFS (0x400340F4) /**< (MCAN1) Transmit Event FIFO Status Register */ 83 #define REG_MCAN1_TXEFA (0x400340F8) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */ 84 85 #else 86 87 #define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< (MCAN1) Core Release Register */ 88 #define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< (MCAN1) Endian Register */ 89 #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< (MCAN1) Customer Register */ 90 #define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< (MCAN1) Data Bit Timing and Prescaler Register */ 91 #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< (MCAN1) Test Register */ 92 #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< (MCAN1) RAM Watchdog Register */ 93 #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< (MCAN1) CC Control Register */ 94 #define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */ 95 #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< (MCAN1) Timestamp Counter Configuration Register */ 96 #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< (MCAN1) Timestamp Counter Value Register */ 97 #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< (MCAN1) Timeout Counter Configuration Register */ 98 #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< (MCAN1) Timeout Counter Value Register */ 99 #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< (MCAN1) Error Counter Register */ 100 #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< (MCAN1) Protocol Status Register */ 101 #define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< (MCAN1) Transmit Delay Compensation Register */ 102 #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< (MCAN1) Interrupt Register */ 103 #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< (MCAN1) Interrupt Enable Register */ 104 #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< (MCAN1) Interrupt Line Select Register */ 105 #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< (MCAN1) Interrupt Line Enable Register */ 106 #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< (MCAN1) Global Filter Configuration Register */ 107 #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< (MCAN1) Standard ID Filter Configuration Register */ 108 #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< (MCAN1) Extended ID Filter Configuration Register */ 109 #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< (MCAN1) Extended ID AND Mask Register */ 110 #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< (MCAN1) High Priority Message Status Register */ 111 #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< (MCAN1) New Data 1 Register */ 112 #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< (MCAN1) New Data 2 Register */ 113 #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< (MCAN1) Receive FIFO 0 Configuration Register */ 114 #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< (MCAN1) Receive FIFO 0 Status Register */ 115 #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */ 116 #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< (MCAN1) Receive Rx Buffer Configuration Register */ 117 #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< (MCAN1) Receive FIFO 1 Configuration Register */ 118 #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< (MCAN1) Receive FIFO 1 Status Register */ 119 #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */ 120 #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 121 #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< (MCAN1) Transmit Buffer Configuration Register */ 122 #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< (MCAN1) Transmit FIFO/Queue Status Register */ 123 #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */ 124 #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< (MCAN1) Transmit Buffer Request Pending Register */ 125 #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< (MCAN1) Transmit Buffer Add Request Register */ 126 #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< (MCAN1) Transmit Buffer Cancellation Request Register */ 127 #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */ 128 #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */ 129 #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 130 #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 131 #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< (MCAN1) Transmit Event FIFO Configuration Register */ 132 #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< (MCAN1) Transmit Event FIFO Status Register */ 133 #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */ 134 135 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* ========== Instance Parameter definitions for MCAN1 peripheral ========== */ 138 #define MCAN1_INSTANCE_ID 37 139 #define MCAN1_CLOCK_ID 37 140 141 #endif /* _SAMV71_MCAN1_INSTANCE_ */ 142
