1 /** 2 * \file 3 * 4 * \brief Instance description for ISI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_ISI_INSTANCE_H_ 32 #define _SAMV71_ISI_INSTANCE_H_ 33 34 /* ========== Register definition for ISI peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_ISI_CFG1 (0x4004C000) /**< (ISI) ISI Configuration 1 Register */ 38 #define REG_ISI_CFG2 (0x4004C004) /**< (ISI) ISI Configuration 2 Register */ 39 #define REG_ISI_PSIZE (0x4004C008) /**< (ISI) ISI Preview Size Register */ 40 #define REG_ISI_PDECF (0x4004C00C) /**< (ISI) ISI Preview Decimation Factor Register */ 41 #define REG_ISI_Y2R_SET0 (0x4004C010) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 42 #define REG_ISI_Y2R_SET1 (0x4004C014) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 43 #define REG_ISI_R2Y_SET0 (0x4004C018) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 44 #define REG_ISI_R2Y_SET1 (0x4004C01C) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 45 #define REG_ISI_R2Y_SET2 (0x4004C020) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 46 #define REG_ISI_CR (0x4004C024) /**< (ISI) ISI Control Register */ 47 #define REG_ISI_SR (0x4004C028) /**< (ISI) ISI Status Register */ 48 #define REG_ISI_IER (0x4004C02C) /**< (ISI) ISI Interrupt Enable Register */ 49 #define REG_ISI_IDR (0x4004C030) /**< (ISI) ISI Interrupt Disable Register */ 50 #define REG_ISI_IMR (0x4004C034) /**< (ISI) ISI Interrupt Mask Register */ 51 #define REG_ISI_DMA_CHER (0x4004C038) /**< (ISI) DMA Channel Enable Register */ 52 #define REG_ISI_DMA_CHDR (0x4004C03C) /**< (ISI) DMA Channel Disable Register */ 53 #define REG_ISI_DMA_CHSR (0x4004C040) /**< (ISI) DMA Channel Status Register */ 54 #define REG_ISI_DMA_P_ADDR (0x4004C044) /**< (ISI) DMA Preview Base Address Register */ 55 #define REG_ISI_DMA_P_CTRL (0x4004C048) /**< (ISI) DMA Preview Control Register */ 56 #define REG_ISI_DMA_P_DSCR (0x4004C04C) /**< (ISI) DMA Preview Descriptor Address Register */ 57 #define REG_ISI_DMA_C_ADDR (0x4004C050) /**< (ISI) DMA Codec Base Address Register */ 58 #define REG_ISI_DMA_C_CTRL (0x4004C054) /**< (ISI) DMA Codec Control Register */ 59 #define REG_ISI_DMA_C_DSCR (0x4004C058) /**< (ISI) DMA Codec Descriptor Address Register */ 60 #define REG_ISI_WPMR (0x4004C0E4) /**< (ISI) Write Protection Mode Register */ 61 #define REG_ISI_WPSR (0x4004C0E8) /**< (ISI) Write Protection Status Register */ 62 63 #else 64 65 #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< (ISI) ISI Configuration 1 Register */ 66 #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< (ISI) ISI Configuration 2 Register */ 67 #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< (ISI) ISI Preview Size Register */ 68 #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< (ISI) ISI Preview Decimation Factor Register */ 69 #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 70 #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 71 #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 72 #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 73 #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 74 #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< (ISI) ISI Control Register */ 75 #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< (ISI) ISI Status Register */ 76 #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< (ISI) ISI Interrupt Enable Register */ 77 #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< (ISI) ISI Interrupt Disable Register */ 78 #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< (ISI) ISI Interrupt Mask Register */ 79 #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< (ISI) DMA Channel Enable Register */ 80 #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< (ISI) DMA Channel Disable Register */ 81 #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< (ISI) DMA Channel Status Register */ 82 #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< (ISI) DMA Preview Base Address Register */ 83 #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< (ISI) DMA Preview Control Register */ 84 #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< (ISI) DMA Preview Descriptor Address Register */ 85 #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< (ISI) DMA Codec Base Address Register */ 86 #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< (ISI) DMA Codec Control Register */ 87 #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< (ISI) DMA Codec Descriptor Address Register */ 88 #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< (ISI) Write Protection Mode Register */ 89 #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< (ISI) Write Protection Status Register */ 90 91 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 93 /* ========== Instance Parameter definitions for ISI peripheral ========== */ 94 #define ISI_INSTANCE_ID 59 95 #define ISI_CLOCK_ID 59 96 97 #endif /* _SAMV71_ISI_INSTANCE_ */ 98
