1 /** 2 * \file 3 * 4 * \brief Instance description for I2SC0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_I2SC0_INSTANCE_H_ 32 #define _SAMV71_I2SC0_INSTANCE_H_ 33 34 /* ========== Register definition for I2SC0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_I2SC0_CR (0x4008C000) /**< (I2SC0) Control Register */ 38 #define REG_I2SC0_MR (0x4008C004) /**< (I2SC0) Mode Register */ 39 #define REG_I2SC0_SR (0x4008C008) /**< (I2SC0) Status Register */ 40 #define REG_I2SC0_SCR (0x4008C00C) /**< (I2SC0) Status Clear Register */ 41 #define REG_I2SC0_SSR (0x4008C010) /**< (I2SC0) Status Set Register */ 42 #define REG_I2SC0_IER (0x4008C014) /**< (I2SC0) Interrupt Enable Register */ 43 #define REG_I2SC0_IDR (0x4008C018) /**< (I2SC0) Interrupt Disable Register */ 44 #define REG_I2SC0_IMR (0x4008C01C) /**< (I2SC0) Interrupt Mask Register */ 45 #define REG_I2SC0_RHR (0x4008C020) /**< (I2SC0) Receiver Holding Register */ 46 #define REG_I2SC0_THR (0x4008C024) /**< (I2SC0) Transmitter Holding Register */ 47 48 #else 49 50 #define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */ 51 #define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< (I2SC0) Mode Register */ 52 #define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< (I2SC0) Status Register */ 53 #define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */ 54 #define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */ 55 #define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Register */ 56 #define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Register */ 57 #define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< (I2SC0) Interrupt Mask Register */ 58 #define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< (I2SC0) Receiver Holding Register */ 59 #define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Register */ 60 61 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* ========== Instance Parameter definitions for I2SC0 peripheral ========== */ 64 #define I2SC0_INSTANCE_ID 69 65 #define I2SC0_CLOCK_ID 69 66 #define I2SC0_DMAC_ID_TX_LEFT 44 67 #define I2SC0_DMAC_ID_RX_LEFT 45 68 #define I2SC0_DMAC_ID_TX_RIGHT 48 69 #define I2SC0_DMAC_ID_RX_RIGHT 49 70 71 #endif /* _SAMV71_I2SC0_INSTANCE_ */ 72
