1 /** 2 * \file 3 * 4 * \brief Component description for XDMAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_XDMAC_COMPONENT_H_ 32 #define _SAMV71_XDMAC_COMPONENT_H_ 33 #define _SAMV71_XDMAC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Extensible DMA Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR XDMAC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define XDMAC_11161 /**< (XDMAC) Module ID */ 46 #define REV_XDMAC K /**< (XDMAC) Module revision */ 47 48 /* -------- XDMAC_CIE : (XDMAC Offset: 0x00) (/W 32) Channel Interrupt Enable Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t BIE:1; /**< bit: 0 End of Block Interrupt Enable Bit */ 54 uint32_t LIE:1; /**< bit: 1 End of Linked List Interrupt Enable Bit */ 55 uint32_t DIE:1; /**< bit: 2 End of Disable Interrupt Enable Bit */ 56 uint32_t FIE:1; /**< bit: 3 End of Flush Interrupt Enable Bit */ 57 uint32_t RBIE:1; /**< bit: 4 Read Bus Error Interrupt Enable Bit */ 58 uint32_t WBIE:1; /**< bit: 5 Write Bus Error Interrupt Enable Bit */ 59 uint32_t ROIE:1; /**< bit: 6 Request Overflow Error Interrupt Enable Bit */ 60 uint32_t :25; /**< bit: 7..31 Reserved */ 61 } bit; /**< Structure used for bit access */ 62 uint32_t reg; /**< Type used for register access */ 63 } XDMAC_CIE_Type; 64 #endif 65 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define XDMAC_CIE_OFFSET (0x00) /**< (XDMAC_CIE) Channel Interrupt Enable Register Offset */ 68 69 #define XDMAC_CIE_BIE_Pos 0 /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Position */ 70 #define XDMAC_CIE_BIE_Msk (_U_(0x1) << XDMAC_CIE_BIE_Pos) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Mask */ 71 #define XDMAC_CIE_BIE XDMAC_CIE_BIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_BIE_Msk instead */ 72 #define XDMAC_CIE_LIE_Pos 1 /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Position */ 73 #define XDMAC_CIE_LIE_Msk (_U_(0x1) << XDMAC_CIE_LIE_Pos) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Mask */ 74 #define XDMAC_CIE_LIE XDMAC_CIE_LIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_LIE_Msk instead */ 75 #define XDMAC_CIE_DIE_Pos 2 /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Position */ 76 #define XDMAC_CIE_DIE_Msk (_U_(0x1) << XDMAC_CIE_DIE_Pos) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Mask */ 77 #define XDMAC_CIE_DIE XDMAC_CIE_DIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_DIE_Msk instead */ 78 #define XDMAC_CIE_FIE_Pos 3 /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Position */ 79 #define XDMAC_CIE_FIE_Msk (_U_(0x1) << XDMAC_CIE_FIE_Pos) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Mask */ 80 #define XDMAC_CIE_FIE XDMAC_CIE_FIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_FIE_Msk instead */ 81 #define XDMAC_CIE_RBIE_Pos 4 /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Position */ 82 #define XDMAC_CIE_RBIE_Msk (_U_(0x1) << XDMAC_CIE_RBIE_Pos) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Mask */ 83 #define XDMAC_CIE_RBIE XDMAC_CIE_RBIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_RBIE_Msk instead */ 84 #define XDMAC_CIE_WBIE_Pos 5 /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Position */ 85 #define XDMAC_CIE_WBIE_Msk (_U_(0x1) << XDMAC_CIE_WBIE_Pos) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Mask */ 86 #define XDMAC_CIE_WBIE XDMAC_CIE_WBIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_WBIE_Msk instead */ 87 #define XDMAC_CIE_ROIE_Pos 6 /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Position */ 88 #define XDMAC_CIE_ROIE_Msk (_U_(0x1) << XDMAC_CIE_ROIE_Pos) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Mask */ 89 #define XDMAC_CIE_ROIE XDMAC_CIE_ROIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_ROIE_Msk instead */ 90 #define XDMAC_CIE_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIE) Register MASK (Use XDMAC_CIE_Msk instead) */ 91 #define XDMAC_CIE_Msk _U_(0x7F) /**< (XDMAC_CIE) Register Mask */ 92 93 94 /* -------- XDMAC_CID : (XDMAC Offset: 0x04) (/W 32) Channel Interrupt Disable Register -------- */ 95 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 96 #if COMPONENT_TYPEDEF_STYLE == 'N' 97 typedef union { 98 struct { 99 uint32_t BID:1; /**< bit: 0 End of Block Interrupt Disable Bit */ 100 uint32_t LID:1; /**< bit: 1 End of Linked List Interrupt Disable Bit */ 101 uint32_t DID:1; /**< bit: 2 End of Disable Interrupt Disable Bit */ 102 uint32_t FID:1; /**< bit: 3 End of Flush Interrupt Disable Bit */ 103 uint32_t RBEID:1; /**< bit: 4 Read Bus Error Interrupt Disable Bit */ 104 uint32_t WBEID:1; /**< bit: 5 Write Bus Error Interrupt Disable Bit */ 105 uint32_t ROID:1; /**< bit: 6 Request Overflow Error Interrupt Disable Bit */ 106 uint32_t :25; /**< bit: 7..31 Reserved */ 107 } bit; /**< Structure used for bit access */ 108 uint32_t reg; /**< Type used for register access */ 109 } XDMAC_CID_Type; 110 #endif 111 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 #define XDMAC_CID_OFFSET (0x04) /**< (XDMAC_CID) Channel Interrupt Disable Register Offset */ 114 115 #define XDMAC_CID_BID_Pos 0 /**< (XDMAC_CID) End of Block Interrupt Disable Bit Position */ 116 #define XDMAC_CID_BID_Msk (_U_(0x1) << XDMAC_CID_BID_Pos) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Mask */ 117 #define XDMAC_CID_BID XDMAC_CID_BID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_BID_Msk instead */ 118 #define XDMAC_CID_LID_Pos 1 /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Position */ 119 #define XDMAC_CID_LID_Msk (_U_(0x1) << XDMAC_CID_LID_Pos) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Mask */ 120 #define XDMAC_CID_LID XDMAC_CID_LID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_LID_Msk instead */ 121 #define XDMAC_CID_DID_Pos 2 /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Position */ 122 #define XDMAC_CID_DID_Msk (_U_(0x1) << XDMAC_CID_DID_Pos) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Mask */ 123 #define XDMAC_CID_DID XDMAC_CID_DID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_DID_Msk instead */ 124 #define XDMAC_CID_FID_Pos 3 /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Position */ 125 #define XDMAC_CID_FID_Msk (_U_(0x1) << XDMAC_CID_FID_Pos) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Mask */ 126 #define XDMAC_CID_FID XDMAC_CID_FID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_FID_Msk instead */ 127 #define XDMAC_CID_RBEID_Pos 4 /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Position */ 128 #define XDMAC_CID_RBEID_Msk (_U_(0x1) << XDMAC_CID_RBEID_Pos) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Mask */ 129 #define XDMAC_CID_RBEID XDMAC_CID_RBEID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_RBEID_Msk instead */ 130 #define XDMAC_CID_WBEID_Pos 5 /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Position */ 131 #define XDMAC_CID_WBEID_Msk (_U_(0x1) << XDMAC_CID_WBEID_Pos) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Mask */ 132 #define XDMAC_CID_WBEID XDMAC_CID_WBEID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_WBEID_Msk instead */ 133 #define XDMAC_CID_ROID_Pos 6 /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Position */ 134 #define XDMAC_CID_ROID_Msk (_U_(0x1) << XDMAC_CID_ROID_Pos) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Mask */ 135 #define XDMAC_CID_ROID XDMAC_CID_ROID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_ROID_Msk instead */ 136 #define XDMAC_CID_MASK _U_(0x7F) /**< \deprecated (XDMAC_CID) Register MASK (Use XDMAC_CID_Msk instead) */ 137 #define XDMAC_CID_Msk _U_(0x7F) /**< (XDMAC_CID) Register Mask */ 138 139 140 /* -------- XDMAC_CIM : (XDMAC Offset: 0x08) (R/ 32) Channel Interrupt Mask Register -------- */ 141 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 142 #if COMPONENT_TYPEDEF_STYLE == 'N' 143 typedef union { 144 struct { 145 uint32_t BIM:1; /**< bit: 0 End of Block Interrupt Mask Bit */ 146 uint32_t LIM:1; /**< bit: 1 End of Linked List Interrupt Mask Bit */ 147 uint32_t DIM:1; /**< bit: 2 End of Disable Interrupt Mask Bit */ 148 uint32_t FIM:1; /**< bit: 3 End of Flush Interrupt Mask Bit */ 149 uint32_t RBEIM:1; /**< bit: 4 Read Bus Error Interrupt Mask Bit */ 150 uint32_t WBEIM:1; /**< bit: 5 Write Bus Error Interrupt Mask Bit */ 151 uint32_t ROIM:1; /**< bit: 6 Request Overflow Error Interrupt Mask Bit */ 152 uint32_t :25; /**< bit: 7..31 Reserved */ 153 } bit; /**< Structure used for bit access */ 154 uint32_t reg; /**< Type used for register access */ 155 } XDMAC_CIM_Type; 156 #endif 157 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define XDMAC_CIM_OFFSET (0x08) /**< (XDMAC_CIM) Channel Interrupt Mask Register Offset */ 160 161 #define XDMAC_CIM_BIM_Pos 0 /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Position */ 162 #define XDMAC_CIM_BIM_Msk (_U_(0x1) << XDMAC_CIM_BIM_Pos) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Mask */ 163 #define XDMAC_CIM_BIM XDMAC_CIM_BIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_BIM_Msk instead */ 164 #define XDMAC_CIM_LIM_Pos 1 /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Position */ 165 #define XDMAC_CIM_LIM_Msk (_U_(0x1) << XDMAC_CIM_LIM_Pos) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Mask */ 166 #define XDMAC_CIM_LIM XDMAC_CIM_LIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_LIM_Msk instead */ 167 #define XDMAC_CIM_DIM_Pos 2 /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Position */ 168 #define XDMAC_CIM_DIM_Msk (_U_(0x1) << XDMAC_CIM_DIM_Pos) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Mask */ 169 #define XDMAC_CIM_DIM XDMAC_CIM_DIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_DIM_Msk instead */ 170 #define XDMAC_CIM_FIM_Pos 3 /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Position */ 171 #define XDMAC_CIM_FIM_Msk (_U_(0x1) << XDMAC_CIM_FIM_Pos) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Mask */ 172 #define XDMAC_CIM_FIM XDMAC_CIM_FIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_FIM_Msk instead */ 173 #define XDMAC_CIM_RBEIM_Pos 4 /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Position */ 174 #define XDMAC_CIM_RBEIM_Msk (_U_(0x1) << XDMAC_CIM_RBEIM_Pos) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Mask */ 175 #define XDMAC_CIM_RBEIM XDMAC_CIM_RBEIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_RBEIM_Msk instead */ 176 #define XDMAC_CIM_WBEIM_Pos 5 /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Position */ 177 #define XDMAC_CIM_WBEIM_Msk (_U_(0x1) << XDMAC_CIM_WBEIM_Pos) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Mask */ 178 #define XDMAC_CIM_WBEIM XDMAC_CIM_WBEIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_WBEIM_Msk instead */ 179 #define XDMAC_CIM_ROIM_Pos 6 /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Position */ 180 #define XDMAC_CIM_ROIM_Msk (_U_(0x1) << XDMAC_CIM_ROIM_Pos) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Mask */ 181 #define XDMAC_CIM_ROIM XDMAC_CIM_ROIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_ROIM_Msk instead */ 182 #define XDMAC_CIM_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIM) Register MASK (Use XDMAC_CIM_Msk instead) */ 183 #define XDMAC_CIM_Msk _U_(0x7F) /**< (XDMAC_CIM) Register Mask */ 184 185 186 /* -------- XDMAC_CIS : (XDMAC Offset: 0x0c) (R/ 32) Channel Interrupt Status Register -------- */ 187 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 188 #if COMPONENT_TYPEDEF_STYLE == 'N' 189 typedef union { 190 struct { 191 uint32_t BIS:1; /**< bit: 0 End of Block Interrupt Status Bit */ 192 uint32_t LIS:1; /**< bit: 1 End of Linked List Interrupt Status Bit */ 193 uint32_t DIS:1; /**< bit: 2 End of Disable Interrupt Status Bit */ 194 uint32_t FIS:1; /**< bit: 3 End of Flush Interrupt Status Bit */ 195 uint32_t RBEIS:1; /**< bit: 4 Read Bus Error Interrupt Status Bit */ 196 uint32_t WBEIS:1; /**< bit: 5 Write Bus Error Interrupt Status Bit */ 197 uint32_t ROIS:1; /**< bit: 6 Request Overflow Error Interrupt Status Bit */ 198 uint32_t :25; /**< bit: 7..31 Reserved */ 199 } bit; /**< Structure used for bit access */ 200 uint32_t reg; /**< Type used for register access */ 201 } XDMAC_CIS_Type; 202 #endif 203 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define XDMAC_CIS_OFFSET (0x0C) /**< (XDMAC_CIS) Channel Interrupt Status Register Offset */ 206 207 #define XDMAC_CIS_BIS_Pos 0 /**< (XDMAC_CIS) End of Block Interrupt Status Bit Position */ 208 #define XDMAC_CIS_BIS_Msk (_U_(0x1) << XDMAC_CIS_BIS_Pos) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Mask */ 209 #define XDMAC_CIS_BIS XDMAC_CIS_BIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_BIS_Msk instead */ 210 #define XDMAC_CIS_LIS_Pos 1 /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Position */ 211 #define XDMAC_CIS_LIS_Msk (_U_(0x1) << XDMAC_CIS_LIS_Pos) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Mask */ 212 #define XDMAC_CIS_LIS XDMAC_CIS_LIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_LIS_Msk instead */ 213 #define XDMAC_CIS_DIS_Pos 2 /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Position */ 214 #define XDMAC_CIS_DIS_Msk (_U_(0x1) << XDMAC_CIS_DIS_Pos) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Mask */ 215 #define XDMAC_CIS_DIS XDMAC_CIS_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_DIS_Msk instead */ 216 #define XDMAC_CIS_FIS_Pos 3 /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Position */ 217 #define XDMAC_CIS_FIS_Msk (_U_(0x1) << XDMAC_CIS_FIS_Pos) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Mask */ 218 #define XDMAC_CIS_FIS XDMAC_CIS_FIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_FIS_Msk instead */ 219 #define XDMAC_CIS_RBEIS_Pos 4 /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Position */ 220 #define XDMAC_CIS_RBEIS_Msk (_U_(0x1) << XDMAC_CIS_RBEIS_Pos) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Mask */ 221 #define XDMAC_CIS_RBEIS XDMAC_CIS_RBEIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_RBEIS_Msk instead */ 222 #define XDMAC_CIS_WBEIS_Pos 5 /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Position */ 223 #define XDMAC_CIS_WBEIS_Msk (_U_(0x1) << XDMAC_CIS_WBEIS_Pos) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Mask */ 224 #define XDMAC_CIS_WBEIS XDMAC_CIS_WBEIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_WBEIS_Msk instead */ 225 #define XDMAC_CIS_ROIS_Pos 6 /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Position */ 226 #define XDMAC_CIS_ROIS_Msk (_U_(0x1) << XDMAC_CIS_ROIS_Pos) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Mask */ 227 #define XDMAC_CIS_ROIS XDMAC_CIS_ROIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_ROIS_Msk instead */ 228 #define XDMAC_CIS_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIS) Register MASK (Use XDMAC_CIS_Msk instead) */ 229 #define XDMAC_CIS_Msk _U_(0x7F) /**< (XDMAC_CIS) Register Mask */ 230 231 232 /* -------- XDMAC_CSA : (XDMAC Offset: 0x10) (R/W 32) Channel Source Address Register -------- */ 233 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 234 #if COMPONENT_TYPEDEF_STYLE == 'N' 235 typedef union { 236 struct { 237 uint32_t SA:32; /**< bit: 0..31 Channel x Source Address */ 238 } bit; /**< Structure used for bit access */ 239 uint32_t reg; /**< Type used for register access */ 240 } XDMAC_CSA_Type; 241 #endif 242 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define XDMAC_CSA_OFFSET (0x10) /**< (XDMAC_CSA) Channel Source Address Register Offset */ 245 246 #define XDMAC_CSA_SA_Pos 0 /**< (XDMAC_CSA) Channel x Source Address Position */ 247 #define XDMAC_CSA_SA_Msk (_U_(0xFFFFFFFF) << XDMAC_CSA_SA_Pos) /**< (XDMAC_CSA) Channel x Source Address Mask */ 248 #define XDMAC_CSA_SA(value) (XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)) 249 #define XDMAC_CSA_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CSA) Register MASK (Use XDMAC_CSA_Msk instead) */ 250 #define XDMAC_CSA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CSA) Register Mask */ 251 252 253 /* -------- XDMAC_CDA : (XDMAC Offset: 0x14) (R/W 32) Channel Destination Address Register -------- */ 254 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 255 #if COMPONENT_TYPEDEF_STYLE == 'N' 256 typedef union { 257 struct { 258 uint32_t DA:32; /**< bit: 0..31 Channel x Destination Address */ 259 } bit; /**< Structure used for bit access */ 260 uint32_t reg; /**< Type used for register access */ 261 } XDMAC_CDA_Type; 262 #endif 263 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 264 265 #define XDMAC_CDA_OFFSET (0x14) /**< (XDMAC_CDA) Channel Destination Address Register Offset */ 266 267 #define XDMAC_CDA_DA_Pos 0 /**< (XDMAC_CDA) Channel x Destination Address Position */ 268 #define XDMAC_CDA_DA_Msk (_U_(0xFFFFFFFF) << XDMAC_CDA_DA_Pos) /**< (XDMAC_CDA) Channel x Destination Address Mask */ 269 #define XDMAC_CDA_DA(value) (XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)) 270 #define XDMAC_CDA_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CDA) Register MASK (Use XDMAC_CDA_Msk instead) */ 271 #define XDMAC_CDA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDA) Register Mask */ 272 273 274 /* -------- XDMAC_CNDA : (XDMAC Offset: 0x18) (R/W 32) Channel Next Descriptor Address Register -------- */ 275 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 276 #if COMPONENT_TYPEDEF_STYLE == 'N' 277 typedef union { 278 struct { 279 uint32_t NDAIF:1; /**< bit: 0 Channel x Next Descriptor Interface */ 280 uint32_t :1; /**< bit: 1 Reserved */ 281 uint32_t NDA:30; /**< bit: 2..31 Channel x Next Descriptor Address */ 282 } bit; /**< Structure used for bit access */ 283 uint32_t reg; /**< Type used for register access */ 284 } XDMAC_CNDA_Type; 285 #endif 286 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 287 288 #define XDMAC_CNDA_OFFSET (0x18) /**< (XDMAC_CNDA) Channel Next Descriptor Address Register Offset */ 289 290 #define XDMAC_CNDA_NDAIF_Pos 0 /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Position */ 291 #define XDMAC_CNDA_NDAIF_Msk (_U_(0x1) << XDMAC_CNDA_NDAIF_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Mask */ 292 #define XDMAC_CNDA_NDAIF XDMAC_CNDA_NDAIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDA_NDAIF_Msk instead */ 293 #define XDMAC_CNDA_NDA_Pos 2 /**< (XDMAC_CNDA) Channel x Next Descriptor Address Position */ 294 #define XDMAC_CNDA_NDA_Msk (_U_(0x3FFFFFFF) << XDMAC_CNDA_NDA_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Mask */ 295 #define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)) 296 #define XDMAC_CNDA_MASK _U_(0xFFFFFFFD) /**< \deprecated (XDMAC_CNDA) Register MASK (Use XDMAC_CNDA_Msk instead) */ 297 #define XDMAC_CNDA_Msk _U_(0xFFFFFFFD) /**< (XDMAC_CNDA) Register Mask */ 298 299 300 /* -------- XDMAC_CNDC : (XDMAC Offset: 0x1c) (R/W 32) Channel Next Descriptor Control Register -------- */ 301 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 302 #if COMPONENT_TYPEDEF_STYLE == 'N' 303 typedef union { 304 struct { 305 uint32_t NDE:1; /**< bit: 0 Channel x Next Descriptor Enable */ 306 uint32_t NDSUP:1; /**< bit: 1 Channel x Next Descriptor Source Update */ 307 uint32_t NDDUP:1; /**< bit: 2 Channel x Next Descriptor Destination Update */ 308 uint32_t NDVIEW:2; /**< bit: 3..4 Channel x Next Descriptor View */ 309 uint32_t :27; /**< bit: 5..31 Reserved */ 310 } bit; /**< Structure used for bit access */ 311 uint32_t reg; /**< Type used for register access */ 312 } XDMAC_CNDC_Type; 313 #endif 314 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 315 316 #define XDMAC_CNDC_OFFSET (0x1C) /**< (XDMAC_CNDC) Channel Next Descriptor Control Register Offset */ 317 318 #define XDMAC_CNDC_NDE_Pos 0 /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Position */ 319 #define XDMAC_CNDC_NDE_Msk (_U_(0x1) << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Mask */ 320 #define XDMAC_CNDC_NDE XDMAC_CNDC_NDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDE_Msk instead */ 321 #define XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val _U_(0x0) /**< (XDMAC_CNDC) Descriptor fetch is disabled. */ 322 #define XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val _U_(0x1) /**< (XDMAC_CNDC) Descriptor fetch is enabled. */ 323 #define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is disabled. Position */ 324 #define XDMAC_CNDC_NDE_DSCR_FETCH_EN (XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is enabled. Position */ 325 #define XDMAC_CNDC_NDSUP_Pos 1 /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Position */ 326 #define XDMAC_CNDC_NDSUP_Msk (_U_(0x1) << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Mask */ 327 #define XDMAC_CNDC_NDSUP XDMAC_CNDC_NDSUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDSUP_Msk instead */ 328 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Source parameters remain unchanged. */ 329 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ 330 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters remain unchanged. Position */ 331 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. Position */ 332 #define XDMAC_CNDC_NDDUP_Pos 2 /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Position */ 333 #define XDMAC_CNDC_NDDUP_Msk (_U_(0x1) << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Mask */ 334 #define XDMAC_CNDC_NDDUP XDMAC_CNDC_NDDUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDDUP_Msk instead */ 335 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Destination parameters remain unchanged. */ 336 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ 337 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters remain unchanged. Position */ 338 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. Position */ 339 #define XDMAC_CNDC_NDVIEW_Pos 3 /**< (XDMAC_CNDC) Channel x Next Descriptor View Position */ 340 #define XDMAC_CNDC_NDVIEW_Msk (_U_(0x3) << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor View Mask */ 341 #define XDMAC_CNDC_NDVIEW(value) (XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)) 342 #define XDMAC_CNDC_NDVIEW_NDV0_Val _U_(0x0) /**< (XDMAC_CNDC) Next Descriptor View 0 */ 343 #define XDMAC_CNDC_NDVIEW_NDV1_Val _U_(0x1) /**< (XDMAC_CNDC) Next Descriptor View 1 */ 344 #define XDMAC_CNDC_NDVIEW_NDV2_Val _U_(0x2) /**< (XDMAC_CNDC) Next Descriptor View 2 */ 345 #define XDMAC_CNDC_NDVIEW_NDV3_Val _U_(0x3) /**< (XDMAC_CNDC) Next Descriptor View 3 */ 346 #define XDMAC_CNDC_NDVIEW_NDV0 (XDMAC_CNDC_NDVIEW_NDV0_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 0 Position */ 347 #define XDMAC_CNDC_NDVIEW_NDV1 (XDMAC_CNDC_NDVIEW_NDV1_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 1 Position */ 348 #define XDMAC_CNDC_NDVIEW_NDV2 (XDMAC_CNDC_NDVIEW_NDV2_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 2 Position */ 349 #define XDMAC_CNDC_NDVIEW_NDV3 (XDMAC_CNDC_NDVIEW_NDV3_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 3 Position */ 350 #define XDMAC_CNDC_MASK _U_(0x1F) /**< \deprecated (XDMAC_CNDC) Register MASK (Use XDMAC_CNDC_Msk instead) */ 351 #define XDMAC_CNDC_Msk _U_(0x1F) /**< (XDMAC_CNDC) Register Mask */ 352 353 354 /* -------- XDMAC_CUBC : (XDMAC Offset: 0x20) (R/W 32) Channel Microblock Control Register -------- */ 355 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 356 #if COMPONENT_TYPEDEF_STYLE == 'N' 357 typedef union { 358 struct { 359 uint32_t UBLEN:24; /**< bit: 0..23 Channel x Microblock Length */ 360 uint32_t :8; /**< bit: 24..31 Reserved */ 361 } bit; /**< Structure used for bit access */ 362 uint32_t reg; /**< Type used for register access */ 363 } XDMAC_CUBC_Type; 364 #endif 365 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 366 367 #define XDMAC_CUBC_OFFSET (0x20) /**< (XDMAC_CUBC) Channel Microblock Control Register Offset */ 368 369 #define XDMAC_CUBC_UBLEN_Pos 0 /**< (XDMAC_CUBC) Channel x Microblock Length Position */ 370 #define XDMAC_CUBC_UBLEN_Msk (_U_(0xFFFFFF) << XDMAC_CUBC_UBLEN_Pos) /**< (XDMAC_CUBC) Channel x Microblock Length Mask */ 371 #define XDMAC_CUBC_UBLEN(value) (XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)) 372 #define XDMAC_CUBC_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CUBC) Register MASK (Use XDMAC_CUBC_Msk instead) */ 373 #define XDMAC_CUBC_Msk _U_(0xFFFFFF) /**< (XDMAC_CUBC) Register Mask */ 374 375 376 /* -------- XDMAC_CBC : (XDMAC Offset: 0x24) (R/W 32) Channel Block Control Register -------- */ 377 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 378 #if COMPONENT_TYPEDEF_STYLE == 'N' 379 typedef union { 380 struct { 381 uint32_t BLEN:12; /**< bit: 0..11 Channel x Block Length */ 382 uint32_t :20; /**< bit: 12..31 Reserved */ 383 } bit; /**< Structure used for bit access */ 384 uint32_t reg; /**< Type used for register access */ 385 } XDMAC_CBC_Type; 386 #endif 387 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 #define XDMAC_CBC_OFFSET (0x24) /**< (XDMAC_CBC) Channel Block Control Register Offset */ 390 391 #define XDMAC_CBC_BLEN_Pos 0 /**< (XDMAC_CBC) Channel x Block Length Position */ 392 #define XDMAC_CBC_BLEN_Msk (_U_(0xFFF) << XDMAC_CBC_BLEN_Pos) /**< (XDMAC_CBC) Channel x Block Length Mask */ 393 #define XDMAC_CBC_BLEN(value) (XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)) 394 #define XDMAC_CBC_MASK _U_(0xFFF) /**< \deprecated (XDMAC_CBC) Register MASK (Use XDMAC_CBC_Msk instead) */ 395 #define XDMAC_CBC_Msk _U_(0xFFF) /**< (XDMAC_CBC) Register Mask */ 396 397 398 /* -------- XDMAC_CC : (XDMAC Offset: 0x28) (R/W 32) Channel Configuration Register -------- */ 399 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 400 #if COMPONENT_TYPEDEF_STYLE == 'N' 401 typedef union { 402 struct { 403 uint32_t TYPE:1; /**< bit: 0 Channel x Transfer Type */ 404 uint32_t MBSIZE:2; /**< bit: 1..2 Channel x Memory Burst Size */ 405 uint32_t :1; /**< bit: 3 Reserved */ 406 uint32_t DSYNC:1; /**< bit: 4 Channel x Synchronization */ 407 uint32_t :1; /**< bit: 5 Reserved */ 408 uint32_t SWREQ:1; /**< bit: 6 Channel x Software Request Trigger */ 409 uint32_t MEMSET:1; /**< bit: 7 Channel x Fill Block of memory */ 410 uint32_t CSIZE:3; /**< bit: 8..10 Channel x Chunk Size */ 411 uint32_t DWIDTH:2; /**< bit: 11..12 Channel x Data Width */ 412 uint32_t SIF:1; /**< bit: 13 Channel x Source Interface Identifier */ 413 uint32_t DIF:1; /**< bit: 14 Channel x Destination Interface Identifier */ 414 uint32_t :1; /**< bit: 15 Reserved */ 415 uint32_t SAM:2; /**< bit: 16..17 Channel x Source Addressing Mode */ 416 uint32_t DAM:2; /**< bit: 18..19 Channel x Destination Addressing Mode */ 417 uint32_t :1; /**< bit: 20 Reserved */ 418 uint32_t INITD:1; /**< bit: 21 Channel Initialization Terminated (this bit is read-only) */ 419 uint32_t RDIP:1; /**< bit: 22 Read in Progress (this bit is read-only) */ 420 uint32_t WRIP:1; /**< bit: 23 Write in Progress (this bit is read-only) */ 421 uint32_t PERID:7; /**< bit: 24..30 Channel x Peripheral Hardware Request Line Identifier */ 422 uint32_t :1; /**< bit: 31 Reserved */ 423 } bit; /**< Structure used for bit access */ 424 uint32_t reg; /**< Type used for register access */ 425 } XDMAC_CC_Type; 426 #endif 427 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 428 429 #define XDMAC_CC_OFFSET (0x28) /**< (XDMAC_CC) Channel Configuration Register Offset */ 430 431 #define XDMAC_CC_TYPE_Pos 0 /**< (XDMAC_CC) Channel x Transfer Type Position */ 432 #define XDMAC_CC_TYPE_Msk (_U_(0x1) << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Channel x Transfer Type Mask */ 433 #define XDMAC_CC_TYPE XDMAC_CC_TYPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_TYPE_Msk instead */ 434 #define XDMAC_CC_TYPE_MEM_TRAN_Val _U_(0x0) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). */ 435 #define XDMAC_CC_TYPE_PER_TRAN_Val _U_(0x1) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). */ 436 #define XDMAC_CC_TYPE_MEM_TRAN (XDMAC_CC_TYPE_MEM_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). Position */ 437 #define XDMAC_CC_TYPE_PER_TRAN (XDMAC_CC_TYPE_PER_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). Position */ 438 #define XDMAC_CC_MBSIZE_Pos 1 /**< (XDMAC_CC) Channel x Memory Burst Size Position */ 439 #define XDMAC_CC_MBSIZE_Msk (_U_(0x3) << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) Channel x Memory Burst Size Mask */ 440 #define XDMAC_CC_MBSIZE(value) (XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)) 441 #define XDMAC_CC_MBSIZE_SINGLE_Val _U_(0x0) /**< (XDMAC_CC) The memory burst size is set to one. */ 442 #define XDMAC_CC_MBSIZE_FOUR_Val _U_(0x1) /**< (XDMAC_CC) The memory burst size is set to four. */ 443 #define XDMAC_CC_MBSIZE_EIGHT_Val _U_(0x2) /**< (XDMAC_CC) The memory burst size is set to eight. */ 444 #define XDMAC_CC_MBSIZE_SIXTEEN_Val _U_(0x3) /**< (XDMAC_CC) The memory burst size is set to sixteen. */ 445 #define XDMAC_CC_MBSIZE_SINGLE (XDMAC_CC_MBSIZE_SINGLE_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to one. Position */ 446 #define XDMAC_CC_MBSIZE_FOUR (XDMAC_CC_MBSIZE_FOUR_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to four. Position */ 447 #define XDMAC_CC_MBSIZE_EIGHT (XDMAC_CC_MBSIZE_EIGHT_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to eight. Position */ 448 #define XDMAC_CC_MBSIZE_SIXTEEN (XDMAC_CC_MBSIZE_SIXTEEN_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to sixteen. Position */ 449 #define XDMAC_CC_DSYNC_Pos 4 /**< (XDMAC_CC) Channel x Synchronization Position */ 450 #define XDMAC_CC_DSYNC_Msk (_U_(0x1) << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Channel x Synchronization Mask */ 451 #define XDMAC_CC_DSYNC XDMAC_CC_DSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_DSYNC_Msk instead */ 452 #define XDMAC_CC_DSYNC_PER2MEM_Val _U_(0x0) /**< (XDMAC_CC) Peripheral-to-memory transfer. */ 453 #define XDMAC_CC_DSYNC_MEM2PER_Val _U_(0x1) /**< (XDMAC_CC) Memory-to-peripheral transfer. */ 454 #define XDMAC_CC_DSYNC_PER2MEM (XDMAC_CC_DSYNC_PER2MEM_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Peripheral-to-memory transfer. Position */ 455 #define XDMAC_CC_DSYNC_MEM2PER (XDMAC_CC_DSYNC_MEM2PER_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Memory-to-peripheral transfer. Position */ 456 #define XDMAC_CC_SWREQ_Pos 6 /**< (XDMAC_CC) Channel x Software Request Trigger Position */ 457 #define XDMAC_CC_SWREQ_Msk (_U_(0x1) << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Channel x Software Request Trigger Mask */ 458 #define XDMAC_CC_SWREQ XDMAC_CC_SWREQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_SWREQ_Msk instead */ 459 #define XDMAC_CC_SWREQ_HWR_CONNECTED_Val _U_(0x0) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ 460 #define XDMAC_CC_SWREQ_SWR_CONNECTED_Val _U_(0x1) /**< (XDMAC_CC) Software request is connected to the peripheral request line. */ 461 #define XDMAC_CC_SWREQ_HWR_CONNECTED (XDMAC_CC_SWREQ_HWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. Position */ 462 #define XDMAC_CC_SWREQ_SWR_CONNECTED (XDMAC_CC_SWREQ_SWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Software request is connected to the peripheral request line. Position */ 463 #define XDMAC_CC_MEMSET_Pos 7 /**< (XDMAC_CC) Channel x Fill Block of memory Position */ 464 #define XDMAC_CC_MEMSET_Msk (_U_(0x1) << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Channel x Fill Block of memory Mask */ 465 #define XDMAC_CC_MEMSET XDMAC_CC_MEMSET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_MEMSET_Msk instead */ 466 #define XDMAC_CC_MEMSET_NORMAL_MODE_Val _U_(0x0) /**< (XDMAC_CC) Memset is not activated. */ 467 #define XDMAC_CC_MEMSET_HW_MODE_Val _U_(0x1) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. */ 468 #define XDMAC_CC_MEMSET_NORMAL_MODE (XDMAC_CC_MEMSET_NORMAL_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Memset is not activated. Position */ 469 #define XDMAC_CC_MEMSET_HW_MODE (XDMAC_CC_MEMSET_HW_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. Position */ 470 #define XDMAC_CC_CSIZE_Pos 8 /**< (XDMAC_CC) Channel x Chunk Size Position */ 471 #define XDMAC_CC_CSIZE_Msk (_U_(0x7) << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) Channel x Chunk Size Mask */ 472 #define XDMAC_CC_CSIZE(value) (XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)) 473 #define XDMAC_CC_CSIZE_CHK_1_Val _U_(0x0) /**< (XDMAC_CC) 1 data transferred */ 474 #define XDMAC_CC_CSIZE_CHK_2_Val _U_(0x1) /**< (XDMAC_CC) 2 data transferred */ 475 #define XDMAC_CC_CSIZE_CHK_4_Val _U_(0x2) /**< (XDMAC_CC) 4 data transferred */ 476 #define XDMAC_CC_CSIZE_CHK_8_Val _U_(0x3) /**< (XDMAC_CC) 8 data transferred */ 477 #define XDMAC_CC_CSIZE_CHK_16_Val _U_(0x4) /**< (XDMAC_CC) 16 data transferred */ 478 #define XDMAC_CC_CSIZE_CHK_1 (XDMAC_CC_CSIZE_CHK_1_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 1 data transferred Position */ 479 #define XDMAC_CC_CSIZE_CHK_2 (XDMAC_CC_CSIZE_CHK_2_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 2 data transferred Position */ 480 #define XDMAC_CC_CSIZE_CHK_4 (XDMAC_CC_CSIZE_CHK_4_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 4 data transferred Position */ 481 #define XDMAC_CC_CSIZE_CHK_8 (XDMAC_CC_CSIZE_CHK_8_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 8 data transferred Position */ 482 #define XDMAC_CC_CSIZE_CHK_16 (XDMAC_CC_CSIZE_CHK_16_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 16 data transferred Position */ 483 #define XDMAC_CC_DWIDTH_Pos 11 /**< (XDMAC_CC) Channel x Data Width Position */ 484 #define XDMAC_CC_DWIDTH_Msk (_U_(0x3) << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) Channel x Data Width Mask */ 485 #define XDMAC_CC_DWIDTH(value) (XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)) 486 #define XDMAC_CC_DWIDTH_BYTE_Val _U_(0x0) /**< (XDMAC_CC) The data size is set to 8 bits */ 487 #define XDMAC_CC_DWIDTH_HALFWORD_Val _U_(0x1) /**< (XDMAC_CC) The data size is set to 16 bits */ 488 #define XDMAC_CC_DWIDTH_WORD_Val _U_(0x2) /**< (XDMAC_CC) The data size is set to 32 bits */ 489 #define XDMAC_CC_DWIDTH_BYTE (XDMAC_CC_DWIDTH_BYTE_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 8 bits Position */ 490 #define XDMAC_CC_DWIDTH_HALFWORD (XDMAC_CC_DWIDTH_HALFWORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 16 bits Position */ 491 #define XDMAC_CC_DWIDTH_WORD (XDMAC_CC_DWIDTH_WORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 32 bits Position */ 492 #define XDMAC_CC_SIF_Pos 13 /**< (XDMAC_CC) Channel x Source Interface Identifier Position */ 493 #define XDMAC_CC_SIF_Msk (_U_(0x1) << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) Channel x Source Interface Identifier Mask */ 494 #define XDMAC_CC_SIF XDMAC_CC_SIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_SIF_Msk instead */ 495 #define XDMAC_CC_SIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is read through the system bus interface 0. */ 496 #define XDMAC_CC_SIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is read through the system bus interface 1. */ 497 #define XDMAC_CC_SIF_AHB_IF0 (XDMAC_CC_SIF_AHB_IF0_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 0. Position */ 498 #define XDMAC_CC_SIF_AHB_IF1 (XDMAC_CC_SIF_AHB_IF1_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 1. Position */ 499 #define XDMAC_CC_DIF_Pos 14 /**< (XDMAC_CC) Channel x Destination Interface Identifier Position */ 500 #define XDMAC_CC_DIF_Msk (_U_(0x1) << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) Channel x Destination Interface Identifier Mask */ 501 #define XDMAC_CC_DIF XDMAC_CC_DIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_DIF_Msk instead */ 502 #define XDMAC_CC_DIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is written through the system bus interface 0. */ 503 #define XDMAC_CC_DIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is written though the system bus interface 1. */ 504 #define XDMAC_CC_DIF_AHB_IF0 (XDMAC_CC_DIF_AHB_IF0_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written through the system bus interface 0. Position */ 505 #define XDMAC_CC_DIF_AHB_IF1 (XDMAC_CC_DIF_AHB_IF1_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written though the system bus interface 1. Position */ 506 #define XDMAC_CC_SAM_Pos 16 /**< (XDMAC_CC) Channel x Source Addressing Mode Position */ 507 #define XDMAC_CC_SAM_Msk (_U_(0x3) << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) Channel x Source Addressing Mode Mask */ 508 #define XDMAC_CC_SAM(value) (XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)) 509 #define XDMAC_CC_SAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ 510 #define XDMAC_CC_SAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ 511 #define XDMAC_CC_SAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ 512 #define XDMAC_CC_SAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ 513 #define XDMAC_CC_SAM_FIXED_AM (XDMAC_CC_SAM_FIXED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ 514 #define XDMAC_CC_SAM_INCREMENTED_AM (XDMAC_CC_SAM_INCREMENTED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ 515 #define XDMAC_CC_SAM_UBS_AM (XDMAC_CC_SAM_UBS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ 516 #define XDMAC_CC_SAM_UBS_DS_AM (XDMAC_CC_SAM_UBS_DS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Position */ 517 #define XDMAC_CC_DAM_Pos 18 /**< (XDMAC_CC) Channel x Destination Addressing Mode Position */ 518 #define XDMAC_CC_DAM_Msk (_U_(0x3) << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) Channel x Destination Addressing Mode Mask */ 519 #define XDMAC_CC_DAM(value) (XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)) 520 #define XDMAC_CC_DAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ 521 #define XDMAC_CC_DAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ 522 #define XDMAC_CC_DAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ 523 #define XDMAC_CC_DAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. */ 524 #define XDMAC_CC_DAM_FIXED_AM (XDMAC_CC_DAM_FIXED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ 525 #define XDMAC_CC_DAM_INCREMENTED_AM (XDMAC_CC_DAM_INCREMENTED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ 526 #define XDMAC_CC_DAM_UBS_AM (XDMAC_CC_DAM_UBS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ 527 #define XDMAC_CC_DAM_UBS_DS_AM (XDMAC_CC_DAM_UBS_DS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. Position */ 528 #define XDMAC_CC_INITD_Pos 21 /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Position */ 529 #define XDMAC_CC_INITD_Msk (_U_(0x1) << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Mask */ 530 #define XDMAC_CC_INITD XDMAC_CC_INITD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_INITD_Msk instead */ 531 #define XDMAC_CC_INITD_IN_PROGRESS_Val _U_(0x0) /**< (XDMAC_CC) Channel initialization is in progress. */ 532 #define XDMAC_CC_INITD_TERMINATED_Val _U_(0x1) /**< (XDMAC_CC) Channel initialization is completed. */ 533 #define XDMAC_CC_INITD_IN_PROGRESS (XDMAC_CC_INITD_IN_PROGRESS_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is in progress. Position */ 534 #define XDMAC_CC_INITD_TERMINATED (XDMAC_CC_INITD_TERMINATED_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is completed. Position */ 535 #define XDMAC_CC_RDIP_Pos 22 /**< (XDMAC_CC) Read in Progress (this bit is read-only) Position */ 536 #define XDMAC_CC_RDIP_Msk (_U_(0x1) << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Mask */ 537 #define XDMAC_CC_RDIP XDMAC_CC_RDIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_RDIP_Msk instead */ 538 #define XDMAC_CC_RDIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active read transaction on the bus. */ 539 #define XDMAC_CC_RDIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A read transaction is in progress. */ 540 #define XDMAC_CC_RDIP_DONE (XDMAC_CC_RDIP_DONE_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) No active read transaction on the bus. Position */ 541 #define XDMAC_CC_RDIP_IN_PROGRESS (XDMAC_CC_RDIP_IN_PROGRESS_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) A read transaction is in progress. Position */ 542 #define XDMAC_CC_WRIP_Pos 23 /**< (XDMAC_CC) Write in Progress (this bit is read-only) Position */ 543 #define XDMAC_CC_WRIP_Msk (_U_(0x1) << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Mask */ 544 #define XDMAC_CC_WRIP XDMAC_CC_WRIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_WRIP_Msk instead */ 545 #define XDMAC_CC_WRIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active write transaction on the bus. */ 546 #define XDMAC_CC_WRIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A write transaction is in progress. */ 547 #define XDMAC_CC_WRIP_DONE (XDMAC_CC_WRIP_DONE_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) No active write transaction on the bus. Position */ 548 #define XDMAC_CC_WRIP_IN_PROGRESS (XDMAC_CC_WRIP_IN_PROGRESS_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) A write transaction is in progress. Position */ 549 #define XDMAC_CC_PERID_Pos 24 /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Position */ 550 #define XDMAC_CC_PERID_Msk (_U_(0x7F) << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Mask */ 551 #define XDMAC_CC_PERID(value) (XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)) 552 #define XDMAC_CC_PERID_HSMCI_Val _U_(0x0) /**< (XDMAC_CC) HSMCI */ 553 #define XDMAC_CC_PERID_SPI0_TX_Val _U_(0x1) /**< (XDMAC_CC) SPI0_TX */ 554 #define XDMAC_CC_PERID_SPI0_RX_Val _U_(0x2) /**< (XDMAC_CC) SPI0_RX */ 555 #define XDMAC_CC_PERID_SPI1_TX_Val _U_(0x3) /**< (XDMAC_CC) SPI1_TX */ 556 #define XDMAC_CC_PERID_SPI1_RX_Val _U_(0x4) /**< (XDMAC_CC) SPI1_RX */ 557 #define XDMAC_CC_PERID_QSPI_TX_Val _U_(0x5) /**< (XDMAC_CC) QSPI_TX */ 558 #define XDMAC_CC_PERID_QSPI_RX_Val _U_(0x6) /**< (XDMAC_CC) QSPI_RX */ 559 #define XDMAC_CC_PERID_USART0_TX_Val _U_(0x7) /**< (XDMAC_CC) USART0_TX */ 560 #define XDMAC_CC_PERID_USART0_RX_Val _U_(0x8) /**< (XDMAC_CC) USART0_RX */ 561 #define XDMAC_CC_PERID_USART1_TX_Val _U_(0x9) /**< (XDMAC_CC) USART1_TX */ 562 #define XDMAC_CC_PERID_USART1_RX_Val _U_(0xA) /**< (XDMAC_CC) USART1_RX */ 563 #define XDMAC_CC_PERID_USART2_TX_Val _U_(0xB) /**< (XDMAC_CC) USART2_TX */ 564 #define XDMAC_CC_PERID_USART2_RX_Val _U_(0xC) /**< (XDMAC_CC) USART2_RX */ 565 #define XDMAC_CC_PERID_PWM0_Val _U_(0xD) /**< (XDMAC_CC) PWM0 */ 566 #define XDMAC_CC_PERID_TWIHS0_TX_Val _U_(0xE) /**< (XDMAC_CC) TWIHS0_TX */ 567 #define XDMAC_CC_PERID_TWIHS0_RX_Val _U_(0xF) /**< (XDMAC_CC) TWIHS0_RX */ 568 #define XDMAC_CC_PERID_TWIHS1_TX_Val _U_(0x10) /**< (XDMAC_CC) TWIHS1_TX */ 569 #define XDMAC_CC_PERID_TWIHS1_RX_Val _U_(0x11) /**< (XDMAC_CC) TWIHS1_RX */ 570 #define XDMAC_CC_PERID_TWIHS2_TX_Val _U_(0x12) /**< (XDMAC_CC) TWIHS2_TX */ 571 #define XDMAC_CC_PERID_TWIHS2_RX_Val _U_(0x13) /**< (XDMAC_CC) TWIHS2_RX */ 572 #define XDMAC_CC_PERID_UART0_TX_Val _U_(0x14) /**< (XDMAC_CC) UART0_TX */ 573 #define XDMAC_CC_PERID_UART0_RX_Val _U_(0x15) /**< (XDMAC_CC) UART0_RX */ 574 #define XDMAC_CC_PERID_UART1_TX_Val _U_(0x16) /**< (XDMAC_CC) UART1_TX */ 575 #define XDMAC_CC_PERID_UART1_RX_Val _U_(0x17) /**< (XDMAC_CC) UART1_RX */ 576 #define XDMAC_CC_PERID_UART2_TX_Val _U_(0x18) /**< (XDMAC_CC) UART2_TX */ 577 #define XDMAC_CC_PERID_UART2_RX_Val _U_(0x19) /**< (XDMAC_CC) UART2_RX */ 578 #define XDMAC_CC_PERID_UART3_TX_Val _U_(0x1A) /**< (XDMAC_CC) UART3_TX */ 579 #define XDMAC_CC_PERID_UART3_RX_Val _U_(0x1B) /**< (XDMAC_CC) UART3_RX */ 580 #define XDMAC_CC_PERID_UART4_TX_Val _U_(0x1C) /**< (XDMAC_CC) UART4_TX */ 581 #define XDMAC_CC_PERID_UART4_RX_Val _U_(0x1D) /**< (XDMAC_CC) UART4_RX */ 582 #define XDMAC_CC_PERID_DACC0_Val _U_(0x1E) /**< (XDMAC_CC) DACC0 */ 583 #define XDMAC_CC_PERID_DACC1_Val _U_(0x1F) /**< (XDMAC_CC) DACC1 */ 584 #define XDMAC_CC_PERID_SSC_TX_Val _U_(0x20) /**< (XDMAC_CC) SSC_TX */ 585 #define XDMAC_CC_PERID_SSC_RX_Val _U_(0x21) /**< (XDMAC_CC) SSC_RX */ 586 #define XDMAC_CC_PERID_PIOA_Val _U_(0x22) /**< (XDMAC_CC) PIOA */ 587 #define XDMAC_CC_PERID_AFEC0_Val _U_(0x23) /**< (XDMAC_CC) AFEC0 */ 588 #define XDMAC_CC_PERID_AFEC1_Val _U_(0x24) /**< (XDMAC_CC) AFEC1 */ 589 #define XDMAC_CC_PERID_AES_TX_Val _U_(0x25) /**< (XDMAC_CC) AES_TX */ 590 #define XDMAC_CC_PERID_AES_RX_Val _U_(0x26) /**< (XDMAC_CC) AES_RX */ 591 #define XDMAC_CC_PERID_PWM1_Val _U_(0x27) /**< (XDMAC_CC) PWM1 */ 592 #define XDMAC_CC_PERID_TC0_Val _U_(0x28) /**< (XDMAC_CC) TC0 */ 593 #define XDMAC_CC_PERID_TC3_Val _U_(0x29) /**< (XDMAC_CC) TC3 */ 594 #define XDMAC_CC_PERID_TC6_Val _U_(0x2A) /**< (XDMAC_CC) TC6 */ 595 #define XDMAC_CC_PERID_TC9_Val _U_(0x2B) /**< (XDMAC_CC) TC9 */ 596 #define XDMAC_CC_PERID_I2SC0_TX_LEFT_Val _U_(0x2C) /**< (XDMAC_CC) I2SC0_TX_LEFT */ 597 #define XDMAC_CC_PERID_I2SC0_RX_LEFT_Val _U_(0x2D) /**< (XDMAC_CC) I2SC0_RX_LEFT */ 598 #define XDMAC_CC_PERID_I2SC1_TX_LEFT_Val _U_(0x2E) /**< (XDMAC_CC) I2SC1_TX_LEFT */ 599 #define XDMAC_CC_PERID_I2SC1_RX_LEFT_Val _U_(0x2F) /**< (XDMAC_CC) I2SC1_RX_LEFT */ 600 #define XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val _U_(0x30) /**< (XDMAC_CC) I2SC0_TX_RIGHT */ 601 #define XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val _U_(0x31) /**< (XDMAC_CC) I2SC0_RX_RIGHT */ 602 #define XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val _U_(0x32) /**< (XDMAC_CC) I2SC1_TX_RIGHT */ 603 #define XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val _U_(0x33) /**< (XDMAC_CC) I2SC1_RX_RIGHT */ 604 #define XDMAC_CC_PERID_HSMCI (XDMAC_CC_PERID_HSMCI_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) HSMCI Position */ 605 #define XDMAC_CC_PERID_SPI0_TX (XDMAC_CC_PERID_SPI0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_TX Position */ 606 #define XDMAC_CC_PERID_SPI0_RX (XDMAC_CC_PERID_SPI0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_RX Position */ 607 #define XDMAC_CC_PERID_SPI1_TX (XDMAC_CC_PERID_SPI1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_TX Position */ 608 #define XDMAC_CC_PERID_SPI1_RX (XDMAC_CC_PERID_SPI1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_RX Position */ 609 #define XDMAC_CC_PERID_QSPI_TX (XDMAC_CC_PERID_QSPI_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_TX Position */ 610 #define XDMAC_CC_PERID_QSPI_RX (XDMAC_CC_PERID_QSPI_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_RX Position */ 611 #define XDMAC_CC_PERID_USART0_TX (XDMAC_CC_PERID_USART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_TX Position */ 612 #define XDMAC_CC_PERID_USART0_RX (XDMAC_CC_PERID_USART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_RX Position */ 613 #define XDMAC_CC_PERID_USART1_TX (XDMAC_CC_PERID_USART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_TX Position */ 614 #define XDMAC_CC_PERID_USART1_RX (XDMAC_CC_PERID_USART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_RX Position */ 615 #define XDMAC_CC_PERID_USART2_TX (XDMAC_CC_PERID_USART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_TX Position */ 616 #define XDMAC_CC_PERID_USART2_RX (XDMAC_CC_PERID_USART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_RX Position */ 617 #define XDMAC_CC_PERID_PWM0 (XDMAC_CC_PERID_PWM0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM0 Position */ 618 #define XDMAC_CC_PERID_TWIHS0_TX (XDMAC_CC_PERID_TWIHS0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_TX Position */ 619 #define XDMAC_CC_PERID_TWIHS0_RX (XDMAC_CC_PERID_TWIHS0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_RX Position */ 620 #define XDMAC_CC_PERID_TWIHS1_TX (XDMAC_CC_PERID_TWIHS1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_TX Position */ 621 #define XDMAC_CC_PERID_TWIHS1_RX (XDMAC_CC_PERID_TWIHS1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_RX Position */ 622 #define XDMAC_CC_PERID_TWIHS2_TX (XDMAC_CC_PERID_TWIHS2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_TX Position */ 623 #define XDMAC_CC_PERID_TWIHS2_RX (XDMAC_CC_PERID_TWIHS2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_RX Position */ 624 #define XDMAC_CC_PERID_UART0_TX (XDMAC_CC_PERID_UART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_TX Position */ 625 #define XDMAC_CC_PERID_UART0_RX (XDMAC_CC_PERID_UART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_RX Position */ 626 #define XDMAC_CC_PERID_UART1_TX (XDMAC_CC_PERID_UART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_TX Position */ 627 #define XDMAC_CC_PERID_UART1_RX (XDMAC_CC_PERID_UART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_RX Position */ 628 #define XDMAC_CC_PERID_UART2_TX (XDMAC_CC_PERID_UART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_TX Position */ 629 #define XDMAC_CC_PERID_UART2_RX (XDMAC_CC_PERID_UART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_RX Position */ 630 #define XDMAC_CC_PERID_UART3_TX (XDMAC_CC_PERID_UART3_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_TX Position */ 631 #define XDMAC_CC_PERID_UART3_RX (XDMAC_CC_PERID_UART3_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_RX Position */ 632 #define XDMAC_CC_PERID_UART4_TX (XDMAC_CC_PERID_UART4_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_TX Position */ 633 #define XDMAC_CC_PERID_UART4_RX (XDMAC_CC_PERID_UART4_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_RX Position */ 634 #define XDMAC_CC_PERID_DACC0 (XDMAC_CC_PERID_DACC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC0 Position */ 635 #define XDMAC_CC_PERID_DACC1 (XDMAC_CC_PERID_DACC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC1 Position */ 636 #define XDMAC_CC_PERID_SSC_TX (XDMAC_CC_PERID_SSC_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_TX Position */ 637 #define XDMAC_CC_PERID_SSC_RX (XDMAC_CC_PERID_SSC_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_RX Position */ 638 #define XDMAC_CC_PERID_PIOA (XDMAC_CC_PERID_PIOA_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PIOA Position */ 639 #define XDMAC_CC_PERID_AFEC0 (XDMAC_CC_PERID_AFEC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC0 Position */ 640 #define XDMAC_CC_PERID_AFEC1 (XDMAC_CC_PERID_AFEC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC1 Position */ 641 #define XDMAC_CC_PERID_AES_TX (XDMAC_CC_PERID_AES_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_TX Position */ 642 #define XDMAC_CC_PERID_AES_RX (XDMAC_CC_PERID_AES_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_RX Position */ 643 #define XDMAC_CC_PERID_PWM1 (XDMAC_CC_PERID_PWM1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM1 Position */ 644 #define XDMAC_CC_PERID_TC0 (XDMAC_CC_PERID_TC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC0 Position */ 645 #define XDMAC_CC_PERID_TC3 (XDMAC_CC_PERID_TC3_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC3 Position */ 646 #define XDMAC_CC_PERID_TC6 (XDMAC_CC_PERID_TC6_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC6 Position */ 647 #define XDMAC_CC_PERID_TC9 (XDMAC_CC_PERID_TC9_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC9 Position */ 648 #define XDMAC_CC_PERID_I2SC0_TX_LEFT (XDMAC_CC_PERID_I2SC0_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_LEFT Position */ 649 #define XDMAC_CC_PERID_I2SC0_RX_LEFT (XDMAC_CC_PERID_I2SC0_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_LEFT Position */ 650 #define XDMAC_CC_PERID_I2SC1_TX_LEFT (XDMAC_CC_PERID_I2SC1_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_LEFT Position */ 651 #define XDMAC_CC_PERID_I2SC1_RX_LEFT (XDMAC_CC_PERID_I2SC1_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_LEFT Position */ 652 #define XDMAC_CC_PERID_I2SC0_TX_RIGHT (XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_RIGHT Position */ 653 #define XDMAC_CC_PERID_I2SC0_RX_RIGHT (XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_RIGHT Position */ 654 #define XDMAC_CC_PERID_I2SC1_TX_RIGHT (XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_RIGHT Position */ 655 #define XDMAC_CC_PERID_I2SC1_RX_RIGHT (XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_RIGHT Position */ 656 #define XDMAC_CC_MASK _U_(0x7FEF7FD7) /**< \deprecated (XDMAC_CC) Register MASK (Use XDMAC_CC_Msk instead) */ 657 #define XDMAC_CC_Msk _U_(0x7FEF7FD7) /**< (XDMAC_CC) Register Mask */ 658 659 660 /* -------- XDMAC_CDS_MSP : (XDMAC Offset: 0x2c) (R/W 32) Channel Data Stride Memory Set Pattern -------- */ 661 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 662 #if COMPONENT_TYPEDEF_STYLE == 'N' 663 typedef union { 664 struct { 665 uint32_t SDS_MSP:16; /**< bit: 0..15 Channel x Source Data stride or Memory Set Pattern */ 666 uint32_t DDS_MSP:16; /**< bit: 16..31 Channel x Destination Data Stride or Memory Set Pattern */ 667 } bit; /**< Structure used for bit access */ 668 uint32_t reg; /**< Type used for register access */ 669 } XDMAC_CDS_MSP_Type; 670 #endif 671 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 672 673 #define XDMAC_CDS_MSP_OFFSET (0x2C) /**< (XDMAC_CDS_MSP) Channel Data Stride Memory Set Pattern Offset */ 674 675 #define XDMAC_CDS_MSP_SDS_MSP_Pos 0 /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Position */ 676 #define XDMAC_CDS_MSP_SDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Mask */ 677 #define XDMAC_CDS_MSP_SDS_MSP(value) (XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)) 678 #define XDMAC_CDS_MSP_DDS_MSP_Pos 16 /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Position */ 679 #define XDMAC_CDS_MSP_DDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Mask */ 680 #define XDMAC_CDS_MSP_DDS_MSP(value) (XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)) 681 #define XDMAC_CDS_MSP_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CDS_MSP) Register MASK (Use XDMAC_CDS_MSP_Msk instead) */ 682 #define XDMAC_CDS_MSP_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDS_MSP) Register Mask */ 683 684 685 /* -------- XDMAC_CSUS : (XDMAC Offset: 0x30) (R/W 32) Channel Source Microblock Stride -------- */ 686 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 687 #if COMPONENT_TYPEDEF_STYLE == 'N' 688 typedef union { 689 struct { 690 uint32_t SUBS:24; /**< bit: 0..23 Channel x Source Microblock Stride */ 691 uint32_t :8; /**< bit: 24..31 Reserved */ 692 } bit; /**< Structure used for bit access */ 693 uint32_t reg; /**< Type used for register access */ 694 } XDMAC_CSUS_Type; 695 #endif 696 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 697 698 #define XDMAC_CSUS_OFFSET (0x30) /**< (XDMAC_CSUS) Channel Source Microblock Stride Offset */ 699 700 #define XDMAC_CSUS_SUBS_Pos 0 /**< (XDMAC_CSUS) Channel x Source Microblock Stride Position */ 701 #define XDMAC_CSUS_SUBS_Msk (_U_(0xFFFFFF) << XDMAC_CSUS_SUBS_Pos) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Mask */ 702 #define XDMAC_CSUS_SUBS(value) (XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)) 703 #define XDMAC_CSUS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CSUS) Register MASK (Use XDMAC_CSUS_Msk instead) */ 704 #define XDMAC_CSUS_Msk _U_(0xFFFFFF) /**< (XDMAC_CSUS) Register Mask */ 705 706 707 /* -------- XDMAC_CDUS : (XDMAC Offset: 0x34) (R/W 32) Channel Destination Microblock Stride -------- */ 708 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 709 #if COMPONENT_TYPEDEF_STYLE == 'N' 710 typedef union { 711 struct { 712 uint32_t DUBS:24; /**< bit: 0..23 Channel x Destination Microblock Stride */ 713 uint32_t :8; /**< bit: 24..31 Reserved */ 714 } bit; /**< Structure used for bit access */ 715 uint32_t reg; /**< Type used for register access */ 716 } XDMAC_CDUS_Type; 717 #endif 718 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 719 720 #define XDMAC_CDUS_OFFSET (0x34) /**< (XDMAC_CDUS) Channel Destination Microblock Stride Offset */ 721 722 #define XDMAC_CDUS_DUBS_Pos 0 /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Position */ 723 #define XDMAC_CDUS_DUBS_Msk (_U_(0xFFFFFF) << XDMAC_CDUS_DUBS_Pos) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Mask */ 724 #define XDMAC_CDUS_DUBS(value) (XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)) 725 #define XDMAC_CDUS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CDUS) Register MASK (Use XDMAC_CDUS_Msk instead) */ 726 #define XDMAC_CDUS_Msk _U_(0xFFFFFF) /**< (XDMAC_CDUS) Register Mask */ 727 728 729 /* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) (R/ 32) Global Type Register -------- */ 730 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 731 #if COMPONENT_TYPEDEF_STYLE == 'N' 732 typedef union { 733 struct { 734 uint32_t NB_CH:5; /**< bit: 0..4 Number of Channels Minus One */ 735 uint32_t FIFO_SZ:11; /**< bit: 5..15 Number of Bytes */ 736 uint32_t NB_REQ:7; /**< bit: 16..22 Number of Peripheral Requests Minus One */ 737 uint32_t :9; /**< bit: 23..31 Reserved */ 738 } bit; /**< Structure used for bit access */ 739 uint32_t reg; /**< Type used for register access */ 740 } XDMAC_GTYPE_Type; 741 #endif 742 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 743 744 #define XDMAC_GTYPE_OFFSET (0x00) /**< (XDMAC_GTYPE) Global Type Register Offset */ 745 746 #define XDMAC_GTYPE_NB_CH_Pos 0 /**< (XDMAC_GTYPE) Number of Channels Minus One Position */ 747 #define XDMAC_GTYPE_NB_CH_Msk (_U_(0x1F) << XDMAC_GTYPE_NB_CH_Pos) /**< (XDMAC_GTYPE) Number of Channels Minus One Mask */ 748 #define XDMAC_GTYPE_NB_CH(value) (XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)) 749 #define XDMAC_GTYPE_FIFO_SZ_Pos 5 /**< (XDMAC_GTYPE) Number of Bytes Position */ 750 #define XDMAC_GTYPE_FIFO_SZ_Msk (_U_(0x7FF) << XDMAC_GTYPE_FIFO_SZ_Pos) /**< (XDMAC_GTYPE) Number of Bytes Mask */ 751 #define XDMAC_GTYPE_FIFO_SZ(value) (XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)) 752 #define XDMAC_GTYPE_NB_REQ_Pos 16 /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Position */ 753 #define XDMAC_GTYPE_NB_REQ_Msk (_U_(0x7F) << XDMAC_GTYPE_NB_REQ_Pos) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Mask */ 754 #define XDMAC_GTYPE_NB_REQ(value) (XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)) 755 #define XDMAC_GTYPE_MASK _U_(0x7FFFFF) /**< \deprecated (XDMAC_GTYPE) Register MASK (Use XDMAC_GTYPE_Msk instead) */ 756 #define XDMAC_GTYPE_Msk _U_(0x7FFFFF) /**< (XDMAC_GTYPE) Register Mask */ 757 758 759 /* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) (R/W 32) Global Configuration Register -------- */ 760 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 761 #if COMPONENT_TYPEDEF_STYLE == 'N' 762 typedef union { 763 struct { 764 uint32_t CGDISREG:1; /**< bit: 0 Configuration Registers Clock Gating Disable */ 765 uint32_t CGDISPIPE:1; /**< bit: 1 Pipeline Clock Gating Disable */ 766 uint32_t CGDISFIFO:1; /**< bit: 2 FIFO Clock Gating Disable */ 767 uint32_t CGDISIF:1; /**< bit: 3 Bus Interface Clock Gating Disable */ 768 uint32_t :4; /**< bit: 4..7 Reserved */ 769 uint32_t BXKBEN:1; /**< bit: 8 Boundary X Kilobyte Enable */ 770 uint32_t :23; /**< bit: 9..31 Reserved */ 771 } bit; /**< Structure used for bit access */ 772 uint32_t reg; /**< Type used for register access */ 773 } XDMAC_GCFG_Type; 774 #endif 775 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 776 777 #define XDMAC_GCFG_OFFSET (0x04) /**< (XDMAC_GCFG) Global Configuration Register Offset */ 778 779 #define XDMAC_GCFG_CGDISREG_Pos 0 /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Position */ 780 #define XDMAC_GCFG_CGDISREG_Msk (_U_(0x1) << XDMAC_GCFG_CGDISREG_Pos) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Mask */ 781 #define XDMAC_GCFG_CGDISREG XDMAC_GCFG_CGDISREG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISREG_Msk instead */ 782 #define XDMAC_GCFG_CGDISPIPE_Pos 1 /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Position */ 783 #define XDMAC_GCFG_CGDISPIPE_Msk (_U_(0x1) << XDMAC_GCFG_CGDISPIPE_Pos) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Mask */ 784 #define XDMAC_GCFG_CGDISPIPE XDMAC_GCFG_CGDISPIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISPIPE_Msk instead */ 785 #define XDMAC_GCFG_CGDISFIFO_Pos 2 /**< (XDMAC_GCFG) FIFO Clock Gating Disable Position */ 786 #define XDMAC_GCFG_CGDISFIFO_Msk (_U_(0x1) << XDMAC_GCFG_CGDISFIFO_Pos) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Mask */ 787 #define XDMAC_GCFG_CGDISFIFO XDMAC_GCFG_CGDISFIFO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISFIFO_Msk instead */ 788 #define XDMAC_GCFG_CGDISIF_Pos 3 /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Position */ 789 #define XDMAC_GCFG_CGDISIF_Msk (_U_(0x1) << XDMAC_GCFG_CGDISIF_Pos) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Mask */ 790 #define XDMAC_GCFG_CGDISIF XDMAC_GCFG_CGDISIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISIF_Msk instead */ 791 #define XDMAC_GCFG_BXKBEN_Pos 8 /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Position */ 792 #define XDMAC_GCFG_BXKBEN_Msk (_U_(0x1) << XDMAC_GCFG_BXKBEN_Pos) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Mask */ 793 #define XDMAC_GCFG_BXKBEN XDMAC_GCFG_BXKBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_BXKBEN_Msk instead */ 794 #define XDMAC_GCFG_MASK _U_(0x10F) /**< \deprecated (XDMAC_GCFG) Register MASK (Use XDMAC_GCFG_Msk instead) */ 795 #define XDMAC_GCFG_Msk _U_(0x10F) /**< (XDMAC_GCFG) Register Mask */ 796 797 798 /* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) (R/W 32) Global Weighted Arbiter Configuration Register -------- */ 799 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 800 #if COMPONENT_TYPEDEF_STYLE == 'N' 801 typedef union { 802 struct { 803 uint32_t PW0:4; /**< bit: 0..3 Pool Weight 0 */ 804 uint32_t PW1:4; /**< bit: 4..7 Pool Weight 1 */ 805 uint32_t PW2:4; /**< bit: 8..11 Pool Weight 2 */ 806 uint32_t PW3:4; /**< bit: 12..15 Pool Weight 3 */ 807 uint32_t :16; /**< bit: 16..31 Reserved */ 808 } bit; /**< Structure used for bit access */ 809 uint32_t reg; /**< Type used for register access */ 810 } XDMAC_GWAC_Type; 811 #endif 812 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 813 814 #define XDMAC_GWAC_OFFSET (0x08) /**< (XDMAC_GWAC) Global Weighted Arbiter Configuration Register Offset */ 815 816 #define XDMAC_GWAC_PW0_Pos 0 /**< (XDMAC_GWAC) Pool Weight 0 Position */ 817 #define XDMAC_GWAC_PW0_Msk (_U_(0xF) << XDMAC_GWAC_PW0_Pos) /**< (XDMAC_GWAC) Pool Weight 0 Mask */ 818 #define XDMAC_GWAC_PW0(value) (XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)) 819 #define XDMAC_GWAC_PW1_Pos 4 /**< (XDMAC_GWAC) Pool Weight 1 Position */ 820 #define XDMAC_GWAC_PW1_Msk (_U_(0xF) << XDMAC_GWAC_PW1_Pos) /**< (XDMAC_GWAC) Pool Weight 1 Mask */ 821 #define XDMAC_GWAC_PW1(value) (XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)) 822 #define XDMAC_GWAC_PW2_Pos 8 /**< (XDMAC_GWAC) Pool Weight 2 Position */ 823 #define XDMAC_GWAC_PW2_Msk (_U_(0xF) << XDMAC_GWAC_PW2_Pos) /**< (XDMAC_GWAC) Pool Weight 2 Mask */ 824 #define XDMAC_GWAC_PW2(value) (XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)) 825 #define XDMAC_GWAC_PW3_Pos 12 /**< (XDMAC_GWAC) Pool Weight 3 Position */ 826 #define XDMAC_GWAC_PW3_Msk (_U_(0xF) << XDMAC_GWAC_PW3_Pos) /**< (XDMAC_GWAC) Pool Weight 3 Mask */ 827 #define XDMAC_GWAC_PW3(value) (XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)) 828 #define XDMAC_GWAC_MASK _U_(0xFFFF) /**< \deprecated (XDMAC_GWAC) Register MASK (Use XDMAC_GWAC_Msk instead) */ 829 #define XDMAC_GWAC_Msk _U_(0xFFFF) /**< (XDMAC_GWAC) Register Mask */ 830 831 832 /* -------- XDMAC_GIE : (XDMAC Offset: 0x0c) (/W 32) Global Interrupt Enable Register -------- */ 833 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 834 #if COMPONENT_TYPEDEF_STYLE == 'N' 835 typedef union { 836 struct { 837 uint32_t IE0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Enable Bit */ 838 uint32_t IE1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Enable Bit */ 839 uint32_t IE2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Enable Bit */ 840 uint32_t IE3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Enable Bit */ 841 uint32_t IE4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Enable Bit */ 842 uint32_t IE5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Enable Bit */ 843 uint32_t IE6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Enable Bit */ 844 uint32_t IE7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Enable Bit */ 845 uint32_t IE8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Enable Bit */ 846 uint32_t IE9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Enable Bit */ 847 uint32_t IE10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Enable Bit */ 848 uint32_t IE11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Enable Bit */ 849 uint32_t IE12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Enable Bit */ 850 uint32_t IE13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Enable Bit */ 851 uint32_t IE14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Enable Bit */ 852 uint32_t IE15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Enable Bit */ 853 uint32_t IE16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Enable Bit */ 854 uint32_t IE17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Enable Bit */ 855 uint32_t IE18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Enable Bit */ 856 uint32_t IE19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Enable Bit */ 857 uint32_t IE20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Enable Bit */ 858 uint32_t IE21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Enable Bit */ 859 uint32_t IE22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Enable Bit */ 860 uint32_t IE23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Enable Bit */ 861 uint32_t :8; /**< bit: 24..31 Reserved */ 862 } bit; /**< Structure used for bit access */ 863 struct { 864 uint32_t IE:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Enable Bit */ 865 uint32_t :8; /**< bit: 24..31 Reserved */ 866 } vec; /**< Structure used for vec access */ 867 uint32_t reg; /**< Type used for register access */ 868 } XDMAC_GIE_Type; 869 #endif 870 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 871 872 #define XDMAC_GIE_OFFSET (0x0C) /**< (XDMAC_GIE) Global Interrupt Enable Register Offset */ 873 874 #define XDMAC_GIE_IE0_Pos 0 /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Position */ 875 #define XDMAC_GIE_IE0_Msk (_U_(0x1) << XDMAC_GIE_IE0_Pos) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Mask */ 876 #define XDMAC_GIE_IE0 XDMAC_GIE_IE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE0_Msk instead */ 877 #define XDMAC_GIE_IE1_Pos 1 /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Position */ 878 #define XDMAC_GIE_IE1_Msk (_U_(0x1) << XDMAC_GIE_IE1_Pos) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Mask */ 879 #define XDMAC_GIE_IE1 XDMAC_GIE_IE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE1_Msk instead */ 880 #define XDMAC_GIE_IE2_Pos 2 /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Position */ 881 #define XDMAC_GIE_IE2_Msk (_U_(0x1) << XDMAC_GIE_IE2_Pos) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Mask */ 882 #define XDMAC_GIE_IE2 XDMAC_GIE_IE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE2_Msk instead */ 883 #define XDMAC_GIE_IE3_Pos 3 /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Position */ 884 #define XDMAC_GIE_IE3_Msk (_U_(0x1) << XDMAC_GIE_IE3_Pos) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Mask */ 885 #define XDMAC_GIE_IE3 XDMAC_GIE_IE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE3_Msk instead */ 886 #define XDMAC_GIE_IE4_Pos 4 /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Position */ 887 #define XDMAC_GIE_IE4_Msk (_U_(0x1) << XDMAC_GIE_IE4_Pos) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Mask */ 888 #define XDMAC_GIE_IE4 XDMAC_GIE_IE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE4_Msk instead */ 889 #define XDMAC_GIE_IE5_Pos 5 /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Position */ 890 #define XDMAC_GIE_IE5_Msk (_U_(0x1) << XDMAC_GIE_IE5_Pos) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Mask */ 891 #define XDMAC_GIE_IE5 XDMAC_GIE_IE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE5_Msk instead */ 892 #define XDMAC_GIE_IE6_Pos 6 /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Position */ 893 #define XDMAC_GIE_IE6_Msk (_U_(0x1) << XDMAC_GIE_IE6_Pos) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Mask */ 894 #define XDMAC_GIE_IE6 XDMAC_GIE_IE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE6_Msk instead */ 895 #define XDMAC_GIE_IE7_Pos 7 /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Position */ 896 #define XDMAC_GIE_IE7_Msk (_U_(0x1) << XDMAC_GIE_IE7_Pos) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Mask */ 897 #define XDMAC_GIE_IE7 XDMAC_GIE_IE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE7_Msk instead */ 898 #define XDMAC_GIE_IE8_Pos 8 /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Position */ 899 #define XDMAC_GIE_IE8_Msk (_U_(0x1) << XDMAC_GIE_IE8_Pos) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Mask */ 900 #define XDMAC_GIE_IE8 XDMAC_GIE_IE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE8_Msk instead */ 901 #define XDMAC_GIE_IE9_Pos 9 /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Position */ 902 #define XDMAC_GIE_IE9_Msk (_U_(0x1) << XDMAC_GIE_IE9_Pos) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Mask */ 903 #define XDMAC_GIE_IE9 XDMAC_GIE_IE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE9_Msk instead */ 904 #define XDMAC_GIE_IE10_Pos 10 /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Position */ 905 #define XDMAC_GIE_IE10_Msk (_U_(0x1) << XDMAC_GIE_IE10_Pos) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Mask */ 906 #define XDMAC_GIE_IE10 XDMAC_GIE_IE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE10_Msk instead */ 907 #define XDMAC_GIE_IE11_Pos 11 /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Position */ 908 #define XDMAC_GIE_IE11_Msk (_U_(0x1) << XDMAC_GIE_IE11_Pos) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Mask */ 909 #define XDMAC_GIE_IE11 XDMAC_GIE_IE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE11_Msk instead */ 910 #define XDMAC_GIE_IE12_Pos 12 /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Position */ 911 #define XDMAC_GIE_IE12_Msk (_U_(0x1) << XDMAC_GIE_IE12_Pos) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Mask */ 912 #define XDMAC_GIE_IE12 XDMAC_GIE_IE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE12_Msk instead */ 913 #define XDMAC_GIE_IE13_Pos 13 /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Position */ 914 #define XDMAC_GIE_IE13_Msk (_U_(0x1) << XDMAC_GIE_IE13_Pos) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Mask */ 915 #define XDMAC_GIE_IE13 XDMAC_GIE_IE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE13_Msk instead */ 916 #define XDMAC_GIE_IE14_Pos 14 /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Position */ 917 #define XDMAC_GIE_IE14_Msk (_U_(0x1) << XDMAC_GIE_IE14_Pos) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Mask */ 918 #define XDMAC_GIE_IE14 XDMAC_GIE_IE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE14_Msk instead */ 919 #define XDMAC_GIE_IE15_Pos 15 /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Position */ 920 #define XDMAC_GIE_IE15_Msk (_U_(0x1) << XDMAC_GIE_IE15_Pos) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Mask */ 921 #define XDMAC_GIE_IE15 XDMAC_GIE_IE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE15_Msk instead */ 922 #define XDMAC_GIE_IE16_Pos 16 /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Position */ 923 #define XDMAC_GIE_IE16_Msk (_U_(0x1) << XDMAC_GIE_IE16_Pos) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Mask */ 924 #define XDMAC_GIE_IE16 XDMAC_GIE_IE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE16_Msk instead */ 925 #define XDMAC_GIE_IE17_Pos 17 /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Position */ 926 #define XDMAC_GIE_IE17_Msk (_U_(0x1) << XDMAC_GIE_IE17_Pos) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Mask */ 927 #define XDMAC_GIE_IE17 XDMAC_GIE_IE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE17_Msk instead */ 928 #define XDMAC_GIE_IE18_Pos 18 /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Position */ 929 #define XDMAC_GIE_IE18_Msk (_U_(0x1) << XDMAC_GIE_IE18_Pos) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Mask */ 930 #define XDMAC_GIE_IE18 XDMAC_GIE_IE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE18_Msk instead */ 931 #define XDMAC_GIE_IE19_Pos 19 /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Position */ 932 #define XDMAC_GIE_IE19_Msk (_U_(0x1) << XDMAC_GIE_IE19_Pos) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Mask */ 933 #define XDMAC_GIE_IE19 XDMAC_GIE_IE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE19_Msk instead */ 934 #define XDMAC_GIE_IE20_Pos 20 /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Position */ 935 #define XDMAC_GIE_IE20_Msk (_U_(0x1) << XDMAC_GIE_IE20_Pos) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Mask */ 936 #define XDMAC_GIE_IE20 XDMAC_GIE_IE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE20_Msk instead */ 937 #define XDMAC_GIE_IE21_Pos 21 /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Position */ 938 #define XDMAC_GIE_IE21_Msk (_U_(0x1) << XDMAC_GIE_IE21_Pos) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Mask */ 939 #define XDMAC_GIE_IE21 XDMAC_GIE_IE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE21_Msk instead */ 940 #define XDMAC_GIE_IE22_Pos 22 /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Position */ 941 #define XDMAC_GIE_IE22_Msk (_U_(0x1) << XDMAC_GIE_IE22_Pos) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Mask */ 942 #define XDMAC_GIE_IE22 XDMAC_GIE_IE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE22_Msk instead */ 943 #define XDMAC_GIE_IE23_Pos 23 /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Position */ 944 #define XDMAC_GIE_IE23_Msk (_U_(0x1) << XDMAC_GIE_IE23_Pos) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Mask */ 945 #define XDMAC_GIE_IE23 XDMAC_GIE_IE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE23_Msk instead */ 946 #define XDMAC_GIE_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIE) Register MASK (Use XDMAC_GIE_Msk instead) */ 947 #define XDMAC_GIE_Msk _U_(0xFFFFFF) /**< (XDMAC_GIE) Register Mask */ 948 949 #define XDMAC_GIE_IE_Pos 0 /**< (XDMAC_GIE Position) XDMAC Channel 23 Interrupt Enable Bit */ 950 #define XDMAC_GIE_IE_Msk (_U_(0xFFFFFF) << XDMAC_GIE_IE_Pos) /**< (XDMAC_GIE Mask) IE */ 951 #define XDMAC_GIE_IE(value) (XDMAC_GIE_IE_Msk & ((value) << XDMAC_GIE_IE_Pos)) 952 953 /* -------- XDMAC_GID : (XDMAC Offset: 0x10) (/W 32) Global Interrupt Disable Register -------- */ 954 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 955 #if COMPONENT_TYPEDEF_STYLE == 'N' 956 typedef union { 957 struct { 958 uint32_t ID0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Disable Bit */ 959 uint32_t ID1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Disable Bit */ 960 uint32_t ID2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Disable Bit */ 961 uint32_t ID3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Disable Bit */ 962 uint32_t ID4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Disable Bit */ 963 uint32_t ID5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Disable Bit */ 964 uint32_t ID6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Disable Bit */ 965 uint32_t ID7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Disable Bit */ 966 uint32_t ID8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Disable Bit */ 967 uint32_t ID9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Disable Bit */ 968 uint32_t ID10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Disable Bit */ 969 uint32_t ID11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Disable Bit */ 970 uint32_t ID12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Disable Bit */ 971 uint32_t ID13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Disable Bit */ 972 uint32_t ID14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Disable Bit */ 973 uint32_t ID15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Disable Bit */ 974 uint32_t ID16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Disable Bit */ 975 uint32_t ID17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Disable Bit */ 976 uint32_t ID18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Disable Bit */ 977 uint32_t ID19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Disable Bit */ 978 uint32_t ID20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Disable Bit */ 979 uint32_t ID21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Disable Bit */ 980 uint32_t ID22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Disable Bit */ 981 uint32_t ID23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Disable Bit */ 982 uint32_t :8; /**< bit: 24..31 Reserved */ 983 } bit; /**< Structure used for bit access */ 984 struct { 985 uint32_t ID:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Disable Bit */ 986 uint32_t :8; /**< bit: 24..31 Reserved */ 987 } vec; /**< Structure used for vec access */ 988 uint32_t reg; /**< Type used for register access */ 989 } XDMAC_GID_Type; 990 #endif 991 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 992 993 #define XDMAC_GID_OFFSET (0x10) /**< (XDMAC_GID) Global Interrupt Disable Register Offset */ 994 995 #define XDMAC_GID_ID0_Pos 0 /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Position */ 996 #define XDMAC_GID_ID0_Msk (_U_(0x1) << XDMAC_GID_ID0_Pos) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Mask */ 997 #define XDMAC_GID_ID0 XDMAC_GID_ID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID0_Msk instead */ 998 #define XDMAC_GID_ID1_Pos 1 /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Position */ 999 #define XDMAC_GID_ID1_Msk (_U_(0x1) << XDMAC_GID_ID1_Pos) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Mask */ 1000 #define XDMAC_GID_ID1 XDMAC_GID_ID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID1_Msk instead */ 1001 #define XDMAC_GID_ID2_Pos 2 /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Position */ 1002 #define XDMAC_GID_ID2_Msk (_U_(0x1) << XDMAC_GID_ID2_Pos) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Mask */ 1003 #define XDMAC_GID_ID2 XDMAC_GID_ID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID2_Msk instead */ 1004 #define XDMAC_GID_ID3_Pos 3 /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Position */ 1005 #define XDMAC_GID_ID3_Msk (_U_(0x1) << XDMAC_GID_ID3_Pos) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Mask */ 1006 #define XDMAC_GID_ID3 XDMAC_GID_ID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID3_Msk instead */ 1007 #define XDMAC_GID_ID4_Pos 4 /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Position */ 1008 #define XDMAC_GID_ID4_Msk (_U_(0x1) << XDMAC_GID_ID4_Pos) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Mask */ 1009 #define XDMAC_GID_ID4 XDMAC_GID_ID4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID4_Msk instead */ 1010 #define XDMAC_GID_ID5_Pos 5 /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Position */ 1011 #define XDMAC_GID_ID5_Msk (_U_(0x1) << XDMAC_GID_ID5_Pos) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Mask */ 1012 #define XDMAC_GID_ID5 XDMAC_GID_ID5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID5_Msk instead */ 1013 #define XDMAC_GID_ID6_Pos 6 /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Position */ 1014 #define XDMAC_GID_ID6_Msk (_U_(0x1) << XDMAC_GID_ID6_Pos) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Mask */ 1015 #define XDMAC_GID_ID6 XDMAC_GID_ID6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID6_Msk instead */ 1016 #define XDMAC_GID_ID7_Pos 7 /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Position */ 1017 #define XDMAC_GID_ID7_Msk (_U_(0x1) << XDMAC_GID_ID7_Pos) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Mask */ 1018 #define XDMAC_GID_ID7 XDMAC_GID_ID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID7_Msk instead */ 1019 #define XDMAC_GID_ID8_Pos 8 /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Position */ 1020 #define XDMAC_GID_ID8_Msk (_U_(0x1) << XDMAC_GID_ID8_Pos) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Mask */ 1021 #define XDMAC_GID_ID8 XDMAC_GID_ID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID8_Msk instead */ 1022 #define XDMAC_GID_ID9_Pos 9 /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Position */ 1023 #define XDMAC_GID_ID9_Msk (_U_(0x1) << XDMAC_GID_ID9_Pos) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Mask */ 1024 #define XDMAC_GID_ID9 XDMAC_GID_ID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID9_Msk instead */ 1025 #define XDMAC_GID_ID10_Pos 10 /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Position */ 1026 #define XDMAC_GID_ID10_Msk (_U_(0x1) << XDMAC_GID_ID10_Pos) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Mask */ 1027 #define XDMAC_GID_ID10 XDMAC_GID_ID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID10_Msk instead */ 1028 #define XDMAC_GID_ID11_Pos 11 /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Position */ 1029 #define XDMAC_GID_ID11_Msk (_U_(0x1) << XDMAC_GID_ID11_Pos) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Mask */ 1030 #define XDMAC_GID_ID11 XDMAC_GID_ID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID11_Msk instead */ 1031 #define XDMAC_GID_ID12_Pos 12 /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Position */ 1032 #define XDMAC_GID_ID12_Msk (_U_(0x1) << XDMAC_GID_ID12_Pos) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Mask */ 1033 #define XDMAC_GID_ID12 XDMAC_GID_ID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID12_Msk instead */ 1034 #define XDMAC_GID_ID13_Pos 13 /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Position */ 1035 #define XDMAC_GID_ID13_Msk (_U_(0x1) << XDMAC_GID_ID13_Pos) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Mask */ 1036 #define XDMAC_GID_ID13 XDMAC_GID_ID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID13_Msk instead */ 1037 #define XDMAC_GID_ID14_Pos 14 /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Position */ 1038 #define XDMAC_GID_ID14_Msk (_U_(0x1) << XDMAC_GID_ID14_Pos) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Mask */ 1039 #define XDMAC_GID_ID14 XDMAC_GID_ID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID14_Msk instead */ 1040 #define XDMAC_GID_ID15_Pos 15 /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Position */ 1041 #define XDMAC_GID_ID15_Msk (_U_(0x1) << XDMAC_GID_ID15_Pos) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Mask */ 1042 #define XDMAC_GID_ID15 XDMAC_GID_ID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID15_Msk instead */ 1043 #define XDMAC_GID_ID16_Pos 16 /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Position */ 1044 #define XDMAC_GID_ID16_Msk (_U_(0x1) << XDMAC_GID_ID16_Pos) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Mask */ 1045 #define XDMAC_GID_ID16 XDMAC_GID_ID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID16_Msk instead */ 1046 #define XDMAC_GID_ID17_Pos 17 /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Position */ 1047 #define XDMAC_GID_ID17_Msk (_U_(0x1) << XDMAC_GID_ID17_Pos) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Mask */ 1048 #define XDMAC_GID_ID17 XDMAC_GID_ID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID17_Msk instead */ 1049 #define XDMAC_GID_ID18_Pos 18 /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Position */ 1050 #define XDMAC_GID_ID18_Msk (_U_(0x1) << XDMAC_GID_ID18_Pos) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Mask */ 1051 #define XDMAC_GID_ID18 XDMAC_GID_ID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID18_Msk instead */ 1052 #define XDMAC_GID_ID19_Pos 19 /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Position */ 1053 #define XDMAC_GID_ID19_Msk (_U_(0x1) << XDMAC_GID_ID19_Pos) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Mask */ 1054 #define XDMAC_GID_ID19 XDMAC_GID_ID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID19_Msk instead */ 1055 #define XDMAC_GID_ID20_Pos 20 /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Position */ 1056 #define XDMAC_GID_ID20_Msk (_U_(0x1) << XDMAC_GID_ID20_Pos) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Mask */ 1057 #define XDMAC_GID_ID20 XDMAC_GID_ID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID20_Msk instead */ 1058 #define XDMAC_GID_ID21_Pos 21 /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Position */ 1059 #define XDMAC_GID_ID21_Msk (_U_(0x1) << XDMAC_GID_ID21_Pos) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Mask */ 1060 #define XDMAC_GID_ID21 XDMAC_GID_ID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID21_Msk instead */ 1061 #define XDMAC_GID_ID22_Pos 22 /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Position */ 1062 #define XDMAC_GID_ID22_Msk (_U_(0x1) << XDMAC_GID_ID22_Pos) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Mask */ 1063 #define XDMAC_GID_ID22 XDMAC_GID_ID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID22_Msk instead */ 1064 #define XDMAC_GID_ID23_Pos 23 /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Position */ 1065 #define XDMAC_GID_ID23_Msk (_U_(0x1) << XDMAC_GID_ID23_Pos) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Mask */ 1066 #define XDMAC_GID_ID23 XDMAC_GID_ID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID23_Msk instead */ 1067 #define XDMAC_GID_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GID) Register MASK (Use XDMAC_GID_Msk instead) */ 1068 #define XDMAC_GID_Msk _U_(0xFFFFFF) /**< (XDMAC_GID) Register Mask */ 1069 1070 #define XDMAC_GID_ID_Pos 0 /**< (XDMAC_GID Position) XDMAC Channel 23 Interrupt Disable Bit */ 1071 #define XDMAC_GID_ID_Msk (_U_(0xFFFFFF) << XDMAC_GID_ID_Pos) /**< (XDMAC_GID Mask) ID */ 1072 #define XDMAC_GID_ID(value) (XDMAC_GID_ID_Msk & ((value) << XDMAC_GID_ID_Pos)) 1073 1074 /* -------- XDMAC_GIM : (XDMAC Offset: 0x14) (R/ 32) Global Interrupt Mask Register -------- */ 1075 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1076 #if COMPONENT_TYPEDEF_STYLE == 'N' 1077 typedef union { 1078 struct { 1079 uint32_t IM0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Mask Bit */ 1080 uint32_t IM1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Mask Bit */ 1081 uint32_t IM2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Mask Bit */ 1082 uint32_t IM3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Mask Bit */ 1083 uint32_t IM4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Mask Bit */ 1084 uint32_t IM5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Mask Bit */ 1085 uint32_t IM6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Mask Bit */ 1086 uint32_t IM7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Mask Bit */ 1087 uint32_t IM8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Mask Bit */ 1088 uint32_t IM9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Mask Bit */ 1089 uint32_t IM10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Mask Bit */ 1090 uint32_t IM11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Mask Bit */ 1091 uint32_t IM12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Mask Bit */ 1092 uint32_t IM13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Mask Bit */ 1093 uint32_t IM14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Mask Bit */ 1094 uint32_t IM15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Mask Bit */ 1095 uint32_t IM16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Mask Bit */ 1096 uint32_t IM17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Mask Bit */ 1097 uint32_t IM18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Mask Bit */ 1098 uint32_t IM19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Mask Bit */ 1099 uint32_t IM20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Mask Bit */ 1100 uint32_t IM21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Mask Bit */ 1101 uint32_t IM22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Mask Bit */ 1102 uint32_t IM23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Mask Bit */ 1103 uint32_t :8; /**< bit: 24..31 Reserved */ 1104 } bit; /**< Structure used for bit access */ 1105 struct { 1106 uint32_t IM:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Mask Bit */ 1107 uint32_t :8; /**< bit: 24..31 Reserved */ 1108 } vec; /**< Structure used for vec access */ 1109 uint32_t reg; /**< Type used for register access */ 1110 } XDMAC_GIM_Type; 1111 #endif 1112 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1113 1114 #define XDMAC_GIM_OFFSET (0x14) /**< (XDMAC_GIM) Global Interrupt Mask Register Offset */ 1115 1116 #define XDMAC_GIM_IM0_Pos 0 /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Position */ 1117 #define XDMAC_GIM_IM0_Msk (_U_(0x1) << XDMAC_GIM_IM0_Pos) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Mask */ 1118 #define XDMAC_GIM_IM0 XDMAC_GIM_IM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM0_Msk instead */ 1119 #define XDMAC_GIM_IM1_Pos 1 /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Position */ 1120 #define XDMAC_GIM_IM1_Msk (_U_(0x1) << XDMAC_GIM_IM1_Pos) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Mask */ 1121 #define XDMAC_GIM_IM1 XDMAC_GIM_IM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM1_Msk instead */ 1122 #define XDMAC_GIM_IM2_Pos 2 /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Position */ 1123 #define XDMAC_GIM_IM2_Msk (_U_(0x1) << XDMAC_GIM_IM2_Pos) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Mask */ 1124 #define XDMAC_GIM_IM2 XDMAC_GIM_IM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM2_Msk instead */ 1125 #define XDMAC_GIM_IM3_Pos 3 /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Position */ 1126 #define XDMAC_GIM_IM3_Msk (_U_(0x1) << XDMAC_GIM_IM3_Pos) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Mask */ 1127 #define XDMAC_GIM_IM3 XDMAC_GIM_IM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM3_Msk instead */ 1128 #define XDMAC_GIM_IM4_Pos 4 /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Position */ 1129 #define XDMAC_GIM_IM4_Msk (_U_(0x1) << XDMAC_GIM_IM4_Pos) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Mask */ 1130 #define XDMAC_GIM_IM4 XDMAC_GIM_IM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM4_Msk instead */ 1131 #define XDMAC_GIM_IM5_Pos 5 /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Position */ 1132 #define XDMAC_GIM_IM5_Msk (_U_(0x1) << XDMAC_GIM_IM5_Pos) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Mask */ 1133 #define XDMAC_GIM_IM5 XDMAC_GIM_IM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM5_Msk instead */ 1134 #define XDMAC_GIM_IM6_Pos 6 /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Position */ 1135 #define XDMAC_GIM_IM6_Msk (_U_(0x1) << XDMAC_GIM_IM6_Pos) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Mask */ 1136 #define XDMAC_GIM_IM6 XDMAC_GIM_IM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM6_Msk instead */ 1137 #define XDMAC_GIM_IM7_Pos 7 /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Position */ 1138 #define XDMAC_GIM_IM7_Msk (_U_(0x1) << XDMAC_GIM_IM7_Pos) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Mask */ 1139 #define XDMAC_GIM_IM7 XDMAC_GIM_IM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM7_Msk instead */ 1140 #define XDMAC_GIM_IM8_Pos 8 /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Position */ 1141 #define XDMAC_GIM_IM8_Msk (_U_(0x1) << XDMAC_GIM_IM8_Pos) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Mask */ 1142 #define XDMAC_GIM_IM8 XDMAC_GIM_IM8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM8_Msk instead */ 1143 #define XDMAC_GIM_IM9_Pos 9 /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Position */ 1144 #define XDMAC_GIM_IM9_Msk (_U_(0x1) << XDMAC_GIM_IM9_Pos) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Mask */ 1145 #define XDMAC_GIM_IM9 XDMAC_GIM_IM9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM9_Msk instead */ 1146 #define XDMAC_GIM_IM10_Pos 10 /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Position */ 1147 #define XDMAC_GIM_IM10_Msk (_U_(0x1) << XDMAC_GIM_IM10_Pos) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Mask */ 1148 #define XDMAC_GIM_IM10 XDMAC_GIM_IM10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM10_Msk instead */ 1149 #define XDMAC_GIM_IM11_Pos 11 /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Position */ 1150 #define XDMAC_GIM_IM11_Msk (_U_(0x1) << XDMAC_GIM_IM11_Pos) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Mask */ 1151 #define XDMAC_GIM_IM11 XDMAC_GIM_IM11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM11_Msk instead */ 1152 #define XDMAC_GIM_IM12_Pos 12 /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Position */ 1153 #define XDMAC_GIM_IM12_Msk (_U_(0x1) << XDMAC_GIM_IM12_Pos) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Mask */ 1154 #define XDMAC_GIM_IM12 XDMAC_GIM_IM12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM12_Msk instead */ 1155 #define XDMAC_GIM_IM13_Pos 13 /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Position */ 1156 #define XDMAC_GIM_IM13_Msk (_U_(0x1) << XDMAC_GIM_IM13_Pos) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Mask */ 1157 #define XDMAC_GIM_IM13 XDMAC_GIM_IM13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM13_Msk instead */ 1158 #define XDMAC_GIM_IM14_Pos 14 /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Position */ 1159 #define XDMAC_GIM_IM14_Msk (_U_(0x1) << XDMAC_GIM_IM14_Pos) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Mask */ 1160 #define XDMAC_GIM_IM14 XDMAC_GIM_IM14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM14_Msk instead */ 1161 #define XDMAC_GIM_IM15_Pos 15 /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Position */ 1162 #define XDMAC_GIM_IM15_Msk (_U_(0x1) << XDMAC_GIM_IM15_Pos) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Mask */ 1163 #define XDMAC_GIM_IM15 XDMAC_GIM_IM15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM15_Msk instead */ 1164 #define XDMAC_GIM_IM16_Pos 16 /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Position */ 1165 #define XDMAC_GIM_IM16_Msk (_U_(0x1) << XDMAC_GIM_IM16_Pos) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Mask */ 1166 #define XDMAC_GIM_IM16 XDMAC_GIM_IM16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM16_Msk instead */ 1167 #define XDMAC_GIM_IM17_Pos 17 /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Position */ 1168 #define XDMAC_GIM_IM17_Msk (_U_(0x1) << XDMAC_GIM_IM17_Pos) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Mask */ 1169 #define XDMAC_GIM_IM17 XDMAC_GIM_IM17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM17_Msk instead */ 1170 #define XDMAC_GIM_IM18_Pos 18 /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Position */ 1171 #define XDMAC_GIM_IM18_Msk (_U_(0x1) << XDMAC_GIM_IM18_Pos) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Mask */ 1172 #define XDMAC_GIM_IM18 XDMAC_GIM_IM18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM18_Msk instead */ 1173 #define XDMAC_GIM_IM19_Pos 19 /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Position */ 1174 #define XDMAC_GIM_IM19_Msk (_U_(0x1) << XDMAC_GIM_IM19_Pos) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Mask */ 1175 #define XDMAC_GIM_IM19 XDMAC_GIM_IM19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM19_Msk instead */ 1176 #define XDMAC_GIM_IM20_Pos 20 /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Position */ 1177 #define XDMAC_GIM_IM20_Msk (_U_(0x1) << XDMAC_GIM_IM20_Pos) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Mask */ 1178 #define XDMAC_GIM_IM20 XDMAC_GIM_IM20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM20_Msk instead */ 1179 #define XDMAC_GIM_IM21_Pos 21 /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Position */ 1180 #define XDMAC_GIM_IM21_Msk (_U_(0x1) << XDMAC_GIM_IM21_Pos) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Mask */ 1181 #define XDMAC_GIM_IM21 XDMAC_GIM_IM21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM21_Msk instead */ 1182 #define XDMAC_GIM_IM22_Pos 22 /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Position */ 1183 #define XDMAC_GIM_IM22_Msk (_U_(0x1) << XDMAC_GIM_IM22_Pos) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Mask */ 1184 #define XDMAC_GIM_IM22 XDMAC_GIM_IM22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM22_Msk instead */ 1185 #define XDMAC_GIM_IM23_Pos 23 /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Position */ 1186 #define XDMAC_GIM_IM23_Msk (_U_(0x1) << XDMAC_GIM_IM23_Pos) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Mask */ 1187 #define XDMAC_GIM_IM23 XDMAC_GIM_IM23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM23_Msk instead */ 1188 #define XDMAC_GIM_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIM) Register MASK (Use XDMAC_GIM_Msk instead) */ 1189 #define XDMAC_GIM_Msk _U_(0xFFFFFF) /**< (XDMAC_GIM) Register Mask */ 1190 1191 #define XDMAC_GIM_IM_Pos 0 /**< (XDMAC_GIM Position) XDMAC Channel 23 Interrupt Mask Bit */ 1192 #define XDMAC_GIM_IM_Msk (_U_(0xFFFFFF) << XDMAC_GIM_IM_Pos) /**< (XDMAC_GIM Mask) IM */ 1193 #define XDMAC_GIM_IM(value) (XDMAC_GIM_IM_Msk & ((value) << XDMAC_GIM_IM_Pos)) 1194 1195 /* -------- XDMAC_GIS : (XDMAC Offset: 0x18) (R/ 32) Global Interrupt Status Register -------- */ 1196 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1197 #if COMPONENT_TYPEDEF_STYLE == 'N' 1198 typedef union { 1199 struct { 1200 uint32_t IS0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Status Bit */ 1201 uint32_t IS1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Status Bit */ 1202 uint32_t IS2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Status Bit */ 1203 uint32_t IS3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Status Bit */ 1204 uint32_t IS4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Status Bit */ 1205 uint32_t IS5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Status Bit */ 1206 uint32_t IS6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Status Bit */ 1207 uint32_t IS7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Status Bit */ 1208 uint32_t IS8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Status Bit */ 1209 uint32_t IS9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Status Bit */ 1210 uint32_t IS10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Status Bit */ 1211 uint32_t IS11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Status Bit */ 1212 uint32_t IS12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Status Bit */ 1213 uint32_t IS13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Status Bit */ 1214 uint32_t IS14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Status Bit */ 1215 uint32_t IS15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Status Bit */ 1216 uint32_t IS16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Status Bit */ 1217 uint32_t IS17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Status Bit */ 1218 uint32_t IS18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Status Bit */ 1219 uint32_t IS19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Status Bit */ 1220 uint32_t IS20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Status Bit */ 1221 uint32_t IS21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Status Bit */ 1222 uint32_t IS22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Status Bit */ 1223 uint32_t IS23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Status Bit */ 1224 uint32_t :8; /**< bit: 24..31 Reserved */ 1225 } bit; /**< Structure used for bit access */ 1226 struct { 1227 uint32_t IS:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Status Bit */ 1228 uint32_t :8; /**< bit: 24..31 Reserved */ 1229 } vec; /**< Structure used for vec access */ 1230 uint32_t reg; /**< Type used for register access */ 1231 } XDMAC_GIS_Type; 1232 #endif 1233 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1234 1235 #define XDMAC_GIS_OFFSET (0x18) /**< (XDMAC_GIS) Global Interrupt Status Register Offset */ 1236 1237 #define XDMAC_GIS_IS0_Pos 0 /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Position */ 1238 #define XDMAC_GIS_IS0_Msk (_U_(0x1) << XDMAC_GIS_IS0_Pos) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Mask */ 1239 #define XDMAC_GIS_IS0 XDMAC_GIS_IS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS0_Msk instead */ 1240 #define XDMAC_GIS_IS1_Pos 1 /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Position */ 1241 #define XDMAC_GIS_IS1_Msk (_U_(0x1) << XDMAC_GIS_IS1_Pos) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Mask */ 1242 #define XDMAC_GIS_IS1 XDMAC_GIS_IS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS1_Msk instead */ 1243 #define XDMAC_GIS_IS2_Pos 2 /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Position */ 1244 #define XDMAC_GIS_IS2_Msk (_U_(0x1) << XDMAC_GIS_IS2_Pos) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Mask */ 1245 #define XDMAC_GIS_IS2 XDMAC_GIS_IS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS2_Msk instead */ 1246 #define XDMAC_GIS_IS3_Pos 3 /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Position */ 1247 #define XDMAC_GIS_IS3_Msk (_U_(0x1) << XDMAC_GIS_IS3_Pos) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Mask */ 1248 #define XDMAC_GIS_IS3 XDMAC_GIS_IS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS3_Msk instead */ 1249 #define XDMAC_GIS_IS4_Pos 4 /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Position */ 1250 #define XDMAC_GIS_IS4_Msk (_U_(0x1) << XDMAC_GIS_IS4_Pos) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Mask */ 1251 #define XDMAC_GIS_IS4 XDMAC_GIS_IS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS4_Msk instead */ 1252 #define XDMAC_GIS_IS5_Pos 5 /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Position */ 1253 #define XDMAC_GIS_IS5_Msk (_U_(0x1) << XDMAC_GIS_IS5_Pos) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Mask */ 1254 #define XDMAC_GIS_IS5 XDMAC_GIS_IS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS5_Msk instead */ 1255 #define XDMAC_GIS_IS6_Pos 6 /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Position */ 1256 #define XDMAC_GIS_IS6_Msk (_U_(0x1) << XDMAC_GIS_IS6_Pos) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Mask */ 1257 #define XDMAC_GIS_IS6 XDMAC_GIS_IS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS6_Msk instead */ 1258 #define XDMAC_GIS_IS7_Pos 7 /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Position */ 1259 #define XDMAC_GIS_IS7_Msk (_U_(0x1) << XDMAC_GIS_IS7_Pos) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Mask */ 1260 #define XDMAC_GIS_IS7 XDMAC_GIS_IS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS7_Msk instead */ 1261 #define XDMAC_GIS_IS8_Pos 8 /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Position */ 1262 #define XDMAC_GIS_IS8_Msk (_U_(0x1) << XDMAC_GIS_IS8_Pos) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Mask */ 1263 #define XDMAC_GIS_IS8 XDMAC_GIS_IS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS8_Msk instead */ 1264 #define XDMAC_GIS_IS9_Pos 9 /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Position */ 1265 #define XDMAC_GIS_IS9_Msk (_U_(0x1) << XDMAC_GIS_IS9_Pos) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Mask */ 1266 #define XDMAC_GIS_IS9 XDMAC_GIS_IS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS9_Msk instead */ 1267 #define XDMAC_GIS_IS10_Pos 10 /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Position */ 1268 #define XDMAC_GIS_IS10_Msk (_U_(0x1) << XDMAC_GIS_IS10_Pos) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Mask */ 1269 #define XDMAC_GIS_IS10 XDMAC_GIS_IS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS10_Msk instead */ 1270 #define XDMAC_GIS_IS11_Pos 11 /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Position */ 1271 #define XDMAC_GIS_IS11_Msk (_U_(0x1) << XDMAC_GIS_IS11_Pos) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Mask */ 1272 #define XDMAC_GIS_IS11 XDMAC_GIS_IS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS11_Msk instead */ 1273 #define XDMAC_GIS_IS12_Pos 12 /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Position */ 1274 #define XDMAC_GIS_IS12_Msk (_U_(0x1) << XDMAC_GIS_IS12_Pos) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Mask */ 1275 #define XDMAC_GIS_IS12 XDMAC_GIS_IS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS12_Msk instead */ 1276 #define XDMAC_GIS_IS13_Pos 13 /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Position */ 1277 #define XDMAC_GIS_IS13_Msk (_U_(0x1) << XDMAC_GIS_IS13_Pos) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Mask */ 1278 #define XDMAC_GIS_IS13 XDMAC_GIS_IS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS13_Msk instead */ 1279 #define XDMAC_GIS_IS14_Pos 14 /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Position */ 1280 #define XDMAC_GIS_IS14_Msk (_U_(0x1) << XDMAC_GIS_IS14_Pos) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Mask */ 1281 #define XDMAC_GIS_IS14 XDMAC_GIS_IS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS14_Msk instead */ 1282 #define XDMAC_GIS_IS15_Pos 15 /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Position */ 1283 #define XDMAC_GIS_IS15_Msk (_U_(0x1) << XDMAC_GIS_IS15_Pos) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Mask */ 1284 #define XDMAC_GIS_IS15 XDMAC_GIS_IS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS15_Msk instead */ 1285 #define XDMAC_GIS_IS16_Pos 16 /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Position */ 1286 #define XDMAC_GIS_IS16_Msk (_U_(0x1) << XDMAC_GIS_IS16_Pos) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Mask */ 1287 #define XDMAC_GIS_IS16 XDMAC_GIS_IS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS16_Msk instead */ 1288 #define XDMAC_GIS_IS17_Pos 17 /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Position */ 1289 #define XDMAC_GIS_IS17_Msk (_U_(0x1) << XDMAC_GIS_IS17_Pos) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Mask */ 1290 #define XDMAC_GIS_IS17 XDMAC_GIS_IS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS17_Msk instead */ 1291 #define XDMAC_GIS_IS18_Pos 18 /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Position */ 1292 #define XDMAC_GIS_IS18_Msk (_U_(0x1) << XDMAC_GIS_IS18_Pos) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Mask */ 1293 #define XDMAC_GIS_IS18 XDMAC_GIS_IS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS18_Msk instead */ 1294 #define XDMAC_GIS_IS19_Pos 19 /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Position */ 1295 #define XDMAC_GIS_IS19_Msk (_U_(0x1) << XDMAC_GIS_IS19_Pos) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Mask */ 1296 #define XDMAC_GIS_IS19 XDMAC_GIS_IS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS19_Msk instead */ 1297 #define XDMAC_GIS_IS20_Pos 20 /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Position */ 1298 #define XDMAC_GIS_IS20_Msk (_U_(0x1) << XDMAC_GIS_IS20_Pos) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Mask */ 1299 #define XDMAC_GIS_IS20 XDMAC_GIS_IS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS20_Msk instead */ 1300 #define XDMAC_GIS_IS21_Pos 21 /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Position */ 1301 #define XDMAC_GIS_IS21_Msk (_U_(0x1) << XDMAC_GIS_IS21_Pos) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Mask */ 1302 #define XDMAC_GIS_IS21 XDMAC_GIS_IS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS21_Msk instead */ 1303 #define XDMAC_GIS_IS22_Pos 22 /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Position */ 1304 #define XDMAC_GIS_IS22_Msk (_U_(0x1) << XDMAC_GIS_IS22_Pos) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Mask */ 1305 #define XDMAC_GIS_IS22 XDMAC_GIS_IS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS22_Msk instead */ 1306 #define XDMAC_GIS_IS23_Pos 23 /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Position */ 1307 #define XDMAC_GIS_IS23_Msk (_U_(0x1) << XDMAC_GIS_IS23_Pos) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Mask */ 1308 #define XDMAC_GIS_IS23 XDMAC_GIS_IS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS23_Msk instead */ 1309 #define XDMAC_GIS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIS) Register MASK (Use XDMAC_GIS_Msk instead) */ 1310 #define XDMAC_GIS_Msk _U_(0xFFFFFF) /**< (XDMAC_GIS) Register Mask */ 1311 1312 #define XDMAC_GIS_IS_Pos 0 /**< (XDMAC_GIS Position) XDMAC Channel 23 Interrupt Status Bit */ 1313 #define XDMAC_GIS_IS_Msk (_U_(0xFFFFFF) << XDMAC_GIS_IS_Pos) /**< (XDMAC_GIS Mask) IS */ 1314 #define XDMAC_GIS_IS(value) (XDMAC_GIS_IS_Msk & ((value) << XDMAC_GIS_IS_Pos)) 1315 1316 /* -------- XDMAC_GE : (XDMAC Offset: 0x1c) (/W 32) Global Channel Enable Register -------- */ 1317 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1318 #if COMPONENT_TYPEDEF_STYLE == 'N' 1319 typedef union { 1320 struct { 1321 uint32_t EN0:1; /**< bit: 0 XDMAC Channel 0 Enable Bit */ 1322 uint32_t EN1:1; /**< bit: 1 XDMAC Channel 1 Enable Bit */ 1323 uint32_t EN2:1; /**< bit: 2 XDMAC Channel 2 Enable Bit */ 1324 uint32_t EN3:1; /**< bit: 3 XDMAC Channel 3 Enable Bit */ 1325 uint32_t EN4:1; /**< bit: 4 XDMAC Channel 4 Enable Bit */ 1326 uint32_t EN5:1; /**< bit: 5 XDMAC Channel 5 Enable Bit */ 1327 uint32_t EN6:1; /**< bit: 6 XDMAC Channel 6 Enable Bit */ 1328 uint32_t EN7:1; /**< bit: 7 XDMAC Channel 7 Enable Bit */ 1329 uint32_t EN8:1; /**< bit: 8 XDMAC Channel 8 Enable Bit */ 1330 uint32_t EN9:1; /**< bit: 9 XDMAC Channel 9 Enable Bit */ 1331 uint32_t EN10:1; /**< bit: 10 XDMAC Channel 10 Enable Bit */ 1332 uint32_t EN11:1; /**< bit: 11 XDMAC Channel 11 Enable Bit */ 1333 uint32_t EN12:1; /**< bit: 12 XDMAC Channel 12 Enable Bit */ 1334 uint32_t EN13:1; /**< bit: 13 XDMAC Channel 13 Enable Bit */ 1335 uint32_t EN14:1; /**< bit: 14 XDMAC Channel 14 Enable Bit */ 1336 uint32_t EN15:1; /**< bit: 15 XDMAC Channel 15 Enable Bit */ 1337 uint32_t EN16:1; /**< bit: 16 XDMAC Channel 16 Enable Bit */ 1338 uint32_t EN17:1; /**< bit: 17 XDMAC Channel 17 Enable Bit */ 1339 uint32_t EN18:1; /**< bit: 18 XDMAC Channel 18 Enable Bit */ 1340 uint32_t EN19:1; /**< bit: 19 XDMAC Channel 19 Enable Bit */ 1341 uint32_t EN20:1; /**< bit: 20 XDMAC Channel 20 Enable Bit */ 1342 uint32_t EN21:1; /**< bit: 21 XDMAC Channel 21 Enable Bit */ 1343 uint32_t EN22:1; /**< bit: 22 XDMAC Channel 22 Enable Bit */ 1344 uint32_t EN23:1; /**< bit: 23 XDMAC Channel 23 Enable Bit */ 1345 uint32_t :8; /**< bit: 24..31 Reserved */ 1346 } bit; /**< Structure used for bit access */ 1347 struct { 1348 uint32_t EN:24; /**< bit: 0..23 XDMAC Channel 23 Enable Bit */ 1349 uint32_t :8; /**< bit: 24..31 Reserved */ 1350 } vec; /**< Structure used for vec access */ 1351 uint32_t reg; /**< Type used for register access */ 1352 } XDMAC_GE_Type; 1353 #endif 1354 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1355 1356 #define XDMAC_GE_OFFSET (0x1C) /**< (XDMAC_GE) Global Channel Enable Register Offset */ 1357 1358 #define XDMAC_GE_EN0_Pos 0 /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Position */ 1359 #define XDMAC_GE_EN0_Msk (_U_(0x1) << XDMAC_GE_EN0_Pos) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Mask */ 1360 #define XDMAC_GE_EN0 XDMAC_GE_EN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN0_Msk instead */ 1361 #define XDMAC_GE_EN1_Pos 1 /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Position */ 1362 #define XDMAC_GE_EN1_Msk (_U_(0x1) << XDMAC_GE_EN1_Pos) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Mask */ 1363 #define XDMAC_GE_EN1 XDMAC_GE_EN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN1_Msk instead */ 1364 #define XDMAC_GE_EN2_Pos 2 /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Position */ 1365 #define XDMAC_GE_EN2_Msk (_U_(0x1) << XDMAC_GE_EN2_Pos) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Mask */ 1366 #define XDMAC_GE_EN2 XDMAC_GE_EN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN2_Msk instead */ 1367 #define XDMAC_GE_EN3_Pos 3 /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Position */ 1368 #define XDMAC_GE_EN3_Msk (_U_(0x1) << XDMAC_GE_EN3_Pos) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Mask */ 1369 #define XDMAC_GE_EN3 XDMAC_GE_EN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN3_Msk instead */ 1370 #define XDMAC_GE_EN4_Pos 4 /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Position */ 1371 #define XDMAC_GE_EN4_Msk (_U_(0x1) << XDMAC_GE_EN4_Pos) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Mask */ 1372 #define XDMAC_GE_EN4 XDMAC_GE_EN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN4_Msk instead */ 1373 #define XDMAC_GE_EN5_Pos 5 /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Position */ 1374 #define XDMAC_GE_EN5_Msk (_U_(0x1) << XDMAC_GE_EN5_Pos) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Mask */ 1375 #define XDMAC_GE_EN5 XDMAC_GE_EN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN5_Msk instead */ 1376 #define XDMAC_GE_EN6_Pos 6 /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Position */ 1377 #define XDMAC_GE_EN6_Msk (_U_(0x1) << XDMAC_GE_EN6_Pos) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Mask */ 1378 #define XDMAC_GE_EN6 XDMAC_GE_EN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN6_Msk instead */ 1379 #define XDMAC_GE_EN7_Pos 7 /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Position */ 1380 #define XDMAC_GE_EN7_Msk (_U_(0x1) << XDMAC_GE_EN7_Pos) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Mask */ 1381 #define XDMAC_GE_EN7 XDMAC_GE_EN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN7_Msk instead */ 1382 #define XDMAC_GE_EN8_Pos 8 /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Position */ 1383 #define XDMAC_GE_EN8_Msk (_U_(0x1) << XDMAC_GE_EN8_Pos) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Mask */ 1384 #define XDMAC_GE_EN8 XDMAC_GE_EN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN8_Msk instead */ 1385 #define XDMAC_GE_EN9_Pos 9 /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Position */ 1386 #define XDMAC_GE_EN9_Msk (_U_(0x1) << XDMAC_GE_EN9_Pos) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Mask */ 1387 #define XDMAC_GE_EN9 XDMAC_GE_EN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN9_Msk instead */ 1388 #define XDMAC_GE_EN10_Pos 10 /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Position */ 1389 #define XDMAC_GE_EN10_Msk (_U_(0x1) << XDMAC_GE_EN10_Pos) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Mask */ 1390 #define XDMAC_GE_EN10 XDMAC_GE_EN10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN10_Msk instead */ 1391 #define XDMAC_GE_EN11_Pos 11 /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Position */ 1392 #define XDMAC_GE_EN11_Msk (_U_(0x1) << XDMAC_GE_EN11_Pos) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Mask */ 1393 #define XDMAC_GE_EN11 XDMAC_GE_EN11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN11_Msk instead */ 1394 #define XDMAC_GE_EN12_Pos 12 /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Position */ 1395 #define XDMAC_GE_EN12_Msk (_U_(0x1) << XDMAC_GE_EN12_Pos) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Mask */ 1396 #define XDMAC_GE_EN12 XDMAC_GE_EN12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN12_Msk instead */ 1397 #define XDMAC_GE_EN13_Pos 13 /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Position */ 1398 #define XDMAC_GE_EN13_Msk (_U_(0x1) << XDMAC_GE_EN13_Pos) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Mask */ 1399 #define XDMAC_GE_EN13 XDMAC_GE_EN13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN13_Msk instead */ 1400 #define XDMAC_GE_EN14_Pos 14 /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Position */ 1401 #define XDMAC_GE_EN14_Msk (_U_(0x1) << XDMAC_GE_EN14_Pos) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Mask */ 1402 #define XDMAC_GE_EN14 XDMAC_GE_EN14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN14_Msk instead */ 1403 #define XDMAC_GE_EN15_Pos 15 /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Position */ 1404 #define XDMAC_GE_EN15_Msk (_U_(0x1) << XDMAC_GE_EN15_Pos) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Mask */ 1405 #define XDMAC_GE_EN15 XDMAC_GE_EN15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN15_Msk instead */ 1406 #define XDMAC_GE_EN16_Pos 16 /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Position */ 1407 #define XDMAC_GE_EN16_Msk (_U_(0x1) << XDMAC_GE_EN16_Pos) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Mask */ 1408 #define XDMAC_GE_EN16 XDMAC_GE_EN16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN16_Msk instead */ 1409 #define XDMAC_GE_EN17_Pos 17 /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Position */ 1410 #define XDMAC_GE_EN17_Msk (_U_(0x1) << XDMAC_GE_EN17_Pos) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Mask */ 1411 #define XDMAC_GE_EN17 XDMAC_GE_EN17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN17_Msk instead */ 1412 #define XDMAC_GE_EN18_Pos 18 /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Position */ 1413 #define XDMAC_GE_EN18_Msk (_U_(0x1) << XDMAC_GE_EN18_Pos) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Mask */ 1414 #define XDMAC_GE_EN18 XDMAC_GE_EN18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN18_Msk instead */ 1415 #define XDMAC_GE_EN19_Pos 19 /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Position */ 1416 #define XDMAC_GE_EN19_Msk (_U_(0x1) << XDMAC_GE_EN19_Pos) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Mask */ 1417 #define XDMAC_GE_EN19 XDMAC_GE_EN19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN19_Msk instead */ 1418 #define XDMAC_GE_EN20_Pos 20 /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Position */ 1419 #define XDMAC_GE_EN20_Msk (_U_(0x1) << XDMAC_GE_EN20_Pos) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Mask */ 1420 #define XDMAC_GE_EN20 XDMAC_GE_EN20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN20_Msk instead */ 1421 #define XDMAC_GE_EN21_Pos 21 /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Position */ 1422 #define XDMAC_GE_EN21_Msk (_U_(0x1) << XDMAC_GE_EN21_Pos) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Mask */ 1423 #define XDMAC_GE_EN21 XDMAC_GE_EN21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN21_Msk instead */ 1424 #define XDMAC_GE_EN22_Pos 22 /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Position */ 1425 #define XDMAC_GE_EN22_Msk (_U_(0x1) << XDMAC_GE_EN22_Pos) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Mask */ 1426 #define XDMAC_GE_EN22 XDMAC_GE_EN22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN22_Msk instead */ 1427 #define XDMAC_GE_EN23_Pos 23 /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Position */ 1428 #define XDMAC_GE_EN23_Msk (_U_(0x1) << XDMAC_GE_EN23_Pos) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Mask */ 1429 #define XDMAC_GE_EN23 XDMAC_GE_EN23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN23_Msk instead */ 1430 #define XDMAC_GE_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GE) Register MASK (Use XDMAC_GE_Msk instead) */ 1431 #define XDMAC_GE_Msk _U_(0xFFFFFF) /**< (XDMAC_GE) Register Mask */ 1432 1433 #define XDMAC_GE_EN_Pos 0 /**< (XDMAC_GE Position) XDMAC Channel 23 Enable Bit */ 1434 #define XDMAC_GE_EN_Msk (_U_(0xFFFFFF) << XDMAC_GE_EN_Pos) /**< (XDMAC_GE Mask) EN */ 1435 #define XDMAC_GE_EN(value) (XDMAC_GE_EN_Msk & ((value) << XDMAC_GE_EN_Pos)) 1436 1437 /* -------- XDMAC_GD : (XDMAC Offset: 0x20) (/W 32) Global Channel Disable Register -------- */ 1438 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1439 #if COMPONENT_TYPEDEF_STYLE == 'N' 1440 typedef union { 1441 struct { 1442 uint32_t DI0:1; /**< bit: 0 XDMAC Channel 0 Disable Bit */ 1443 uint32_t DI1:1; /**< bit: 1 XDMAC Channel 1 Disable Bit */ 1444 uint32_t DI2:1; /**< bit: 2 XDMAC Channel 2 Disable Bit */ 1445 uint32_t DI3:1; /**< bit: 3 XDMAC Channel 3 Disable Bit */ 1446 uint32_t DI4:1; /**< bit: 4 XDMAC Channel 4 Disable Bit */ 1447 uint32_t DI5:1; /**< bit: 5 XDMAC Channel 5 Disable Bit */ 1448 uint32_t DI6:1; /**< bit: 6 XDMAC Channel 6 Disable Bit */ 1449 uint32_t DI7:1; /**< bit: 7 XDMAC Channel 7 Disable Bit */ 1450 uint32_t DI8:1; /**< bit: 8 XDMAC Channel 8 Disable Bit */ 1451 uint32_t DI9:1; /**< bit: 9 XDMAC Channel 9 Disable Bit */ 1452 uint32_t DI10:1; /**< bit: 10 XDMAC Channel 10 Disable Bit */ 1453 uint32_t DI11:1; /**< bit: 11 XDMAC Channel 11 Disable Bit */ 1454 uint32_t DI12:1; /**< bit: 12 XDMAC Channel 12 Disable Bit */ 1455 uint32_t DI13:1; /**< bit: 13 XDMAC Channel 13 Disable Bit */ 1456 uint32_t DI14:1; /**< bit: 14 XDMAC Channel 14 Disable Bit */ 1457 uint32_t DI15:1; /**< bit: 15 XDMAC Channel 15 Disable Bit */ 1458 uint32_t DI16:1; /**< bit: 16 XDMAC Channel 16 Disable Bit */ 1459 uint32_t DI17:1; /**< bit: 17 XDMAC Channel 17 Disable Bit */ 1460 uint32_t DI18:1; /**< bit: 18 XDMAC Channel 18 Disable Bit */ 1461 uint32_t DI19:1; /**< bit: 19 XDMAC Channel 19 Disable Bit */ 1462 uint32_t DI20:1; /**< bit: 20 XDMAC Channel 20 Disable Bit */ 1463 uint32_t DI21:1; /**< bit: 21 XDMAC Channel 21 Disable Bit */ 1464 uint32_t DI22:1; /**< bit: 22 XDMAC Channel 22 Disable Bit */ 1465 uint32_t DI23:1; /**< bit: 23 XDMAC Channel 23 Disable Bit */ 1466 uint32_t :8; /**< bit: 24..31 Reserved */ 1467 } bit; /**< Structure used for bit access */ 1468 struct { 1469 uint32_t DI:24; /**< bit: 0..23 XDMAC Channel 23 Disable Bit */ 1470 uint32_t :8; /**< bit: 24..31 Reserved */ 1471 } vec; /**< Structure used for vec access */ 1472 uint32_t reg; /**< Type used for register access */ 1473 } XDMAC_GD_Type; 1474 #endif 1475 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1476 1477 #define XDMAC_GD_OFFSET (0x20) /**< (XDMAC_GD) Global Channel Disable Register Offset */ 1478 1479 #define XDMAC_GD_DI0_Pos 0 /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Position */ 1480 #define XDMAC_GD_DI0_Msk (_U_(0x1) << XDMAC_GD_DI0_Pos) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Mask */ 1481 #define XDMAC_GD_DI0 XDMAC_GD_DI0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI0_Msk instead */ 1482 #define XDMAC_GD_DI1_Pos 1 /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Position */ 1483 #define XDMAC_GD_DI1_Msk (_U_(0x1) << XDMAC_GD_DI1_Pos) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Mask */ 1484 #define XDMAC_GD_DI1 XDMAC_GD_DI1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI1_Msk instead */ 1485 #define XDMAC_GD_DI2_Pos 2 /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Position */ 1486 #define XDMAC_GD_DI2_Msk (_U_(0x1) << XDMAC_GD_DI2_Pos) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Mask */ 1487 #define XDMAC_GD_DI2 XDMAC_GD_DI2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI2_Msk instead */ 1488 #define XDMAC_GD_DI3_Pos 3 /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Position */ 1489 #define XDMAC_GD_DI3_Msk (_U_(0x1) << XDMAC_GD_DI3_Pos) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Mask */ 1490 #define XDMAC_GD_DI3 XDMAC_GD_DI3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI3_Msk instead */ 1491 #define XDMAC_GD_DI4_Pos 4 /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Position */ 1492 #define XDMAC_GD_DI4_Msk (_U_(0x1) << XDMAC_GD_DI4_Pos) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Mask */ 1493 #define XDMAC_GD_DI4 XDMAC_GD_DI4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI4_Msk instead */ 1494 #define XDMAC_GD_DI5_Pos 5 /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Position */ 1495 #define XDMAC_GD_DI5_Msk (_U_(0x1) << XDMAC_GD_DI5_Pos) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Mask */ 1496 #define XDMAC_GD_DI5 XDMAC_GD_DI5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI5_Msk instead */ 1497 #define XDMAC_GD_DI6_Pos 6 /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Position */ 1498 #define XDMAC_GD_DI6_Msk (_U_(0x1) << XDMAC_GD_DI6_Pos) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Mask */ 1499 #define XDMAC_GD_DI6 XDMAC_GD_DI6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI6_Msk instead */ 1500 #define XDMAC_GD_DI7_Pos 7 /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Position */ 1501 #define XDMAC_GD_DI7_Msk (_U_(0x1) << XDMAC_GD_DI7_Pos) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Mask */ 1502 #define XDMAC_GD_DI7 XDMAC_GD_DI7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI7_Msk instead */ 1503 #define XDMAC_GD_DI8_Pos 8 /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Position */ 1504 #define XDMAC_GD_DI8_Msk (_U_(0x1) << XDMAC_GD_DI8_Pos) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Mask */ 1505 #define XDMAC_GD_DI8 XDMAC_GD_DI8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI8_Msk instead */ 1506 #define XDMAC_GD_DI9_Pos 9 /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Position */ 1507 #define XDMAC_GD_DI9_Msk (_U_(0x1) << XDMAC_GD_DI9_Pos) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Mask */ 1508 #define XDMAC_GD_DI9 XDMAC_GD_DI9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI9_Msk instead */ 1509 #define XDMAC_GD_DI10_Pos 10 /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Position */ 1510 #define XDMAC_GD_DI10_Msk (_U_(0x1) << XDMAC_GD_DI10_Pos) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Mask */ 1511 #define XDMAC_GD_DI10 XDMAC_GD_DI10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI10_Msk instead */ 1512 #define XDMAC_GD_DI11_Pos 11 /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Position */ 1513 #define XDMAC_GD_DI11_Msk (_U_(0x1) << XDMAC_GD_DI11_Pos) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Mask */ 1514 #define XDMAC_GD_DI11 XDMAC_GD_DI11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI11_Msk instead */ 1515 #define XDMAC_GD_DI12_Pos 12 /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Position */ 1516 #define XDMAC_GD_DI12_Msk (_U_(0x1) << XDMAC_GD_DI12_Pos) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Mask */ 1517 #define XDMAC_GD_DI12 XDMAC_GD_DI12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI12_Msk instead */ 1518 #define XDMAC_GD_DI13_Pos 13 /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Position */ 1519 #define XDMAC_GD_DI13_Msk (_U_(0x1) << XDMAC_GD_DI13_Pos) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Mask */ 1520 #define XDMAC_GD_DI13 XDMAC_GD_DI13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI13_Msk instead */ 1521 #define XDMAC_GD_DI14_Pos 14 /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Position */ 1522 #define XDMAC_GD_DI14_Msk (_U_(0x1) << XDMAC_GD_DI14_Pos) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Mask */ 1523 #define XDMAC_GD_DI14 XDMAC_GD_DI14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI14_Msk instead */ 1524 #define XDMAC_GD_DI15_Pos 15 /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Position */ 1525 #define XDMAC_GD_DI15_Msk (_U_(0x1) << XDMAC_GD_DI15_Pos) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Mask */ 1526 #define XDMAC_GD_DI15 XDMAC_GD_DI15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI15_Msk instead */ 1527 #define XDMAC_GD_DI16_Pos 16 /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Position */ 1528 #define XDMAC_GD_DI16_Msk (_U_(0x1) << XDMAC_GD_DI16_Pos) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Mask */ 1529 #define XDMAC_GD_DI16 XDMAC_GD_DI16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI16_Msk instead */ 1530 #define XDMAC_GD_DI17_Pos 17 /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Position */ 1531 #define XDMAC_GD_DI17_Msk (_U_(0x1) << XDMAC_GD_DI17_Pos) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Mask */ 1532 #define XDMAC_GD_DI17 XDMAC_GD_DI17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI17_Msk instead */ 1533 #define XDMAC_GD_DI18_Pos 18 /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Position */ 1534 #define XDMAC_GD_DI18_Msk (_U_(0x1) << XDMAC_GD_DI18_Pos) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Mask */ 1535 #define XDMAC_GD_DI18 XDMAC_GD_DI18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI18_Msk instead */ 1536 #define XDMAC_GD_DI19_Pos 19 /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Position */ 1537 #define XDMAC_GD_DI19_Msk (_U_(0x1) << XDMAC_GD_DI19_Pos) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Mask */ 1538 #define XDMAC_GD_DI19 XDMAC_GD_DI19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI19_Msk instead */ 1539 #define XDMAC_GD_DI20_Pos 20 /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Position */ 1540 #define XDMAC_GD_DI20_Msk (_U_(0x1) << XDMAC_GD_DI20_Pos) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Mask */ 1541 #define XDMAC_GD_DI20 XDMAC_GD_DI20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI20_Msk instead */ 1542 #define XDMAC_GD_DI21_Pos 21 /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Position */ 1543 #define XDMAC_GD_DI21_Msk (_U_(0x1) << XDMAC_GD_DI21_Pos) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Mask */ 1544 #define XDMAC_GD_DI21 XDMAC_GD_DI21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI21_Msk instead */ 1545 #define XDMAC_GD_DI22_Pos 22 /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Position */ 1546 #define XDMAC_GD_DI22_Msk (_U_(0x1) << XDMAC_GD_DI22_Pos) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Mask */ 1547 #define XDMAC_GD_DI22 XDMAC_GD_DI22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI22_Msk instead */ 1548 #define XDMAC_GD_DI23_Pos 23 /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Position */ 1549 #define XDMAC_GD_DI23_Msk (_U_(0x1) << XDMAC_GD_DI23_Pos) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Mask */ 1550 #define XDMAC_GD_DI23 XDMAC_GD_DI23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI23_Msk instead */ 1551 #define XDMAC_GD_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GD) Register MASK (Use XDMAC_GD_Msk instead) */ 1552 #define XDMAC_GD_Msk _U_(0xFFFFFF) /**< (XDMAC_GD) Register Mask */ 1553 1554 #define XDMAC_GD_DI_Pos 0 /**< (XDMAC_GD Position) XDMAC Channel 23 Disable Bit */ 1555 #define XDMAC_GD_DI_Msk (_U_(0xFFFFFF) << XDMAC_GD_DI_Pos) /**< (XDMAC_GD Mask) DI */ 1556 #define XDMAC_GD_DI(value) (XDMAC_GD_DI_Msk & ((value) << XDMAC_GD_DI_Pos)) 1557 1558 /* -------- XDMAC_GS : (XDMAC Offset: 0x24) (R/ 32) Global Channel Status Register -------- */ 1559 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1560 #if COMPONENT_TYPEDEF_STYLE == 'N' 1561 typedef union { 1562 struct { 1563 uint32_t ST0:1; /**< bit: 0 XDMAC Channel 0 Status Bit */ 1564 uint32_t ST1:1; /**< bit: 1 XDMAC Channel 1 Status Bit */ 1565 uint32_t ST2:1; /**< bit: 2 XDMAC Channel 2 Status Bit */ 1566 uint32_t ST3:1; /**< bit: 3 XDMAC Channel 3 Status Bit */ 1567 uint32_t ST4:1; /**< bit: 4 XDMAC Channel 4 Status Bit */ 1568 uint32_t ST5:1; /**< bit: 5 XDMAC Channel 5 Status Bit */ 1569 uint32_t ST6:1; /**< bit: 6 XDMAC Channel 6 Status Bit */ 1570 uint32_t ST7:1; /**< bit: 7 XDMAC Channel 7 Status Bit */ 1571 uint32_t ST8:1; /**< bit: 8 XDMAC Channel 8 Status Bit */ 1572 uint32_t ST9:1; /**< bit: 9 XDMAC Channel 9 Status Bit */ 1573 uint32_t ST10:1; /**< bit: 10 XDMAC Channel 10 Status Bit */ 1574 uint32_t ST11:1; /**< bit: 11 XDMAC Channel 11 Status Bit */ 1575 uint32_t ST12:1; /**< bit: 12 XDMAC Channel 12 Status Bit */ 1576 uint32_t ST13:1; /**< bit: 13 XDMAC Channel 13 Status Bit */ 1577 uint32_t ST14:1; /**< bit: 14 XDMAC Channel 14 Status Bit */ 1578 uint32_t ST15:1; /**< bit: 15 XDMAC Channel 15 Status Bit */ 1579 uint32_t ST16:1; /**< bit: 16 XDMAC Channel 16 Status Bit */ 1580 uint32_t ST17:1; /**< bit: 17 XDMAC Channel 17 Status Bit */ 1581 uint32_t ST18:1; /**< bit: 18 XDMAC Channel 18 Status Bit */ 1582 uint32_t ST19:1; /**< bit: 19 XDMAC Channel 19 Status Bit */ 1583 uint32_t ST20:1; /**< bit: 20 XDMAC Channel 20 Status Bit */ 1584 uint32_t ST21:1; /**< bit: 21 XDMAC Channel 21 Status Bit */ 1585 uint32_t ST22:1; /**< bit: 22 XDMAC Channel 22 Status Bit */ 1586 uint32_t ST23:1; /**< bit: 23 XDMAC Channel 23 Status Bit */ 1587 uint32_t :8; /**< bit: 24..31 Reserved */ 1588 } bit; /**< Structure used for bit access */ 1589 struct { 1590 uint32_t ST:24; /**< bit: 0..23 XDMAC Channel 23 Status Bit */ 1591 uint32_t :8; /**< bit: 24..31 Reserved */ 1592 } vec; /**< Structure used for vec access */ 1593 uint32_t reg; /**< Type used for register access */ 1594 } XDMAC_GS_Type; 1595 #endif 1596 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1597 1598 #define XDMAC_GS_OFFSET (0x24) /**< (XDMAC_GS) Global Channel Status Register Offset */ 1599 1600 #define XDMAC_GS_ST0_Pos 0 /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Position */ 1601 #define XDMAC_GS_ST0_Msk (_U_(0x1) << XDMAC_GS_ST0_Pos) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Mask */ 1602 #define XDMAC_GS_ST0 XDMAC_GS_ST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST0_Msk instead */ 1603 #define XDMAC_GS_ST1_Pos 1 /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Position */ 1604 #define XDMAC_GS_ST1_Msk (_U_(0x1) << XDMAC_GS_ST1_Pos) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Mask */ 1605 #define XDMAC_GS_ST1 XDMAC_GS_ST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST1_Msk instead */ 1606 #define XDMAC_GS_ST2_Pos 2 /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Position */ 1607 #define XDMAC_GS_ST2_Msk (_U_(0x1) << XDMAC_GS_ST2_Pos) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Mask */ 1608 #define XDMAC_GS_ST2 XDMAC_GS_ST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST2_Msk instead */ 1609 #define XDMAC_GS_ST3_Pos 3 /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Position */ 1610 #define XDMAC_GS_ST3_Msk (_U_(0x1) << XDMAC_GS_ST3_Pos) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Mask */ 1611 #define XDMAC_GS_ST3 XDMAC_GS_ST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST3_Msk instead */ 1612 #define XDMAC_GS_ST4_Pos 4 /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Position */ 1613 #define XDMAC_GS_ST4_Msk (_U_(0x1) << XDMAC_GS_ST4_Pos) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Mask */ 1614 #define XDMAC_GS_ST4 XDMAC_GS_ST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST4_Msk instead */ 1615 #define XDMAC_GS_ST5_Pos 5 /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Position */ 1616 #define XDMAC_GS_ST5_Msk (_U_(0x1) << XDMAC_GS_ST5_Pos) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Mask */ 1617 #define XDMAC_GS_ST5 XDMAC_GS_ST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST5_Msk instead */ 1618 #define XDMAC_GS_ST6_Pos 6 /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Position */ 1619 #define XDMAC_GS_ST6_Msk (_U_(0x1) << XDMAC_GS_ST6_Pos) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Mask */ 1620 #define XDMAC_GS_ST6 XDMAC_GS_ST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST6_Msk instead */ 1621 #define XDMAC_GS_ST7_Pos 7 /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Position */ 1622 #define XDMAC_GS_ST7_Msk (_U_(0x1) << XDMAC_GS_ST7_Pos) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Mask */ 1623 #define XDMAC_GS_ST7 XDMAC_GS_ST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST7_Msk instead */ 1624 #define XDMAC_GS_ST8_Pos 8 /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Position */ 1625 #define XDMAC_GS_ST8_Msk (_U_(0x1) << XDMAC_GS_ST8_Pos) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Mask */ 1626 #define XDMAC_GS_ST8 XDMAC_GS_ST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST8_Msk instead */ 1627 #define XDMAC_GS_ST9_Pos 9 /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Position */ 1628 #define XDMAC_GS_ST9_Msk (_U_(0x1) << XDMAC_GS_ST9_Pos) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Mask */ 1629 #define XDMAC_GS_ST9 XDMAC_GS_ST9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST9_Msk instead */ 1630 #define XDMAC_GS_ST10_Pos 10 /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Position */ 1631 #define XDMAC_GS_ST10_Msk (_U_(0x1) << XDMAC_GS_ST10_Pos) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Mask */ 1632 #define XDMAC_GS_ST10 XDMAC_GS_ST10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST10_Msk instead */ 1633 #define XDMAC_GS_ST11_Pos 11 /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Position */ 1634 #define XDMAC_GS_ST11_Msk (_U_(0x1) << XDMAC_GS_ST11_Pos) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Mask */ 1635 #define XDMAC_GS_ST11 XDMAC_GS_ST11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST11_Msk instead */ 1636 #define XDMAC_GS_ST12_Pos 12 /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Position */ 1637 #define XDMAC_GS_ST12_Msk (_U_(0x1) << XDMAC_GS_ST12_Pos) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Mask */ 1638 #define XDMAC_GS_ST12 XDMAC_GS_ST12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST12_Msk instead */ 1639 #define XDMAC_GS_ST13_Pos 13 /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Position */ 1640 #define XDMAC_GS_ST13_Msk (_U_(0x1) << XDMAC_GS_ST13_Pos) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Mask */ 1641 #define XDMAC_GS_ST13 XDMAC_GS_ST13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST13_Msk instead */ 1642 #define XDMAC_GS_ST14_Pos 14 /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Position */ 1643 #define XDMAC_GS_ST14_Msk (_U_(0x1) << XDMAC_GS_ST14_Pos) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Mask */ 1644 #define XDMAC_GS_ST14 XDMAC_GS_ST14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST14_Msk instead */ 1645 #define XDMAC_GS_ST15_Pos 15 /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Position */ 1646 #define XDMAC_GS_ST15_Msk (_U_(0x1) << XDMAC_GS_ST15_Pos) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Mask */ 1647 #define XDMAC_GS_ST15 XDMAC_GS_ST15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST15_Msk instead */ 1648 #define XDMAC_GS_ST16_Pos 16 /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Position */ 1649 #define XDMAC_GS_ST16_Msk (_U_(0x1) << XDMAC_GS_ST16_Pos) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Mask */ 1650 #define XDMAC_GS_ST16 XDMAC_GS_ST16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST16_Msk instead */ 1651 #define XDMAC_GS_ST17_Pos 17 /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Position */ 1652 #define XDMAC_GS_ST17_Msk (_U_(0x1) << XDMAC_GS_ST17_Pos) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Mask */ 1653 #define XDMAC_GS_ST17 XDMAC_GS_ST17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST17_Msk instead */ 1654 #define XDMAC_GS_ST18_Pos 18 /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Position */ 1655 #define XDMAC_GS_ST18_Msk (_U_(0x1) << XDMAC_GS_ST18_Pos) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Mask */ 1656 #define XDMAC_GS_ST18 XDMAC_GS_ST18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST18_Msk instead */ 1657 #define XDMAC_GS_ST19_Pos 19 /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Position */ 1658 #define XDMAC_GS_ST19_Msk (_U_(0x1) << XDMAC_GS_ST19_Pos) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Mask */ 1659 #define XDMAC_GS_ST19 XDMAC_GS_ST19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST19_Msk instead */ 1660 #define XDMAC_GS_ST20_Pos 20 /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Position */ 1661 #define XDMAC_GS_ST20_Msk (_U_(0x1) << XDMAC_GS_ST20_Pos) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Mask */ 1662 #define XDMAC_GS_ST20 XDMAC_GS_ST20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST20_Msk instead */ 1663 #define XDMAC_GS_ST21_Pos 21 /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Position */ 1664 #define XDMAC_GS_ST21_Msk (_U_(0x1) << XDMAC_GS_ST21_Pos) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Mask */ 1665 #define XDMAC_GS_ST21 XDMAC_GS_ST21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST21_Msk instead */ 1666 #define XDMAC_GS_ST22_Pos 22 /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Position */ 1667 #define XDMAC_GS_ST22_Msk (_U_(0x1) << XDMAC_GS_ST22_Pos) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Mask */ 1668 #define XDMAC_GS_ST22 XDMAC_GS_ST22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST22_Msk instead */ 1669 #define XDMAC_GS_ST23_Pos 23 /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Position */ 1670 #define XDMAC_GS_ST23_Msk (_U_(0x1) << XDMAC_GS_ST23_Pos) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Mask */ 1671 #define XDMAC_GS_ST23 XDMAC_GS_ST23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST23_Msk instead */ 1672 #define XDMAC_GS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GS) Register MASK (Use XDMAC_GS_Msk instead) */ 1673 #define XDMAC_GS_Msk _U_(0xFFFFFF) /**< (XDMAC_GS) Register Mask */ 1674 1675 #define XDMAC_GS_ST_Pos 0 /**< (XDMAC_GS Position) XDMAC Channel 23 Status Bit */ 1676 #define XDMAC_GS_ST_Msk (_U_(0xFFFFFF) << XDMAC_GS_ST_Pos) /**< (XDMAC_GS Mask) ST */ 1677 #define XDMAC_GS_ST(value) (XDMAC_GS_ST_Msk & ((value) << XDMAC_GS_ST_Pos)) 1678 1679 /* -------- XDMAC_GRS : (XDMAC Offset: 0x28) (R/W 32) Global Channel Read Suspend Register -------- */ 1680 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1681 #if COMPONENT_TYPEDEF_STYLE == 'N' 1682 typedef union { 1683 struct { 1684 uint32_t RS0:1; /**< bit: 0 XDMAC Channel 0 Read Suspend Bit */ 1685 uint32_t RS1:1; /**< bit: 1 XDMAC Channel 1 Read Suspend Bit */ 1686 uint32_t RS2:1; /**< bit: 2 XDMAC Channel 2 Read Suspend Bit */ 1687 uint32_t RS3:1; /**< bit: 3 XDMAC Channel 3 Read Suspend Bit */ 1688 uint32_t RS4:1; /**< bit: 4 XDMAC Channel 4 Read Suspend Bit */ 1689 uint32_t RS5:1; /**< bit: 5 XDMAC Channel 5 Read Suspend Bit */ 1690 uint32_t RS6:1; /**< bit: 6 XDMAC Channel 6 Read Suspend Bit */ 1691 uint32_t RS7:1; /**< bit: 7 XDMAC Channel 7 Read Suspend Bit */ 1692 uint32_t RS8:1; /**< bit: 8 XDMAC Channel 8 Read Suspend Bit */ 1693 uint32_t RS9:1; /**< bit: 9 XDMAC Channel 9 Read Suspend Bit */ 1694 uint32_t RS10:1; /**< bit: 10 XDMAC Channel 10 Read Suspend Bit */ 1695 uint32_t RS11:1; /**< bit: 11 XDMAC Channel 11 Read Suspend Bit */ 1696 uint32_t RS12:1; /**< bit: 12 XDMAC Channel 12 Read Suspend Bit */ 1697 uint32_t RS13:1; /**< bit: 13 XDMAC Channel 13 Read Suspend Bit */ 1698 uint32_t RS14:1; /**< bit: 14 XDMAC Channel 14 Read Suspend Bit */ 1699 uint32_t RS15:1; /**< bit: 15 XDMAC Channel 15 Read Suspend Bit */ 1700 uint32_t RS16:1; /**< bit: 16 XDMAC Channel 16 Read Suspend Bit */ 1701 uint32_t RS17:1; /**< bit: 17 XDMAC Channel 17 Read Suspend Bit */ 1702 uint32_t RS18:1; /**< bit: 18 XDMAC Channel 18 Read Suspend Bit */ 1703 uint32_t RS19:1; /**< bit: 19 XDMAC Channel 19 Read Suspend Bit */ 1704 uint32_t RS20:1; /**< bit: 20 XDMAC Channel 20 Read Suspend Bit */ 1705 uint32_t RS21:1; /**< bit: 21 XDMAC Channel 21 Read Suspend Bit */ 1706 uint32_t RS22:1; /**< bit: 22 XDMAC Channel 22 Read Suspend Bit */ 1707 uint32_t RS23:1; /**< bit: 23 XDMAC Channel 23 Read Suspend Bit */ 1708 uint32_t :8; /**< bit: 24..31 Reserved */ 1709 } bit; /**< Structure used for bit access */ 1710 struct { 1711 uint32_t RS:24; /**< bit: 0..23 XDMAC Channel 23 Read Suspend Bit */ 1712 uint32_t :8; /**< bit: 24..31 Reserved */ 1713 } vec; /**< Structure used for vec access */ 1714 uint32_t reg; /**< Type used for register access */ 1715 } XDMAC_GRS_Type; 1716 #endif 1717 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1718 1719 #define XDMAC_GRS_OFFSET (0x28) /**< (XDMAC_GRS) Global Channel Read Suspend Register Offset */ 1720 1721 #define XDMAC_GRS_RS0_Pos 0 /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Position */ 1722 #define XDMAC_GRS_RS0_Msk (_U_(0x1) << XDMAC_GRS_RS0_Pos) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Mask */ 1723 #define XDMAC_GRS_RS0 XDMAC_GRS_RS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS0_Msk instead */ 1724 #define XDMAC_GRS_RS1_Pos 1 /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Position */ 1725 #define XDMAC_GRS_RS1_Msk (_U_(0x1) << XDMAC_GRS_RS1_Pos) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Mask */ 1726 #define XDMAC_GRS_RS1 XDMAC_GRS_RS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS1_Msk instead */ 1727 #define XDMAC_GRS_RS2_Pos 2 /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Position */ 1728 #define XDMAC_GRS_RS2_Msk (_U_(0x1) << XDMAC_GRS_RS2_Pos) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Mask */ 1729 #define XDMAC_GRS_RS2 XDMAC_GRS_RS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS2_Msk instead */ 1730 #define XDMAC_GRS_RS3_Pos 3 /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Position */ 1731 #define XDMAC_GRS_RS3_Msk (_U_(0x1) << XDMAC_GRS_RS3_Pos) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Mask */ 1732 #define XDMAC_GRS_RS3 XDMAC_GRS_RS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS3_Msk instead */ 1733 #define XDMAC_GRS_RS4_Pos 4 /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Position */ 1734 #define XDMAC_GRS_RS4_Msk (_U_(0x1) << XDMAC_GRS_RS4_Pos) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Mask */ 1735 #define XDMAC_GRS_RS4 XDMAC_GRS_RS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS4_Msk instead */ 1736 #define XDMAC_GRS_RS5_Pos 5 /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Position */ 1737 #define XDMAC_GRS_RS5_Msk (_U_(0x1) << XDMAC_GRS_RS5_Pos) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Mask */ 1738 #define XDMAC_GRS_RS5 XDMAC_GRS_RS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS5_Msk instead */ 1739 #define XDMAC_GRS_RS6_Pos 6 /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Position */ 1740 #define XDMAC_GRS_RS6_Msk (_U_(0x1) << XDMAC_GRS_RS6_Pos) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Mask */ 1741 #define XDMAC_GRS_RS6 XDMAC_GRS_RS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS6_Msk instead */ 1742 #define XDMAC_GRS_RS7_Pos 7 /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Position */ 1743 #define XDMAC_GRS_RS7_Msk (_U_(0x1) << XDMAC_GRS_RS7_Pos) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Mask */ 1744 #define XDMAC_GRS_RS7 XDMAC_GRS_RS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS7_Msk instead */ 1745 #define XDMAC_GRS_RS8_Pos 8 /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Position */ 1746 #define XDMAC_GRS_RS8_Msk (_U_(0x1) << XDMAC_GRS_RS8_Pos) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Mask */ 1747 #define XDMAC_GRS_RS8 XDMAC_GRS_RS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS8_Msk instead */ 1748 #define XDMAC_GRS_RS9_Pos 9 /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Position */ 1749 #define XDMAC_GRS_RS9_Msk (_U_(0x1) << XDMAC_GRS_RS9_Pos) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Mask */ 1750 #define XDMAC_GRS_RS9 XDMAC_GRS_RS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS9_Msk instead */ 1751 #define XDMAC_GRS_RS10_Pos 10 /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Position */ 1752 #define XDMAC_GRS_RS10_Msk (_U_(0x1) << XDMAC_GRS_RS10_Pos) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Mask */ 1753 #define XDMAC_GRS_RS10 XDMAC_GRS_RS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS10_Msk instead */ 1754 #define XDMAC_GRS_RS11_Pos 11 /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Position */ 1755 #define XDMAC_GRS_RS11_Msk (_U_(0x1) << XDMAC_GRS_RS11_Pos) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Mask */ 1756 #define XDMAC_GRS_RS11 XDMAC_GRS_RS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS11_Msk instead */ 1757 #define XDMAC_GRS_RS12_Pos 12 /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Position */ 1758 #define XDMAC_GRS_RS12_Msk (_U_(0x1) << XDMAC_GRS_RS12_Pos) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Mask */ 1759 #define XDMAC_GRS_RS12 XDMAC_GRS_RS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS12_Msk instead */ 1760 #define XDMAC_GRS_RS13_Pos 13 /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Position */ 1761 #define XDMAC_GRS_RS13_Msk (_U_(0x1) << XDMAC_GRS_RS13_Pos) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Mask */ 1762 #define XDMAC_GRS_RS13 XDMAC_GRS_RS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS13_Msk instead */ 1763 #define XDMAC_GRS_RS14_Pos 14 /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Position */ 1764 #define XDMAC_GRS_RS14_Msk (_U_(0x1) << XDMAC_GRS_RS14_Pos) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Mask */ 1765 #define XDMAC_GRS_RS14 XDMAC_GRS_RS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS14_Msk instead */ 1766 #define XDMAC_GRS_RS15_Pos 15 /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Position */ 1767 #define XDMAC_GRS_RS15_Msk (_U_(0x1) << XDMAC_GRS_RS15_Pos) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Mask */ 1768 #define XDMAC_GRS_RS15 XDMAC_GRS_RS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS15_Msk instead */ 1769 #define XDMAC_GRS_RS16_Pos 16 /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Position */ 1770 #define XDMAC_GRS_RS16_Msk (_U_(0x1) << XDMAC_GRS_RS16_Pos) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Mask */ 1771 #define XDMAC_GRS_RS16 XDMAC_GRS_RS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS16_Msk instead */ 1772 #define XDMAC_GRS_RS17_Pos 17 /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Position */ 1773 #define XDMAC_GRS_RS17_Msk (_U_(0x1) << XDMAC_GRS_RS17_Pos) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Mask */ 1774 #define XDMAC_GRS_RS17 XDMAC_GRS_RS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS17_Msk instead */ 1775 #define XDMAC_GRS_RS18_Pos 18 /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Position */ 1776 #define XDMAC_GRS_RS18_Msk (_U_(0x1) << XDMAC_GRS_RS18_Pos) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Mask */ 1777 #define XDMAC_GRS_RS18 XDMAC_GRS_RS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS18_Msk instead */ 1778 #define XDMAC_GRS_RS19_Pos 19 /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Position */ 1779 #define XDMAC_GRS_RS19_Msk (_U_(0x1) << XDMAC_GRS_RS19_Pos) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Mask */ 1780 #define XDMAC_GRS_RS19 XDMAC_GRS_RS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS19_Msk instead */ 1781 #define XDMAC_GRS_RS20_Pos 20 /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Position */ 1782 #define XDMAC_GRS_RS20_Msk (_U_(0x1) << XDMAC_GRS_RS20_Pos) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Mask */ 1783 #define XDMAC_GRS_RS20 XDMAC_GRS_RS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS20_Msk instead */ 1784 #define XDMAC_GRS_RS21_Pos 21 /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Position */ 1785 #define XDMAC_GRS_RS21_Msk (_U_(0x1) << XDMAC_GRS_RS21_Pos) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Mask */ 1786 #define XDMAC_GRS_RS21 XDMAC_GRS_RS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS21_Msk instead */ 1787 #define XDMAC_GRS_RS22_Pos 22 /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Position */ 1788 #define XDMAC_GRS_RS22_Msk (_U_(0x1) << XDMAC_GRS_RS22_Pos) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Mask */ 1789 #define XDMAC_GRS_RS22 XDMAC_GRS_RS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS22_Msk instead */ 1790 #define XDMAC_GRS_RS23_Pos 23 /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Position */ 1791 #define XDMAC_GRS_RS23_Msk (_U_(0x1) << XDMAC_GRS_RS23_Pos) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Mask */ 1792 #define XDMAC_GRS_RS23 XDMAC_GRS_RS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS23_Msk instead */ 1793 #define XDMAC_GRS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRS) Register MASK (Use XDMAC_GRS_Msk instead) */ 1794 #define XDMAC_GRS_Msk _U_(0xFFFFFF) /**< (XDMAC_GRS) Register Mask */ 1795 1796 #define XDMAC_GRS_RS_Pos 0 /**< (XDMAC_GRS Position) XDMAC Channel 23 Read Suspend Bit */ 1797 #define XDMAC_GRS_RS_Msk (_U_(0xFFFFFF) << XDMAC_GRS_RS_Pos) /**< (XDMAC_GRS Mask) RS */ 1798 #define XDMAC_GRS_RS(value) (XDMAC_GRS_RS_Msk & ((value) << XDMAC_GRS_RS_Pos)) 1799 1800 /* -------- XDMAC_GWS : (XDMAC Offset: 0x2c) (R/W 32) Global Channel Write Suspend Register -------- */ 1801 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1802 #if COMPONENT_TYPEDEF_STYLE == 'N' 1803 typedef union { 1804 struct { 1805 uint32_t WS0:1; /**< bit: 0 XDMAC Channel 0 Write Suspend Bit */ 1806 uint32_t WS1:1; /**< bit: 1 XDMAC Channel 1 Write Suspend Bit */ 1807 uint32_t WS2:1; /**< bit: 2 XDMAC Channel 2 Write Suspend Bit */ 1808 uint32_t WS3:1; /**< bit: 3 XDMAC Channel 3 Write Suspend Bit */ 1809 uint32_t WS4:1; /**< bit: 4 XDMAC Channel 4 Write Suspend Bit */ 1810 uint32_t WS5:1; /**< bit: 5 XDMAC Channel 5 Write Suspend Bit */ 1811 uint32_t WS6:1; /**< bit: 6 XDMAC Channel 6 Write Suspend Bit */ 1812 uint32_t WS7:1; /**< bit: 7 XDMAC Channel 7 Write Suspend Bit */ 1813 uint32_t WS8:1; /**< bit: 8 XDMAC Channel 8 Write Suspend Bit */ 1814 uint32_t WS9:1; /**< bit: 9 XDMAC Channel 9 Write Suspend Bit */ 1815 uint32_t WS10:1; /**< bit: 10 XDMAC Channel 10 Write Suspend Bit */ 1816 uint32_t WS11:1; /**< bit: 11 XDMAC Channel 11 Write Suspend Bit */ 1817 uint32_t WS12:1; /**< bit: 12 XDMAC Channel 12 Write Suspend Bit */ 1818 uint32_t WS13:1; /**< bit: 13 XDMAC Channel 13 Write Suspend Bit */ 1819 uint32_t WS14:1; /**< bit: 14 XDMAC Channel 14 Write Suspend Bit */ 1820 uint32_t WS15:1; /**< bit: 15 XDMAC Channel 15 Write Suspend Bit */ 1821 uint32_t WS16:1; /**< bit: 16 XDMAC Channel 16 Write Suspend Bit */ 1822 uint32_t WS17:1; /**< bit: 17 XDMAC Channel 17 Write Suspend Bit */ 1823 uint32_t WS18:1; /**< bit: 18 XDMAC Channel 18 Write Suspend Bit */ 1824 uint32_t WS19:1; /**< bit: 19 XDMAC Channel 19 Write Suspend Bit */ 1825 uint32_t WS20:1; /**< bit: 20 XDMAC Channel 20 Write Suspend Bit */ 1826 uint32_t WS21:1; /**< bit: 21 XDMAC Channel 21 Write Suspend Bit */ 1827 uint32_t WS22:1; /**< bit: 22 XDMAC Channel 22 Write Suspend Bit */ 1828 uint32_t WS23:1; /**< bit: 23 XDMAC Channel 23 Write Suspend Bit */ 1829 uint32_t :8; /**< bit: 24..31 Reserved */ 1830 } bit; /**< Structure used for bit access */ 1831 struct { 1832 uint32_t WS:24; /**< bit: 0..23 XDMAC Channel 23 Write Suspend Bit */ 1833 uint32_t :8; /**< bit: 24..31 Reserved */ 1834 } vec; /**< Structure used for vec access */ 1835 uint32_t reg; /**< Type used for register access */ 1836 } XDMAC_GWS_Type; 1837 #endif 1838 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1839 1840 #define XDMAC_GWS_OFFSET (0x2C) /**< (XDMAC_GWS) Global Channel Write Suspend Register Offset */ 1841 1842 #define XDMAC_GWS_WS0_Pos 0 /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Position */ 1843 #define XDMAC_GWS_WS0_Msk (_U_(0x1) << XDMAC_GWS_WS0_Pos) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Mask */ 1844 #define XDMAC_GWS_WS0 XDMAC_GWS_WS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS0_Msk instead */ 1845 #define XDMAC_GWS_WS1_Pos 1 /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Position */ 1846 #define XDMAC_GWS_WS1_Msk (_U_(0x1) << XDMAC_GWS_WS1_Pos) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Mask */ 1847 #define XDMAC_GWS_WS1 XDMAC_GWS_WS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS1_Msk instead */ 1848 #define XDMAC_GWS_WS2_Pos 2 /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Position */ 1849 #define XDMAC_GWS_WS2_Msk (_U_(0x1) << XDMAC_GWS_WS2_Pos) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Mask */ 1850 #define XDMAC_GWS_WS2 XDMAC_GWS_WS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS2_Msk instead */ 1851 #define XDMAC_GWS_WS3_Pos 3 /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Position */ 1852 #define XDMAC_GWS_WS3_Msk (_U_(0x1) << XDMAC_GWS_WS3_Pos) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Mask */ 1853 #define XDMAC_GWS_WS3 XDMAC_GWS_WS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS3_Msk instead */ 1854 #define XDMAC_GWS_WS4_Pos 4 /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Position */ 1855 #define XDMAC_GWS_WS4_Msk (_U_(0x1) << XDMAC_GWS_WS4_Pos) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Mask */ 1856 #define XDMAC_GWS_WS4 XDMAC_GWS_WS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS4_Msk instead */ 1857 #define XDMAC_GWS_WS5_Pos 5 /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Position */ 1858 #define XDMAC_GWS_WS5_Msk (_U_(0x1) << XDMAC_GWS_WS5_Pos) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Mask */ 1859 #define XDMAC_GWS_WS5 XDMAC_GWS_WS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS5_Msk instead */ 1860 #define XDMAC_GWS_WS6_Pos 6 /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Position */ 1861 #define XDMAC_GWS_WS6_Msk (_U_(0x1) << XDMAC_GWS_WS6_Pos) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Mask */ 1862 #define XDMAC_GWS_WS6 XDMAC_GWS_WS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS6_Msk instead */ 1863 #define XDMAC_GWS_WS7_Pos 7 /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Position */ 1864 #define XDMAC_GWS_WS7_Msk (_U_(0x1) << XDMAC_GWS_WS7_Pos) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Mask */ 1865 #define XDMAC_GWS_WS7 XDMAC_GWS_WS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS7_Msk instead */ 1866 #define XDMAC_GWS_WS8_Pos 8 /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Position */ 1867 #define XDMAC_GWS_WS8_Msk (_U_(0x1) << XDMAC_GWS_WS8_Pos) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Mask */ 1868 #define XDMAC_GWS_WS8 XDMAC_GWS_WS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS8_Msk instead */ 1869 #define XDMAC_GWS_WS9_Pos 9 /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Position */ 1870 #define XDMAC_GWS_WS9_Msk (_U_(0x1) << XDMAC_GWS_WS9_Pos) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Mask */ 1871 #define XDMAC_GWS_WS9 XDMAC_GWS_WS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS9_Msk instead */ 1872 #define XDMAC_GWS_WS10_Pos 10 /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Position */ 1873 #define XDMAC_GWS_WS10_Msk (_U_(0x1) << XDMAC_GWS_WS10_Pos) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Mask */ 1874 #define XDMAC_GWS_WS10 XDMAC_GWS_WS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS10_Msk instead */ 1875 #define XDMAC_GWS_WS11_Pos 11 /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Position */ 1876 #define XDMAC_GWS_WS11_Msk (_U_(0x1) << XDMAC_GWS_WS11_Pos) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Mask */ 1877 #define XDMAC_GWS_WS11 XDMAC_GWS_WS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS11_Msk instead */ 1878 #define XDMAC_GWS_WS12_Pos 12 /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Position */ 1879 #define XDMAC_GWS_WS12_Msk (_U_(0x1) << XDMAC_GWS_WS12_Pos) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Mask */ 1880 #define XDMAC_GWS_WS12 XDMAC_GWS_WS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS12_Msk instead */ 1881 #define XDMAC_GWS_WS13_Pos 13 /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Position */ 1882 #define XDMAC_GWS_WS13_Msk (_U_(0x1) << XDMAC_GWS_WS13_Pos) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Mask */ 1883 #define XDMAC_GWS_WS13 XDMAC_GWS_WS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS13_Msk instead */ 1884 #define XDMAC_GWS_WS14_Pos 14 /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Position */ 1885 #define XDMAC_GWS_WS14_Msk (_U_(0x1) << XDMAC_GWS_WS14_Pos) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Mask */ 1886 #define XDMAC_GWS_WS14 XDMAC_GWS_WS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS14_Msk instead */ 1887 #define XDMAC_GWS_WS15_Pos 15 /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Position */ 1888 #define XDMAC_GWS_WS15_Msk (_U_(0x1) << XDMAC_GWS_WS15_Pos) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Mask */ 1889 #define XDMAC_GWS_WS15 XDMAC_GWS_WS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS15_Msk instead */ 1890 #define XDMAC_GWS_WS16_Pos 16 /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Position */ 1891 #define XDMAC_GWS_WS16_Msk (_U_(0x1) << XDMAC_GWS_WS16_Pos) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Mask */ 1892 #define XDMAC_GWS_WS16 XDMAC_GWS_WS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS16_Msk instead */ 1893 #define XDMAC_GWS_WS17_Pos 17 /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Position */ 1894 #define XDMAC_GWS_WS17_Msk (_U_(0x1) << XDMAC_GWS_WS17_Pos) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Mask */ 1895 #define XDMAC_GWS_WS17 XDMAC_GWS_WS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS17_Msk instead */ 1896 #define XDMAC_GWS_WS18_Pos 18 /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Position */ 1897 #define XDMAC_GWS_WS18_Msk (_U_(0x1) << XDMAC_GWS_WS18_Pos) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Mask */ 1898 #define XDMAC_GWS_WS18 XDMAC_GWS_WS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS18_Msk instead */ 1899 #define XDMAC_GWS_WS19_Pos 19 /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Position */ 1900 #define XDMAC_GWS_WS19_Msk (_U_(0x1) << XDMAC_GWS_WS19_Pos) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Mask */ 1901 #define XDMAC_GWS_WS19 XDMAC_GWS_WS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS19_Msk instead */ 1902 #define XDMAC_GWS_WS20_Pos 20 /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Position */ 1903 #define XDMAC_GWS_WS20_Msk (_U_(0x1) << XDMAC_GWS_WS20_Pos) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Mask */ 1904 #define XDMAC_GWS_WS20 XDMAC_GWS_WS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS20_Msk instead */ 1905 #define XDMAC_GWS_WS21_Pos 21 /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Position */ 1906 #define XDMAC_GWS_WS21_Msk (_U_(0x1) << XDMAC_GWS_WS21_Pos) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Mask */ 1907 #define XDMAC_GWS_WS21 XDMAC_GWS_WS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS21_Msk instead */ 1908 #define XDMAC_GWS_WS22_Pos 22 /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Position */ 1909 #define XDMAC_GWS_WS22_Msk (_U_(0x1) << XDMAC_GWS_WS22_Pos) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Mask */ 1910 #define XDMAC_GWS_WS22 XDMAC_GWS_WS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS22_Msk instead */ 1911 #define XDMAC_GWS_WS23_Pos 23 /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Position */ 1912 #define XDMAC_GWS_WS23_Msk (_U_(0x1) << XDMAC_GWS_WS23_Pos) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Mask */ 1913 #define XDMAC_GWS_WS23 XDMAC_GWS_WS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS23_Msk instead */ 1914 #define XDMAC_GWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GWS) Register MASK (Use XDMAC_GWS_Msk instead) */ 1915 #define XDMAC_GWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GWS) Register Mask */ 1916 1917 #define XDMAC_GWS_WS_Pos 0 /**< (XDMAC_GWS Position) XDMAC Channel 23 Write Suspend Bit */ 1918 #define XDMAC_GWS_WS_Msk (_U_(0xFFFFFF) << XDMAC_GWS_WS_Pos) /**< (XDMAC_GWS Mask) WS */ 1919 #define XDMAC_GWS_WS(value) (XDMAC_GWS_WS_Msk & ((value) << XDMAC_GWS_WS_Pos)) 1920 1921 /* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) (/W 32) Global Channel Read Write Suspend Register -------- */ 1922 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1923 #if COMPONENT_TYPEDEF_STYLE == 'N' 1924 typedef union { 1925 struct { 1926 uint32_t RWS0:1; /**< bit: 0 XDMAC Channel 0 Read Write Suspend Bit */ 1927 uint32_t RWS1:1; /**< bit: 1 XDMAC Channel 1 Read Write Suspend Bit */ 1928 uint32_t RWS2:1; /**< bit: 2 XDMAC Channel 2 Read Write Suspend Bit */ 1929 uint32_t RWS3:1; /**< bit: 3 XDMAC Channel 3 Read Write Suspend Bit */ 1930 uint32_t RWS4:1; /**< bit: 4 XDMAC Channel 4 Read Write Suspend Bit */ 1931 uint32_t RWS5:1; /**< bit: 5 XDMAC Channel 5 Read Write Suspend Bit */ 1932 uint32_t RWS6:1; /**< bit: 6 XDMAC Channel 6 Read Write Suspend Bit */ 1933 uint32_t RWS7:1; /**< bit: 7 XDMAC Channel 7 Read Write Suspend Bit */ 1934 uint32_t RWS8:1; /**< bit: 8 XDMAC Channel 8 Read Write Suspend Bit */ 1935 uint32_t RWS9:1; /**< bit: 9 XDMAC Channel 9 Read Write Suspend Bit */ 1936 uint32_t RWS10:1; /**< bit: 10 XDMAC Channel 10 Read Write Suspend Bit */ 1937 uint32_t RWS11:1; /**< bit: 11 XDMAC Channel 11 Read Write Suspend Bit */ 1938 uint32_t RWS12:1; /**< bit: 12 XDMAC Channel 12 Read Write Suspend Bit */ 1939 uint32_t RWS13:1; /**< bit: 13 XDMAC Channel 13 Read Write Suspend Bit */ 1940 uint32_t RWS14:1; /**< bit: 14 XDMAC Channel 14 Read Write Suspend Bit */ 1941 uint32_t RWS15:1; /**< bit: 15 XDMAC Channel 15 Read Write Suspend Bit */ 1942 uint32_t RWS16:1; /**< bit: 16 XDMAC Channel 16 Read Write Suspend Bit */ 1943 uint32_t RWS17:1; /**< bit: 17 XDMAC Channel 17 Read Write Suspend Bit */ 1944 uint32_t RWS18:1; /**< bit: 18 XDMAC Channel 18 Read Write Suspend Bit */ 1945 uint32_t RWS19:1; /**< bit: 19 XDMAC Channel 19 Read Write Suspend Bit */ 1946 uint32_t RWS20:1; /**< bit: 20 XDMAC Channel 20 Read Write Suspend Bit */ 1947 uint32_t RWS21:1; /**< bit: 21 XDMAC Channel 21 Read Write Suspend Bit */ 1948 uint32_t RWS22:1; /**< bit: 22 XDMAC Channel 22 Read Write Suspend Bit */ 1949 uint32_t RWS23:1; /**< bit: 23 XDMAC Channel 23 Read Write Suspend Bit */ 1950 uint32_t :8; /**< bit: 24..31 Reserved */ 1951 } bit; /**< Structure used for bit access */ 1952 struct { 1953 uint32_t RWS:24; /**< bit: 0..23 XDMAC Channel 23 Read Write Suspend Bit */ 1954 uint32_t :8; /**< bit: 24..31 Reserved */ 1955 } vec; /**< Structure used for vec access */ 1956 uint32_t reg; /**< Type used for register access */ 1957 } XDMAC_GRWS_Type; 1958 #endif 1959 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1960 1961 #define XDMAC_GRWS_OFFSET (0x30) /**< (XDMAC_GRWS) Global Channel Read Write Suspend Register Offset */ 1962 1963 #define XDMAC_GRWS_RWS0_Pos 0 /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Position */ 1964 #define XDMAC_GRWS_RWS0_Msk (_U_(0x1) << XDMAC_GRWS_RWS0_Pos) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Mask */ 1965 #define XDMAC_GRWS_RWS0 XDMAC_GRWS_RWS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS0_Msk instead */ 1966 #define XDMAC_GRWS_RWS1_Pos 1 /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Position */ 1967 #define XDMAC_GRWS_RWS1_Msk (_U_(0x1) << XDMAC_GRWS_RWS1_Pos) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Mask */ 1968 #define XDMAC_GRWS_RWS1 XDMAC_GRWS_RWS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS1_Msk instead */ 1969 #define XDMAC_GRWS_RWS2_Pos 2 /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Position */ 1970 #define XDMAC_GRWS_RWS2_Msk (_U_(0x1) << XDMAC_GRWS_RWS2_Pos) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Mask */ 1971 #define XDMAC_GRWS_RWS2 XDMAC_GRWS_RWS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS2_Msk instead */ 1972 #define XDMAC_GRWS_RWS3_Pos 3 /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Position */ 1973 #define XDMAC_GRWS_RWS3_Msk (_U_(0x1) << XDMAC_GRWS_RWS3_Pos) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Mask */ 1974 #define XDMAC_GRWS_RWS3 XDMAC_GRWS_RWS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS3_Msk instead */ 1975 #define XDMAC_GRWS_RWS4_Pos 4 /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Position */ 1976 #define XDMAC_GRWS_RWS4_Msk (_U_(0x1) << XDMAC_GRWS_RWS4_Pos) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Mask */ 1977 #define XDMAC_GRWS_RWS4 XDMAC_GRWS_RWS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS4_Msk instead */ 1978 #define XDMAC_GRWS_RWS5_Pos 5 /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Position */ 1979 #define XDMAC_GRWS_RWS5_Msk (_U_(0x1) << XDMAC_GRWS_RWS5_Pos) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Mask */ 1980 #define XDMAC_GRWS_RWS5 XDMAC_GRWS_RWS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS5_Msk instead */ 1981 #define XDMAC_GRWS_RWS6_Pos 6 /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Position */ 1982 #define XDMAC_GRWS_RWS6_Msk (_U_(0x1) << XDMAC_GRWS_RWS6_Pos) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Mask */ 1983 #define XDMAC_GRWS_RWS6 XDMAC_GRWS_RWS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS6_Msk instead */ 1984 #define XDMAC_GRWS_RWS7_Pos 7 /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Position */ 1985 #define XDMAC_GRWS_RWS7_Msk (_U_(0x1) << XDMAC_GRWS_RWS7_Pos) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Mask */ 1986 #define XDMAC_GRWS_RWS7 XDMAC_GRWS_RWS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS7_Msk instead */ 1987 #define XDMAC_GRWS_RWS8_Pos 8 /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Position */ 1988 #define XDMAC_GRWS_RWS8_Msk (_U_(0x1) << XDMAC_GRWS_RWS8_Pos) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Mask */ 1989 #define XDMAC_GRWS_RWS8 XDMAC_GRWS_RWS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS8_Msk instead */ 1990 #define XDMAC_GRWS_RWS9_Pos 9 /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Position */ 1991 #define XDMAC_GRWS_RWS9_Msk (_U_(0x1) << XDMAC_GRWS_RWS9_Pos) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Mask */ 1992 #define XDMAC_GRWS_RWS9 XDMAC_GRWS_RWS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS9_Msk instead */ 1993 #define XDMAC_GRWS_RWS10_Pos 10 /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Position */ 1994 #define XDMAC_GRWS_RWS10_Msk (_U_(0x1) << XDMAC_GRWS_RWS10_Pos) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Mask */ 1995 #define XDMAC_GRWS_RWS10 XDMAC_GRWS_RWS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS10_Msk instead */ 1996 #define XDMAC_GRWS_RWS11_Pos 11 /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Position */ 1997 #define XDMAC_GRWS_RWS11_Msk (_U_(0x1) << XDMAC_GRWS_RWS11_Pos) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Mask */ 1998 #define XDMAC_GRWS_RWS11 XDMAC_GRWS_RWS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS11_Msk instead */ 1999 #define XDMAC_GRWS_RWS12_Pos 12 /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Position */ 2000 #define XDMAC_GRWS_RWS12_Msk (_U_(0x1) << XDMAC_GRWS_RWS12_Pos) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Mask */ 2001 #define XDMAC_GRWS_RWS12 XDMAC_GRWS_RWS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS12_Msk instead */ 2002 #define XDMAC_GRWS_RWS13_Pos 13 /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Position */ 2003 #define XDMAC_GRWS_RWS13_Msk (_U_(0x1) << XDMAC_GRWS_RWS13_Pos) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Mask */ 2004 #define XDMAC_GRWS_RWS13 XDMAC_GRWS_RWS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS13_Msk instead */ 2005 #define XDMAC_GRWS_RWS14_Pos 14 /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Position */ 2006 #define XDMAC_GRWS_RWS14_Msk (_U_(0x1) << XDMAC_GRWS_RWS14_Pos) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Mask */ 2007 #define XDMAC_GRWS_RWS14 XDMAC_GRWS_RWS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS14_Msk instead */ 2008 #define XDMAC_GRWS_RWS15_Pos 15 /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Position */ 2009 #define XDMAC_GRWS_RWS15_Msk (_U_(0x1) << XDMAC_GRWS_RWS15_Pos) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Mask */ 2010 #define XDMAC_GRWS_RWS15 XDMAC_GRWS_RWS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS15_Msk instead */ 2011 #define XDMAC_GRWS_RWS16_Pos 16 /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Position */ 2012 #define XDMAC_GRWS_RWS16_Msk (_U_(0x1) << XDMAC_GRWS_RWS16_Pos) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Mask */ 2013 #define XDMAC_GRWS_RWS16 XDMAC_GRWS_RWS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS16_Msk instead */ 2014 #define XDMAC_GRWS_RWS17_Pos 17 /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Position */ 2015 #define XDMAC_GRWS_RWS17_Msk (_U_(0x1) << XDMAC_GRWS_RWS17_Pos) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Mask */ 2016 #define XDMAC_GRWS_RWS17 XDMAC_GRWS_RWS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS17_Msk instead */ 2017 #define XDMAC_GRWS_RWS18_Pos 18 /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Position */ 2018 #define XDMAC_GRWS_RWS18_Msk (_U_(0x1) << XDMAC_GRWS_RWS18_Pos) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Mask */ 2019 #define XDMAC_GRWS_RWS18 XDMAC_GRWS_RWS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS18_Msk instead */ 2020 #define XDMAC_GRWS_RWS19_Pos 19 /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Position */ 2021 #define XDMAC_GRWS_RWS19_Msk (_U_(0x1) << XDMAC_GRWS_RWS19_Pos) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Mask */ 2022 #define XDMAC_GRWS_RWS19 XDMAC_GRWS_RWS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS19_Msk instead */ 2023 #define XDMAC_GRWS_RWS20_Pos 20 /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Position */ 2024 #define XDMAC_GRWS_RWS20_Msk (_U_(0x1) << XDMAC_GRWS_RWS20_Pos) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Mask */ 2025 #define XDMAC_GRWS_RWS20 XDMAC_GRWS_RWS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS20_Msk instead */ 2026 #define XDMAC_GRWS_RWS21_Pos 21 /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Position */ 2027 #define XDMAC_GRWS_RWS21_Msk (_U_(0x1) << XDMAC_GRWS_RWS21_Pos) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Mask */ 2028 #define XDMAC_GRWS_RWS21 XDMAC_GRWS_RWS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS21_Msk instead */ 2029 #define XDMAC_GRWS_RWS22_Pos 22 /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Position */ 2030 #define XDMAC_GRWS_RWS22_Msk (_U_(0x1) << XDMAC_GRWS_RWS22_Pos) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Mask */ 2031 #define XDMAC_GRWS_RWS22 XDMAC_GRWS_RWS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS22_Msk instead */ 2032 #define XDMAC_GRWS_RWS23_Pos 23 /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Position */ 2033 #define XDMAC_GRWS_RWS23_Msk (_U_(0x1) << XDMAC_GRWS_RWS23_Pos) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Mask */ 2034 #define XDMAC_GRWS_RWS23 XDMAC_GRWS_RWS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS23_Msk instead */ 2035 #define XDMAC_GRWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRWS) Register MASK (Use XDMAC_GRWS_Msk instead) */ 2036 #define XDMAC_GRWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GRWS) Register Mask */ 2037 2038 #define XDMAC_GRWS_RWS_Pos 0 /**< (XDMAC_GRWS Position) XDMAC Channel 23 Read Write Suspend Bit */ 2039 #define XDMAC_GRWS_RWS_Msk (_U_(0xFFFFFF) << XDMAC_GRWS_RWS_Pos) /**< (XDMAC_GRWS Mask) RWS */ 2040 #define XDMAC_GRWS_RWS(value) (XDMAC_GRWS_RWS_Msk & ((value) << XDMAC_GRWS_RWS_Pos)) 2041 2042 /* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) (/W 32) Global Channel Read Write Resume Register -------- */ 2043 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2044 #if COMPONENT_TYPEDEF_STYLE == 'N' 2045 typedef union { 2046 struct { 2047 uint32_t RWR0:1; /**< bit: 0 XDMAC Channel 0 Read Write Resume Bit */ 2048 uint32_t RWR1:1; /**< bit: 1 XDMAC Channel 1 Read Write Resume Bit */ 2049 uint32_t RWR2:1; /**< bit: 2 XDMAC Channel 2 Read Write Resume Bit */ 2050 uint32_t RWR3:1; /**< bit: 3 XDMAC Channel 3 Read Write Resume Bit */ 2051 uint32_t RWR4:1; /**< bit: 4 XDMAC Channel 4 Read Write Resume Bit */ 2052 uint32_t RWR5:1; /**< bit: 5 XDMAC Channel 5 Read Write Resume Bit */ 2053 uint32_t RWR6:1; /**< bit: 6 XDMAC Channel 6 Read Write Resume Bit */ 2054 uint32_t RWR7:1; /**< bit: 7 XDMAC Channel 7 Read Write Resume Bit */ 2055 uint32_t RWR8:1; /**< bit: 8 XDMAC Channel 8 Read Write Resume Bit */ 2056 uint32_t RWR9:1; /**< bit: 9 XDMAC Channel 9 Read Write Resume Bit */ 2057 uint32_t RWR10:1; /**< bit: 10 XDMAC Channel 10 Read Write Resume Bit */ 2058 uint32_t RWR11:1; /**< bit: 11 XDMAC Channel 11 Read Write Resume Bit */ 2059 uint32_t RWR12:1; /**< bit: 12 XDMAC Channel 12 Read Write Resume Bit */ 2060 uint32_t RWR13:1; /**< bit: 13 XDMAC Channel 13 Read Write Resume Bit */ 2061 uint32_t RWR14:1; /**< bit: 14 XDMAC Channel 14 Read Write Resume Bit */ 2062 uint32_t RWR15:1; /**< bit: 15 XDMAC Channel 15 Read Write Resume Bit */ 2063 uint32_t RWR16:1; /**< bit: 16 XDMAC Channel 16 Read Write Resume Bit */ 2064 uint32_t RWR17:1; /**< bit: 17 XDMAC Channel 17 Read Write Resume Bit */ 2065 uint32_t RWR18:1; /**< bit: 18 XDMAC Channel 18 Read Write Resume Bit */ 2066 uint32_t RWR19:1; /**< bit: 19 XDMAC Channel 19 Read Write Resume Bit */ 2067 uint32_t RWR20:1; /**< bit: 20 XDMAC Channel 20 Read Write Resume Bit */ 2068 uint32_t RWR21:1; /**< bit: 21 XDMAC Channel 21 Read Write Resume Bit */ 2069 uint32_t RWR22:1; /**< bit: 22 XDMAC Channel 22 Read Write Resume Bit */ 2070 uint32_t RWR23:1; /**< bit: 23 XDMAC Channel 23 Read Write Resume Bit */ 2071 uint32_t :8; /**< bit: 24..31 Reserved */ 2072 } bit; /**< Structure used for bit access */ 2073 struct { 2074 uint32_t RWR:24; /**< bit: 0..23 XDMAC Channel 23 Read Write Resume Bit */ 2075 uint32_t :8; /**< bit: 24..31 Reserved */ 2076 } vec; /**< Structure used for vec access */ 2077 uint32_t reg; /**< Type used for register access */ 2078 } XDMAC_GRWR_Type; 2079 #endif 2080 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2081 2082 #define XDMAC_GRWR_OFFSET (0x34) /**< (XDMAC_GRWR) Global Channel Read Write Resume Register Offset */ 2083 2084 #define XDMAC_GRWR_RWR0_Pos 0 /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Position */ 2085 #define XDMAC_GRWR_RWR0_Msk (_U_(0x1) << XDMAC_GRWR_RWR0_Pos) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Mask */ 2086 #define XDMAC_GRWR_RWR0 XDMAC_GRWR_RWR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR0_Msk instead */ 2087 #define XDMAC_GRWR_RWR1_Pos 1 /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Position */ 2088 #define XDMAC_GRWR_RWR1_Msk (_U_(0x1) << XDMAC_GRWR_RWR1_Pos) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Mask */ 2089 #define XDMAC_GRWR_RWR1 XDMAC_GRWR_RWR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR1_Msk instead */ 2090 #define XDMAC_GRWR_RWR2_Pos 2 /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Position */ 2091 #define XDMAC_GRWR_RWR2_Msk (_U_(0x1) << XDMAC_GRWR_RWR2_Pos) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Mask */ 2092 #define XDMAC_GRWR_RWR2 XDMAC_GRWR_RWR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR2_Msk instead */ 2093 #define XDMAC_GRWR_RWR3_Pos 3 /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Position */ 2094 #define XDMAC_GRWR_RWR3_Msk (_U_(0x1) << XDMAC_GRWR_RWR3_Pos) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Mask */ 2095 #define XDMAC_GRWR_RWR3 XDMAC_GRWR_RWR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR3_Msk instead */ 2096 #define XDMAC_GRWR_RWR4_Pos 4 /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Position */ 2097 #define XDMAC_GRWR_RWR4_Msk (_U_(0x1) << XDMAC_GRWR_RWR4_Pos) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Mask */ 2098 #define XDMAC_GRWR_RWR4 XDMAC_GRWR_RWR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR4_Msk instead */ 2099 #define XDMAC_GRWR_RWR5_Pos 5 /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Position */ 2100 #define XDMAC_GRWR_RWR5_Msk (_U_(0x1) << XDMAC_GRWR_RWR5_Pos) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Mask */ 2101 #define XDMAC_GRWR_RWR5 XDMAC_GRWR_RWR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR5_Msk instead */ 2102 #define XDMAC_GRWR_RWR6_Pos 6 /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Position */ 2103 #define XDMAC_GRWR_RWR6_Msk (_U_(0x1) << XDMAC_GRWR_RWR6_Pos) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Mask */ 2104 #define XDMAC_GRWR_RWR6 XDMAC_GRWR_RWR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR6_Msk instead */ 2105 #define XDMAC_GRWR_RWR7_Pos 7 /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Position */ 2106 #define XDMAC_GRWR_RWR7_Msk (_U_(0x1) << XDMAC_GRWR_RWR7_Pos) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Mask */ 2107 #define XDMAC_GRWR_RWR7 XDMAC_GRWR_RWR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR7_Msk instead */ 2108 #define XDMAC_GRWR_RWR8_Pos 8 /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Position */ 2109 #define XDMAC_GRWR_RWR8_Msk (_U_(0x1) << XDMAC_GRWR_RWR8_Pos) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Mask */ 2110 #define XDMAC_GRWR_RWR8 XDMAC_GRWR_RWR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR8_Msk instead */ 2111 #define XDMAC_GRWR_RWR9_Pos 9 /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Position */ 2112 #define XDMAC_GRWR_RWR9_Msk (_U_(0x1) << XDMAC_GRWR_RWR9_Pos) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Mask */ 2113 #define XDMAC_GRWR_RWR9 XDMAC_GRWR_RWR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR9_Msk instead */ 2114 #define XDMAC_GRWR_RWR10_Pos 10 /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Position */ 2115 #define XDMAC_GRWR_RWR10_Msk (_U_(0x1) << XDMAC_GRWR_RWR10_Pos) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Mask */ 2116 #define XDMAC_GRWR_RWR10 XDMAC_GRWR_RWR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR10_Msk instead */ 2117 #define XDMAC_GRWR_RWR11_Pos 11 /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Position */ 2118 #define XDMAC_GRWR_RWR11_Msk (_U_(0x1) << XDMAC_GRWR_RWR11_Pos) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Mask */ 2119 #define XDMAC_GRWR_RWR11 XDMAC_GRWR_RWR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR11_Msk instead */ 2120 #define XDMAC_GRWR_RWR12_Pos 12 /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Position */ 2121 #define XDMAC_GRWR_RWR12_Msk (_U_(0x1) << XDMAC_GRWR_RWR12_Pos) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Mask */ 2122 #define XDMAC_GRWR_RWR12 XDMAC_GRWR_RWR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR12_Msk instead */ 2123 #define XDMAC_GRWR_RWR13_Pos 13 /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Position */ 2124 #define XDMAC_GRWR_RWR13_Msk (_U_(0x1) << XDMAC_GRWR_RWR13_Pos) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Mask */ 2125 #define XDMAC_GRWR_RWR13 XDMAC_GRWR_RWR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR13_Msk instead */ 2126 #define XDMAC_GRWR_RWR14_Pos 14 /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Position */ 2127 #define XDMAC_GRWR_RWR14_Msk (_U_(0x1) << XDMAC_GRWR_RWR14_Pos) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Mask */ 2128 #define XDMAC_GRWR_RWR14 XDMAC_GRWR_RWR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR14_Msk instead */ 2129 #define XDMAC_GRWR_RWR15_Pos 15 /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Position */ 2130 #define XDMAC_GRWR_RWR15_Msk (_U_(0x1) << XDMAC_GRWR_RWR15_Pos) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Mask */ 2131 #define XDMAC_GRWR_RWR15 XDMAC_GRWR_RWR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR15_Msk instead */ 2132 #define XDMAC_GRWR_RWR16_Pos 16 /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Position */ 2133 #define XDMAC_GRWR_RWR16_Msk (_U_(0x1) << XDMAC_GRWR_RWR16_Pos) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Mask */ 2134 #define XDMAC_GRWR_RWR16 XDMAC_GRWR_RWR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR16_Msk instead */ 2135 #define XDMAC_GRWR_RWR17_Pos 17 /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Position */ 2136 #define XDMAC_GRWR_RWR17_Msk (_U_(0x1) << XDMAC_GRWR_RWR17_Pos) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Mask */ 2137 #define XDMAC_GRWR_RWR17 XDMAC_GRWR_RWR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR17_Msk instead */ 2138 #define XDMAC_GRWR_RWR18_Pos 18 /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Position */ 2139 #define XDMAC_GRWR_RWR18_Msk (_U_(0x1) << XDMAC_GRWR_RWR18_Pos) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Mask */ 2140 #define XDMAC_GRWR_RWR18 XDMAC_GRWR_RWR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR18_Msk instead */ 2141 #define XDMAC_GRWR_RWR19_Pos 19 /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Position */ 2142 #define XDMAC_GRWR_RWR19_Msk (_U_(0x1) << XDMAC_GRWR_RWR19_Pos) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Mask */ 2143 #define XDMAC_GRWR_RWR19 XDMAC_GRWR_RWR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR19_Msk instead */ 2144 #define XDMAC_GRWR_RWR20_Pos 20 /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Position */ 2145 #define XDMAC_GRWR_RWR20_Msk (_U_(0x1) << XDMAC_GRWR_RWR20_Pos) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Mask */ 2146 #define XDMAC_GRWR_RWR20 XDMAC_GRWR_RWR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR20_Msk instead */ 2147 #define XDMAC_GRWR_RWR21_Pos 21 /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Position */ 2148 #define XDMAC_GRWR_RWR21_Msk (_U_(0x1) << XDMAC_GRWR_RWR21_Pos) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Mask */ 2149 #define XDMAC_GRWR_RWR21 XDMAC_GRWR_RWR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR21_Msk instead */ 2150 #define XDMAC_GRWR_RWR22_Pos 22 /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Position */ 2151 #define XDMAC_GRWR_RWR22_Msk (_U_(0x1) << XDMAC_GRWR_RWR22_Pos) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Mask */ 2152 #define XDMAC_GRWR_RWR22 XDMAC_GRWR_RWR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR22_Msk instead */ 2153 #define XDMAC_GRWR_RWR23_Pos 23 /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Position */ 2154 #define XDMAC_GRWR_RWR23_Msk (_U_(0x1) << XDMAC_GRWR_RWR23_Pos) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Mask */ 2155 #define XDMAC_GRWR_RWR23 XDMAC_GRWR_RWR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR23_Msk instead */ 2156 #define XDMAC_GRWR_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRWR) Register MASK (Use XDMAC_GRWR_Msk instead) */ 2157 #define XDMAC_GRWR_Msk _U_(0xFFFFFF) /**< (XDMAC_GRWR) Register Mask */ 2158 2159 #define XDMAC_GRWR_RWR_Pos 0 /**< (XDMAC_GRWR Position) XDMAC Channel 23 Read Write Resume Bit */ 2160 #define XDMAC_GRWR_RWR_Msk (_U_(0xFFFFFF) << XDMAC_GRWR_RWR_Pos) /**< (XDMAC_GRWR Mask) RWR */ 2161 #define XDMAC_GRWR_RWR(value) (XDMAC_GRWR_RWR_Msk & ((value) << XDMAC_GRWR_RWR_Pos)) 2162 2163 /* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) (/W 32) Global Channel Software Request Register -------- */ 2164 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2165 #if COMPONENT_TYPEDEF_STYLE == 'N' 2166 typedef union { 2167 struct { 2168 uint32_t SWREQ0:1; /**< bit: 0 XDMAC Channel 0 Software Request Bit */ 2169 uint32_t SWREQ1:1; /**< bit: 1 XDMAC Channel 1 Software Request Bit */ 2170 uint32_t SWREQ2:1; /**< bit: 2 XDMAC Channel 2 Software Request Bit */ 2171 uint32_t SWREQ3:1; /**< bit: 3 XDMAC Channel 3 Software Request Bit */ 2172 uint32_t SWREQ4:1; /**< bit: 4 XDMAC Channel 4 Software Request Bit */ 2173 uint32_t SWREQ5:1; /**< bit: 5 XDMAC Channel 5 Software Request Bit */ 2174 uint32_t SWREQ6:1; /**< bit: 6 XDMAC Channel 6 Software Request Bit */ 2175 uint32_t SWREQ7:1; /**< bit: 7 XDMAC Channel 7 Software Request Bit */ 2176 uint32_t SWREQ8:1; /**< bit: 8 XDMAC Channel 8 Software Request Bit */ 2177 uint32_t SWREQ9:1; /**< bit: 9 XDMAC Channel 9 Software Request Bit */ 2178 uint32_t SWREQ10:1; /**< bit: 10 XDMAC Channel 10 Software Request Bit */ 2179 uint32_t SWREQ11:1; /**< bit: 11 XDMAC Channel 11 Software Request Bit */ 2180 uint32_t SWREQ12:1; /**< bit: 12 XDMAC Channel 12 Software Request Bit */ 2181 uint32_t SWREQ13:1; /**< bit: 13 XDMAC Channel 13 Software Request Bit */ 2182 uint32_t SWREQ14:1; /**< bit: 14 XDMAC Channel 14 Software Request Bit */ 2183 uint32_t SWREQ15:1; /**< bit: 15 XDMAC Channel 15 Software Request Bit */ 2184 uint32_t SWREQ16:1; /**< bit: 16 XDMAC Channel 16 Software Request Bit */ 2185 uint32_t SWREQ17:1; /**< bit: 17 XDMAC Channel 17 Software Request Bit */ 2186 uint32_t SWREQ18:1; /**< bit: 18 XDMAC Channel 18 Software Request Bit */ 2187 uint32_t SWREQ19:1; /**< bit: 19 XDMAC Channel 19 Software Request Bit */ 2188 uint32_t SWREQ20:1; /**< bit: 20 XDMAC Channel 20 Software Request Bit */ 2189 uint32_t SWREQ21:1; /**< bit: 21 XDMAC Channel 21 Software Request Bit */ 2190 uint32_t SWREQ22:1; /**< bit: 22 XDMAC Channel 22 Software Request Bit */ 2191 uint32_t SWREQ23:1; /**< bit: 23 XDMAC Channel 23 Software Request Bit */ 2192 uint32_t :8; /**< bit: 24..31 Reserved */ 2193 } bit; /**< Structure used for bit access */ 2194 struct { 2195 uint32_t SWREQ:24; /**< bit: 0..23 XDMAC Channel 23 Software Request Bit */ 2196 uint32_t :8; /**< bit: 24..31 Reserved */ 2197 } vec; /**< Structure used for vec access */ 2198 uint32_t reg; /**< Type used for register access */ 2199 } XDMAC_GSWR_Type; 2200 #endif 2201 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2202 2203 #define XDMAC_GSWR_OFFSET (0x38) /**< (XDMAC_GSWR) Global Channel Software Request Register Offset */ 2204 2205 #define XDMAC_GSWR_SWREQ0_Pos 0 /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Position */ 2206 #define XDMAC_GSWR_SWREQ0_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ0_Pos) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Mask */ 2207 #define XDMAC_GSWR_SWREQ0 XDMAC_GSWR_SWREQ0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ0_Msk instead */ 2208 #define XDMAC_GSWR_SWREQ1_Pos 1 /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Position */ 2209 #define XDMAC_GSWR_SWREQ1_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ1_Pos) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Mask */ 2210 #define XDMAC_GSWR_SWREQ1 XDMAC_GSWR_SWREQ1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ1_Msk instead */ 2211 #define XDMAC_GSWR_SWREQ2_Pos 2 /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Position */ 2212 #define XDMAC_GSWR_SWREQ2_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ2_Pos) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Mask */ 2213 #define XDMAC_GSWR_SWREQ2 XDMAC_GSWR_SWREQ2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ2_Msk instead */ 2214 #define XDMAC_GSWR_SWREQ3_Pos 3 /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Position */ 2215 #define XDMAC_GSWR_SWREQ3_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ3_Pos) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Mask */ 2216 #define XDMAC_GSWR_SWREQ3 XDMAC_GSWR_SWREQ3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ3_Msk instead */ 2217 #define XDMAC_GSWR_SWREQ4_Pos 4 /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Position */ 2218 #define XDMAC_GSWR_SWREQ4_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ4_Pos) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Mask */ 2219 #define XDMAC_GSWR_SWREQ4 XDMAC_GSWR_SWREQ4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ4_Msk instead */ 2220 #define XDMAC_GSWR_SWREQ5_Pos 5 /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Position */ 2221 #define XDMAC_GSWR_SWREQ5_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ5_Pos) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Mask */ 2222 #define XDMAC_GSWR_SWREQ5 XDMAC_GSWR_SWREQ5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ5_Msk instead */ 2223 #define XDMAC_GSWR_SWREQ6_Pos 6 /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Position */ 2224 #define XDMAC_GSWR_SWREQ6_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ6_Pos) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Mask */ 2225 #define XDMAC_GSWR_SWREQ6 XDMAC_GSWR_SWREQ6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ6_Msk instead */ 2226 #define XDMAC_GSWR_SWREQ7_Pos 7 /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Position */ 2227 #define XDMAC_GSWR_SWREQ7_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ7_Pos) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Mask */ 2228 #define XDMAC_GSWR_SWREQ7 XDMAC_GSWR_SWREQ7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ7_Msk instead */ 2229 #define XDMAC_GSWR_SWREQ8_Pos 8 /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Position */ 2230 #define XDMAC_GSWR_SWREQ8_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ8_Pos) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Mask */ 2231 #define XDMAC_GSWR_SWREQ8 XDMAC_GSWR_SWREQ8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ8_Msk instead */ 2232 #define XDMAC_GSWR_SWREQ9_Pos 9 /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Position */ 2233 #define XDMAC_GSWR_SWREQ9_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ9_Pos) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Mask */ 2234 #define XDMAC_GSWR_SWREQ9 XDMAC_GSWR_SWREQ9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ9_Msk instead */ 2235 #define XDMAC_GSWR_SWREQ10_Pos 10 /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Position */ 2236 #define XDMAC_GSWR_SWREQ10_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ10_Pos) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Mask */ 2237 #define XDMAC_GSWR_SWREQ10 XDMAC_GSWR_SWREQ10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ10_Msk instead */ 2238 #define XDMAC_GSWR_SWREQ11_Pos 11 /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Position */ 2239 #define XDMAC_GSWR_SWREQ11_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ11_Pos) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Mask */ 2240 #define XDMAC_GSWR_SWREQ11 XDMAC_GSWR_SWREQ11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ11_Msk instead */ 2241 #define XDMAC_GSWR_SWREQ12_Pos 12 /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Position */ 2242 #define XDMAC_GSWR_SWREQ12_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ12_Pos) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Mask */ 2243 #define XDMAC_GSWR_SWREQ12 XDMAC_GSWR_SWREQ12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ12_Msk instead */ 2244 #define XDMAC_GSWR_SWREQ13_Pos 13 /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Position */ 2245 #define XDMAC_GSWR_SWREQ13_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ13_Pos) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Mask */ 2246 #define XDMAC_GSWR_SWREQ13 XDMAC_GSWR_SWREQ13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ13_Msk instead */ 2247 #define XDMAC_GSWR_SWREQ14_Pos 14 /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Position */ 2248 #define XDMAC_GSWR_SWREQ14_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ14_Pos) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Mask */ 2249 #define XDMAC_GSWR_SWREQ14 XDMAC_GSWR_SWREQ14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ14_Msk instead */ 2250 #define XDMAC_GSWR_SWREQ15_Pos 15 /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Position */ 2251 #define XDMAC_GSWR_SWREQ15_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ15_Pos) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Mask */ 2252 #define XDMAC_GSWR_SWREQ15 XDMAC_GSWR_SWREQ15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ15_Msk instead */ 2253 #define XDMAC_GSWR_SWREQ16_Pos 16 /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Position */ 2254 #define XDMAC_GSWR_SWREQ16_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ16_Pos) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Mask */ 2255 #define XDMAC_GSWR_SWREQ16 XDMAC_GSWR_SWREQ16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ16_Msk instead */ 2256 #define XDMAC_GSWR_SWREQ17_Pos 17 /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Position */ 2257 #define XDMAC_GSWR_SWREQ17_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ17_Pos) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Mask */ 2258 #define XDMAC_GSWR_SWREQ17 XDMAC_GSWR_SWREQ17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ17_Msk instead */ 2259 #define XDMAC_GSWR_SWREQ18_Pos 18 /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Position */ 2260 #define XDMAC_GSWR_SWREQ18_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ18_Pos) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Mask */ 2261 #define XDMAC_GSWR_SWREQ18 XDMAC_GSWR_SWREQ18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ18_Msk instead */ 2262 #define XDMAC_GSWR_SWREQ19_Pos 19 /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Position */ 2263 #define XDMAC_GSWR_SWREQ19_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ19_Pos) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Mask */ 2264 #define XDMAC_GSWR_SWREQ19 XDMAC_GSWR_SWREQ19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ19_Msk instead */ 2265 #define XDMAC_GSWR_SWREQ20_Pos 20 /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Position */ 2266 #define XDMAC_GSWR_SWREQ20_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ20_Pos) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Mask */ 2267 #define XDMAC_GSWR_SWREQ20 XDMAC_GSWR_SWREQ20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ20_Msk instead */ 2268 #define XDMAC_GSWR_SWREQ21_Pos 21 /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Position */ 2269 #define XDMAC_GSWR_SWREQ21_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ21_Pos) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Mask */ 2270 #define XDMAC_GSWR_SWREQ21 XDMAC_GSWR_SWREQ21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ21_Msk instead */ 2271 #define XDMAC_GSWR_SWREQ22_Pos 22 /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Position */ 2272 #define XDMAC_GSWR_SWREQ22_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ22_Pos) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Mask */ 2273 #define XDMAC_GSWR_SWREQ22 XDMAC_GSWR_SWREQ22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ22_Msk instead */ 2274 #define XDMAC_GSWR_SWREQ23_Pos 23 /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Position */ 2275 #define XDMAC_GSWR_SWREQ23_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ23_Pos) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Mask */ 2276 #define XDMAC_GSWR_SWREQ23 XDMAC_GSWR_SWREQ23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ23_Msk instead */ 2277 #define XDMAC_GSWR_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWR) Register MASK (Use XDMAC_GSWR_Msk instead) */ 2278 #define XDMAC_GSWR_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWR) Register Mask */ 2279 2280 #define XDMAC_GSWR_SWREQ_Pos 0 /**< (XDMAC_GSWR Position) XDMAC Channel 23 Software Request Bit */ 2281 #define XDMAC_GSWR_SWREQ_Msk (_U_(0xFFFFFF) << XDMAC_GSWR_SWREQ_Pos) /**< (XDMAC_GSWR Mask) SWREQ */ 2282 #define XDMAC_GSWR_SWREQ(value) (XDMAC_GSWR_SWREQ_Msk & ((value) << XDMAC_GSWR_SWREQ_Pos)) 2283 2284 /* -------- XDMAC_GSWS : (XDMAC Offset: 0x3c) (R/ 32) Global Channel Software Request Status Register -------- */ 2285 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2286 #if COMPONENT_TYPEDEF_STYLE == 'N' 2287 typedef union { 2288 struct { 2289 uint32_t SWRS0:1; /**< bit: 0 XDMAC Channel 0 Software Request Status Bit */ 2290 uint32_t SWRS1:1; /**< bit: 1 XDMAC Channel 1 Software Request Status Bit */ 2291 uint32_t SWRS2:1; /**< bit: 2 XDMAC Channel 2 Software Request Status Bit */ 2292 uint32_t SWRS3:1; /**< bit: 3 XDMAC Channel 3 Software Request Status Bit */ 2293 uint32_t SWRS4:1; /**< bit: 4 XDMAC Channel 4 Software Request Status Bit */ 2294 uint32_t SWRS5:1; /**< bit: 5 XDMAC Channel 5 Software Request Status Bit */ 2295 uint32_t SWRS6:1; /**< bit: 6 XDMAC Channel 6 Software Request Status Bit */ 2296 uint32_t SWRS7:1; /**< bit: 7 XDMAC Channel 7 Software Request Status Bit */ 2297 uint32_t SWRS8:1; /**< bit: 8 XDMAC Channel 8 Software Request Status Bit */ 2298 uint32_t SWRS9:1; /**< bit: 9 XDMAC Channel 9 Software Request Status Bit */ 2299 uint32_t SWRS10:1; /**< bit: 10 XDMAC Channel 10 Software Request Status Bit */ 2300 uint32_t SWRS11:1; /**< bit: 11 XDMAC Channel 11 Software Request Status Bit */ 2301 uint32_t SWRS12:1; /**< bit: 12 XDMAC Channel 12 Software Request Status Bit */ 2302 uint32_t SWRS13:1; /**< bit: 13 XDMAC Channel 13 Software Request Status Bit */ 2303 uint32_t SWRS14:1; /**< bit: 14 XDMAC Channel 14 Software Request Status Bit */ 2304 uint32_t SWRS15:1; /**< bit: 15 XDMAC Channel 15 Software Request Status Bit */ 2305 uint32_t SWRS16:1; /**< bit: 16 XDMAC Channel 16 Software Request Status Bit */ 2306 uint32_t SWRS17:1; /**< bit: 17 XDMAC Channel 17 Software Request Status Bit */ 2307 uint32_t SWRS18:1; /**< bit: 18 XDMAC Channel 18 Software Request Status Bit */ 2308 uint32_t SWRS19:1; /**< bit: 19 XDMAC Channel 19 Software Request Status Bit */ 2309 uint32_t SWRS20:1; /**< bit: 20 XDMAC Channel 20 Software Request Status Bit */ 2310 uint32_t SWRS21:1; /**< bit: 21 XDMAC Channel 21 Software Request Status Bit */ 2311 uint32_t SWRS22:1; /**< bit: 22 XDMAC Channel 22 Software Request Status Bit */ 2312 uint32_t SWRS23:1; /**< bit: 23 XDMAC Channel 23 Software Request Status Bit */ 2313 uint32_t :8; /**< bit: 24..31 Reserved */ 2314 } bit; /**< Structure used for bit access */ 2315 struct { 2316 uint32_t SWRS:24; /**< bit: 0..23 XDMAC Channel 23 Software Request Status Bit */ 2317 uint32_t :8; /**< bit: 24..31 Reserved */ 2318 } vec; /**< Structure used for vec access */ 2319 uint32_t reg; /**< Type used for register access */ 2320 } XDMAC_GSWS_Type; 2321 #endif 2322 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2323 2324 #define XDMAC_GSWS_OFFSET (0x3C) /**< (XDMAC_GSWS) Global Channel Software Request Status Register Offset */ 2325 2326 #define XDMAC_GSWS_SWRS0_Pos 0 /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Position */ 2327 #define XDMAC_GSWS_SWRS0_Msk (_U_(0x1) << XDMAC_GSWS_SWRS0_Pos) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Mask */ 2328 #define XDMAC_GSWS_SWRS0 XDMAC_GSWS_SWRS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS0_Msk instead */ 2329 #define XDMAC_GSWS_SWRS1_Pos 1 /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Position */ 2330 #define XDMAC_GSWS_SWRS1_Msk (_U_(0x1) << XDMAC_GSWS_SWRS1_Pos) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Mask */ 2331 #define XDMAC_GSWS_SWRS1 XDMAC_GSWS_SWRS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS1_Msk instead */ 2332 #define XDMAC_GSWS_SWRS2_Pos 2 /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Position */ 2333 #define XDMAC_GSWS_SWRS2_Msk (_U_(0x1) << XDMAC_GSWS_SWRS2_Pos) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Mask */ 2334 #define XDMAC_GSWS_SWRS2 XDMAC_GSWS_SWRS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS2_Msk instead */ 2335 #define XDMAC_GSWS_SWRS3_Pos 3 /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Position */ 2336 #define XDMAC_GSWS_SWRS3_Msk (_U_(0x1) << XDMAC_GSWS_SWRS3_Pos) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Mask */ 2337 #define XDMAC_GSWS_SWRS3 XDMAC_GSWS_SWRS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS3_Msk instead */ 2338 #define XDMAC_GSWS_SWRS4_Pos 4 /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Position */ 2339 #define XDMAC_GSWS_SWRS4_Msk (_U_(0x1) << XDMAC_GSWS_SWRS4_Pos) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Mask */ 2340 #define XDMAC_GSWS_SWRS4 XDMAC_GSWS_SWRS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS4_Msk instead */ 2341 #define XDMAC_GSWS_SWRS5_Pos 5 /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Position */ 2342 #define XDMAC_GSWS_SWRS5_Msk (_U_(0x1) << XDMAC_GSWS_SWRS5_Pos) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Mask */ 2343 #define XDMAC_GSWS_SWRS5 XDMAC_GSWS_SWRS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS5_Msk instead */ 2344 #define XDMAC_GSWS_SWRS6_Pos 6 /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Position */ 2345 #define XDMAC_GSWS_SWRS6_Msk (_U_(0x1) << XDMAC_GSWS_SWRS6_Pos) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Mask */ 2346 #define XDMAC_GSWS_SWRS6 XDMAC_GSWS_SWRS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS6_Msk instead */ 2347 #define XDMAC_GSWS_SWRS7_Pos 7 /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Position */ 2348 #define XDMAC_GSWS_SWRS7_Msk (_U_(0x1) << XDMAC_GSWS_SWRS7_Pos) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Mask */ 2349 #define XDMAC_GSWS_SWRS7 XDMAC_GSWS_SWRS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS7_Msk instead */ 2350 #define XDMAC_GSWS_SWRS8_Pos 8 /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Position */ 2351 #define XDMAC_GSWS_SWRS8_Msk (_U_(0x1) << XDMAC_GSWS_SWRS8_Pos) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Mask */ 2352 #define XDMAC_GSWS_SWRS8 XDMAC_GSWS_SWRS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS8_Msk instead */ 2353 #define XDMAC_GSWS_SWRS9_Pos 9 /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Position */ 2354 #define XDMAC_GSWS_SWRS9_Msk (_U_(0x1) << XDMAC_GSWS_SWRS9_Pos) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Mask */ 2355 #define XDMAC_GSWS_SWRS9 XDMAC_GSWS_SWRS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS9_Msk instead */ 2356 #define XDMAC_GSWS_SWRS10_Pos 10 /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Position */ 2357 #define XDMAC_GSWS_SWRS10_Msk (_U_(0x1) << XDMAC_GSWS_SWRS10_Pos) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Mask */ 2358 #define XDMAC_GSWS_SWRS10 XDMAC_GSWS_SWRS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS10_Msk instead */ 2359 #define XDMAC_GSWS_SWRS11_Pos 11 /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Position */ 2360 #define XDMAC_GSWS_SWRS11_Msk (_U_(0x1) << XDMAC_GSWS_SWRS11_Pos) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Mask */ 2361 #define XDMAC_GSWS_SWRS11 XDMAC_GSWS_SWRS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS11_Msk instead */ 2362 #define XDMAC_GSWS_SWRS12_Pos 12 /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Position */ 2363 #define XDMAC_GSWS_SWRS12_Msk (_U_(0x1) << XDMAC_GSWS_SWRS12_Pos) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Mask */ 2364 #define XDMAC_GSWS_SWRS12 XDMAC_GSWS_SWRS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS12_Msk instead */ 2365 #define XDMAC_GSWS_SWRS13_Pos 13 /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Position */ 2366 #define XDMAC_GSWS_SWRS13_Msk (_U_(0x1) << XDMAC_GSWS_SWRS13_Pos) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Mask */ 2367 #define XDMAC_GSWS_SWRS13 XDMAC_GSWS_SWRS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS13_Msk instead */ 2368 #define XDMAC_GSWS_SWRS14_Pos 14 /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Position */ 2369 #define XDMAC_GSWS_SWRS14_Msk (_U_(0x1) << XDMAC_GSWS_SWRS14_Pos) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Mask */ 2370 #define XDMAC_GSWS_SWRS14 XDMAC_GSWS_SWRS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS14_Msk instead */ 2371 #define XDMAC_GSWS_SWRS15_Pos 15 /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Position */ 2372 #define XDMAC_GSWS_SWRS15_Msk (_U_(0x1) << XDMAC_GSWS_SWRS15_Pos) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Mask */ 2373 #define XDMAC_GSWS_SWRS15 XDMAC_GSWS_SWRS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS15_Msk instead */ 2374 #define XDMAC_GSWS_SWRS16_Pos 16 /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Position */ 2375 #define XDMAC_GSWS_SWRS16_Msk (_U_(0x1) << XDMAC_GSWS_SWRS16_Pos) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Mask */ 2376 #define XDMAC_GSWS_SWRS16 XDMAC_GSWS_SWRS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS16_Msk instead */ 2377 #define XDMAC_GSWS_SWRS17_Pos 17 /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Position */ 2378 #define XDMAC_GSWS_SWRS17_Msk (_U_(0x1) << XDMAC_GSWS_SWRS17_Pos) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Mask */ 2379 #define XDMAC_GSWS_SWRS17 XDMAC_GSWS_SWRS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS17_Msk instead */ 2380 #define XDMAC_GSWS_SWRS18_Pos 18 /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Position */ 2381 #define XDMAC_GSWS_SWRS18_Msk (_U_(0x1) << XDMAC_GSWS_SWRS18_Pos) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Mask */ 2382 #define XDMAC_GSWS_SWRS18 XDMAC_GSWS_SWRS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS18_Msk instead */ 2383 #define XDMAC_GSWS_SWRS19_Pos 19 /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Position */ 2384 #define XDMAC_GSWS_SWRS19_Msk (_U_(0x1) << XDMAC_GSWS_SWRS19_Pos) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Mask */ 2385 #define XDMAC_GSWS_SWRS19 XDMAC_GSWS_SWRS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS19_Msk instead */ 2386 #define XDMAC_GSWS_SWRS20_Pos 20 /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Position */ 2387 #define XDMAC_GSWS_SWRS20_Msk (_U_(0x1) << XDMAC_GSWS_SWRS20_Pos) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Mask */ 2388 #define XDMAC_GSWS_SWRS20 XDMAC_GSWS_SWRS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS20_Msk instead */ 2389 #define XDMAC_GSWS_SWRS21_Pos 21 /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Position */ 2390 #define XDMAC_GSWS_SWRS21_Msk (_U_(0x1) << XDMAC_GSWS_SWRS21_Pos) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Mask */ 2391 #define XDMAC_GSWS_SWRS21 XDMAC_GSWS_SWRS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS21_Msk instead */ 2392 #define XDMAC_GSWS_SWRS22_Pos 22 /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Position */ 2393 #define XDMAC_GSWS_SWRS22_Msk (_U_(0x1) << XDMAC_GSWS_SWRS22_Pos) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Mask */ 2394 #define XDMAC_GSWS_SWRS22 XDMAC_GSWS_SWRS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS22_Msk instead */ 2395 #define XDMAC_GSWS_SWRS23_Pos 23 /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Position */ 2396 #define XDMAC_GSWS_SWRS23_Msk (_U_(0x1) << XDMAC_GSWS_SWRS23_Pos) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Mask */ 2397 #define XDMAC_GSWS_SWRS23 XDMAC_GSWS_SWRS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS23_Msk instead */ 2398 #define XDMAC_GSWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWS) Register MASK (Use XDMAC_GSWS_Msk instead) */ 2399 #define XDMAC_GSWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWS) Register Mask */ 2400 2401 #define XDMAC_GSWS_SWRS_Pos 0 /**< (XDMAC_GSWS Position) XDMAC Channel 23 Software Request Status Bit */ 2402 #define XDMAC_GSWS_SWRS_Msk (_U_(0xFFFFFF) << XDMAC_GSWS_SWRS_Pos) /**< (XDMAC_GSWS Mask) SWRS */ 2403 #define XDMAC_GSWS_SWRS(value) (XDMAC_GSWS_SWRS_Msk & ((value) << XDMAC_GSWS_SWRS_Pos)) 2404 2405 /* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) (/W 32) Global Channel Software Flush Request Register -------- */ 2406 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2407 #if COMPONENT_TYPEDEF_STYLE == 'N' 2408 typedef union { 2409 struct { 2410 uint32_t SWF0:1; /**< bit: 0 XDMAC Channel 0 Software Flush Request Bit */ 2411 uint32_t SWF1:1; /**< bit: 1 XDMAC Channel 1 Software Flush Request Bit */ 2412 uint32_t SWF2:1; /**< bit: 2 XDMAC Channel 2 Software Flush Request Bit */ 2413 uint32_t SWF3:1; /**< bit: 3 XDMAC Channel 3 Software Flush Request Bit */ 2414 uint32_t SWF4:1; /**< bit: 4 XDMAC Channel 4 Software Flush Request Bit */ 2415 uint32_t SWF5:1; /**< bit: 5 XDMAC Channel 5 Software Flush Request Bit */ 2416 uint32_t SWF6:1; /**< bit: 6 XDMAC Channel 6 Software Flush Request Bit */ 2417 uint32_t SWF7:1; /**< bit: 7 XDMAC Channel 7 Software Flush Request Bit */ 2418 uint32_t SWF8:1; /**< bit: 8 XDMAC Channel 8 Software Flush Request Bit */ 2419 uint32_t SWF9:1; /**< bit: 9 XDMAC Channel 9 Software Flush Request Bit */ 2420 uint32_t SWF10:1; /**< bit: 10 XDMAC Channel 10 Software Flush Request Bit */ 2421 uint32_t SWF11:1; /**< bit: 11 XDMAC Channel 11 Software Flush Request Bit */ 2422 uint32_t SWF12:1; /**< bit: 12 XDMAC Channel 12 Software Flush Request Bit */ 2423 uint32_t SWF13:1; /**< bit: 13 XDMAC Channel 13 Software Flush Request Bit */ 2424 uint32_t SWF14:1; /**< bit: 14 XDMAC Channel 14 Software Flush Request Bit */ 2425 uint32_t SWF15:1; /**< bit: 15 XDMAC Channel 15 Software Flush Request Bit */ 2426 uint32_t SWF16:1; /**< bit: 16 XDMAC Channel 16 Software Flush Request Bit */ 2427 uint32_t SWF17:1; /**< bit: 17 XDMAC Channel 17 Software Flush Request Bit */ 2428 uint32_t SWF18:1; /**< bit: 18 XDMAC Channel 18 Software Flush Request Bit */ 2429 uint32_t SWF19:1; /**< bit: 19 XDMAC Channel 19 Software Flush Request Bit */ 2430 uint32_t SWF20:1; /**< bit: 20 XDMAC Channel 20 Software Flush Request Bit */ 2431 uint32_t SWF21:1; /**< bit: 21 XDMAC Channel 21 Software Flush Request Bit */ 2432 uint32_t SWF22:1; /**< bit: 22 XDMAC Channel 22 Software Flush Request Bit */ 2433 uint32_t SWF23:1; /**< bit: 23 XDMAC Channel 23 Software Flush Request Bit */ 2434 uint32_t :8; /**< bit: 24..31 Reserved */ 2435 } bit; /**< Structure used for bit access */ 2436 struct { 2437 uint32_t SWF:24; /**< bit: 0..23 XDMAC Channel 23 Software Flush Request Bit */ 2438 uint32_t :8; /**< bit: 24..31 Reserved */ 2439 } vec; /**< Structure used for vec access */ 2440 uint32_t reg; /**< Type used for register access */ 2441 } XDMAC_GSWF_Type; 2442 #endif 2443 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2444 2445 #define XDMAC_GSWF_OFFSET (0x40) /**< (XDMAC_GSWF) Global Channel Software Flush Request Register Offset */ 2446 2447 #define XDMAC_GSWF_SWF0_Pos 0 /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Position */ 2448 #define XDMAC_GSWF_SWF0_Msk (_U_(0x1) << XDMAC_GSWF_SWF0_Pos) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Mask */ 2449 #define XDMAC_GSWF_SWF0 XDMAC_GSWF_SWF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF0_Msk instead */ 2450 #define XDMAC_GSWF_SWF1_Pos 1 /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Position */ 2451 #define XDMAC_GSWF_SWF1_Msk (_U_(0x1) << XDMAC_GSWF_SWF1_Pos) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Mask */ 2452 #define XDMAC_GSWF_SWF1 XDMAC_GSWF_SWF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF1_Msk instead */ 2453 #define XDMAC_GSWF_SWF2_Pos 2 /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Position */ 2454 #define XDMAC_GSWF_SWF2_Msk (_U_(0x1) << XDMAC_GSWF_SWF2_Pos) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Mask */ 2455 #define XDMAC_GSWF_SWF2 XDMAC_GSWF_SWF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF2_Msk instead */ 2456 #define XDMAC_GSWF_SWF3_Pos 3 /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Position */ 2457 #define XDMAC_GSWF_SWF3_Msk (_U_(0x1) << XDMAC_GSWF_SWF3_Pos) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Mask */ 2458 #define XDMAC_GSWF_SWF3 XDMAC_GSWF_SWF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF3_Msk instead */ 2459 #define XDMAC_GSWF_SWF4_Pos 4 /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Position */ 2460 #define XDMAC_GSWF_SWF4_Msk (_U_(0x1) << XDMAC_GSWF_SWF4_Pos) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Mask */ 2461 #define XDMAC_GSWF_SWF4 XDMAC_GSWF_SWF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF4_Msk instead */ 2462 #define XDMAC_GSWF_SWF5_Pos 5 /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Position */ 2463 #define XDMAC_GSWF_SWF5_Msk (_U_(0x1) << XDMAC_GSWF_SWF5_Pos) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Mask */ 2464 #define XDMAC_GSWF_SWF5 XDMAC_GSWF_SWF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF5_Msk instead */ 2465 #define XDMAC_GSWF_SWF6_Pos 6 /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Position */ 2466 #define XDMAC_GSWF_SWF6_Msk (_U_(0x1) << XDMAC_GSWF_SWF6_Pos) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Mask */ 2467 #define XDMAC_GSWF_SWF6 XDMAC_GSWF_SWF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF6_Msk instead */ 2468 #define XDMAC_GSWF_SWF7_Pos 7 /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Position */ 2469 #define XDMAC_GSWF_SWF7_Msk (_U_(0x1) << XDMAC_GSWF_SWF7_Pos) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Mask */ 2470 #define XDMAC_GSWF_SWF7 XDMAC_GSWF_SWF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF7_Msk instead */ 2471 #define XDMAC_GSWF_SWF8_Pos 8 /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Position */ 2472 #define XDMAC_GSWF_SWF8_Msk (_U_(0x1) << XDMAC_GSWF_SWF8_Pos) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Mask */ 2473 #define XDMAC_GSWF_SWF8 XDMAC_GSWF_SWF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF8_Msk instead */ 2474 #define XDMAC_GSWF_SWF9_Pos 9 /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Position */ 2475 #define XDMAC_GSWF_SWF9_Msk (_U_(0x1) << XDMAC_GSWF_SWF9_Pos) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Mask */ 2476 #define XDMAC_GSWF_SWF9 XDMAC_GSWF_SWF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF9_Msk instead */ 2477 #define XDMAC_GSWF_SWF10_Pos 10 /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Position */ 2478 #define XDMAC_GSWF_SWF10_Msk (_U_(0x1) << XDMAC_GSWF_SWF10_Pos) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Mask */ 2479 #define XDMAC_GSWF_SWF10 XDMAC_GSWF_SWF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF10_Msk instead */ 2480 #define XDMAC_GSWF_SWF11_Pos 11 /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Position */ 2481 #define XDMAC_GSWF_SWF11_Msk (_U_(0x1) << XDMAC_GSWF_SWF11_Pos) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Mask */ 2482 #define XDMAC_GSWF_SWF11 XDMAC_GSWF_SWF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF11_Msk instead */ 2483 #define XDMAC_GSWF_SWF12_Pos 12 /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Position */ 2484 #define XDMAC_GSWF_SWF12_Msk (_U_(0x1) << XDMAC_GSWF_SWF12_Pos) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Mask */ 2485 #define XDMAC_GSWF_SWF12 XDMAC_GSWF_SWF12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF12_Msk instead */ 2486 #define XDMAC_GSWF_SWF13_Pos 13 /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Position */ 2487 #define XDMAC_GSWF_SWF13_Msk (_U_(0x1) << XDMAC_GSWF_SWF13_Pos) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Mask */ 2488 #define XDMAC_GSWF_SWF13 XDMAC_GSWF_SWF13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF13_Msk instead */ 2489 #define XDMAC_GSWF_SWF14_Pos 14 /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Position */ 2490 #define XDMAC_GSWF_SWF14_Msk (_U_(0x1) << XDMAC_GSWF_SWF14_Pos) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Mask */ 2491 #define XDMAC_GSWF_SWF14 XDMAC_GSWF_SWF14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF14_Msk instead */ 2492 #define XDMAC_GSWF_SWF15_Pos 15 /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Position */ 2493 #define XDMAC_GSWF_SWF15_Msk (_U_(0x1) << XDMAC_GSWF_SWF15_Pos) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Mask */ 2494 #define XDMAC_GSWF_SWF15 XDMAC_GSWF_SWF15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF15_Msk instead */ 2495 #define XDMAC_GSWF_SWF16_Pos 16 /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Position */ 2496 #define XDMAC_GSWF_SWF16_Msk (_U_(0x1) << XDMAC_GSWF_SWF16_Pos) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Mask */ 2497 #define XDMAC_GSWF_SWF16 XDMAC_GSWF_SWF16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF16_Msk instead */ 2498 #define XDMAC_GSWF_SWF17_Pos 17 /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Position */ 2499 #define XDMAC_GSWF_SWF17_Msk (_U_(0x1) << XDMAC_GSWF_SWF17_Pos) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Mask */ 2500 #define XDMAC_GSWF_SWF17 XDMAC_GSWF_SWF17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF17_Msk instead */ 2501 #define XDMAC_GSWF_SWF18_Pos 18 /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Position */ 2502 #define XDMAC_GSWF_SWF18_Msk (_U_(0x1) << XDMAC_GSWF_SWF18_Pos) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Mask */ 2503 #define XDMAC_GSWF_SWF18 XDMAC_GSWF_SWF18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF18_Msk instead */ 2504 #define XDMAC_GSWF_SWF19_Pos 19 /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Position */ 2505 #define XDMAC_GSWF_SWF19_Msk (_U_(0x1) << XDMAC_GSWF_SWF19_Pos) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Mask */ 2506 #define XDMAC_GSWF_SWF19 XDMAC_GSWF_SWF19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF19_Msk instead */ 2507 #define XDMAC_GSWF_SWF20_Pos 20 /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Position */ 2508 #define XDMAC_GSWF_SWF20_Msk (_U_(0x1) << XDMAC_GSWF_SWF20_Pos) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Mask */ 2509 #define XDMAC_GSWF_SWF20 XDMAC_GSWF_SWF20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF20_Msk instead */ 2510 #define XDMAC_GSWF_SWF21_Pos 21 /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Position */ 2511 #define XDMAC_GSWF_SWF21_Msk (_U_(0x1) << XDMAC_GSWF_SWF21_Pos) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Mask */ 2512 #define XDMAC_GSWF_SWF21 XDMAC_GSWF_SWF21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF21_Msk instead */ 2513 #define XDMAC_GSWF_SWF22_Pos 22 /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Position */ 2514 #define XDMAC_GSWF_SWF22_Msk (_U_(0x1) << XDMAC_GSWF_SWF22_Pos) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Mask */ 2515 #define XDMAC_GSWF_SWF22 XDMAC_GSWF_SWF22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF22_Msk instead */ 2516 #define XDMAC_GSWF_SWF23_Pos 23 /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Position */ 2517 #define XDMAC_GSWF_SWF23_Msk (_U_(0x1) << XDMAC_GSWF_SWF23_Pos) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Mask */ 2518 #define XDMAC_GSWF_SWF23 XDMAC_GSWF_SWF23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF23_Msk instead */ 2519 #define XDMAC_GSWF_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWF) Register MASK (Use XDMAC_GSWF_Msk instead) */ 2520 #define XDMAC_GSWF_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWF) Register Mask */ 2521 2522 #define XDMAC_GSWF_SWF_Pos 0 /**< (XDMAC_GSWF Position) XDMAC Channel 23 Software Flush Request Bit */ 2523 #define XDMAC_GSWF_SWF_Msk (_U_(0xFFFFFF) << XDMAC_GSWF_SWF_Pos) /**< (XDMAC_GSWF Mask) SWF */ 2524 #define XDMAC_GSWF_SWF(value) (XDMAC_GSWF_SWF_Msk & ((value) << XDMAC_GSWF_SWF_Pos)) 2525 2526 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2527 #if COMPONENT_TYPEDEF_STYLE == 'R' 2528 /** \brief XDMAC_CHID hardware registers */ 2529 typedef struct { 2530 __O uint32_t XDMAC_CIE; /**< (XDMAC_CHID Offset: 0x00) Channel Interrupt Enable Register */ 2531 __O uint32_t XDMAC_CID; /**< (XDMAC_CHID Offset: 0x04) Channel Interrupt Disable Register */ 2532 __I uint32_t XDMAC_CIM; /**< (XDMAC_CHID Offset: 0x08) Channel Interrupt Mask Register */ 2533 __I uint32_t XDMAC_CIS; /**< (XDMAC_CHID Offset: 0x0C) Channel Interrupt Status Register */ 2534 __IO uint32_t XDMAC_CSA; /**< (XDMAC_CHID Offset: 0x10) Channel Source Address Register */ 2535 __IO uint32_t XDMAC_CDA; /**< (XDMAC_CHID Offset: 0x14) Channel Destination Address Register */ 2536 __IO uint32_t XDMAC_CNDA; /**< (XDMAC_CHID Offset: 0x18) Channel Next Descriptor Address Register */ 2537 __IO uint32_t XDMAC_CNDC; /**< (XDMAC_CHID Offset: 0x1C) Channel Next Descriptor Control Register */ 2538 __IO uint32_t XDMAC_CUBC; /**< (XDMAC_CHID Offset: 0x20) Channel Microblock Control Register */ 2539 __IO uint32_t XDMAC_CBC; /**< (XDMAC_CHID Offset: 0x24) Channel Block Control Register */ 2540 __IO uint32_t XDMAC_CC; /**< (XDMAC_CHID Offset: 0x28) Channel Configuration Register */ 2541 __IO uint32_t XDMAC_CDS_MSP; /**< (XDMAC_CHID Offset: 0x2C) Channel Data Stride Memory Set Pattern */ 2542 __IO uint32_t XDMAC_CSUS; /**< (XDMAC_CHID Offset: 0x30) Channel Source Microblock Stride */ 2543 __IO uint32_t XDMAC_CDUS; /**< (XDMAC_CHID Offset: 0x34) Channel Destination Microblock Stride */ 2544 __I uint8_t Reserved1[8]; 2545 } XdmacChid; 2546 2547 #define XDMACCHID_NUMBER 24 2548 /** \brief XDMAC hardware registers */ 2549 typedef struct { 2550 __I uint32_t XDMAC_GTYPE; /**< (XDMAC Offset: 0x00) Global Type Register */ 2551 __IO uint32_t XDMAC_GCFG; /**< (XDMAC Offset: 0x04) Global Configuration Register */ 2552 __IO uint32_t XDMAC_GWAC; /**< (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register */ 2553 __O uint32_t XDMAC_GIE; /**< (XDMAC Offset: 0x0C) Global Interrupt Enable Register */ 2554 __O uint32_t XDMAC_GID; /**< (XDMAC Offset: 0x10) Global Interrupt Disable Register */ 2555 __I uint32_t XDMAC_GIM; /**< (XDMAC Offset: 0x14) Global Interrupt Mask Register */ 2556 __I uint32_t XDMAC_GIS; /**< (XDMAC Offset: 0x18) Global Interrupt Status Register */ 2557 __O uint32_t XDMAC_GE; /**< (XDMAC Offset: 0x1C) Global Channel Enable Register */ 2558 __O uint32_t XDMAC_GD; /**< (XDMAC Offset: 0x20) Global Channel Disable Register */ 2559 __I uint32_t XDMAC_GS; /**< (XDMAC Offset: 0x24) Global Channel Status Register */ 2560 __IO uint32_t XDMAC_GRS; /**< (XDMAC Offset: 0x28) Global Channel Read Suspend Register */ 2561 __IO uint32_t XDMAC_GWS; /**< (XDMAC Offset: 0x2C) Global Channel Write Suspend Register */ 2562 __O uint32_t XDMAC_GRWS; /**< (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register */ 2563 __O uint32_t XDMAC_GRWR; /**< (XDMAC Offset: 0x34) Global Channel Read Write Resume Register */ 2564 __O uint32_t XDMAC_GSWR; /**< (XDMAC Offset: 0x38) Global Channel Software Request Register */ 2565 __I uint32_t XDMAC_GSWS; /**< (XDMAC Offset: 0x3C) Global Channel Software Request Status Register */ 2566 __O uint32_t XDMAC_GSWF; /**< (XDMAC Offset: 0x40) Global Channel Software Flush Request Register */ 2567 __I uint8_t Reserved1[12]; 2568 XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< Offset: 0x50 Channel Interrupt Enable Register */ 2569 } Xdmac; 2570 2571 #elif COMPONENT_TYPEDEF_STYLE == 'N' 2572 /** \brief XDMAC_CHID hardware registers */ 2573 typedef struct { 2574 __O XDMAC_CIE_Type XDMAC_CIE; /**< Offset: 0x00 ( /W 32) Channel Interrupt Enable Register */ 2575 __O XDMAC_CID_Type XDMAC_CID; /**< Offset: 0x04 ( /W 32) Channel Interrupt Disable Register */ 2576 __I XDMAC_CIM_Type XDMAC_CIM; /**< Offset: 0x08 (R/ 32) Channel Interrupt Mask Register */ 2577 __I XDMAC_CIS_Type XDMAC_CIS; /**< Offset: 0x0C (R/ 32) Channel Interrupt Status Register */ 2578 __IO XDMAC_CSA_Type XDMAC_CSA; /**< Offset: 0x10 (R/W 32) Channel Source Address Register */ 2579 __IO XDMAC_CDA_Type XDMAC_CDA; /**< Offset: 0x14 (R/W 32) Channel Destination Address Register */ 2580 __IO XDMAC_CNDA_Type XDMAC_CNDA; /**< Offset: 0x18 (R/W 32) Channel Next Descriptor Address Register */ 2581 __IO XDMAC_CNDC_Type XDMAC_CNDC; /**< Offset: 0x1C (R/W 32) Channel Next Descriptor Control Register */ 2582 __IO XDMAC_CUBC_Type XDMAC_CUBC; /**< Offset: 0x20 (R/W 32) Channel Microblock Control Register */ 2583 __IO XDMAC_CBC_Type XDMAC_CBC; /**< Offset: 0x24 (R/W 32) Channel Block Control Register */ 2584 __IO XDMAC_CC_Type XDMAC_CC; /**< Offset: 0x28 (R/W 32) Channel Configuration Register */ 2585 __IO XDMAC_CDS_MSP_Type XDMAC_CDS_MSP; /**< Offset: 0x2C (R/W 32) Channel Data Stride Memory Set Pattern */ 2586 __IO XDMAC_CSUS_Type XDMAC_CSUS; /**< Offset: 0x30 (R/W 32) Channel Source Microblock Stride */ 2587 __IO XDMAC_CDUS_Type XDMAC_CDUS; /**< Offset: 0x34 (R/W 32) Channel Destination Microblock Stride */ 2588 __I uint8_t Reserved1[8]; 2589 } XdmacChid; 2590 2591 /** \brief XDMAC hardware registers */ 2592 typedef struct { 2593 __I XDMAC_GTYPE_Type XDMAC_GTYPE; /**< Offset: 0x00 (R/ 32) Global Type Register */ 2594 __IO XDMAC_GCFG_Type XDMAC_GCFG; /**< Offset: 0x04 (R/W 32) Global Configuration Register */ 2595 __IO XDMAC_GWAC_Type XDMAC_GWAC; /**< Offset: 0x08 (R/W 32) Global Weighted Arbiter Configuration Register */ 2596 __O XDMAC_GIE_Type XDMAC_GIE; /**< Offset: 0x0C ( /W 32) Global Interrupt Enable Register */ 2597 __O XDMAC_GID_Type XDMAC_GID; /**< Offset: 0x10 ( /W 32) Global Interrupt Disable Register */ 2598 __I XDMAC_GIM_Type XDMAC_GIM; /**< Offset: 0x14 (R/ 32) Global Interrupt Mask Register */ 2599 __I XDMAC_GIS_Type XDMAC_GIS; /**< Offset: 0x18 (R/ 32) Global Interrupt Status Register */ 2600 __O XDMAC_GE_Type XDMAC_GE; /**< Offset: 0x1C ( /W 32) Global Channel Enable Register */ 2601 __O XDMAC_GD_Type XDMAC_GD; /**< Offset: 0x20 ( /W 32) Global Channel Disable Register */ 2602 __I XDMAC_GS_Type XDMAC_GS; /**< Offset: 0x24 (R/ 32) Global Channel Status Register */ 2603 __IO XDMAC_GRS_Type XDMAC_GRS; /**< Offset: 0x28 (R/W 32) Global Channel Read Suspend Register */ 2604 __IO XDMAC_GWS_Type XDMAC_GWS; /**< Offset: 0x2C (R/W 32) Global Channel Write Suspend Register */ 2605 __O XDMAC_GRWS_Type XDMAC_GRWS; /**< Offset: 0x30 ( /W 32) Global Channel Read Write Suspend Register */ 2606 __O XDMAC_GRWR_Type XDMAC_GRWR; /**< Offset: 0x34 ( /W 32) Global Channel Read Write Resume Register */ 2607 __O XDMAC_GSWR_Type XDMAC_GSWR; /**< Offset: 0x38 ( /W 32) Global Channel Software Request Register */ 2608 __I XDMAC_GSWS_Type XDMAC_GSWS; /**< Offset: 0x3C (R/ 32) Global Channel Software Request Status Register */ 2609 __O XDMAC_GSWF_Type XDMAC_GSWF; /**< Offset: 0x40 ( /W 32) Global Channel Software Flush Request Register */ 2610 __I uint8_t Reserved1[12]; 2611 XdmacChid XDMAC_CHID[24]; /**< Offset: 0x50 Channel Interrupt Enable Register */ 2612 } Xdmac; 2613 2614 #else /* COMPONENT_TYPEDEF_STYLE */ 2615 #error Unknown component typedef style 2616 #endif /* COMPONENT_TYPEDEF_STYLE */ 2617 2618 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2619 /** @} end of Extensible DMA Controller */ 2620 2621 #endif /* _SAMV71_XDMAC_COMPONENT_H_ */ 2622
