1 /** 2 * \file 3 * 4 * \brief Component description for UTMI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_UTMI_COMPONENT_H_ 32 #define _SAMV71_UTMI_COMPONENT_H_ 33 #define _SAMV71_UTMI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 USB Transmitter Interface Macrocell 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR UTMI */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define UTMI_11300 /**< (UTMI) Module ID */ 46 #define REV_UTMI A /**< (UTMI) Module revision */ 47 48 /* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t RES0:1; /**< bit: 0 USB PORTx Reset */ 54 uint32_t :3; /**< bit: 1..3 Reserved */ 55 uint32_t ARIE:1; /**< bit: 4 OHCI Asynchronous Resume Interrupt Enable */ 56 uint32_t APPSTART:1; /**< bit: 5 Reserved */ 57 uint32_t :17; /**< bit: 6..22 Reserved */ 58 uint32_t UDPPUDIS:1; /**< bit: 23 USB Device Pull-up Disable */ 59 uint32_t :8; /**< bit: 24..31 Reserved */ 60 } bit; /**< Structure used for bit access */ 61 struct { 62 uint32_t RES:1; /**< bit: 0 USB PORTx Reset */ 63 uint32_t :31; /**< bit: 1..31 Reserved */ 64 } vec; /**< Structure used for vec access */ 65 uint32_t reg; /**< Type used for register access */ 66 } UTMI_OHCIICR_Type; 67 #endif 68 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 #define UTMI_OHCIICR_OFFSET (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */ 71 72 #define UTMI_OHCIICR_RES0_Pos 0 /**< (UTMI_OHCIICR) USB PORTx Reset Position */ 73 #define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */ 74 #define UTMI_OHCIICR_RES0 UTMI_OHCIICR_RES0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_RES0_Msk instead */ 75 #define UTMI_OHCIICR_ARIE_Pos 4 /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */ 76 #define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */ 77 #define UTMI_OHCIICR_ARIE UTMI_OHCIICR_ARIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_ARIE_Msk instead */ 78 #define UTMI_OHCIICR_APPSTART_Pos 5 /**< (UTMI_OHCIICR) Reserved Position */ 79 #define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */ 80 #define UTMI_OHCIICR_APPSTART UTMI_OHCIICR_APPSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_APPSTART_Msk instead */ 81 #define UTMI_OHCIICR_UDPPUDIS_Pos 23 /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */ 82 #define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */ 83 #define UTMI_OHCIICR_UDPPUDIS UTMI_OHCIICR_UDPPUDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_UDPPUDIS_Msk instead */ 84 #define UTMI_OHCIICR_MASK _U_(0x800031) /**< \deprecated (UTMI_OHCIICR) Register MASK (Use UTMI_OHCIICR_Msk instead) */ 85 #define UTMI_OHCIICR_Msk _U_(0x800031) /**< (UTMI_OHCIICR) Register Mask */ 86 87 #define UTMI_OHCIICR_RES_Pos 0 /**< (UTMI_OHCIICR Position) USB PORTx Reset */ 88 #define UTMI_OHCIICR_RES_Msk (_U_(0x1) << UTMI_OHCIICR_RES_Pos) /**< (UTMI_OHCIICR Mask) RES */ 89 #define UTMI_OHCIICR_RES(value) (UTMI_OHCIICR_RES_Msk & ((value) << UTMI_OHCIICR_RES_Pos)) 90 91 /* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */ 92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 93 #if COMPONENT_TYPEDEF_STYLE == 'N' 94 typedef union { 95 struct { 96 uint32_t FREQ:2; /**< bit: 0..1 UTMI Reference Clock Frequency */ 97 uint32_t :30; /**< bit: 2..31 Reserved */ 98 } bit; /**< Structure used for bit access */ 99 uint32_t reg; /**< Type used for register access */ 100 } UTMI_CKTRIM_Type; 101 #endif 102 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define UTMI_CKTRIM_OFFSET (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */ 105 106 #define UTMI_CKTRIM_FREQ_Pos 0 /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */ 107 #define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */ 108 #define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)) 109 #define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */ 110 #define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */ 111 #define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */ 112 #define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */ 113 #define UTMI_CKTRIM_MASK _U_(0x03) /**< \deprecated (UTMI_CKTRIM) Register MASK (Use UTMI_CKTRIM_Msk instead) */ 114 #define UTMI_CKTRIM_Msk _U_(0x03) /**< (UTMI_CKTRIM) Register Mask */ 115 116 117 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 118 #if COMPONENT_TYPEDEF_STYLE == 'R' 119 /** \brief UTMI hardware registers */ 120 typedef struct { 121 __I uint8_t Reserved1[16]; 122 __IO uint32_t UTMI_OHCIICR; /**< (UTMI Offset: 0x10) OHCI Interrupt Configuration Register */ 123 __I uint8_t Reserved2[28]; 124 __IO uint32_t UTMI_CKTRIM; /**< (UTMI Offset: 0x30) UTMI Clock Trimming Register */ 125 } Utmi; 126 127 #elif COMPONENT_TYPEDEF_STYLE == 'N' 128 /** \brief UTMI hardware registers */ 129 typedef struct { 130 __I uint8_t Reserved1[16]; 131 __IO UTMI_OHCIICR_Type UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */ 132 __I uint8_t Reserved2[28]; 133 __IO UTMI_CKTRIM_Type UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */ 134 } Utmi; 135 136 #else /* COMPONENT_TYPEDEF_STYLE */ 137 #error Unknown component typedef style 138 #endif /* COMPONENT_TYPEDEF_STYLE */ 139 140 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 /** @} end of USB Transmitter Interface Macrocell */ 142 143 #endif /* _SAMV71_UTMI_COMPONENT_H_ */ 144
