1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_TC_COMPONENT_H_ 32 #define _SAMV71_TC_COMPONENT_H_ 33 #define _SAMV71_TC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Timer Counter 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR TC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define TC_6082 /**< (TC) Module ID */ 46 #define REV_TC ZL /**< (TC) Module revision */ 47 48 /* -------- TC_CCR : (TC Offset: 0x00) (/W 32) Channel Control Register (channel = 0) -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t CLKEN:1; /**< bit: 0 Counter Clock Enable Command */ 54 uint32_t CLKDIS:1; /**< bit: 1 Counter Clock Disable Command */ 55 uint32_t SWTRG:1; /**< bit: 2 Software Trigger Command */ 56 uint32_t :29; /**< bit: 3..31 Reserved */ 57 } bit; /**< Structure used for bit access */ 58 uint32_t reg; /**< Type used for register access */ 59 } TC_CCR_Type; 60 #endif 61 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define TC_CCR_OFFSET (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */ 64 65 #define TC_CCR_CLKEN_Pos 0 /**< (TC_CCR) Counter Clock Enable Command Position */ 66 #define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */ 67 #define TC_CCR_CLKEN TC_CCR_CLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKEN_Msk instead */ 68 #define TC_CCR_CLKDIS_Pos 1 /**< (TC_CCR) Counter Clock Disable Command Position */ 69 #define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */ 70 #define TC_CCR_CLKDIS TC_CCR_CLKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKDIS_Msk instead */ 71 #define TC_CCR_SWTRG_Pos 2 /**< (TC_CCR) Software Trigger Command Position */ 72 #define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */ 73 #define TC_CCR_SWTRG TC_CCR_SWTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_SWTRG_Msk instead */ 74 #define TC_CCR_MASK _U_(0x07) /**< \deprecated (TC_CCR) Register MASK (Use TC_CCR_Msk instead) */ 75 #define TC_CCR_Msk _U_(0x07) /**< (TC_CCR) Register Mask */ 76 77 78 /* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */ 79 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 80 #if COMPONENT_TYPEDEF_STYLE == 'N' 81 typedef union { 82 struct { 83 uint32_t TCCLKS:3; /**< bit: 0..2 Clock Selection */ 84 uint32_t CLKI:1; /**< bit: 3 Clock Invert */ 85 uint32_t BURST:2; /**< bit: 4..5 Burst Signal Selection */ 86 uint32_t :9; /**< bit: 6..14 Reserved */ 87 uint32_t WAVE:1; /**< bit: 15 Waveform Mode */ 88 uint32_t :16; /**< bit: 16..31 Reserved */ 89 } bit; /**< Structure used for bit access */ 90 struct { // CAPTURE mode 91 uint32_t :6; /**< bit: 0..5 Reserved */ 92 uint32_t LDBSTOP:1; /**< bit: 6 Counter Clock Stopped with RB Loading */ 93 uint32_t LDBDIS:1; /**< bit: 7 Counter Clock Disable with RB Loading */ 94 uint32_t ETRGEDG:2; /**< bit: 8..9 External Trigger Edge Selection */ 95 uint32_t ABETRG:1; /**< bit: 10 TIOAx or TIOBx External Trigger Selection */ 96 uint32_t :3; /**< bit: 11..13 Reserved */ 97 uint32_t CPCTRG:1; /**< bit: 14 RC Compare Trigger Enable */ 98 uint32_t :1; /**< bit: 15 Reserved */ 99 uint32_t LDRA:2; /**< bit: 16..17 RA Loading Edge Selection */ 100 uint32_t LDRB:2; /**< bit: 18..19 RB Loading Edge Selection */ 101 uint32_t SBSMPLR:3; /**< bit: 20..22 Loading Edge Subsampling Ratio */ 102 uint32_t :9; /**< bit: 23..31 Reserved */ 103 } CAPTURE; /**< Structure used for CAPTURE mode access */ 104 struct { // WAVEFORM mode 105 uint32_t :6; /**< bit: 0..5 Reserved */ 106 uint32_t CPCSTOP:1; /**< bit: 6 Counter Clock Stopped with RC Compare */ 107 uint32_t CPCDIS:1; /**< bit: 7 Counter Clock Disable with RC Loading */ 108 uint32_t EEVTEDG:2; /**< bit: 8..9 External Event Edge Selection */ 109 uint32_t EEVT:2; /**< bit: 10..11 External Event Selection */ 110 uint32_t ENETRG:1; /**< bit: 12 External Event Trigger Enable */ 111 uint32_t WAVSEL:2; /**< bit: 13..14 Waveform Selection */ 112 uint32_t :1; /**< bit: 15 Reserved */ 113 uint32_t ACPA:2; /**< bit: 16..17 RA Compare Effect on TIOAx */ 114 uint32_t ACPC:2; /**< bit: 18..19 RC Compare Effect on TIOAx */ 115 uint32_t AEEVT:2; /**< bit: 20..21 External Event Effect on TIOAx */ 116 uint32_t ASWTRG:2; /**< bit: 22..23 Software Trigger Effect on TIOAx */ 117 uint32_t BCPB:2; /**< bit: 24..25 RB Compare Effect on TIOBx */ 118 uint32_t BCPC:2; /**< bit: 26..27 RC Compare Effect on TIOBx */ 119 uint32_t BEEVT:2; /**< bit: 28..29 External Event Effect on TIOBx */ 120 uint32_t BSWTRG:2; /**< bit: 30..31 Software Trigger Effect on TIOBx */ 121 } WAVEFORM; /**< Structure used for WAVEFORM mode access */ 122 uint32_t reg; /**< Type used for register access */ 123 } TC_CMR_Type; 124 #endif 125 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 126 127 #define TC_CMR_OFFSET (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */ 128 129 #define TC_CMR_TCCLKS_Pos 0 /**< (TC_CMR) Clock Selection Position */ 130 #define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */ 131 #define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) 132 #define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ 133 #define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ 134 #define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ 135 #define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ 136 #define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ 137 #define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */ 138 #define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */ 139 #define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */ 140 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */ 141 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */ 142 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */ 143 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */ 144 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */ 145 #define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */ 146 #define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */ 147 #define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */ 148 #define TC_CMR_CLKI_Pos 3 /**< (TC_CMR) Clock Invert Position */ 149 #define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */ 150 #define TC_CMR_CLKI TC_CMR_CLKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CLKI_Msk instead */ 151 #define TC_CMR_BURST_Pos 4 /**< (TC_CMR) Burst Signal Selection Position */ 152 #define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */ 153 #define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) 154 #define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ 155 #define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */ 156 #define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */ 157 #define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */ 158 #define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 159 #define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ 160 #define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ 161 #define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ 162 #define TC_CMR_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ 163 #define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ 164 #define TC_CMR_LDBSTOP TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */ 165 #define TC_CMR_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ 166 #define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ 167 #define TC_CMR_LDBDIS TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */ 168 #define TC_CMR_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ 169 #define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ 170 #define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) 171 #define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ 172 #define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ 173 #define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ 174 #define TC_CMR_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */ 175 #define TC_CMR_ETRGEDG_NONE (TC_CMR_ETRGEDG_NONE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 176 #define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ 177 #define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ 178 #define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ 179 #define TC_CMR_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ 180 #define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ 181 #define TC_CMR_ABETRG TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */ 182 #define TC_CMR_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ 183 #define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ 184 #define TC_CMR_CPCTRG TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */ 185 #define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */ 186 #define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ 187 #define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */ 188 #define TC_CMR_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ 189 #define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ 190 #define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)) 191 #define TC_CMR_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */ 192 #define TC_CMR_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ 193 #define TC_CMR_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ 194 #define TC_CMR_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ 195 #define TC_CMR_LDRA_NONE (TC_CMR_LDRA_NONE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) None Position */ 196 #define TC_CMR_LDRA_RISING (TC_CMR_LDRA_RISING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 197 #define TC_CMR_LDRA_FALLING (TC_CMR_LDRA_FALLING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 198 #define TC_CMR_LDRA_EDGE (TC_CMR_LDRA_EDGE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 199 #define TC_CMR_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ 200 #define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ 201 #define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)) 202 #define TC_CMR_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */ 203 #define TC_CMR_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ 204 #define TC_CMR_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ 205 #define TC_CMR_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ 206 #define TC_CMR_LDRB_NONE (TC_CMR_LDRB_NONE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) None Position */ 207 #define TC_CMR_LDRB_RISING (TC_CMR_LDRB_RISING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 208 #define TC_CMR_LDRB_FALLING (TC_CMR_LDRB_FALLING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 209 #define TC_CMR_LDRB_EDGE (TC_CMR_LDRB_EDGE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 210 #define TC_CMR_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ 211 #define TC_CMR_SBSMPLR_Msk (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ 212 #define TC_CMR_SBSMPLR(value) (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)) 213 #define TC_CMR_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */ 214 #define TC_CMR_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */ 215 #define TC_CMR_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */ 216 #define TC_CMR_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */ 217 #define TC_CMR_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */ 218 #define TC_CMR_SBSMPLR_ONE (TC_CMR_SBSMPLR_ONE_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ 219 #define TC_CMR_SBSMPLR_HALF (TC_CMR_SBSMPLR_HALF_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ 220 #define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ 221 #define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ 222 #define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ 223 #define TC_CMR_MASK _U_(0x7FC7FF) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */ 224 #define TC_CMR_Msk _U_(0x7FC7FF) /**< (TC_CMR) Register Mask */ 225 226 /* CAPTURE mode */ 227 #define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ 228 #define TC_CMR_CAPTURE_LDBSTOP_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ 229 #define TC_CMR_CAPTURE_LDBSTOP TC_CMR_CAPTURE_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBSTOP_Msk instead */ 230 #define TC_CMR_CAPTURE_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ 231 #define TC_CMR_CAPTURE_LDBDIS_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ 232 #define TC_CMR_CAPTURE_LDBDIS TC_CMR_CAPTURE_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBDIS_Msk instead */ 233 #define TC_CMR_CAPTURE_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ 234 #define TC_CMR_CAPTURE_ETRGEDG_Msk (_U_(0x3) << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ 235 #define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) 236 #define TC_CMR_CAPTURE_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE The clock is not gated by an external signal. */ 237 #define TC_CMR_CAPTURE_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge */ 238 #define TC_CMR_CAPTURE_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge */ 239 #define TC_CMR_CAPTURE_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge */ 240 #define TC_CMR_CAPTURE_ETRGEDG_NONE (TC_CMR_CAPTURE_ETRGEDG_NONE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 241 #define TC_CMR_CAPTURE_ETRGEDG_RISING (TC_CMR_CAPTURE_ETRGEDG_RISING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ 242 #define TC_CMR_CAPTURE_ETRGEDG_FALLING (TC_CMR_CAPTURE_ETRGEDG_FALLING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ 243 #define TC_CMR_CAPTURE_ETRGEDG_EDGE (TC_CMR_CAPTURE_ETRGEDG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ 244 #define TC_CMR_CAPTURE_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ 245 #define TC_CMR_CAPTURE_ABETRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ 246 #define TC_CMR_CAPTURE_ABETRG TC_CMR_CAPTURE_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_ABETRG_Msk instead */ 247 #define TC_CMR_CAPTURE_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ 248 #define TC_CMR_CAPTURE_CPCTRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ 249 #define TC_CMR_CAPTURE_CPCTRG TC_CMR_CAPTURE_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_CPCTRG_Msk instead */ 250 #define TC_CMR_CAPTURE_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ 251 #define TC_CMR_CAPTURE_LDRA_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ 252 #define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) 253 #define TC_CMR_CAPTURE_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ 254 #define TC_CMR_CAPTURE_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 255 #define TC_CMR_CAPTURE_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 256 #define TC_CMR_CAPTURE_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 257 #define TC_CMR_CAPTURE_LDRA_NONE (TC_CMR_CAPTURE_LDRA_NONE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) None Position */ 258 #define TC_CMR_CAPTURE_LDRA_RISING (TC_CMR_CAPTURE_LDRA_RISING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 259 #define TC_CMR_CAPTURE_LDRA_FALLING (TC_CMR_CAPTURE_LDRA_FALLING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 260 #define TC_CMR_CAPTURE_LDRA_EDGE (TC_CMR_CAPTURE_LDRA_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 261 #define TC_CMR_CAPTURE_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ 262 #define TC_CMR_CAPTURE_LDRB_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ 263 #define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) 264 #define TC_CMR_CAPTURE_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ 265 #define TC_CMR_CAPTURE_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 266 #define TC_CMR_CAPTURE_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 267 #define TC_CMR_CAPTURE_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 268 #define TC_CMR_CAPTURE_LDRB_NONE (TC_CMR_CAPTURE_LDRB_NONE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) None Position */ 269 #define TC_CMR_CAPTURE_LDRB_RISING (TC_CMR_CAPTURE_LDRB_RISING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 270 #define TC_CMR_CAPTURE_LDRB_FALLING (TC_CMR_CAPTURE_LDRB_FALLING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 271 #define TC_CMR_CAPTURE_LDRB_EDGE (TC_CMR_CAPTURE_LDRB_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 272 #define TC_CMR_CAPTURE_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ 273 #define TC_CMR_CAPTURE_SBSMPLR_Msk (_U_(0x7) << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ 274 #define TC_CMR_CAPTURE_SBSMPLR(value) (TC_CMR_CAPTURE_SBSMPLR_Msk & ((value) << TC_CMR_CAPTURE_SBSMPLR_Pos)) 275 #define TC_CMR_CAPTURE_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE Load a Capture Register each selected edge */ 276 #define TC_CMR_CAPTURE_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) CAPTURE Load a Capture Register every 2 selected edges */ 277 #define TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) CAPTURE Load a Capture Register every 4 selected edges */ 278 #define TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) CAPTURE Load a Capture Register every 8 selected edges */ 279 #define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) CAPTURE Load a Capture Register every 16 selected edges */ 280 #define TC_CMR_CAPTURE_SBSMPLR_ONE (TC_CMR_CAPTURE_SBSMPLR_ONE_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ 281 #define TC_CMR_CAPTURE_SBSMPLR_HALF (TC_CMR_CAPTURE_SBSMPLR_HALF_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ 282 #define TC_CMR_CAPTURE_SBSMPLR_FOURTH (TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ 283 #define TC_CMR_CAPTURE_SBSMPLR_EIGHTH (TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ 284 #define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH (TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ 285 #define TC_CMR_CAPTURE_MASK _U_(0x7F47C0) /**< \deprecated (TC_CMR_CAPTURE) Register MASK (Use TC_CMR_CAPTURE_Msk instead) */ 286 #define TC_CMR_CAPTURE_Msk _U_(0x7F47C0) /**< (TC_CMR_CAPTURE) Register Mask */ 287 288 /* WAVEFORM mode */ 289 #define TC_CMR_WAVEFORM_CPCSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RC Compare Position */ 290 #define TC_CMR_WAVEFORM_CPCSTOP_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RC Compare Mask */ 291 #define TC_CMR_WAVEFORM_CPCSTOP TC_CMR_WAVEFORM_CPCSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCSTOP_Msk instead */ 292 #define TC_CMR_WAVEFORM_CPCDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RC Loading Position */ 293 #define TC_CMR_WAVEFORM_CPCDIS_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RC Loading Mask */ 294 #define TC_CMR_WAVEFORM_CPCDIS TC_CMR_WAVEFORM_CPCDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCDIS_Msk instead */ 295 #define TC_CMR_WAVEFORM_EEVTEDG_Pos 8 /**< (TC_CMR) External Event Edge Selection Position */ 296 #define TC_CMR_WAVEFORM_EEVTEDG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) External Event Edge Selection Mask */ 297 #define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) 298 #define TC_CMR_WAVEFORM_EEVTEDG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM None */ 299 #define TC_CMR_WAVEFORM_EEVTEDG_RISING_Val _U_(0x1) /**< (TC_CMR) WAVEFORM Rising edge */ 300 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) WAVEFORM Falling edge */ 301 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM Each edges */ 302 #define TC_CMR_WAVEFORM_EEVTEDG_NONE (TC_CMR_WAVEFORM_EEVTEDG_NONE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) None Position */ 303 #define TC_CMR_WAVEFORM_EEVTEDG_RISING (TC_CMR_WAVEFORM_EEVTEDG_RISING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Rising edge Position */ 304 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING (TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Falling edge Position */ 305 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Each edges Position */ 306 #define TC_CMR_WAVEFORM_EEVT_Pos 10 /**< (TC_CMR) External Event Selection Position */ 307 #define TC_CMR_WAVEFORM_EEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) External Event Selection Mask */ 308 #define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) 309 #define TC_CMR_WAVEFORM_EEVT_TIOB_Val _U_(0x0) /**< (TC_CMR) WAVEFORM TIOB */ 310 #define TC_CMR_WAVEFORM_EEVT_XC0_Val _U_(0x1) /**< (TC_CMR) WAVEFORM XC0 */ 311 #define TC_CMR_WAVEFORM_EEVT_XC1_Val _U_(0x2) /**< (TC_CMR) WAVEFORM XC1 */ 312 #define TC_CMR_WAVEFORM_EEVT_XC2_Val _U_(0x3) /**< (TC_CMR) WAVEFORM XC2 */ 313 #define TC_CMR_WAVEFORM_EEVT_TIOB (TC_CMR_WAVEFORM_EEVT_TIOB_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) TIOB Position */ 314 #define TC_CMR_WAVEFORM_EEVT_XC0 (TC_CMR_WAVEFORM_EEVT_XC0_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC0 Position */ 315 #define TC_CMR_WAVEFORM_EEVT_XC1 (TC_CMR_WAVEFORM_EEVT_XC1_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC1 Position */ 316 #define TC_CMR_WAVEFORM_EEVT_XC2 (TC_CMR_WAVEFORM_EEVT_XC2_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC2 Position */ 317 #define TC_CMR_WAVEFORM_ENETRG_Pos 12 /**< (TC_CMR) External Event Trigger Enable Position */ 318 #define TC_CMR_WAVEFORM_ENETRG_Msk (_U_(0x1) << TC_CMR_WAVEFORM_ENETRG_Pos) /**< (TC_CMR) External Event Trigger Enable Mask */ 319 #define TC_CMR_WAVEFORM_ENETRG TC_CMR_WAVEFORM_ENETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_ENETRG_Msk instead */ 320 #define TC_CMR_WAVEFORM_WAVSEL_Pos 13 /**< (TC_CMR) Waveform Selection Position */ 321 #define TC_CMR_WAVEFORM_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) Waveform Selection Mask */ 322 #define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) 323 #define TC_CMR_WAVEFORM_WAVSEL_UP_Val _U_(0x0) /**< (TC_CMR) WAVEFORM UP mode without automatic trigger on RC Compare */ 324 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val _U_(0x1) /**< (TC_CMR) WAVEFORM UPDOWN mode without automatic trigger on RC Compare */ 325 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val _U_(0x2) /**< (TC_CMR) WAVEFORM UP mode with automatic trigger on RC Compare */ 326 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val _U_(0x3) /**< (TC_CMR) WAVEFORM UPDOWN mode with automatic trigger on RC Compare */ 327 #define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ 328 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ 329 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ 330 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ 331 #define TC_CMR_WAVEFORM_ACPA_Pos 16 /**< (TC_CMR) RA Compare Effect on TIOAx Position */ 332 #define TC_CMR_WAVEFORM_ACPA_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) RA Compare Effect on TIOAx Mask */ 333 #define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) 334 #define TC_CMR_WAVEFORM_ACPA_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 335 #define TC_CMR_WAVEFORM_ACPA_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 336 #define TC_CMR_WAVEFORM_ACPA_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 337 #define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 338 #define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) NONE Position */ 339 #define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) SET Position */ 340 #define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) CLEAR Position */ 341 #define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) TOGGLE Position */ 342 #define TC_CMR_WAVEFORM_ACPC_Pos 18 /**< (TC_CMR) RC Compare Effect on TIOAx Position */ 343 #define TC_CMR_WAVEFORM_ACPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOAx Mask */ 344 #define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) 345 #define TC_CMR_WAVEFORM_ACPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 346 #define TC_CMR_WAVEFORM_ACPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 347 #define TC_CMR_WAVEFORM_ACPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 348 #define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 349 #define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) NONE Position */ 350 #define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) SET Position */ 351 #define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) CLEAR Position */ 352 #define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) TOGGLE Position */ 353 #define TC_CMR_WAVEFORM_AEEVT_Pos 20 /**< (TC_CMR) External Event Effect on TIOAx Position */ 354 #define TC_CMR_WAVEFORM_AEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOAx Mask */ 355 #define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) 356 #define TC_CMR_WAVEFORM_AEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 357 #define TC_CMR_WAVEFORM_AEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 358 #define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 359 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 360 #define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) NONE Position */ 361 #define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) SET Position */ 362 #define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 363 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 364 #define TC_CMR_WAVEFORM_ASWTRG_Pos 22 /**< (TC_CMR) Software Trigger Effect on TIOAx Position */ 365 #define TC_CMR_WAVEFORM_ASWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOAx Mask */ 366 #define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) 367 #define TC_CMR_WAVEFORM_ASWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 368 #define TC_CMR_WAVEFORM_ASWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 369 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 370 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 371 #define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) NONE Position */ 372 #define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) SET Position */ 373 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 374 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 375 #define TC_CMR_WAVEFORM_BCPB_Pos 24 /**< (TC_CMR) RB Compare Effect on TIOBx Position */ 376 #define TC_CMR_WAVEFORM_BCPB_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) RB Compare Effect on TIOBx Mask */ 377 #define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) 378 #define TC_CMR_WAVEFORM_BCPB_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 379 #define TC_CMR_WAVEFORM_BCPB_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 380 #define TC_CMR_WAVEFORM_BCPB_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 381 #define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 382 #define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) NONE Position */ 383 #define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) SET Position */ 384 #define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) CLEAR Position */ 385 #define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) TOGGLE Position */ 386 #define TC_CMR_WAVEFORM_BCPC_Pos 26 /**< (TC_CMR) RC Compare Effect on TIOBx Position */ 387 #define TC_CMR_WAVEFORM_BCPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOBx Mask */ 388 #define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) 389 #define TC_CMR_WAVEFORM_BCPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 390 #define TC_CMR_WAVEFORM_BCPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 391 #define TC_CMR_WAVEFORM_BCPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 392 #define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 393 #define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) NONE Position */ 394 #define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) SET Position */ 395 #define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) CLEAR Position */ 396 #define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) TOGGLE Position */ 397 #define TC_CMR_WAVEFORM_BEEVT_Pos 28 /**< (TC_CMR) External Event Effect on TIOBx Position */ 398 #define TC_CMR_WAVEFORM_BEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOBx Mask */ 399 #define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) 400 #define TC_CMR_WAVEFORM_BEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 401 #define TC_CMR_WAVEFORM_BEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 402 #define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 403 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 404 #define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) NONE Position */ 405 #define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) SET Position */ 406 #define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 407 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 408 #define TC_CMR_WAVEFORM_BSWTRG_Pos 30 /**< (TC_CMR) Software Trigger Effect on TIOBx Position */ 409 #define TC_CMR_WAVEFORM_BSWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOBx Mask */ 410 #define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) 411 #define TC_CMR_WAVEFORM_BSWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 412 #define TC_CMR_WAVEFORM_BSWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 413 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 414 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 415 #define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) NONE Position */ 416 #define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) SET Position */ 417 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 418 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 419 #define TC_CMR_WAVEFORM_MASK _U_(0xFFFF7FC0) /**< \deprecated (TC_CMR_WAVEFORM) Register MASK (Use TC_CMR_WAVEFORM_Msk instead) */ 420 #define TC_CMR_WAVEFORM_Msk _U_(0xFFFF7FC0) /**< (TC_CMR_WAVEFORM) Register Mask */ 421 422 423 /* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */ 424 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 425 #if COMPONENT_TYPEDEF_STYLE == 'N' 426 typedef union { 427 struct { 428 uint32_t GCEN:1; /**< bit: 0 Gray Count Enable */ 429 uint32_t DOWN:1; /**< bit: 1 Down Count */ 430 uint32_t :30; /**< bit: 2..31 Reserved */ 431 } bit; /**< Structure used for bit access */ 432 uint32_t reg; /**< Type used for register access */ 433 } TC_SMMR_Type; 434 #endif 435 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define TC_SMMR_OFFSET (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */ 438 439 #define TC_SMMR_GCEN_Pos 0 /**< (TC_SMMR) Gray Count Enable Position */ 440 #define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */ 441 #define TC_SMMR_GCEN TC_SMMR_GCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_GCEN_Msk instead */ 442 #define TC_SMMR_DOWN_Pos 1 /**< (TC_SMMR) Down Count Position */ 443 #define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */ 444 #define TC_SMMR_DOWN TC_SMMR_DOWN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_DOWN_Msk instead */ 445 #define TC_SMMR_MASK _U_(0x03) /**< \deprecated (TC_SMMR) Register MASK (Use TC_SMMR_Msk instead) */ 446 #define TC_SMMR_Msk _U_(0x03) /**< (TC_SMMR) Register Mask */ 447 448 449 /* -------- TC_RAB : (TC Offset: 0x0c) (R/ 32) Register AB (channel = 0) -------- */ 450 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 451 #if COMPONENT_TYPEDEF_STYLE == 'N' 452 typedef union { 453 struct { 454 uint32_t RAB:32; /**< bit: 0..31 Register A or Register B */ 455 } bit; /**< Structure used for bit access */ 456 uint32_t reg; /**< Type used for register access */ 457 } TC_RAB_Type; 458 #endif 459 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 460 461 #define TC_RAB_OFFSET (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */ 462 463 #define TC_RAB_RAB_Pos 0 /**< (TC_RAB) Register A or Register B Position */ 464 #define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */ 465 #define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos)) 466 #define TC_RAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RAB) Register MASK (Use TC_RAB_Msk instead) */ 467 #define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */ 468 469 470 /* -------- TC_CV : (TC Offset: 0x10) (R/ 32) Counter Value (channel = 0) -------- */ 471 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 472 #if COMPONENT_TYPEDEF_STYLE == 'N' 473 typedef union { 474 struct { 475 uint32_t CV:32; /**< bit: 0..31 Counter Value */ 476 } bit; /**< Structure used for bit access */ 477 uint32_t reg; /**< Type used for register access */ 478 } TC_CV_Type; 479 #endif 480 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 481 482 #define TC_CV_OFFSET (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */ 483 484 #define TC_CV_CV_Pos 0 /**< (TC_CV) Counter Value Position */ 485 #define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */ 486 #define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) 487 #define TC_CV_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_CV) Register MASK (Use TC_CV_Msk instead) */ 488 #define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */ 489 490 491 /* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */ 492 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 493 #if COMPONENT_TYPEDEF_STYLE == 'N' 494 typedef union { 495 struct { 496 uint32_t RA:32; /**< bit: 0..31 Register A */ 497 } bit; /**< Structure used for bit access */ 498 uint32_t reg; /**< Type used for register access */ 499 } TC_RA_Type; 500 #endif 501 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 502 503 #define TC_RA_OFFSET (0x14) /**< (TC_RA) Register A (channel = 0) Offset */ 504 505 #define TC_RA_RA_Pos 0 /**< (TC_RA) Register A Position */ 506 #define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */ 507 #define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) 508 #define TC_RA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RA) Register MASK (Use TC_RA_Msk instead) */ 509 #define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */ 510 511 512 /* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */ 513 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 514 #if COMPONENT_TYPEDEF_STYLE == 'N' 515 typedef union { 516 struct { 517 uint32_t RB:32; /**< bit: 0..31 Register B */ 518 } bit; /**< Structure used for bit access */ 519 uint32_t reg; /**< Type used for register access */ 520 } TC_RB_Type; 521 #endif 522 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 523 524 #define TC_RB_OFFSET (0x18) /**< (TC_RB) Register B (channel = 0) Offset */ 525 526 #define TC_RB_RB_Pos 0 /**< (TC_RB) Register B Position */ 527 #define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */ 528 #define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) 529 #define TC_RB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RB) Register MASK (Use TC_RB_Msk instead) */ 530 #define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */ 531 532 533 /* -------- TC_RC : (TC Offset: 0x1c) (R/W 32) Register C (channel = 0) -------- */ 534 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 535 #if COMPONENT_TYPEDEF_STYLE == 'N' 536 typedef union { 537 struct { 538 uint32_t RC:32; /**< bit: 0..31 Register C */ 539 } bit; /**< Structure used for bit access */ 540 uint32_t reg; /**< Type used for register access */ 541 } TC_RC_Type; 542 #endif 543 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 544 545 #define TC_RC_OFFSET (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */ 546 547 #define TC_RC_RC_Pos 0 /**< (TC_RC) Register C Position */ 548 #define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */ 549 #define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) 550 #define TC_RC_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RC) Register MASK (Use TC_RC_Msk instead) */ 551 #define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */ 552 553 554 /* -------- TC_SR : (TC Offset: 0x20) (R/ 32) Status Register (channel = 0) -------- */ 555 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 556 #if COMPONENT_TYPEDEF_STYLE == 'N' 557 typedef union { 558 struct { 559 uint32_t COVFS:1; /**< bit: 0 Counter Overflow Status (cleared on read) */ 560 uint32_t LOVRS:1; /**< bit: 1 Load Overrun Status (cleared on read) */ 561 uint32_t CPAS:1; /**< bit: 2 RA Compare Status (cleared on read) */ 562 uint32_t CPBS:1; /**< bit: 3 RB Compare Status (cleared on read) */ 563 uint32_t CPCS:1; /**< bit: 4 RC Compare Status (cleared on read) */ 564 uint32_t LDRAS:1; /**< bit: 5 RA Loading Status (cleared on read) */ 565 uint32_t LDRBS:1; /**< bit: 6 RB Loading Status (cleared on read) */ 566 uint32_t ETRGS:1; /**< bit: 7 External Trigger Status (cleared on read) */ 567 uint32_t :8; /**< bit: 8..15 Reserved */ 568 uint32_t CLKSTA:1; /**< bit: 16 Clock Enabling Status */ 569 uint32_t MTIOA:1; /**< bit: 17 TIOAx Mirror */ 570 uint32_t MTIOB:1; /**< bit: 18 TIOBx Mirror */ 571 uint32_t :13; /**< bit: 19..31 Reserved */ 572 } bit; /**< Structure used for bit access */ 573 uint32_t reg; /**< Type used for register access */ 574 } TC_SR_Type; 575 #endif 576 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 577 578 #define TC_SR_OFFSET (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */ 579 580 #define TC_SR_COVFS_Pos 0 /**< (TC_SR) Counter Overflow Status (cleared on read) Position */ 581 #define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */ 582 #define TC_SR_COVFS TC_SR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_COVFS_Msk instead */ 583 #define TC_SR_LOVRS_Pos 1 /**< (TC_SR) Load Overrun Status (cleared on read) Position */ 584 #define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */ 585 #define TC_SR_LOVRS TC_SR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LOVRS_Msk instead */ 586 #define TC_SR_CPAS_Pos 2 /**< (TC_SR) RA Compare Status (cleared on read) Position */ 587 #define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */ 588 #define TC_SR_CPAS TC_SR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPAS_Msk instead */ 589 #define TC_SR_CPBS_Pos 3 /**< (TC_SR) RB Compare Status (cleared on read) Position */ 590 #define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */ 591 #define TC_SR_CPBS TC_SR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPBS_Msk instead */ 592 #define TC_SR_CPCS_Pos 4 /**< (TC_SR) RC Compare Status (cleared on read) Position */ 593 #define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */ 594 #define TC_SR_CPCS TC_SR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPCS_Msk instead */ 595 #define TC_SR_LDRAS_Pos 5 /**< (TC_SR) RA Loading Status (cleared on read) Position */ 596 #define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */ 597 #define TC_SR_LDRAS TC_SR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRAS_Msk instead */ 598 #define TC_SR_LDRBS_Pos 6 /**< (TC_SR) RB Loading Status (cleared on read) Position */ 599 #define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */ 600 #define TC_SR_LDRBS TC_SR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRBS_Msk instead */ 601 #define TC_SR_ETRGS_Pos 7 /**< (TC_SR) External Trigger Status (cleared on read) Position */ 602 #define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */ 603 #define TC_SR_ETRGS TC_SR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_ETRGS_Msk instead */ 604 #define TC_SR_CLKSTA_Pos 16 /**< (TC_SR) Clock Enabling Status Position */ 605 #define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */ 606 #define TC_SR_CLKSTA TC_SR_CLKSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CLKSTA_Msk instead */ 607 #define TC_SR_MTIOA_Pos 17 /**< (TC_SR) TIOAx Mirror Position */ 608 #define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */ 609 #define TC_SR_MTIOA TC_SR_MTIOA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOA_Msk instead */ 610 #define TC_SR_MTIOB_Pos 18 /**< (TC_SR) TIOBx Mirror Position */ 611 #define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */ 612 #define TC_SR_MTIOB TC_SR_MTIOB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOB_Msk instead */ 613 #define TC_SR_MASK _U_(0x700FF) /**< \deprecated (TC_SR) Register MASK (Use TC_SR_Msk instead) */ 614 #define TC_SR_Msk _U_(0x700FF) /**< (TC_SR) Register Mask */ 615 616 617 /* -------- TC_IER : (TC Offset: 0x24) (/W 32) Interrupt Enable Register (channel = 0) -------- */ 618 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 619 #if COMPONENT_TYPEDEF_STYLE == 'N' 620 typedef union { 621 struct { 622 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 623 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 624 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 625 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 626 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 627 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 628 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 629 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 630 uint32_t :24; /**< bit: 8..31 Reserved */ 631 } bit; /**< Structure used for bit access */ 632 uint32_t reg; /**< Type used for register access */ 633 } TC_IER_Type; 634 #endif 635 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 636 637 #define TC_IER_OFFSET (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */ 638 639 #define TC_IER_COVFS_Pos 0 /**< (TC_IER) Counter Overflow Position */ 640 #define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */ 641 #define TC_IER_COVFS TC_IER_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_COVFS_Msk instead */ 642 #define TC_IER_LOVRS_Pos 1 /**< (TC_IER) Load Overrun Position */ 643 #define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */ 644 #define TC_IER_LOVRS TC_IER_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LOVRS_Msk instead */ 645 #define TC_IER_CPAS_Pos 2 /**< (TC_IER) RA Compare Position */ 646 #define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */ 647 #define TC_IER_CPAS TC_IER_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPAS_Msk instead */ 648 #define TC_IER_CPBS_Pos 3 /**< (TC_IER) RB Compare Position */ 649 #define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */ 650 #define TC_IER_CPBS TC_IER_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPBS_Msk instead */ 651 #define TC_IER_CPCS_Pos 4 /**< (TC_IER) RC Compare Position */ 652 #define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */ 653 #define TC_IER_CPCS TC_IER_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPCS_Msk instead */ 654 #define TC_IER_LDRAS_Pos 5 /**< (TC_IER) RA Loading Position */ 655 #define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */ 656 #define TC_IER_LDRAS TC_IER_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRAS_Msk instead */ 657 #define TC_IER_LDRBS_Pos 6 /**< (TC_IER) RB Loading Position */ 658 #define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */ 659 #define TC_IER_LDRBS TC_IER_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRBS_Msk instead */ 660 #define TC_IER_ETRGS_Pos 7 /**< (TC_IER) External Trigger Position */ 661 #define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */ 662 #define TC_IER_ETRGS TC_IER_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_ETRGS_Msk instead */ 663 #define TC_IER_MASK _U_(0xFF) /**< \deprecated (TC_IER) Register MASK (Use TC_IER_Msk instead) */ 664 #define TC_IER_Msk _U_(0xFF) /**< (TC_IER) Register Mask */ 665 666 667 /* -------- TC_IDR : (TC Offset: 0x28) (/W 32) Interrupt Disable Register (channel = 0) -------- */ 668 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 669 #if COMPONENT_TYPEDEF_STYLE == 'N' 670 typedef union { 671 struct { 672 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 673 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 674 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 675 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 676 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 677 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 678 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 679 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 680 uint32_t :24; /**< bit: 8..31 Reserved */ 681 } bit; /**< Structure used for bit access */ 682 uint32_t reg; /**< Type used for register access */ 683 } TC_IDR_Type; 684 #endif 685 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 686 687 #define TC_IDR_OFFSET (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */ 688 689 #define TC_IDR_COVFS_Pos 0 /**< (TC_IDR) Counter Overflow Position */ 690 #define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */ 691 #define TC_IDR_COVFS TC_IDR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_COVFS_Msk instead */ 692 #define TC_IDR_LOVRS_Pos 1 /**< (TC_IDR) Load Overrun Position */ 693 #define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */ 694 #define TC_IDR_LOVRS TC_IDR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LOVRS_Msk instead */ 695 #define TC_IDR_CPAS_Pos 2 /**< (TC_IDR) RA Compare Position */ 696 #define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */ 697 #define TC_IDR_CPAS TC_IDR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPAS_Msk instead */ 698 #define TC_IDR_CPBS_Pos 3 /**< (TC_IDR) RB Compare Position */ 699 #define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */ 700 #define TC_IDR_CPBS TC_IDR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPBS_Msk instead */ 701 #define TC_IDR_CPCS_Pos 4 /**< (TC_IDR) RC Compare Position */ 702 #define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */ 703 #define TC_IDR_CPCS TC_IDR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPCS_Msk instead */ 704 #define TC_IDR_LDRAS_Pos 5 /**< (TC_IDR) RA Loading Position */ 705 #define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */ 706 #define TC_IDR_LDRAS TC_IDR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRAS_Msk instead */ 707 #define TC_IDR_LDRBS_Pos 6 /**< (TC_IDR) RB Loading Position */ 708 #define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */ 709 #define TC_IDR_LDRBS TC_IDR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRBS_Msk instead */ 710 #define TC_IDR_ETRGS_Pos 7 /**< (TC_IDR) External Trigger Position */ 711 #define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */ 712 #define TC_IDR_ETRGS TC_IDR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_ETRGS_Msk instead */ 713 #define TC_IDR_MASK _U_(0xFF) /**< \deprecated (TC_IDR) Register MASK (Use TC_IDR_Msk instead) */ 714 #define TC_IDR_Msk _U_(0xFF) /**< (TC_IDR) Register Mask */ 715 716 717 /* -------- TC_IMR : (TC Offset: 0x2c) (R/ 32) Interrupt Mask Register (channel = 0) -------- */ 718 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 719 #if COMPONENT_TYPEDEF_STYLE == 'N' 720 typedef union { 721 struct { 722 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 723 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 724 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 725 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 726 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 727 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 728 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 729 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 730 uint32_t :24; /**< bit: 8..31 Reserved */ 731 } bit; /**< Structure used for bit access */ 732 uint32_t reg; /**< Type used for register access */ 733 } TC_IMR_Type; 734 #endif 735 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 736 737 #define TC_IMR_OFFSET (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */ 738 739 #define TC_IMR_COVFS_Pos 0 /**< (TC_IMR) Counter Overflow Position */ 740 #define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */ 741 #define TC_IMR_COVFS TC_IMR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_COVFS_Msk instead */ 742 #define TC_IMR_LOVRS_Pos 1 /**< (TC_IMR) Load Overrun Position */ 743 #define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */ 744 #define TC_IMR_LOVRS TC_IMR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LOVRS_Msk instead */ 745 #define TC_IMR_CPAS_Pos 2 /**< (TC_IMR) RA Compare Position */ 746 #define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */ 747 #define TC_IMR_CPAS TC_IMR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPAS_Msk instead */ 748 #define TC_IMR_CPBS_Pos 3 /**< (TC_IMR) RB Compare Position */ 749 #define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */ 750 #define TC_IMR_CPBS TC_IMR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPBS_Msk instead */ 751 #define TC_IMR_CPCS_Pos 4 /**< (TC_IMR) RC Compare Position */ 752 #define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */ 753 #define TC_IMR_CPCS TC_IMR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPCS_Msk instead */ 754 #define TC_IMR_LDRAS_Pos 5 /**< (TC_IMR) RA Loading Position */ 755 #define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */ 756 #define TC_IMR_LDRAS TC_IMR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRAS_Msk instead */ 757 #define TC_IMR_LDRBS_Pos 6 /**< (TC_IMR) RB Loading Position */ 758 #define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */ 759 #define TC_IMR_LDRBS TC_IMR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRBS_Msk instead */ 760 #define TC_IMR_ETRGS_Pos 7 /**< (TC_IMR) External Trigger Position */ 761 #define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */ 762 #define TC_IMR_ETRGS TC_IMR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_ETRGS_Msk instead */ 763 #define TC_IMR_MASK _U_(0xFF) /**< \deprecated (TC_IMR) Register MASK (Use TC_IMR_Msk instead) */ 764 #define TC_IMR_Msk _U_(0xFF) /**< (TC_IMR) Register Mask */ 765 766 767 /* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */ 768 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 769 #if COMPONENT_TYPEDEF_STYLE == 'N' 770 typedef union { 771 struct { 772 uint32_t TRIGSRCA:2; /**< bit: 0..1 Trigger Source for Input A */ 773 uint32_t :2; /**< bit: 2..3 Reserved */ 774 uint32_t TRIGSRCB:2; /**< bit: 4..5 Trigger Source for Input B */ 775 uint32_t :2; /**< bit: 6..7 Reserved */ 776 uint32_t NODIVCLK:1; /**< bit: 8 No Divided Clock */ 777 uint32_t :23; /**< bit: 9..31 Reserved */ 778 } bit; /**< Structure used for bit access */ 779 uint32_t reg; /**< Type used for register access */ 780 } TC_EMR_Type; 781 #endif 782 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 783 784 #define TC_EMR_OFFSET (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */ 785 786 #define TC_EMR_TRIGSRCA_Pos 0 /**< (TC_EMR) Trigger Source for Input A Position */ 787 #define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */ 788 #define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)) 789 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ 790 #define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */ 791 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */ 792 #define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */ 793 #define TC_EMR_TRIGSRCB_Pos 4 /**< (TC_EMR) Trigger Source for Input B Position */ 794 #define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */ 795 #define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)) 796 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ 797 #define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */ 798 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */ 799 #define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */ 800 #define TC_EMR_NODIVCLK_Pos 8 /**< (TC_EMR) No Divided Clock Position */ 801 #define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */ 802 #define TC_EMR_NODIVCLK TC_EMR_NODIVCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_EMR_NODIVCLK_Msk instead */ 803 #define TC_EMR_MASK _U_(0x133) /**< \deprecated (TC_EMR) Register MASK (Use TC_EMR_Msk instead) */ 804 #define TC_EMR_Msk _U_(0x133) /**< (TC_EMR) Register Mask */ 805 806 807 /* -------- TC_BCR : (TC Offset: 0xc0) (/W 32) Block Control Register -------- */ 808 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 809 #if COMPONENT_TYPEDEF_STYLE == 'N' 810 typedef union { 811 struct { 812 uint32_t SYNC:1; /**< bit: 0 Synchro Command */ 813 uint32_t :31; /**< bit: 1..31 Reserved */ 814 } bit; /**< Structure used for bit access */ 815 uint32_t reg; /**< Type used for register access */ 816 } TC_BCR_Type; 817 #endif 818 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 819 820 #define TC_BCR_OFFSET (0xC0) /**< (TC_BCR) Block Control Register Offset */ 821 822 #define TC_BCR_SYNC_Pos 0 /**< (TC_BCR) Synchro Command Position */ 823 #define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */ 824 #define TC_BCR_SYNC TC_BCR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BCR_SYNC_Msk instead */ 825 #define TC_BCR_MASK _U_(0x01) /**< \deprecated (TC_BCR) Register MASK (Use TC_BCR_Msk instead) */ 826 #define TC_BCR_Msk _U_(0x01) /**< (TC_BCR) Register Mask */ 827 828 829 /* -------- TC_BMR : (TC Offset: 0xc4) (R/W 32) Block Mode Register -------- */ 830 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 831 #if COMPONENT_TYPEDEF_STYLE == 'N' 832 typedef union { 833 struct { 834 uint32_t TC0XC0S:2; /**< bit: 0..1 External Clock Signal 0 Selection */ 835 uint32_t TC1XC1S:2; /**< bit: 2..3 External Clock Signal 1 Selection */ 836 uint32_t TC2XC2S:2; /**< bit: 4..5 External Clock Signal 2 Selection */ 837 uint32_t :2; /**< bit: 6..7 Reserved */ 838 uint32_t QDEN:1; /**< bit: 8 Quadrature Decoder Enabled */ 839 uint32_t POSEN:1; /**< bit: 9 Position Enabled */ 840 uint32_t SPEEDEN:1; /**< bit: 10 Speed Enabled */ 841 uint32_t QDTRANS:1; /**< bit: 11 Quadrature Decoding Transparent */ 842 uint32_t EDGPHA:1; /**< bit: 12 Edge on PHA Count Mode */ 843 uint32_t INVA:1; /**< bit: 13 Inverted PHA */ 844 uint32_t INVB:1; /**< bit: 14 Inverted PHB */ 845 uint32_t INVIDX:1; /**< bit: 15 Inverted Index */ 846 uint32_t SWAP:1; /**< bit: 16 Swap PHA and PHB */ 847 uint32_t IDXPHB:1; /**< bit: 17 Index Pin is PHB Pin */ 848 uint32_t AUTOC:1; /**< bit: 18 AutoCorrection of missing pulses */ 849 uint32_t :1; /**< bit: 19 Reserved */ 850 uint32_t MAXFILT:6; /**< bit: 20..25 Maximum Filter */ 851 uint32_t MAXCMP:4; /**< bit: 26..29 Maximum Consecutive Missing Pulses */ 852 uint32_t :2; /**< bit: 30..31 Reserved */ 853 } bit; /**< Structure used for bit access */ 854 uint32_t reg; /**< Type used for register access */ 855 } TC_BMR_Type; 856 #endif 857 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 858 859 #define TC_BMR_OFFSET (0xC4) /**< (TC_BMR) Block Mode Register Offset */ 860 861 #define TC_BMR_TC0XC0S_Pos 0 /**< (TC_BMR) External Clock Signal 0 Selection Position */ 862 #define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */ 863 #define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) 864 #define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */ 865 #define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */ 866 #define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */ 867 #define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */ 868 #define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */ 869 #define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */ 870 #define TC_BMR_TC1XC1S_Pos 2 /**< (TC_BMR) External Clock Signal 1 Selection Position */ 871 #define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */ 872 #define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) 873 #define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */ 874 #define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */ 875 #define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */ 876 #define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */ 877 #define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */ 878 #define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */ 879 #define TC_BMR_TC2XC2S_Pos 4 /**< (TC_BMR) External Clock Signal 2 Selection Position */ 880 #define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */ 881 #define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) 882 #define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */ 883 #define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */ 884 #define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */ 885 #define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */ 886 #define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */ 887 #define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */ 888 #define TC_BMR_QDEN_Pos 8 /**< (TC_BMR) Quadrature Decoder Enabled Position */ 889 #define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */ 890 #define TC_BMR_QDEN TC_BMR_QDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDEN_Msk instead */ 891 #define TC_BMR_POSEN_Pos 9 /**< (TC_BMR) Position Enabled Position */ 892 #define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */ 893 #define TC_BMR_POSEN TC_BMR_POSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_POSEN_Msk instead */ 894 #define TC_BMR_SPEEDEN_Pos 10 /**< (TC_BMR) Speed Enabled Position */ 895 #define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */ 896 #define TC_BMR_SPEEDEN TC_BMR_SPEEDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SPEEDEN_Msk instead */ 897 #define TC_BMR_QDTRANS_Pos 11 /**< (TC_BMR) Quadrature Decoding Transparent Position */ 898 #define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */ 899 #define TC_BMR_QDTRANS TC_BMR_QDTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDTRANS_Msk instead */ 900 #define TC_BMR_EDGPHA_Pos 12 /**< (TC_BMR) Edge on PHA Count Mode Position */ 901 #define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */ 902 #define TC_BMR_EDGPHA TC_BMR_EDGPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_EDGPHA_Msk instead */ 903 #define TC_BMR_INVA_Pos 13 /**< (TC_BMR) Inverted PHA Position */ 904 #define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */ 905 #define TC_BMR_INVA TC_BMR_INVA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVA_Msk instead */ 906 #define TC_BMR_INVB_Pos 14 /**< (TC_BMR) Inverted PHB Position */ 907 #define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */ 908 #define TC_BMR_INVB TC_BMR_INVB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVB_Msk instead */ 909 #define TC_BMR_INVIDX_Pos 15 /**< (TC_BMR) Inverted Index Position */ 910 #define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */ 911 #define TC_BMR_INVIDX TC_BMR_INVIDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVIDX_Msk instead */ 912 #define TC_BMR_SWAP_Pos 16 /**< (TC_BMR) Swap PHA and PHB Position */ 913 #define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */ 914 #define TC_BMR_SWAP TC_BMR_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SWAP_Msk instead */ 915 #define TC_BMR_IDXPHB_Pos 17 /**< (TC_BMR) Index Pin is PHB Pin Position */ 916 #define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */ 917 #define TC_BMR_IDXPHB TC_BMR_IDXPHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_IDXPHB_Msk instead */ 918 #define TC_BMR_AUTOC_Pos 18 /**< (TC_BMR) AutoCorrection of missing pulses Position */ 919 #define TC_BMR_AUTOC_Msk (_U_(0x1) << TC_BMR_AUTOC_Pos) /**< (TC_BMR) AutoCorrection of missing pulses Mask */ 920 #define TC_BMR_AUTOC TC_BMR_AUTOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_AUTOC_Msk instead */ 921 #define TC_BMR_MAXFILT_Pos 20 /**< (TC_BMR) Maximum Filter Position */ 922 #define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */ 923 #define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)) 924 #define TC_BMR_MAXCMP_Pos 26 /**< (TC_BMR) Maximum Consecutive Missing Pulses Position */ 925 #define TC_BMR_MAXCMP_Msk (_U_(0xF) << TC_BMR_MAXCMP_Pos) /**< (TC_BMR) Maximum Consecutive Missing Pulses Mask */ 926 #define TC_BMR_MAXCMP(value) (TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)) 927 #define TC_BMR_MASK _U_(0x3FF7FF3F) /**< \deprecated (TC_BMR) Register MASK (Use TC_BMR_Msk instead) */ 928 #define TC_BMR_Msk _U_(0x3FF7FF3F) /**< (TC_BMR) Register Mask */ 929 930 931 /* -------- TC_QIER : (TC Offset: 0xc8) (/W 32) QDEC Interrupt Enable Register -------- */ 932 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 933 #if COMPONENT_TYPEDEF_STYLE == 'N' 934 typedef union { 935 struct { 936 uint32_t IDX:1; /**< bit: 0 Index */ 937 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 938 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 939 uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ 940 uint32_t :28; /**< bit: 4..31 Reserved */ 941 } bit; /**< Structure used for bit access */ 942 uint32_t reg; /**< Type used for register access */ 943 } TC_QIER_Type; 944 #endif 945 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 946 947 #define TC_QIER_OFFSET (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */ 948 949 #define TC_QIER_IDX_Pos 0 /**< (TC_QIER) Index Position */ 950 #define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */ 951 #define TC_QIER_IDX TC_QIER_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_IDX_Msk instead */ 952 #define TC_QIER_DIRCHG_Pos 1 /**< (TC_QIER) Direction Change Position */ 953 #define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */ 954 #define TC_QIER_DIRCHG TC_QIER_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_DIRCHG_Msk instead */ 955 #define TC_QIER_QERR_Pos 2 /**< (TC_QIER) Quadrature Error Position */ 956 #define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */ 957 #define TC_QIER_QERR TC_QIER_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_QERR_Msk instead */ 958 #define TC_QIER_MPE_Pos 3 /**< (TC_QIER) Consecutive Missing Pulse Error Position */ 959 #define TC_QIER_MPE_Msk (_U_(0x1) << TC_QIER_MPE_Pos) /**< (TC_QIER) Consecutive Missing Pulse Error Mask */ 960 #define TC_QIER_MPE TC_QIER_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_MPE_Msk instead */ 961 #define TC_QIER_MASK _U_(0x0F) /**< \deprecated (TC_QIER) Register MASK (Use TC_QIER_Msk instead) */ 962 #define TC_QIER_Msk _U_(0x0F) /**< (TC_QIER) Register Mask */ 963 964 965 /* -------- TC_QIDR : (TC Offset: 0xcc) (/W 32) QDEC Interrupt Disable Register -------- */ 966 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 967 #if COMPONENT_TYPEDEF_STYLE == 'N' 968 typedef union { 969 struct { 970 uint32_t IDX:1; /**< bit: 0 Index */ 971 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 972 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 973 uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ 974 uint32_t :28; /**< bit: 4..31 Reserved */ 975 } bit; /**< Structure used for bit access */ 976 uint32_t reg; /**< Type used for register access */ 977 } TC_QIDR_Type; 978 #endif 979 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 980 981 #define TC_QIDR_OFFSET (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */ 982 983 #define TC_QIDR_IDX_Pos 0 /**< (TC_QIDR) Index Position */ 984 #define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */ 985 #define TC_QIDR_IDX TC_QIDR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_IDX_Msk instead */ 986 #define TC_QIDR_DIRCHG_Pos 1 /**< (TC_QIDR) Direction Change Position */ 987 #define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */ 988 #define TC_QIDR_DIRCHG TC_QIDR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_DIRCHG_Msk instead */ 989 #define TC_QIDR_QERR_Pos 2 /**< (TC_QIDR) Quadrature Error Position */ 990 #define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */ 991 #define TC_QIDR_QERR TC_QIDR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_QERR_Msk instead */ 992 #define TC_QIDR_MPE_Pos 3 /**< (TC_QIDR) Consecutive Missing Pulse Error Position */ 993 #define TC_QIDR_MPE_Msk (_U_(0x1) << TC_QIDR_MPE_Pos) /**< (TC_QIDR) Consecutive Missing Pulse Error Mask */ 994 #define TC_QIDR_MPE TC_QIDR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_MPE_Msk instead */ 995 #define TC_QIDR_MASK _U_(0x0F) /**< \deprecated (TC_QIDR) Register MASK (Use TC_QIDR_Msk instead) */ 996 #define TC_QIDR_Msk _U_(0x0F) /**< (TC_QIDR) Register Mask */ 997 998 999 /* -------- TC_QIMR : (TC Offset: 0xd0) (R/ 32) QDEC Interrupt Mask Register -------- */ 1000 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1001 #if COMPONENT_TYPEDEF_STYLE == 'N' 1002 typedef union { 1003 struct { 1004 uint32_t IDX:1; /**< bit: 0 Index */ 1005 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 1006 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 1007 uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ 1008 uint32_t :28; /**< bit: 4..31 Reserved */ 1009 } bit; /**< Structure used for bit access */ 1010 uint32_t reg; /**< Type used for register access */ 1011 } TC_QIMR_Type; 1012 #endif 1013 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1014 1015 #define TC_QIMR_OFFSET (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */ 1016 1017 #define TC_QIMR_IDX_Pos 0 /**< (TC_QIMR) Index Position */ 1018 #define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */ 1019 #define TC_QIMR_IDX TC_QIMR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_IDX_Msk instead */ 1020 #define TC_QIMR_DIRCHG_Pos 1 /**< (TC_QIMR) Direction Change Position */ 1021 #define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */ 1022 #define TC_QIMR_DIRCHG TC_QIMR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_DIRCHG_Msk instead */ 1023 #define TC_QIMR_QERR_Pos 2 /**< (TC_QIMR) Quadrature Error Position */ 1024 #define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */ 1025 #define TC_QIMR_QERR TC_QIMR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_QERR_Msk instead */ 1026 #define TC_QIMR_MPE_Pos 3 /**< (TC_QIMR) Consecutive Missing Pulse Error Position */ 1027 #define TC_QIMR_MPE_Msk (_U_(0x1) << TC_QIMR_MPE_Pos) /**< (TC_QIMR) Consecutive Missing Pulse Error Mask */ 1028 #define TC_QIMR_MPE TC_QIMR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_MPE_Msk instead */ 1029 #define TC_QIMR_MASK _U_(0x0F) /**< \deprecated (TC_QIMR) Register MASK (Use TC_QIMR_Msk instead) */ 1030 #define TC_QIMR_Msk _U_(0x0F) /**< (TC_QIMR) Register Mask */ 1031 1032 1033 /* -------- TC_QISR : (TC Offset: 0xd4) (R/ 32) QDEC Interrupt Status Register -------- */ 1034 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1035 #if COMPONENT_TYPEDEF_STYLE == 'N' 1036 typedef union { 1037 struct { 1038 uint32_t IDX:1; /**< bit: 0 Index */ 1039 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 1040 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 1041 uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ 1042 uint32_t :4; /**< bit: 4..7 Reserved */ 1043 uint32_t DIR:1; /**< bit: 8 Direction */ 1044 uint32_t :23; /**< bit: 9..31 Reserved */ 1045 } bit; /**< Structure used for bit access */ 1046 uint32_t reg; /**< Type used for register access */ 1047 } TC_QISR_Type; 1048 #endif 1049 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1050 1051 #define TC_QISR_OFFSET (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */ 1052 1053 #define TC_QISR_IDX_Pos 0 /**< (TC_QISR) Index Position */ 1054 #define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */ 1055 #define TC_QISR_IDX TC_QISR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_IDX_Msk instead */ 1056 #define TC_QISR_DIRCHG_Pos 1 /**< (TC_QISR) Direction Change Position */ 1057 #define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */ 1058 #define TC_QISR_DIRCHG TC_QISR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIRCHG_Msk instead */ 1059 #define TC_QISR_QERR_Pos 2 /**< (TC_QISR) Quadrature Error Position */ 1060 #define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */ 1061 #define TC_QISR_QERR TC_QISR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_QERR_Msk instead */ 1062 #define TC_QISR_MPE_Pos 3 /**< (TC_QISR) Consecutive Missing Pulse Error Position */ 1063 #define TC_QISR_MPE_Msk (_U_(0x1) << TC_QISR_MPE_Pos) /**< (TC_QISR) Consecutive Missing Pulse Error Mask */ 1064 #define TC_QISR_MPE TC_QISR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_MPE_Msk instead */ 1065 #define TC_QISR_DIR_Pos 8 /**< (TC_QISR) Direction Position */ 1066 #define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */ 1067 #define TC_QISR_DIR TC_QISR_DIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIR_Msk instead */ 1068 #define TC_QISR_MASK _U_(0x10F) /**< \deprecated (TC_QISR) Register MASK (Use TC_QISR_Msk instead) */ 1069 #define TC_QISR_Msk _U_(0x10F) /**< (TC_QISR) Register Mask */ 1070 1071 1072 /* -------- TC_FMR : (TC Offset: 0xd8) (R/W 32) Fault Mode Register -------- */ 1073 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1074 #if COMPONENT_TYPEDEF_STYLE == 'N' 1075 typedef union { 1076 struct { 1077 uint32_t ENCF0:1; /**< bit: 0 Enable Compare Fault Channel 0 */ 1078 uint32_t ENCF1:1; /**< bit: 1 Enable Compare Fault Channel 1 */ 1079 uint32_t :30; /**< bit: 2..31 Reserved */ 1080 } bit; /**< Structure used for bit access */ 1081 struct { 1082 uint32_t ENCF:2; /**< bit: 0..1 Enable Compare Fault Channel x */ 1083 uint32_t :30; /**< bit: 2..31 Reserved */ 1084 } vec; /**< Structure used for vec access */ 1085 uint32_t reg; /**< Type used for register access */ 1086 } TC_FMR_Type; 1087 #endif 1088 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1089 1090 #define TC_FMR_OFFSET (0xD8) /**< (TC_FMR) Fault Mode Register Offset */ 1091 1092 #define TC_FMR_ENCF0_Pos 0 /**< (TC_FMR) Enable Compare Fault Channel 0 Position */ 1093 #define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */ 1094 #define TC_FMR_ENCF0 TC_FMR_ENCF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF0_Msk instead */ 1095 #define TC_FMR_ENCF1_Pos 1 /**< (TC_FMR) Enable Compare Fault Channel 1 Position */ 1096 #define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */ 1097 #define TC_FMR_ENCF1 TC_FMR_ENCF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF1_Msk instead */ 1098 #define TC_FMR_MASK _U_(0x03) /**< \deprecated (TC_FMR) Register MASK (Use TC_FMR_Msk instead) */ 1099 #define TC_FMR_Msk _U_(0x03) /**< (TC_FMR) Register Mask */ 1100 1101 #define TC_FMR_ENCF_Pos 0 /**< (TC_FMR Position) Enable Compare Fault Channel x */ 1102 #define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */ 1103 #define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos)) 1104 1105 /* -------- TC_WPMR : (TC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 1106 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1107 #if COMPONENT_TYPEDEF_STYLE == 'N' 1108 typedef union { 1109 struct { 1110 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 1111 uint32_t :7; /**< bit: 1..7 Reserved */ 1112 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 1113 } bit; /**< Structure used for bit access */ 1114 uint32_t reg; /**< Type used for register access */ 1115 } TC_WPMR_Type; 1116 #endif 1117 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1118 1119 #define TC_WPMR_OFFSET (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */ 1120 1121 #define TC_WPMR_WPEN_Pos 0 /**< (TC_WPMR) Write Protection Enable Position */ 1122 #define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */ 1123 #define TC_WPMR_WPEN TC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_WPMR_WPEN_Msk instead */ 1124 #define TC_WPMR_WPKEY_Pos 8 /**< (TC_WPMR) Write Protection Key Position */ 1125 #define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */ 1126 #define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) 1127 #define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 1128 #define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 1129 #define TC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TC_WPMR) Register MASK (Use TC_WPMR_Msk instead) */ 1130 #define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */ 1131 1132 1133 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1134 #if COMPONENT_TYPEDEF_STYLE == 'R' 1135 /** \brief TC_CHANNEL hardware registers */ 1136 typedef struct { 1137 __O uint32_t TC_CCR; /**< (TC_CHANNEL Offset: 0x00) Channel Control Register (channel = 0) */ 1138 __IO uint32_t TC_CMR; /**< (TC_CHANNEL Offset: 0x04) Channel Mode Register (channel = 0) */ 1139 __IO uint32_t TC_SMMR; /**< (TC_CHANNEL Offset: 0x08) Stepper Motor Mode Register (channel = 0) */ 1140 __I uint32_t TC_RAB; /**< (TC_CHANNEL Offset: 0x0C) Register AB (channel = 0) */ 1141 __I uint32_t TC_CV; /**< (TC_CHANNEL Offset: 0x10) Counter Value (channel = 0) */ 1142 __IO uint32_t TC_RA; /**< (TC_CHANNEL Offset: 0x14) Register A (channel = 0) */ 1143 __IO uint32_t TC_RB; /**< (TC_CHANNEL Offset: 0x18) Register B (channel = 0) */ 1144 __IO uint32_t TC_RC; /**< (TC_CHANNEL Offset: 0x1C) Register C (channel = 0) */ 1145 __I uint32_t TC_SR; /**< (TC_CHANNEL Offset: 0x20) Status Register (channel = 0) */ 1146 __O uint32_t TC_IER; /**< (TC_CHANNEL Offset: 0x24) Interrupt Enable Register (channel = 0) */ 1147 __O uint32_t TC_IDR; /**< (TC_CHANNEL Offset: 0x28) Interrupt Disable Register (channel = 0) */ 1148 __I uint32_t TC_IMR; /**< (TC_CHANNEL Offset: 0x2C) Interrupt Mask Register (channel = 0) */ 1149 __IO uint32_t TC_EMR; /**< (TC_CHANNEL Offset: 0x30) Extended Mode Register (channel = 0) */ 1150 __I uint8_t Reserved1[12]; 1151 } TcChannel; 1152 1153 #define TCCHANNEL_NUMBER 3 1154 /** \brief TC hardware registers */ 1155 typedef struct { 1156 TcChannel TcChannel[TCCHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ 1157 __O uint32_t TC_BCR; /**< (TC Offset: 0xC0) Block Control Register */ 1158 __IO uint32_t TC_BMR; /**< (TC Offset: 0xC4) Block Mode Register */ 1159 __O uint32_t TC_QIER; /**< (TC Offset: 0xC8) QDEC Interrupt Enable Register */ 1160 __O uint32_t TC_QIDR; /**< (TC Offset: 0xCC) QDEC Interrupt Disable Register */ 1161 __I uint32_t TC_QIMR; /**< (TC Offset: 0xD0) QDEC Interrupt Mask Register */ 1162 __I uint32_t TC_QISR; /**< (TC Offset: 0xD4) QDEC Interrupt Status Register */ 1163 __IO uint32_t TC_FMR; /**< (TC Offset: 0xD8) Fault Mode Register */ 1164 __I uint8_t Reserved1[8]; 1165 __IO uint32_t TC_WPMR; /**< (TC Offset: 0xE4) Write Protection Mode Register */ 1166 } Tc; 1167 1168 #elif COMPONENT_TYPEDEF_STYLE == 'N' 1169 /** \brief TC_CHANNEL hardware registers */ 1170 typedef struct { 1171 __O TC_CCR_Type TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */ 1172 __IO TC_CMR_Type TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */ 1173 __IO TC_SMMR_Type TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */ 1174 __I TC_RAB_Type TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */ 1175 __I TC_CV_Type TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */ 1176 __IO TC_RA_Type TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */ 1177 __IO TC_RB_Type TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */ 1178 __IO TC_RC_Type TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */ 1179 __I TC_SR_Type TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */ 1180 __O TC_IER_Type TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */ 1181 __O TC_IDR_Type TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */ 1182 __I TC_IMR_Type TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */ 1183 __IO TC_EMR_Type TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */ 1184 __I uint8_t Reserved1[12]; 1185 } TcChannel; 1186 1187 /** \brief TC hardware registers */ 1188 typedef struct { 1189 TcChannel TcChannel[3]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ 1190 __O TC_BCR_Type TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */ 1191 __IO TC_BMR_Type TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */ 1192 __O TC_QIER_Type TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */ 1193 __O TC_QIDR_Type TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */ 1194 __I TC_QIMR_Type TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */ 1195 __I TC_QISR_Type TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */ 1196 __IO TC_FMR_Type TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */ 1197 __I uint8_t Reserved1[8]; 1198 __IO TC_WPMR_Type TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 1199 } Tc; 1200 1201 #else /* COMPONENT_TYPEDEF_STYLE */ 1202 #error Unknown component typedef style 1203 #endif /* COMPONENT_TYPEDEF_STYLE */ 1204 1205 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1206 /** @} end of Timer Counter */ 1207 1208 #endif /* _SAMV71_TC_COMPONENT_H_ */ 1209
