1 /** 2 * \file 3 * 4 * \brief Component description for RSTC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_RSTC_COMPONENT_H_ 32 #define _SAMV71_RSTC_COMPONENT_H_ 33 #define _SAMV71_RSTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Reset Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR RSTC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define RSTC_11009 /**< (RSTC) Module ID */ 46 #define REV_RSTC N /**< (RSTC) Module revision */ 47 48 /* -------- RSTC_CR : (RSTC Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t PROCRST:1; /**< bit: 0 Processor Reset */ 54 uint32_t :2; /**< bit: 1..2 Reserved */ 55 uint32_t EXTRST:1; /**< bit: 3 External Reset */ 56 uint32_t :20; /**< bit: 4..23 Reserved */ 57 uint32_t KEY:8; /**< bit: 24..31 System Reset Key */ 58 } bit; /**< Structure used for bit access */ 59 uint32_t reg; /**< Type used for register access */ 60 } RSTC_CR_Type; 61 #endif 62 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define RSTC_CR_OFFSET (0x00) /**< (RSTC_CR) Control Register Offset */ 65 66 #define RSTC_CR_PROCRST_Pos 0 /**< (RSTC_CR) Processor Reset Position */ 67 #define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */ 68 #define RSTC_CR_PROCRST RSTC_CR_PROCRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_PROCRST_Msk instead */ 69 #define RSTC_CR_EXTRST_Pos 3 /**< (RSTC_CR) External Reset Position */ 70 #define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */ 71 #define RSTC_CR_EXTRST RSTC_CR_EXTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_EXTRST_Msk instead */ 72 #define RSTC_CR_KEY_Pos 24 /**< (RSTC_CR) System Reset Key Position */ 73 #define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */ 74 #define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)) 75 #define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */ 76 #define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */ 77 #define RSTC_CR_MASK _U_(0xFF000009) /**< \deprecated (RSTC_CR) Register MASK (Use RSTC_CR_Msk instead) */ 78 #define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */ 79 80 81 /* -------- RSTC_SR : (RSTC Offset: 0x04) (R/ 32) Status Register -------- */ 82 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 83 #if COMPONENT_TYPEDEF_STYLE == 'N' 84 typedef union { 85 struct { 86 uint32_t URSTS:1; /**< bit: 0 User Reset Status */ 87 uint32_t :7; /**< bit: 1..7 Reserved */ 88 uint32_t RSTTYP:3; /**< bit: 8..10 Reset Type */ 89 uint32_t :5; /**< bit: 11..15 Reserved */ 90 uint32_t NRSTL:1; /**< bit: 16 NRST Pin Level */ 91 uint32_t SRCMP:1; /**< bit: 17 Software Reset Command in Progress */ 92 uint32_t :14; /**< bit: 18..31 Reserved */ 93 } bit; /**< Structure used for bit access */ 94 uint32_t reg; /**< Type used for register access */ 95 } RSTC_SR_Type; 96 #endif 97 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define RSTC_SR_OFFSET (0x04) /**< (RSTC_SR) Status Register Offset */ 100 101 #define RSTC_SR_URSTS_Pos 0 /**< (RSTC_SR) User Reset Status Position */ 102 #define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */ 103 #define RSTC_SR_URSTS RSTC_SR_URSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_URSTS_Msk instead */ 104 #define RSTC_SR_RSTTYP_Pos 8 /**< (RSTC_SR) Reset Type Position */ 105 #define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */ 106 #define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos)) 107 #define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */ 108 #define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */ 109 #define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */ 110 #define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */ 111 #define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */ 112 #define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */ 113 #define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */ 114 #define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */ 115 #define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */ 116 #define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */ 117 #define RSTC_SR_NRSTL_Pos 16 /**< (RSTC_SR) NRST Pin Level Position */ 118 #define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */ 119 #define RSTC_SR_NRSTL RSTC_SR_NRSTL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_NRSTL_Msk instead */ 120 #define RSTC_SR_SRCMP_Pos 17 /**< (RSTC_SR) Software Reset Command in Progress Position */ 121 #define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */ 122 #define RSTC_SR_SRCMP RSTC_SR_SRCMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_SRCMP_Msk instead */ 123 #define RSTC_SR_MASK _U_(0x30701) /**< \deprecated (RSTC_SR) Register MASK (Use RSTC_SR_Msk instead) */ 124 #define RSTC_SR_Msk _U_(0x30701) /**< (RSTC_SR) Register Mask */ 125 126 127 /* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */ 128 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 129 #if COMPONENT_TYPEDEF_STYLE == 'N' 130 typedef union { 131 struct { 132 uint32_t URSTEN:1; /**< bit: 0 User Reset Enable */ 133 uint32_t :3; /**< bit: 1..3 Reserved */ 134 uint32_t URSTIEN:1; /**< bit: 4 User Reset Interrupt Enable */ 135 uint32_t :3; /**< bit: 5..7 Reserved */ 136 uint32_t ERSTL:4; /**< bit: 8..11 External Reset Length */ 137 uint32_t :12; /**< bit: 12..23 Reserved */ 138 uint32_t KEY:8; /**< bit: 24..31 Write Access Password */ 139 } bit; /**< Structure used for bit access */ 140 uint32_t reg; /**< Type used for register access */ 141 } RSTC_MR_Type; 142 #endif 143 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 #define RSTC_MR_OFFSET (0x08) /**< (RSTC_MR) Mode Register Offset */ 146 147 #define RSTC_MR_URSTEN_Pos 0 /**< (RSTC_MR) User Reset Enable Position */ 148 #define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */ 149 #define RSTC_MR_URSTEN RSTC_MR_URSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTEN_Msk instead */ 150 #define RSTC_MR_URSTIEN_Pos 4 /**< (RSTC_MR) User Reset Interrupt Enable Position */ 151 #define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */ 152 #define RSTC_MR_URSTIEN RSTC_MR_URSTIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTIEN_Msk instead */ 153 #define RSTC_MR_ERSTL_Pos 8 /**< (RSTC_MR) External Reset Length Position */ 154 #define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */ 155 #define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)) 156 #define RSTC_MR_KEY_Pos 24 /**< (RSTC_MR) Write Access Password Position */ 157 #define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */ 158 #define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)) 159 #define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 160 #define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ 161 #define RSTC_MR_MASK _U_(0xFF000F11) /**< \deprecated (RSTC_MR) Register MASK (Use RSTC_MR_Msk instead) */ 162 #define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */ 163 164 165 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 166 #if COMPONENT_TYPEDEF_STYLE == 'R' 167 /** \brief RSTC hardware registers */ 168 typedef struct { 169 __O uint32_t RSTC_CR; /**< (RSTC Offset: 0x00) Control Register */ 170 __I uint32_t RSTC_SR; /**< (RSTC Offset: 0x04) Status Register */ 171 __IO uint32_t RSTC_MR; /**< (RSTC Offset: 0x08) Mode Register */ 172 } Rstc; 173 174 #elif COMPONENT_TYPEDEF_STYLE == 'N' 175 /** \brief RSTC hardware registers */ 176 typedef struct { 177 __O RSTC_CR_Type RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 178 __I RSTC_SR_Type RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */ 179 __IO RSTC_MR_Type RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */ 180 } Rstc; 181 182 #else /* COMPONENT_TYPEDEF_STYLE */ 183 #error Unknown component typedef style 184 #endif /* COMPONENT_TYPEDEF_STYLE */ 185 186 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 /** @} end of Reset Controller */ 188 189 #endif /* _SAMV71_RSTC_COMPONENT_H_ */ 190
