1 /** 2 * \file 3 * 4 * \brief Component description for QSPI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_QSPI_COMPONENT_H_ 32 #define _SAMV71_QSPI_COMPONENT_H_ 33 #define _SAMV71_QSPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Quad Serial Peripheral Interface 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR QSPI */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define QSPI_11171 /**< (QSPI) Module ID */ 46 #define REV_QSPI J /**< (QSPI) Module revision */ 47 48 /* -------- QSPI_CR : (QSPI Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t QSPIEN:1; /**< bit: 0 QSPI Enable */ 54 uint32_t QSPIDIS:1; /**< bit: 1 QSPI Disable */ 55 uint32_t :5; /**< bit: 2..6 Reserved */ 56 uint32_t SWRST:1; /**< bit: 7 QSPI Software Reset */ 57 uint32_t :16; /**< bit: 8..23 Reserved */ 58 uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ 59 uint32_t :7; /**< bit: 25..31 Reserved */ 60 } bit; /**< Structure used for bit access */ 61 uint32_t reg; /**< Type used for register access */ 62 } QSPI_CR_Type; 63 #endif 64 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define QSPI_CR_OFFSET (0x00) /**< (QSPI_CR) Control Register Offset */ 67 68 #define QSPI_CR_QSPIEN_Pos 0 /**< (QSPI_CR) QSPI Enable Position */ 69 #define QSPI_CR_QSPIEN_Msk (_U_(0x1) << QSPI_CR_QSPIEN_Pos) /**< (QSPI_CR) QSPI Enable Mask */ 70 #define QSPI_CR_QSPIEN QSPI_CR_QSPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIEN_Msk instead */ 71 #define QSPI_CR_QSPIDIS_Pos 1 /**< (QSPI_CR) QSPI Disable Position */ 72 #define QSPI_CR_QSPIDIS_Msk (_U_(0x1) << QSPI_CR_QSPIDIS_Pos) /**< (QSPI_CR) QSPI Disable Mask */ 73 #define QSPI_CR_QSPIDIS QSPI_CR_QSPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIDIS_Msk instead */ 74 #define QSPI_CR_SWRST_Pos 7 /**< (QSPI_CR) QSPI Software Reset Position */ 75 #define QSPI_CR_SWRST_Msk (_U_(0x1) << QSPI_CR_SWRST_Pos) /**< (QSPI_CR) QSPI Software Reset Mask */ 76 #define QSPI_CR_SWRST QSPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_SWRST_Msk instead */ 77 #define QSPI_CR_LASTXFER_Pos 24 /**< (QSPI_CR) Last Transfer Position */ 78 #define QSPI_CR_LASTXFER_Msk (_U_(0x1) << QSPI_CR_LASTXFER_Pos) /**< (QSPI_CR) Last Transfer Mask */ 79 #define QSPI_CR_LASTXFER QSPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_LASTXFER_Msk instead */ 80 #define QSPI_CR_MASK _U_(0x1000083) /**< \deprecated (QSPI_CR) Register MASK (Use QSPI_CR_Msk instead) */ 81 #define QSPI_CR_Msk _U_(0x1000083) /**< (QSPI_CR) Register Mask */ 82 83 84 /* -------- QSPI_MR : (QSPI Offset: 0x04) (R/W 32) Mode Register -------- */ 85 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 86 #if COMPONENT_TYPEDEF_STYLE == 'N' 87 typedef union { 88 struct { 89 uint32_t SMM:1; /**< bit: 0 Serial Memory Mode */ 90 uint32_t LLB:1; /**< bit: 1 Local Loopback Enable */ 91 uint32_t WDRBT:1; /**< bit: 2 Wait Data Read Before Transfer */ 92 uint32_t :1; /**< bit: 3 Reserved */ 93 uint32_t CSMODE:2; /**< bit: 4..5 Chip Select Mode */ 94 uint32_t :2; /**< bit: 6..7 Reserved */ 95 uint32_t NBBITS:4; /**< bit: 8..11 Number Of Bits Per Transfer */ 96 uint32_t :4; /**< bit: 12..15 Reserved */ 97 uint32_t DLYBCT:8; /**< bit: 16..23 Delay Between Consecutive Transfers */ 98 uint32_t DLYCS:8; /**< bit: 24..31 Minimum Inactive QCS Delay */ 99 } bit; /**< Structure used for bit access */ 100 uint32_t reg; /**< Type used for register access */ 101 } QSPI_MR_Type; 102 #endif 103 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define QSPI_MR_OFFSET (0x04) /**< (QSPI_MR) Mode Register Offset */ 106 107 #define QSPI_MR_SMM_Pos 0 /**< (QSPI_MR) Serial Memory Mode Position */ 108 #define QSPI_MR_SMM_Msk (_U_(0x1) << QSPI_MR_SMM_Pos) /**< (QSPI_MR) Serial Memory Mode Mask */ 109 #define QSPI_MR_SMM QSPI_MR_SMM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_SMM_Msk instead */ 110 #define QSPI_MR_SMM_SPI_Val _U_(0x0) /**< (QSPI_MR) The QSPI is in SPI mode. */ 111 #define QSPI_MR_SMM_MEMORY_Val _U_(0x1) /**< (QSPI_MR) The QSPI is in Serial Memory mode. */ 112 #define QSPI_MR_SMM_SPI (QSPI_MR_SMM_SPI_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in SPI mode. Position */ 113 #define QSPI_MR_SMM_MEMORY (QSPI_MR_SMM_MEMORY_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in Serial Memory mode. Position */ 114 #define QSPI_MR_LLB_Pos 1 /**< (QSPI_MR) Local Loopback Enable Position */ 115 #define QSPI_MR_LLB_Msk (_U_(0x1) << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local Loopback Enable Mask */ 116 #define QSPI_MR_LLB QSPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_LLB_Msk instead */ 117 #define QSPI_MR_LLB_DISABLED_Val _U_(0x0) /**< (QSPI_MR) Local loopback path disabled. */ 118 #define QSPI_MR_LLB_ENABLED_Val _U_(0x1) /**< (QSPI_MR) Local loopback path enabled. */ 119 #define QSPI_MR_LLB_DISABLED (QSPI_MR_LLB_DISABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path disabled. Position */ 120 #define QSPI_MR_LLB_ENABLED (QSPI_MR_LLB_ENABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path enabled. Position */ 121 #define QSPI_MR_WDRBT_Pos 2 /**< (QSPI_MR) Wait Data Read Before Transfer Position */ 122 #define QSPI_MR_WDRBT_Msk (_U_(0x1) << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) Wait Data Read Before Transfer Mask */ 123 #define QSPI_MR_WDRBT QSPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_WDRBT_Msk instead */ 124 #define QSPI_MR_WDRBT_DISABLED_Val _U_(0x0) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ 125 #define QSPI_MR_WDRBT_ENABLED_Val _U_(0x1) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ 126 #define QSPI_MR_WDRBT_DISABLED (QSPI_MR_WDRBT_DISABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. Position */ 127 #define QSPI_MR_WDRBT_ENABLED (QSPI_MR_WDRBT_ENABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. Position */ 128 #define QSPI_MR_CSMODE_Pos 4 /**< (QSPI_MR) Chip Select Mode Position */ 129 #define QSPI_MR_CSMODE_Msk (_U_(0x3) << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) Chip Select Mode Mask */ 130 #define QSPI_MR_CSMODE(value) (QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)) 131 #define QSPI_MR_CSMODE_NOT_RELOADED_Val _U_(0x0) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ 132 #define QSPI_MR_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ 133 #define QSPI_MR_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. */ 134 #define QSPI_MR_CSMODE_NOT_RELOADED (QSPI_MR_CSMODE_NOT_RELOADED_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. Position */ 135 #define QSPI_MR_CSMODE_LASTXFER (QSPI_MR_CSMODE_LASTXFER_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. Position */ 136 #define QSPI_MR_CSMODE_SYSTEMATICALLY (QSPI_MR_CSMODE_SYSTEMATICALLY_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. Position */ 137 #define QSPI_MR_NBBITS_Pos 8 /**< (QSPI_MR) Number Of Bits Per Transfer Position */ 138 #define QSPI_MR_NBBITS_Msk (_U_(0xF) << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) Number Of Bits Per Transfer Mask */ 139 #define QSPI_MR_NBBITS(value) (QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)) 140 #define QSPI_MR_NBBITS_8_BIT_Val _U_(0x0) /**< (QSPI_MR) 8 bits for transfer */ 141 #define QSPI_MR_NBBITS_16_BIT_Val _U_(0x8) /**< (QSPI_MR) 16 bits for transfer */ 142 #define QSPI_MR_NBBITS_8_BIT (QSPI_MR_NBBITS_8_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 8 bits for transfer Position */ 143 #define QSPI_MR_NBBITS_16_BIT (QSPI_MR_NBBITS_16_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 16 bits for transfer Position */ 144 #define QSPI_MR_DLYBCT_Pos 16 /**< (QSPI_MR) Delay Between Consecutive Transfers Position */ 145 #define QSPI_MR_DLYBCT_Msk (_U_(0xFF) << QSPI_MR_DLYBCT_Pos) /**< (QSPI_MR) Delay Between Consecutive Transfers Mask */ 146 #define QSPI_MR_DLYBCT(value) (QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)) 147 #define QSPI_MR_DLYCS_Pos 24 /**< (QSPI_MR) Minimum Inactive QCS Delay Position */ 148 #define QSPI_MR_DLYCS_Msk (_U_(0xFF) << QSPI_MR_DLYCS_Pos) /**< (QSPI_MR) Minimum Inactive QCS Delay Mask */ 149 #define QSPI_MR_DLYCS(value) (QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)) 150 #define QSPI_MR_MASK _U_(0xFFFF0F37) /**< \deprecated (QSPI_MR) Register MASK (Use QSPI_MR_Msk instead) */ 151 #define QSPI_MR_Msk _U_(0xFFFF0F37) /**< (QSPI_MR) Register Mask */ 152 153 154 /* -------- QSPI_RDR : (QSPI Offset: 0x08) (R/ 32) Receive Data Register -------- */ 155 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 156 #if COMPONENT_TYPEDEF_STYLE == 'N' 157 typedef union { 158 struct { 159 uint32_t RD:16; /**< bit: 0..15 Receive Data */ 160 uint32_t :16; /**< bit: 16..31 Reserved */ 161 } bit; /**< Structure used for bit access */ 162 uint32_t reg; /**< Type used for register access */ 163 } QSPI_RDR_Type; 164 #endif 165 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define QSPI_RDR_OFFSET (0x08) /**< (QSPI_RDR) Receive Data Register Offset */ 168 169 #define QSPI_RDR_RD_Pos 0 /**< (QSPI_RDR) Receive Data Position */ 170 #define QSPI_RDR_RD_Msk (_U_(0xFFFF) << QSPI_RDR_RD_Pos) /**< (QSPI_RDR) Receive Data Mask */ 171 #define QSPI_RDR_RD(value) (QSPI_RDR_RD_Msk & ((value) << QSPI_RDR_RD_Pos)) 172 #define QSPI_RDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_RDR) Register MASK (Use QSPI_RDR_Msk instead) */ 173 #define QSPI_RDR_Msk _U_(0xFFFF) /**< (QSPI_RDR) Register Mask */ 174 175 176 /* -------- QSPI_TDR : (QSPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */ 177 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 178 #if COMPONENT_TYPEDEF_STYLE == 'N' 179 typedef union { 180 struct { 181 uint32_t TD:16; /**< bit: 0..15 Transmit Data */ 182 uint32_t :16; /**< bit: 16..31 Reserved */ 183 } bit; /**< Structure used for bit access */ 184 uint32_t reg; /**< Type used for register access */ 185 } QSPI_TDR_Type; 186 #endif 187 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 #define QSPI_TDR_OFFSET (0x0C) /**< (QSPI_TDR) Transmit Data Register Offset */ 190 191 #define QSPI_TDR_TD_Pos 0 /**< (QSPI_TDR) Transmit Data Position */ 192 #define QSPI_TDR_TD_Msk (_U_(0xFFFF) << QSPI_TDR_TD_Pos) /**< (QSPI_TDR) Transmit Data Mask */ 193 #define QSPI_TDR_TD(value) (QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)) 194 #define QSPI_TDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_TDR) Register MASK (Use QSPI_TDR_Msk instead) */ 195 #define QSPI_TDR_Msk _U_(0xFFFF) /**< (QSPI_TDR) Register Mask */ 196 197 198 /* -------- QSPI_SR : (QSPI Offset: 0x10) (R/ 32) Status Register -------- */ 199 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 200 #if COMPONENT_TYPEDEF_STYLE == 'N' 201 typedef union { 202 struct { 203 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */ 204 uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */ 205 uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty (cleared by writing SPI_TDR) */ 206 uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */ 207 uint32_t :4; /**< bit: 4..7 Reserved */ 208 uint32_t CSR:1; /**< bit: 8 Chip Select Rise (cleared on read) */ 209 uint32_t CSS:1; /**< bit: 9 Chip Select Status */ 210 uint32_t INSTRE:1; /**< bit: 10 Instruction End Status (cleared on read) */ 211 uint32_t :13; /**< bit: 11..23 Reserved */ 212 uint32_t QSPIENS:1; /**< bit: 24 QSPI Enable Status */ 213 uint32_t :7; /**< bit: 25..31 Reserved */ 214 } bit; /**< Structure used for bit access */ 215 uint32_t reg; /**< Type used for register access */ 216 } QSPI_SR_Type; 217 #endif 218 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 219 220 #define QSPI_SR_OFFSET (0x10) /**< (QSPI_SR) Status Register Offset */ 221 222 #define QSPI_SR_RDRF_Pos 0 /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ 223 #define QSPI_SR_RDRF_Msk (_U_(0x1) << QSPI_SR_RDRF_Pos) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ 224 #define QSPI_SR_RDRF QSPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_RDRF_Msk instead */ 225 #define QSPI_SR_TDRE_Pos 1 /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ 226 #define QSPI_SR_TDRE_Msk (_U_(0x1) << QSPI_SR_TDRE_Pos) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ 227 #define QSPI_SR_TDRE QSPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TDRE_Msk instead */ 228 #define QSPI_SR_TXEMPTY_Pos 2 /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ 229 #define QSPI_SR_TXEMPTY_Msk (_U_(0x1) << QSPI_SR_TXEMPTY_Pos) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ 230 #define QSPI_SR_TXEMPTY QSPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TXEMPTY_Msk instead */ 231 #define QSPI_SR_OVRES_Pos 3 /**< (QSPI_SR) Overrun Error Status (cleared on read) Position */ 232 #define QSPI_SR_OVRES_Msk (_U_(0x1) << QSPI_SR_OVRES_Pos) /**< (QSPI_SR) Overrun Error Status (cleared on read) Mask */ 233 #define QSPI_SR_OVRES QSPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_OVRES_Msk instead */ 234 #define QSPI_SR_CSR_Pos 8 /**< (QSPI_SR) Chip Select Rise (cleared on read) Position */ 235 #define QSPI_SR_CSR_Msk (_U_(0x1) << QSPI_SR_CSR_Pos) /**< (QSPI_SR) Chip Select Rise (cleared on read) Mask */ 236 #define QSPI_SR_CSR QSPI_SR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSR_Msk instead */ 237 #define QSPI_SR_CSS_Pos 9 /**< (QSPI_SR) Chip Select Status Position */ 238 #define QSPI_SR_CSS_Msk (_U_(0x1) << QSPI_SR_CSS_Pos) /**< (QSPI_SR) Chip Select Status Mask */ 239 #define QSPI_SR_CSS QSPI_SR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSS_Msk instead */ 240 #define QSPI_SR_INSTRE_Pos 10 /**< (QSPI_SR) Instruction End Status (cleared on read) Position */ 241 #define QSPI_SR_INSTRE_Msk (_U_(0x1) << QSPI_SR_INSTRE_Pos) /**< (QSPI_SR) Instruction End Status (cleared on read) Mask */ 242 #define QSPI_SR_INSTRE QSPI_SR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_INSTRE_Msk instead */ 243 #define QSPI_SR_QSPIENS_Pos 24 /**< (QSPI_SR) QSPI Enable Status Position */ 244 #define QSPI_SR_QSPIENS_Msk (_U_(0x1) << QSPI_SR_QSPIENS_Pos) /**< (QSPI_SR) QSPI Enable Status Mask */ 245 #define QSPI_SR_QSPIENS QSPI_SR_QSPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_QSPIENS_Msk instead */ 246 #define QSPI_SR_MASK _U_(0x100070F) /**< \deprecated (QSPI_SR) Register MASK (Use QSPI_SR_Msk instead) */ 247 #define QSPI_SR_Msk _U_(0x100070F) /**< (QSPI_SR) Register Mask */ 248 249 250 /* -------- QSPI_IER : (QSPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ 251 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 252 #if COMPONENT_TYPEDEF_STYLE == 'N' 253 typedef union { 254 struct { 255 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */ 256 uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Enable */ 257 uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Enable */ 258 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */ 259 uint32_t :4; /**< bit: 4..7 Reserved */ 260 uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Enable */ 261 uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Enable */ 262 uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Enable */ 263 uint32_t :21; /**< bit: 11..31 Reserved */ 264 } bit; /**< Structure used for bit access */ 265 uint32_t reg; /**< Type used for register access */ 266 } QSPI_IER_Type; 267 #endif 268 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 269 270 #define QSPI_IER_OFFSET (0x14) /**< (QSPI_IER) Interrupt Enable Register Offset */ 271 272 #define QSPI_IER_RDRF_Pos 0 /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Position */ 273 #define QSPI_IER_RDRF_Msk (_U_(0x1) << QSPI_IER_RDRF_Pos) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Mask */ 274 #define QSPI_IER_RDRF QSPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_RDRF_Msk instead */ 275 #define QSPI_IER_TDRE_Pos 1 /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Position */ 276 #define QSPI_IER_TDRE_Msk (_U_(0x1) << QSPI_IER_TDRE_Pos) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Mask */ 277 #define QSPI_IER_TDRE QSPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TDRE_Msk instead */ 278 #define QSPI_IER_TXEMPTY_Pos 2 /**< (QSPI_IER) Transmission Registers Empty Enable Position */ 279 #define QSPI_IER_TXEMPTY_Msk (_U_(0x1) << QSPI_IER_TXEMPTY_Pos) /**< (QSPI_IER) Transmission Registers Empty Enable Mask */ 280 #define QSPI_IER_TXEMPTY QSPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TXEMPTY_Msk instead */ 281 #define QSPI_IER_OVRES_Pos 3 /**< (QSPI_IER) Overrun Error Interrupt Enable Position */ 282 #define QSPI_IER_OVRES_Msk (_U_(0x1) << QSPI_IER_OVRES_Pos) /**< (QSPI_IER) Overrun Error Interrupt Enable Mask */ 283 #define QSPI_IER_OVRES QSPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_OVRES_Msk instead */ 284 #define QSPI_IER_CSR_Pos 8 /**< (QSPI_IER) Chip Select Rise Interrupt Enable Position */ 285 #define QSPI_IER_CSR_Msk (_U_(0x1) << QSPI_IER_CSR_Pos) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Mask */ 286 #define QSPI_IER_CSR QSPI_IER_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSR_Msk instead */ 287 #define QSPI_IER_CSS_Pos 9 /**< (QSPI_IER) Chip Select Status Interrupt Enable Position */ 288 #define QSPI_IER_CSS_Msk (_U_(0x1) << QSPI_IER_CSS_Pos) /**< (QSPI_IER) Chip Select Status Interrupt Enable Mask */ 289 #define QSPI_IER_CSS QSPI_IER_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSS_Msk instead */ 290 #define QSPI_IER_INSTRE_Pos 10 /**< (QSPI_IER) Instruction End Interrupt Enable Position */ 291 #define QSPI_IER_INSTRE_Msk (_U_(0x1) << QSPI_IER_INSTRE_Pos) /**< (QSPI_IER) Instruction End Interrupt Enable Mask */ 292 #define QSPI_IER_INSTRE QSPI_IER_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_INSTRE_Msk instead */ 293 #define QSPI_IER_MASK _U_(0x70F) /**< \deprecated (QSPI_IER) Register MASK (Use QSPI_IER_Msk instead) */ 294 #define QSPI_IER_Msk _U_(0x70F) /**< (QSPI_IER) Register Mask */ 295 296 297 /* -------- QSPI_IDR : (QSPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ 298 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 299 #if COMPONENT_TYPEDEF_STYLE == 'N' 300 typedef union { 301 struct { 302 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */ 303 uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Disable */ 304 uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Disable */ 305 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */ 306 uint32_t :4; /**< bit: 4..7 Reserved */ 307 uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Disable */ 308 uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Disable */ 309 uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Disable */ 310 uint32_t :21; /**< bit: 11..31 Reserved */ 311 } bit; /**< Structure used for bit access */ 312 uint32_t reg; /**< Type used for register access */ 313 } QSPI_IDR_Type; 314 #endif 315 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define QSPI_IDR_OFFSET (0x18) /**< (QSPI_IDR) Interrupt Disable Register Offset */ 318 319 #define QSPI_IDR_RDRF_Pos 0 /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Position */ 320 #define QSPI_IDR_RDRF_Msk (_U_(0x1) << QSPI_IDR_RDRF_Pos) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Mask */ 321 #define QSPI_IDR_RDRF QSPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_RDRF_Msk instead */ 322 #define QSPI_IDR_TDRE_Pos 1 /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Position */ 323 #define QSPI_IDR_TDRE_Msk (_U_(0x1) << QSPI_IDR_TDRE_Pos) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Mask */ 324 #define QSPI_IDR_TDRE QSPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TDRE_Msk instead */ 325 #define QSPI_IDR_TXEMPTY_Pos 2 /**< (QSPI_IDR) Transmission Registers Empty Disable Position */ 326 #define QSPI_IDR_TXEMPTY_Msk (_U_(0x1) << QSPI_IDR_TXEMPTY_Pos) /**< (QSPI_IDR) Transmission Registers Empty Disable Mask */ 327 #define QSPI_IDR_TXEMPTY QSPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TXEMPTY_Msk instead */ 328 #define QSPI_IDR_OVRES_Pos 3 /**< (QSPI_IDR) Overrun Error Interrupt Disable Position */ 329 #define QSPI_IDR_OVRES_Msk (_U_(0x1) << QSPI_IDR_OVRES_Pos) /**< (QSPI_IDR) Overrun Error Interrupt Disable Mask */ 330 #define QSPI_IDR_OVRES QSPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_OVRES_Msk instead */ 331 #define QSPI_IDR_CSR_Pos 8 /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Position */ 332 #define QSPI_IDR_CSR_Msk (_U_(0x1) << QSPI_IDR_CSR_Pos) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Mask */ 333 #define QSPI_IDR_CSR QSPI_IDR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSR_Msk instead */ 334 #define QSPI_IDR_CSS_Pos 9 /**< (QSPI_IDR) Chip Select Status Interrupt Disable Position */ 335 #define QSPI_IDR_CSS_Msk (_U_(0x1) << QSPI_IDR_CSS_Pos) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Mask */ 336 #define QSPI_IDR_CSS QSPI_IDR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSS_Msk instead */ 337 #define QSPI_IDR_INSTRE_Pos 10 /**< (QSPI_IDR) Instruction End Interrupt Disable Position */ 338 #define QSPI_IDR_INSTRE_Msk (_U_(0x1) << QSPI_IDR_INSTRE_Pos) /**< (QSPI_IDR) Instruction End Interrupt Disable Mask */ 339 #define QSPI_IDR_INSTRE QSPI_IDR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_INSTRE_Msk instead */ 340 #define QSPI_IDR_MASK _U_(0x70F) /**< \deprecated (QSPI_IDR) Register MASK (Use QSPI_IDR_Msk instead) */ 341 #define QSPI_IDR_Msk _U_(0x70F) /**< (QSPI_IDR) Register Mask */ 342 343 344 /* -------- QSPI_IMR : (QSPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ 345 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 346 #if COMPONENT_TYPEDEF_STYLE == 'N' 347 typedef union { 348 struct { 349 uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */ 350 uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Mask */ 351 uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Mask */ 352 uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */ 353 uint32_t :4; /**< bit: 4..7 Reserved */ 354 uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Mask */ 355 uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Mask */ 356 uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Mask */ 357 uint32_t :21; /**< bit: 11..31 Reserved */ 358 } bit; /**< Structure used for bit access */ 359 uint32_t reg; /**< Type used for register access */ 360 } QSPI_IMR_Type; 361 #endif 362 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 363 364 #define QSPI_IMR_OFFSET (0x1C) /**< (QSPI_IMR) Interrupt Mask Register Offset */ 365 366 #define QSPI_IMR_RDRF_Pos 0 /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Position */ 367 #define QSPI_IMR_RDRF_Msk (_U_(0x1) << QSPI_IMR_RDRF_Pos) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Mask */ 368 #define QSPI_IMR_RDRF QSPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_RDRF_Msk instead */ 369 #define QSPI_IMR_TDRE_Pos 1 /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Position */ 370 #define QSPI_IMR_TDRE_Msk (_U_(0x1) << QSPI_IMR_TDRE_Pos) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Mask */ 371 #define QSPI_IMR_TDRE QSPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TDRE_Msk instead */ 372 #define QSPI_IMR_TXEMPTY_Pos 2 /**< (QSPI_IMR) Transmission Registers Empty Mask Position */ 373 #define QSPI_IMR_TXEMPTY_Msk (_U_(0x1) << QSPI_IMR_TXEMPTY_Pos) /**< (QSPI_IMR) Transmission Registers Empty Mask Mask */ 374 #define QSPI_IMR_TXEMPTY QSPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TXEMPTY_Msk instead */ 375 #define QSPI_IMR_OVRES_Pos 3 /**< (QSPI_IMR) Overrun Error Interrupt Mask Position */ 376 #define QSPI_IMR_OVRES_Msk (_U_(0x1) << QSPI_IMR_OVRES_Pos) /**< (QSPI_IMR) Overrun Error Interrupt Mask Mask */ 377 #define QSPI_IMR_OVRES QSPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_OVRES_Msk instead */ 378 #define QSPI_IMR_CSR_Pos 8 /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Position */ 379 #define QSPI_IMR_CSR_Msk (_U_(0x1) << QSPI_IMR_CSR_Pos) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Mask */ 380 #define QSPI_IMR_CSR QSPI_IMR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSR_Msk instead */ 381 #define QSPI_IMR_CSS_Pos 9 /**< (QSPI_IMR) Chip Select Status Interrupt Mask Position */ 382 #define QSPI_IMR_CSS_Msk (_U_(0x1) << QSPI_IMR_CSS_Pos) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Mask */ 383 #define QSPI_IMR_CSS QSPI_IMR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSS_Msk instead */ 384 #define QSPI_IMR_INSTRE_Pos 10 /**< (QSPI_IMR) Instruction End Interrupt Mask Position */ 385 #define QSPI_IMR_INSTRE_Msk (_U_(0x1) << QSPI_IMR_INSTRE_Pos) /**< (QSPI_IMR) Instruction End Interrupt Mask Mask */ 386 #define QSPI_IMR_INSTRE QSPI_IMR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_INSTRE_Msk instead */ 387 #define QSPI_IMR_MASK _U_(0x70F) /**< \deprecated (QSPI_IMR) Register MASK (Use QSPI_IMR_Msk instead) */ 388 #define QSPI_IMR_Msk _U_(0x70F) /**< (QSPI_IMR) Register Mask */ 389 390 391 /* -------- QSPI_SCR : (QSPI Offset: 0x20) (R/W 32) Serial Clock Register -------- */ 392 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 393 #if COMPONENT_TYPEDEF_STYLE == 'N' 394 typedef union { 395 struct { 396 uint32_t CPOL:1; /**< bit: 0 Clock Polarity */ 397 uint32_t CPHA:1; /**< bit: 1 Clock Phase */ 398 uint32_t :6; /**< bit: 2..7 Reserved */ 399 uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Baud Rate */ 400 uint32_t DLYBS:8; /**< bit: 16..23 Delay Before QSCK */ 401 uint32_t :8; /**< bit: 24..31 Reserved */ 402 } bit; /**< Structure used for bit access */ 403 uint32_t reg; /**< Type used for register access */ 404 } QSPI_SCR_Type; 405 #endif 406 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define QSPI_SCR_OFFSET (0x20) /**< (QSPI_SCR) Serial Clock Register Offset */ 409 410 #define QSPI_SCR_CPOL_Pos 0 /**< (QSPI_SCR) Clock Polarity Position */ 411 #define QSPI_SCR_CPOL_Msk (_U_(0x1) << QSPI_SCR_CPOL_Pos) /**< (QSPI_SCR) Clock Polarity Mask */ 412 #define QSPI_SCR_CPOL QSPI_SCR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPOL_Msk instead */ 413 #define QSPI_SCR_CPHA_Pos 1 /**< (QSPI_SCR) Clock Phase Position */ 414 #define QSPI_SCR_CPHA_Msk (_U_(0x1) << QSPI_SCR_CPHA_Pos) /**< (QSPI_SCR) Clock Phase Mask */ 415 #define QSPI_SCR_CPHA QSPI_SCR_CPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPHA_Msk instead */ 416 #define QSPI_SCR_SCBR_Pos 8 /**< (QSPI_SCR) Serial Clock Baud Rate Position */ 417 #define QSPI_SCR_SCBR_Msk (_U_(0xFF) << QSPI_SCR_SCBR_Pos) /**< (QSPI_SCR) Serial Clock Baud Rate Mask */ 418 #define QSPI_SCR_SCBR(value) (QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)) 419 #define QSPI_SCR_DLYBS_Pos 16 /**< (QSPI_SCR) Delay Before QSCK Position */ 420 #define QSPI_SCR_DLYBS_Msk (_U_(0xFF) << QSPI_SCR_DLYBS_Pos) /**< (QSPI_SCR) Delay Before QSCK Mask */ 421 #define QSPI_SCR_DLYBS(value) (QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)) 422 #define QSPI_SCR_MASK _U_(0xFFFF03) /**< \deprecated (QSPI_SCR) Register MASK (Use QSPI_SCR_Msk instead) */ 423 #define QSPI_SCR_Msk _U_(0xFFFF03) /**< (QSPI_SCR) Register Mask */ 424 425 426 /* -------- QSPI_IAR : (QSPI Offset: 0x30) (R/W 32) Instruction Address Register -------- */ 427 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 428 #if COMPONENT_TYPEDEF_STYLE == 'N' 429 typedef union { 430 struct { 431 uint32_t ADDR:32; /**< bit: 0..31 Address */ 432 } bit; /**< Structure used for bit access */ 433 uint32_t reg; /**< Type used for register access */ 434 } QSPI_IAR_Type; 435 #endif 436 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define QSPI_IAR_OFFSET (0x30) /**< (QSPI_IAR) Instruction Address Register Offset */ 439 440 #define QSPI_IAR_ADDR_Pos 0 /**< (QSPI_IAR) Address Position */ 441 #define QSPI_IAR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_IAR_ADDR_Pos) /**< (QSPI_IAR) Address Mask */ 442 #define QSPI_IAR_ADDR(value) (QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)) 443 #define QSPI_IAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_IAR) Register MASK (Use QSPI_IAR_Msk instead) */ 444 #define QSPI_IAR_Msk _U_(0xFFFFFFFF) /**< (QSPI_IAR) Register Mask */ 445 446 447 /* -------- QSPI_ICR : (QSPI Offset: 0x34) (R/W 32) Instruction Code Register -------- */ 448 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 449 #if COMPONENT_TYPEDEF_STYLE == 'N' 450 typedef union { 451 struct { 452 uint32_t INST:8; /**< bit: 0..7 Instruction Code */ 453 uint32_t :8; /**< bit: 8..15 Reserved */ 454 uint32_t OPT:8; /**< bit: 16..23 Option Code */ 455 uint32_t :8; /**< bit: 24..31 Reserved */ 456 } bit; /**< Structure used for bit access */ 457 uint32_t reg; /**< Type used for register access */ 458 } QSPI_ICR_Type; 459 #endif 460 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define QSPI_ICR_OFFSET (0x34) /**< (QSPI_ICR) Instruction Code Register Offset */ 463 464 #define QSPI_ICR_INST_Pos 0 /**< (QSPI_ICR) Instruction Code Position */ 465 #define QSPI_ICR_INST_Msk (_U_(0xFF) << QSPI_ICR_INST_Pos) /**< (QSPI_ICR) Instruction Code Mask */ 466 #define QSPI_ICR_INST(value) (QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)) 467 #define QSPI_ICR_OPT_Pos 16 /**< (QSPI_ICR) Option Code Position */ 468 #define QSPI_ICR_OPT_Msk (_U_(0xFF) << QSPI_ICR_OPT_Pos) /**< (QSPI_ICR) Option Code Mask */ 469 #define QSPI_ICR_OPT(value) (QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)) 470 #define QSPI_ICR_MASK _U_(0xFF00FF) /**< \deprecated (QSPI_ICR) Register MASK (Use QSPI_ICR_Msk instead) */ 471 #define QSPI_ICR_Msk _U_(0xFF00FF) /**< (QSPI_ICR) Register Mask */ 472 473 474 /* -------- QSPI_IFR : (QSPI Offset: 0x38) (R/W 32) Instruction Frame Register -------- */ 475 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 476 #if COMPONENT_TYPEDEF_STYLE == 'N' 477 typedef union { 478 struct { 479 uint32_t WIDTH:3; /**< bit: 0..2 Width of Instruction Code, Address, Option Code and Data */ 480 uint32_t :1; /**< bit: 3 Reserved */ 481 uint32_t INSTEN:1; /**< bit: 4 Instruction Enable */ 482 uint32_t ADDREN:1; /**< bit: 5 Address Enable */ 483 uint32_t OPTEN:1; /**< bit: 6 Option Enable */ 484 uint32_t DATAEN:1; /**< bit: 7 Data Enable */ 485 uint32_t OPTL:2; /**< bit: 8..9 Option Code Length */ 486 uint32_t ADDRL:1; /**< bit: 10 Address Length */ 487 uint32_t :1; /**< bit: 11 Reserved */ 488 uint32_t TFRTYP:2; /**< bit: 12..13 Data Transfer Type */ 489 uint32_t CRM:1; /**< bit: 14 Continuous Read Mode */ 490 uint32_t :1; /**< bit: 15 Reserved */ 491 uint32_t NBDUM:5; /**< bit: 16..20 Number Of Dummy Cycles */ 492 uint32_t :11; /**< bit: 21..31 Reserved */ 493 } bit; /**< Structure used for bit access */ 494 uint32_t reg; /**< Type used for register access */ 495 } QSPI_IFR_Type; 496 #endif 497 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 498 499 #define QSPI_IFR_OFFSET (0x38) /**< (QSPI_IFR) Instruction Frame Register Offset */ 500 501 #define QSPI_IFR_WIDTH_Pos 0 /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Position */ 502 #define QSPI_IFR_WIDTH_Msk (_U_(0x7) << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Mask */ 503 #define QSPI_IFR_WIDTH(value) (QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)) 504 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ 505 #define QSPI_IFR_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ 506 #define QSPI_IFR_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ 507 #define QSPI_IFR_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ 508 #define QSPI_IFR_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ 509 #define QSPI_IFR_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ 510 #define QSPI_IFR_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ 511 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */ 512 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (QSPI_IFR_WIDTH_DUAL_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */ 513 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (QSPI_IFR_WIDTH_QUAD_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */ 514 #define QSPI_IFR_WIDTH_DUAL_IO (QSPI_IFR_WIDTH_DUAL_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ 515 #define QSPI_IFR_WIDTH_QUAD_IO (QSPI_IFR_WIDTH_QUAD_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ 516 #define QSPI_IFR_WIDTH_DUAL_CMD (QSPI_IFR_WIDTH_DUAL_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ 517 #define QSPI_IFR_WIDTH_QUAD_CMD (QSPI_IFR_WIDTH_QUAD_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ 518 #define QSPI_IFR_INSTEN_Pos 4 /**< (QSPI_IFR) Instruction Enable Position */ 519 #define QSPI_IFR_INSTEN_Msk (_U_(0x1) << QSPI_IFR_INSTEN_Pos) /**< (QSPI_IFR) Instruction Enable Mask */ 520 #define QSPI_IFR_INSTEN QSPI_IFR_INSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_INSTEN_Msk instead */ 521 #define QSPI_IFR_ADDREN_Pos 5 /**< (QSPI_IFR) Address Enable Position */ 522 #define QSPI_IFR_ADDREN_Msk (_U_(0x1) << QSPI_IFR_ADDREN_Pos) /**< (QSPI_IFR) Address Enable Mask */ 523 #define QSPI_IFR_ADDREN QSPI_IFR_ADDREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDREN_Msk instead */ 524 #define QSPI_IFR_OPTEN_Pos 6 /**< (QSPI_IFR) Option Enable Position */ 525 #define QSPI_IFR_OPTEN_Msk (_U_(0x1) << QSPI_IFR_OPTEN_Pos) /**< (QSPI_IFR) Option Enable Mask */ 526 #define QSPI_IFR_OPTEN QSPI_IFR_OPTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_OPTEN_Msk instead */ 527 #define QSPI_IFR_DATAEN_Pos 7 /**< (QSPI_IFR) Data Enable Position */ 528 #define QSPI_IFR_DATAEN_Msk (_U_(0x1) << QSPI_IFR_DATAEN_Pos) /**< (QSPI_IFR) Data Enable Mask */ 529 #define QSPI_IFR_DATAEN QSPI_IFR_DATAEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_DATAEN_Msk instead */ 530 #define QSPI_IFR_OPTL_Pos 8 /**< (QSPI_IFR) Option Code Length Position */ 531 #define QSPI_IFR_OPTL_Msk (_U_(0x3) << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) Option Code Length Mask */ 532 #define QSPI_IFR_OPTL(value) (QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)) 533 #define QSPI_IFR_OPTL_OPTION_1BIT_Val _U_(0x0) /**< (QSPI_IFR) The option code is 1 bit long. */ 534 #define QSPI_IFR_OPTL_OPTION_2BIT_Val _U_(0x1) /**< (QSPI_IFR) The option code is 2 bits long. */ 535 #define QSPI_IFR_OPTL_OPTION_4BIT_Val _U_(0x2) /**< (QSPI_IFR) The option code is 4 bits long. */ 536 #define QSPI_IFR_OPTL_OPTION_8BIT_Val _U_(0x3) /**< (QSPI_IFR) The option code is 8 bits long. */ 537 #define QSPI_IFR_OPTL_OPTION_1BIT (QSPI_IFR_OPTL_OPTION_1BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 1 bit long. Position */ 538 #define QSPI_IFR_OPTL_OPTION_2BIT (QSPI_IFR_OPTL_OPTION_2BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 2 bits long. Position */ 539 #define QSPI_IFR_OPTL_OPTION_4BIT (QSPI_IFR_OPTL_OPTION_4BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 4 bits long. Position */ 540 #define QSPI_IFR_OPTL_OPTION_8BIT (QSPI_IFR_OPTL_OPTION_8BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 8 bits long. Position */ 541 #define QSPI_IFR_ADDRL_Pos 10 /**< (QSPI_IFR) Address Length Position */ 542 #define QSPI_IFR_ADDRL_Msk (_U_(0x1) << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) Address Length Mask */ 543 #define QSPI_IFR_ADDRL QSPI_IFR_ADDRL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDRL_Msk instead */ 544 #define QSPI_IFR_ADDRL_24_BIT_Val _U_(0x0) /**< (QSPI_IFR) The address is 24 bits long. */ 545 #define QSPI_IFR_ADDRL_32_BIT_Val _U_(0x1) /**< (QSPI_IFR) The address is 32 bits long. */ 546 #define QSPI_IFR_ADDRL_24_BIT (QSPI_IFR_ADDRL_24_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 24 bits long. Position */ 547 #define QSPI_IFR_ADDRL_32_BIT (QSPI_IFR_ADDRL_32_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 32 bits long. Position */ 548 #define QSPI_IFR_TFRTYP_Pos 12 /**< (QSPI_IFR) Data Transfer Type Position */ 549 #define QSPI_IFR_TFRTYP_Msk (_U_(0x3) << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Data Transfer Type Mask */ 550 #define QSPI_IFR_TFRTYP(value) (QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)) 551 #define QSPI_IFR_TFRTYP_TRSFR_READ_Val _U_(0x0) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ 552 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val _U_(0x1) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ 553 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_Val _U_(0x2) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ 554 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val _U_(0x3) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ 555 #define QSPI_IFR_TFRTYP_TRSFR_READ (QSPI_IFR_TFRTYP_TRSFR_READ_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. Position */ 556 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. Position */ 557 #define QSPI_IFR_TFRTYP_TRSFR_WRITE (QSPI_IFR_TFRTYP_TRSFR_WRITE_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. Position */ 558 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */ 559 #define QSPI_IFR_CRM_Pos 14 /**< (QSPI_IFR) Continuous Read Mode Position */ 560 #define QSPI_IFR_CRM_Msk (_U_(0x1) << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) Continuous Read Mode Mask */ 561 #define QSPI_IFR_CRM QSPI_IFR_CRM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_CRM_Msk instead */ 562 #define QSPI_IFR_CRM_DISABLED_Val _U_(0x0) /**< (QSPI_IFR) The Continuous Read mode is disabled. */ 563 #define QSPI_IFR_CRM_ENABLED_Val _U_(0x1) /**< (QSPI_IFR) The Continuous Read mode is enabled. */ 564 #define QSPI_IFR_CRM_DISABLED (QSPI_IFR_CRM_DISABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is disabled. Position */ 565 #define QSPI_IFR_CRM_ENABLED (QSPI_IFR_CRM_ENABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is enabled. Position */ 566 #define QSPI_IFR_NBDUM_Pos 16 /**< (QSPI_IFR) Number Of Dummy Cycles Position */ 567 #define QSPI_IFR_NBDUM_Msk (_U_(0x1F) << QSPI_IFR_NBDUM_Pos) /**< (QSPI_IFR) Number Of Dummy Cycles Mask */ 568 #define QSPI_IFR_NBDUM(value) (QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)) 569 #define QSPI_IFR_MASK _U_(0x1F77F7) /**< \deprecated (QSPI_IFR) Register MASK (Use QSPI_IFR_Msk instead) */ 570 #define QSPI_IFR_Msk _U_(0x1F77F7) /**< (QSPI_IFR) Register Mask */ 571 572 573 /* -------- QSPI_SMR : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode Register -------- */ 574 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 575 #if COMPONENT_TYPEDEF_STYLE == 'N' 576 typedef union { 577 struct { 578 uint32_t SCREN:1; /**< bit: 0 Scrambling/Unscrambling Enable */ 579 uint32_t RVDIS:1; /**< bit: 1 Scrambling/Unscrambling Random Value Disable */ 580 uint32_t :30; /**< bit: 2..31 Reserved */ 581 } bit; /**< Structure used for bit access */ 582 uint32_t reg; /**< Type used for register access */ 583 } QSPI_SMR_Type; 584 #endif 585 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 586 587 #define QSPI_SMR_OFFSET (0x40) /**< (QSPI_SMR) Scrambling Mode Register Offset */ 588 589 #define QSPI_SMR_SCREN_Pos 0 /**< (QSPI_SMR) Scrambling/Unscrambling Enable Position */ 590 #define QSPI_SMR_SCREN_Msk (_U_(0x1) << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Mask */ 591 #define QSPI_SMR_SCREN QSPI_SMR_SCREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_SCREN_Msk instead */ 592 #define QSPI_SMR_SCREN_DISABLED_Val _U_(0x0) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. */ 593 #define QSPI_SMR_SCREN_ENABLED_Val _U_(0x1) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. */ 594 #define QSPI_SMR_SCREN_DISABLED (QSPI_SMR_SCREN_DISABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. Position */ 595 #define QSPI_SMR_SCREN_ENABLED (QSPI_SMR_SCREN_ENABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. Position */ 596 #define QSPI_SMR_RVDIS_Pos 1 /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Position */ 597 #define QSPI_SMR_RVDIS_Msk (_U_(0x1) << QSPI_SMR_RVDIS_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Mask */ 598 #define QSPI_SMR_RVDIS QSPI_SMR_RVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_RVDIS_Msk instead */ 599 #define QSPI_SMR_MASK _U_(0x03) /**< \deprecated (QSPI_SMR) Register MASK (Use QSPI_SMR_Msk instead) */ 600 #define QSPI_SMR_Msk _U_(0x03) /**< (QSPI_SMR) Register Mask */ 601 602 603 /* -------- QSPI_SKR : (QSPI Offset: 0x44) (/W 32) Scrambling Key Register -------- */ 604 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 605 #if COMPONENT_TYPEDEF_STYLE == 'N' 606 typedef union { 607 struct { 608 uint32_t USRK:32; /**< bit: 0..31 User Scrambling Key */ 609 } bit; /**< Structure used for bit access */ 610 uint32_t reg; /**< Type used for register access */ 611 } QSPI_SKR_Type; 612 #endif 613 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 614 615 #define QSPI_SKR_OFFSET (0x44) /**< (QSPI_SKR) Scrambling Key Register Offset */ 616 617 #define QSPI_SKR_USRK_Pos 0 /**< (QSPI_SKR) User Scrambling Key Position */ 618 #define QSPI_SKR_USRK_Msk (_U_(0xFFFFFFFF) << QSPI_SKR_USRK_Pos) /**< (QSPI_SKR) User Scrambling Key Mask */ 619 #define QSPI_SKR_USRK(value) (QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)) 620 #define QSPI_SKR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_SKR) Register MASK (Use QSPI_SKR_Msk instead) */ 621 #define QSPI_SKR_Msk _U_(0xFFFFFFFF) /**< (QSPI_SKR) Register Mask */ 622 623 624 /* -------- QSPI_WPMR : (QSPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 625 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 626 #if COMPONENT_TYPEDEF_STYLE == 'N' 627 typedef union { 628 struct { 629 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 630 uint32_t :7; /**< bit: 1..7 Reserved */ 631 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 632 } bit; /**< Structure used for bit access */ 633 uint32_t reg; /**< Type used for register access */ 634 } QSPI_WPMR_Type; 635 #endif 636 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 637 638 #define QSPI_WPMR_OFFSET (0xE4) /**< (QSPI_WPMR) Write Protection Mode Register Offset */ 639 640 #define QSPI_WPMR_WPEN_Pos 0 /**< (QSPI_WPMR) Write Protection Enable Position */ 641 #define QSPI_WPMR_WPEN_Msk (_U_(0x1) << QSPI_WPMR_WPEN_Pos) /**< (QSPI_WPMR) Write Protection Enable Mask */ 642 #define QSPI_WPMR_WPEN QSPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPMR_WPEN_Msk instead */ 643 #define QSPI_WPMR_WPKEY_Pos 8 /**< (QSPI_WPMR) Write Protection Key Position */ 644 #define QSPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Write Protection Key Mask */ 645 #define QSPI_WPMR_WPKEY(value) (QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)) 646 #define QSPI_WPMR_WPKEY_PASSWD_Val _U_(0x515350) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ 647 #define QSPI_WPMR_WPKEY_PASSWD (QSPI_WPMR_WPKEY_PASSWD_Val << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ 648 #define QSPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (QSPI_WPMR) Register MASK (Use QSPI_WPMR_Msk instead) */ 649 #define QSPI_WPMR_Msk _U_(0xFFFFFF01) /**< (QSPI_WPMR) Register Mask */ 650 651 652 /* -------- QSPI_WPSR : (QSPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 653 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 654 #if COMPONENT_TYPEDEF_STYLE == 'N' 655 typedef union { 656 struct { 657 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 658 uint32_t :7; /**< bit: 1..7 Reserved */ 659 uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ 660 uint32_t :16; /**< bit: 16..31 Reserved */ 661 } bit; /**< Structure used for bit access */ 662 uint32_t reg; /**< Type used for register access */ 663 } QSPI_WPSR_Type; 664 #endif 665 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 666 667 #define QSPI_WPSR_OFFSET (0xE8) /**< (QSPI_WPSR) Write Protection Status Register Offset */ 668 669 #define QSPI_WPSR_WPVS_Pos 0 /**< (QSPI_WPSR) Write Protection Violation Status Position */ 670 #define QSPI_WPSR_WPVS_Msk (_U_(0x1) << QSPI_WPSR_WPVS_Pos) /**< (QSPI_WPSR) Write Protection Violation Status Mask */ 671 #define QSPI_WPSR_WPVS QSPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPSR_WPVS_Msk instead */ 672 #define QSPI_WPSR_WPVSRC_Pos 8 /**< (QSPI_WPSR) Write Protection Violation Source Position */ 673 #define QSPI_WPSR_WPVSRC_Msk (_U_(0xFF) << QSPI_WPSR_WPVSRC_Pos) /**< (QSPI_WPSR) Write Protection Violation Source Mask */ 674 #define QSPI_WPSR_WPVSRC(value) (QSPI_WPSR_WPVSRC_Msk & ((value) << QSPI_WPSR_WPVSRC_Pos)) 675 #define QSPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (QSPI_WPSR) Register MASK (Use QSPI_WPSR_Msk instead) */ 676 #define QSPI_WPSR_Msk _U_(0xFF01) /**< (QSPI_WPSR) Register Mask */ 677 678 679 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 680 #if COMPONENT_TYPEDEF_STYLE == 'R' 681 /** \brief QSPI hardware registers */ 682 typedef struct { 683 __O uint32_t QSPI_CR; /**< (QSPI Offset: 0x00) Control Register */ 684 __IO uint32_t QSPI_MR; /**< (QSPI Offset: 0x04) Mode Register */ 685 __I uint32_t QSPI_RDR; /**< (QSPI Offset: 0x08) Receive Data Register */ 686 __O uint32_t QSPI_TDR; /**< (QSPI Offset: 0x0C) Transmit Data Register */ 687 __I uint32_t QSPI_SR; /**< (QSPI Offset: 0x10) Status Register */ 688 __O uint32_t QSPI_IER; /**< (QSPI Offset: 0x14) Interrupt Enable Register */ 689 __O uint32_t QSPI_IDR; /**< (QSPI Offset: 0x18) Interrupt Disable Register */ 690 __I uint32_t QSPI_IMR; /**< (QSPI Offset: 0x1C) Interrupt Mask Register */ 691 __IO uint32_t QSPI_SCR; /**< (QSPI Offset: 0x20) Serial Clock Register */ 692 __I uint8_t Reserved1[12]; 693 __IO uint32_t QSPI_IAR; /**< (QSPI Offset: 0x30) Instruction Address Register */ 694 __IO uint32_t QSPI_ICR; /**< (QSPI Offset: 0x34) Instruction Code Register */ 695 __IO uint32_t QSPI_IFR; /**< (QSPI Offset: 0x38) Instruction Frame Register */ 696 __I uint8_t Reserved2[4]; 697 __IO uint32_t QSPI_SMR; /**< (QSPI Offset: 0x40) Scrambling Mode Register */ 698 __O uint32_t QSPI_SKR; /**< (QSPI Offset: 0x44) Scrambling Key Register */ 699 __I uint8_t Reserved3[156]; 700 __IO uint32_t QSPI_WPMR; /**< (QSPI Offset: 0xE4) Write Protection Mode Register */ 701 __I uint32_t QSPI_WPSR; /**< (QSPI Offset: 0xE8) Write Protection Status Register */ 702 } Qspi; 703 704 #elif COMPONENT_TYPEDEF_STYLE == 'N' 705 /** \brief QSPI hardware registers */ 706 typedef struct { 707 __O QSPI_CR_Type QSPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 708 __IO QSPI_MR_Type QSPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 709 __I QSPI_RDR_Type QSPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ 710 __O QSPI_TDR_Type QSPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ 711 __I QSPI_SR_Type QSPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ 712 __O QSPI_IER_Type QSPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ 713 __O QSPI_IDR_Type QSPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ 714 __I QSPI_IMR_Type QSPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ 715 __IO QSPI_SCR_Type QSPI_SCR; /**< Offset: 0x20 (R/W 32) Serial Clock Register */ 716 __I uint8_t Reserved1[12]; 717 __IO QSPI_IAR_Type QSPI_IAR; /**< Offset: 0x30 (R/W 32) Instruction Address Register */ 718 __IO QSPI_ICR_Type QSPI_ICR; /**< Offset: 0x34 (R/W 32) Instruction Code Register */ 719 __IO QSPI_IFR_Type QSPI_IFR; /**< Offset: 0x38 (R/W 32) Instruction Frame Register */ 720 __I uint8_t Reserved2[4]; 721 __IO QSPI_SMR_Type QSPI_SMR; /**< Offset: 0x40 (R/W 32) Scrambling Mode Register */ 722 __O QSPI_SKR_Type QSPI_SKR; /**< Offset: 0x44 ( /W 32) Scrambling Key Register */ 723 __I uint8_t Reserved3[156]; 724 __IO QSPI_WPMR_Type QSPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 725 __I QSPI_WPSR_Type QSPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 726 } Qspi; 727 728 #else /* COMPONENT_TYPEDEF_STYLE */ 729 #error Unknown component typedef style 730 #endif /* COMPONENT_TYPEDEF_STYLE */ 731 732 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 733 /** @} end of Quad Serial Peripheral Interface */ 734 735 #endif /* _SAMV71_QSPI_COMPONENT_H_ */ 736
