1 /** 2 * \file 3 * 4 * \brief Component description for PMC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_PMC_COMPONENT_H_ 32 #define _SAMV71_PMC_COMPONENT_H_ 33 #define _SAMV71_PMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Power Management Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR PMC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define PMC_44006 /**< (PMC) Module ID */ 46 #define REV_PMC P /**< (PMC) Module revision */ 47 48 /* -------- PMC_SCER : (PMC Offset: 0x00) (/W 32) System Clock Enable Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t :5; /**< bit: 0..4 Reserved */ 54 uint32_t USBCLK:1; /**< bit: 5 Enable USB FS Clock */ 55 uint32_t :2; /**< bit: 6..7 Reserved */ 56 uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Enable */ 57 uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Enable */ 58 uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Enable */ 59 uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Enable */ 60 uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Enable */ 61 uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Enable */ 62 uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Enable */ 63 uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Enable */ 64 uint32_t :16; /**< bit: 16..31 Reserved */ 65 } bit; /**< Structure used for bit access */ 66 struct { 67 uint32_t :8; /**< bit: 0..7 Reserved */ 68 uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Enable */ 69 uint32_t :16; /**< bit: 16..31 Reserved */ 70 } vec; /**< Structure used for vec access */ 71 uint32_t reg; /**< Type used for register access */ 72 } PMC_SCER_Type; 73 #endif 74 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 #define PMC_SCER_OFFSET (0x00) /**< (PMC_SCER) System Clock Enable Register Offset */ 77 78 #define PMC_SCER_USBCLK_Pos 5 /**< (PMC_SCER) Enable USB FS Clock Position */ 79 #define PMC_SCER_USBCLK_Msk (_U_(0x1) << PMC_SCER_USBCLK_Pos) /**< (PMC_SCER) Enable USB FS Clock Mask */ 80 #define PMC_SCER_USBCLK PMC_SCER_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_USBCLK_Msk instead */ 81 #define PMC_SCER_PCK0_Pos 8 /**< (PMC_SCER) Programmable Clock 0 Output Enable Position */ 82 #define PMC_SCER_PCK0_Msk (_U_(0x1) << PMC_SCER_PCK0_Pos) /**< (PMC_SCER) Programmable Clock 0 Output Enable Mask */ 83 #define PMC_SCER_PCK0 PMC_SCER_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK0_Msk instead */ 84 #define PMC_SCER_PCK1_Pos 9 /**< (PMC_SCER) Programmable Clock 1 Output Enable Position */ 85 #define PMC_SCER_PCK1_Msk (_U_(0x1) << PMC_SCER_PCK1_Pos) /**< (PMC_SCER) Programmable Clock 1 Output Enable Mask */ 86 #define PMC_SCER_PCK1 PMC_SCER_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK1_Msk instead */ 87 #define PMC_SCER_PCK2_Pos 10 /**< (PMC_SCER) Programmable Clock 2 Output Enable Position */ 88 #define PMC_SCER_PCK2_Msk (_U_(0x1) << PMC_SCER_PCK2_Pos) /**< (PMC_SCER) Programmable Clock 2 Output Enable Mask */ 89 #define PMC_SCER_PCK2 PMC_SCER_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK2_Msk instead */ 90 #define PMC_SCER_PCK3_Pos 11 /**< (PMC_SCER) Programmable Clock 3 Output Enable Position */ 91 #define PMC_SCER_PCK3_Msk (_U_(0x1) << PMC_SCER_PCK3_Pos) /**< (PMC_SCER) Programmable Clock 3 Output Enable Mask */ 92 #define PMC_SCER_PCK3 PMC_SCER_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK3_Msk instead */ 93 #define PMC_SCER_PCK4_Pos 12 /**< (PMC_SCER) Programmable Clock 4 Output Enable Position */ 94 #define PMC_SCER_PCK4_Msk (_U_(0x1) << PMC_SCER_PCK4_Pos) /**< (PMC_SCER) Programmable Clock 4 Output Enable Mask */ 95 #define PMC_SCER_PCK4 PMC_SCER_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK4_Msk instead */ 96 #define PMC_SCER_PCK5_Pos 13 /**< (PMC_SCER) Programmable Clock 5 Output Enable Position */ 97 #define PMC_SCER_PCK5_Msk (_U_(0x1) << PMC_SCER_PCK5_Pos) /**< (PMC_SCER) Programmable Clock 5 Output Enable Mask */ 98 #define PMC_SCER_PCK5 PMC_SCER_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK5_Msk instead */ 99 #define PMC_SCER_PCK6_Pos 14 /**< (PMC_SCER) Programmable Clock 6 Output Enable Position */ 100 #define PMC_SCER_PCK6_Msk (_U_(0x1) << PMC_SCER_PCK6_Pos) /**< (PMC_SCER) Programmable Clock 6 Output Enable Mask */ 101 #define PMC_SCER_PCK6 PMC_SCER_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK6_Msk instead */ 102 #define PMC_SCER_PCK7_Pos 15 /**< (PMC_SCER) Programmable Clock 7 Output Enable Position */ 103 #define PMC_SCER_PCK7_Msk (_U_(0x1) << PMC_SCER_PCK7_Pos) /**< (PMC_SCER) Programmable Clock 7 Output Enable Mask */ 104 #define PMC_SCER_PCK7 PMC_SCER_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK7_Msk instead */ 105 #define PMC_SCER_MASK _U_(0xFF20) /**< \deprecated (PMC_SCER) Register MASK (Use PMC_SCER_Msk instead) */ 106 #define PMC_SCER_Msk _U_(0xFF20) /**< (PMC_SCER) Register Mask */ 107 108 #define PMC_SCER_PCK_Pos 8 /**< (PMC_SCER Position) Programmable Clock 7 Output Enable */ 109 #define PMC_SCER_PCK_Msk (_U_(0xFF) << PMC_SCER_PCK_Pos) /**< (PMC_SCER Mask) PCK */ 110 #define PMC_SCER_PCK(value) (PMC_SCER_PCK_Msk & ((value) << PMC_SCER_PCK_Pos)) 111 112 /* -------- PMC_SCDR : (PMC Offset: 0x04) (/W 32) System Clock Disable Register -------- */ 113 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 114 #if COMPONENT_TYPEDEF_STYLE == 'N' 115 typedef union { 116 struct { 117 uint32_t :5; /**< bit: 0..4 Reserved */ 118 uint32_t USBCLK:1; /**< bit: 5 Disable USB FS Clock */ 119 uint32_t :2; /**< bit: 6..7 Reserved */ 120 uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Disable */ 121 uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Disable */ 122 uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Disable */ 123 uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Disable */ 124 uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Disable */ 125 uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Disable */ 126 uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Disable */ 127 uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Disable */ 128 uint32_t :16; /**< bit: 16..31 Reserved */ 129 } bit; /**< Structure used for bit access */ 130 struct { 131 uint32_t :8; /**< bit: 0..7 Reserved */ 132 uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Disable */ 133 uint32_t :16; /**< bit: 16..31 Reserved */ 134 } vec; /**< Structure used for vec access */ 135 uint32_t reg; /**< Type used for register access */ 136 } PMC_SCDR_Type; 137 #endif 138 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 139 140 #define PMC_SCDR_OFFSET (0x04) /**< (PMC_SCDR) System Clock Disable Register Offset */ 141 142 #define PMC_SCDR_USBCLK_Pos 5 /**< (PMC_SCDR) Disable USB FS Clock Position */ 143 #define PMC_SCDR_USBCLK_Msk (_U_(0x1) << PMC_SCDR_USBCLK_Pos) /**< (PMC_SCDR) Disable USB FS Clock Mask */ 144 #define PMC_SCDR_USBCLK PMC_SCDR_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_USBCLK_Msk instead */ 145 #define PMC_SCDR_PCK0_Pos 8 /**< (PMC_SCDR) Programmable Clock 0 Output Disable Position */ 146 #define PMC_SCDR_PCK0_Msk (_U_(0x1) << PMC_SCDR_PCK0_Pos) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Mask */ 147 #define PMC_SCDR_PCK0 PMC_SCDR_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK0_Msk instead */ 148 #define PMC_SCDR_PCK1_Pos 9 /**< (PMC_SCDR) Programmable Clock 1 Output Disable Position */ 149 #define PMC_SCDR_PCK1_Msk (_U_(0x1) << PMC_SCDR_PCK1_Pos) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Mask */ 150 #define PMC_SCDR_PCK1 PMC_SCDR_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK1_Msk instead */ 151 #define PMC_SCDR_PCK2_Pos 10 /**< (PMC_SCDR) Programmable Clock 2 Output Disable Position */ 152 #define PMC_SCDR_PCK2_Msk (_U_(0x1) << PMC_SCDR_PCK2_Pos) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Mask */ 153 #define PMC_SCDR_PCK2 PMC_SCDR_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK2_Msk instead */ 154 #define PMC_SCDR_PCK3_Pos 11 /**< (PMC_SCDR) Programmable Clock 3 Output Disable Position */ 155 #define PMC_SCDR_PCK3_Msk (_U_(0x1) << PMC_SCDR_PCK3_Pos) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Mask */ 156 #define PMC_SCDR_PCK3 PMC_SCDR_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK3_Msk instead */ 157 #define PMC_SCDR_PCK4_Pos 12 /**< (PMC_SCDR) Programmable Clock 4 Output Disable Position */ 158 #define PMC_SCDR_PCK4_Msk (_U_(0x1) << PMC_SCDR_PCK4_Pos) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Mask */ 159 #define PMC_SCDR_PCK4 PMC_SCDR_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK4_Msk instead */ 160 #define PMC_SCDR_PCK5_Pos 13 /**< (PMC_SCDR) Programmable Clock 5 Output Disable Position */ 161 #define PMC_SCDR_PCK5_Msk (_U_(0x1) << PMC_SCDR_PCK5_Pos) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Mask */ 162 #define PMC_SCDR_PCK5 PMC_SCDR_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK5_Msk instead */ 163 #define PMC_SCDR_PCK6_Pos 14 /**< (PMC_SCDR) Programmable Clock 6 Output Disable Position */ 164 #define PMC_SCDR_PCK6_Msk (_U_(0x1) << PMC_SCDR_PCK6_Pos) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Mask */ 165 #define PMC_SCDR_PCK6 PMC_SCDR_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK6_Msk instead */ 166 #define PMC_SCDR_PCK7_Pos 15 /**< (PMC_SCDR) Programmable Clock 7 Output Disable Position */ 167 #define PMC_SCDR_PCK7_Msk (_U_(0x1) << PMC_SCDR_PCK7_Pos) /**< (PMC_SCDR) Programmable Clock 7 Output Disable Mask */ 168 #define PMC_SCDR_PCK7 PMC_SCDR_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK7_Msk instead */ 169 #define PMC_SCDR_MASK _U_(0xFF20) /**< \deprecated (PMC_SCDR) Register MASK (Use PMC_SCDR_Msk instead) */ 170 #define PMC_SCDR_Msk _U_(0xFF20) /**< (PMC_SCDR) Register Mask */ 171 172 #define PMC_SCDR_PCK_Pos 8 /**< (PMC_SCDR Position) Programmable Clock 7 Output Disable */ 173 #define PMC_SCDR_PCK_Msk (_U_(0xFF) << PMC_SCDR_PCK_Pos) /**< (PMC_SCDR Mask) PCK */ 174 #define PMC_SCDR_PCK(value) (PMC_SCDR_PCK_Msk & ((value) << PMC_SCDR_PCK_Pos)) 175 176 /* -------- PMC_SCSR : (PMC Offset: 0x08) (R/ 32) System Clock Status Register -------- */ 177 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 178 #if COMPONENT_TYPEDEF_STYLE == 'N' 179 typedef union { 180 struct { 181 uint32_t HCLKS:1; /**< bit: 0 HCLK Status */ 182 uint32_t :4; /**< bit: 1..4 Reserved */ 183 uint32_t USBCLK:1; /**< bit: 5 USB FS Clock Status */ 184 uint32_t :2; /**< bit: 6..7 Reserved */ 185 uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Status */ 186 uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Status */ 187 uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Status */ 188 uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Status */ 189 uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Status */ 190 uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Status */ 191 uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Status */ 192 uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Status */ 193 uint32_t :16; /**< bit: 16..31 Reserved */ 194 } bit; /**< Structure used for bit access */ 195 struct { 196 uint32_t :8; /**< bit: 0..7 Reserved */ 197 uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Status */ 198 uint32_t :16; /**< bit: 16..31 Reserved */ 199 } vec; /**< Structure used for vec access */ 200 uint32_t reg; /**< Type used for register access */ 201 } PMC_SCSR_Type; 202 #endif 203 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define PMC_SCSR_OFFSET (0x08) /**< (PMC_SCSR) System Clock Status Register Offset */ 206 207 #define PMC_SCSR_HCLKS_Pos 0 /**< (PMC_SCSR) HCLK Status Position */ 208 #define PMC_SCSR_HCLKS_Msk (_U_(0x1) << PMC_SCSR_HCLKS_Pos) /**< (PMC_SCSR) HCLK Status Mask */ 209 #define PMC_SCSR_HCLKS PMC_SCSR_HCLKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_HCLKS_Msk instead */ 210 #define PMC_SCSR_USBCLK_Pos 5 /**< (PMC_SCSR) USB FS Clock Status Position */ 211 #define PMC_SCSR_USBCLK_Msk (_U_(0x1) << PMC_SCSR_USBCLK_Pos) /**< (PMC_SCSR) USB FS Clock Status Mask */ 212 #define PMC_SCSR_USBCLK PMC_SCSR_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_USBCLK_Msk instead */ 213 #define PMC_SCSR_PCK0_Pos 8 /**< (PMC_SCSR) Programmable Clock 0 Output Status Position */ 214 #define PMC_SCSR_PCK0_Msk (_U_(0x1) << PMC_SCSR_PCK0_Pos) /**< (PMC_SCSR) Programmable Clock 0 Output Status Mask */ 215 #define PMC_SCSR_PCK0 PMC_SCSR_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK0_Msk instead */ 216 #define PMC_SCSR_PCK1_Pos 9 /**< (PMC_SCSR) Programmable Clock 1 Output Status Position */ 217 #define PMC_SCSR_PCK1_Msk (_U_(0x1) << PMC_SCSR_PCK1_Pos) /**< (PMC_SCSR) Programmable Clock 1 Output Status Mask */ 218 #define PMC_SCSR_PCK1 PMC_SCSR_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK1_Msk instead */ 219 #define PMC_SCSR_PCK2_Pos 10 /**< (PMC_SCSR) Programmable Clock 2 Output Status Position */ 220 #define PMC_SCSR_PCK2_Msk (_U_(0x1) << PMC_SCSR_PCK2_Pos) /**< (PMC_SCSR) Programmable Clock 2 Output Status Mask */ 221 #define PMC_SCSR_PCK2 PMC_SCSR_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK2_Msk instead */ 222 #define PMC_SCSR_PCK3_Pos 11 /**< (PMC_SCSR) Programmable Clock 3 Output Status Position */ 223 #define PMC_SCSR_PCK3_Msk (_U_(0x1) << PMC_SCSR_PCK3_Pos) /**< (PMC_SCSR) Programmable Clock 3 Output Status Mask */ 224 #define PMC_SCSR_PCK3 PMC_SCSR_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK3_Msk instead */ 225 #define PMC_SCSR_PCK4_Pos 12 /**< (PMC_SCSR) Programmable Clock 4 Output Status Position */ 226 #define PMC_SCSR_PCK4_Msk (_U_(0x1) << PMC_SCSR_PCK4_Pos) /**< (PMC_SCSR) Programmable Clock 4 Output Status Mask */ 227 #define PMC_SCSR_PCK4 PMC_SCSR_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK4_Msk instead */ 228 #define PMC_SCSR_PCK5_Pos 13 /**< (PMC_SCSR) Programmable Clock 5 Output Status Position */ 229 #define PMC_SCSR_PCK5_Msk (_U_(0x1) << PMC_SCSR_PCK5_Pos) /**< (PMC_SCSR) Programmable Clock 5 Output Status Mask */ 230 #define PMC_SCSR_PCK5 PMC_SCSR_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK5_Msk instead */ 231 #define PMC_SCSR_PCK6_Pos 14 /**< (PMC_SCSR) Programmable Clock 6 Output Status Position */ 232 #define PMC_SCSR_PCK6_Msk (_U_(0x1) << PMC_SCSR_PCK6_Pos) /**< (PMC_SCSR) Programmable Clock 6 Output Status Mask */ 233 #define PMC_SCSR_PCK6 PMC_SCSR_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK6_Msk instead */ 234 #define PMC_SCSR_PCK7_Pos 15 /**< (PMC_SCSR) Programmable Clock 7 Output Status Position */ 235 #define PMC_SCSR_PCK7_Msk (_U_(0x1) << PMC_SCSR_PCK7_Pos) /**< (PMC_SCSR) Programmable Clock 7 Output Status Mask */ 236 #define PMC_SCSR_PCK7 PMC_SCSR_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK7_Msk instead */ 237 #define PMC_SCSR_MASK _U_(0xFF21) /**< \deprecated (PMC_SCSR) Register MASK (Use PMC_SCSR_Msk instead) */ 238 #define PMC_SCSR_Msk _U_(0xFF21) /**< (PMC_SCSR) Register Mask */ 239 240 #define PMC_SCSR_PCK_Pos 8 /**< (PMC_SCSR Position) Programmable Clock 7 Output Status */ 241 #define PMC_SCSR_PCK_Msk (_U_(0xFF) << PMC_SCSR_PCK_Pos) /**< (PMC_SCSR Mask) PCK */ 242 #define PMC_SCSR_PCK(value) (PMC_SCSR_PCK_Msk & ((value) << PMC_SCSR_PCK_Pos)) 243 244 /* -------- PMC_PCER0 : (PMC Offset: 0x10) (/W 32) Peripheral Clock Enable Register 0 -------- */ 245 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 246 #if COMPONENT_TYPEDEF_STYLE == 'N' 247 typedef union { 248 struct { 249 uint32_t :7; /**< bit: 0..6 Reserved */ 250 uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Enable */ 251 uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Enable */ 252 uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Enable */ 253 uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Enable */ 254 uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Enable */ 255 uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Enable */ 256 uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Enable */ 257 uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Enable */ 258 uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Enable */ 259 uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Enable */ 260 uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Enable */ 261 uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Enable */ 262 uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Enable */ 263 uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Enable */ 264 uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Enable */ 265 uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Enable */ 266 uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Enable */ 267 uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Enable */ 268 uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Enable */ 269 uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Enable */ 270 uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Enable */ 271 uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Enable */ 272 uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Enable */ 273 uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Enable */ 274 uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Enable */ 275 } bit; /**< Structure used for bit access */ 276 struct { 277 uint32_t :7; /**< bit: 0..6 Reserved */ 278 uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Enable */ 279 } vec; /**< Structure used for vec access */ 280 uint32_t reg; /**< Type used for register access */ 281 } PMC_PCER0_Type; 282 #endif 283 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 284 285 #define PMC_PCER0_OFFSET (0x10) /**< (PMC_PCER0) Peripheral Clock Enable Register 0 Offset */ 286 287 #define PMC_PCER0_PID7_Pos 7 /**< (PMC_PCER0) Peripheral Clock 7 Enable Position */ 288 #define PMC_PCER0_PID7_Msk (_U_(0x1) << PMC_PCER0_PID7_Pos) /**< (PMC_PCER0) Peripheral Clock 7 Enable Mask */ 289 #define PMC_PCER0_PID7 PMC_PCER0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID7_Msk instead */ 290 #define PMC_PCER0_PID8_Pos 8 /**< (PMC_PCER0) Peripheral Clock 8 Enable Position */ 291 #define PMC_PCER0_PID8_Msk (_U_(0x1) << PMC_PCER0_PID8_Pos) /**< (PMC_PCER0) Peripheral Clock 8 Enable Mask */ 292 #define PMC_PCER0_PID8 PMC_PCER0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID8_Msk instead */ 293 #define PMC_PCER0_PID9_Pos 9 /**< (PMC_PCER0) Peripheral Clock 9 Enable Position */ 294 #define PMC_PCER0_PID9_Msk (_U_(0x1) << PMC_PCER0_PID9_Pos) /**< (PMC_PCER0) Peripheral Clock 9 Enable Mask */ 295 #define PMC_PCER0_PID9 PMC_PCER0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID9_Msk instead */ 296 #define PMC_PCER0_PID10_Pos 10 /**< (PMC_PCER0) Peripheral Clock 10 Enable Position */ 297 #define PMC_PCER0_PID10_Msk (_U_(0x1) << PMC_PCER0_PID10_Pos) /**< (PMC_PCER0) Peripheral Clock 10 Enable Mask */ 298 #define PMC_PCER0_PID10 PMC_PCER0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID10_Msk instead */ 299 #define PMC_PCER0_PID11_Pos 11 /**< (PMC_PCER0) Peripheral Clock 11 Enable Position */ 300 #define PMC_PCER0_PID11_Msk (_U_(0x1) << PMC_PCER0_PID11_Pos) /**< (PMC_PCER0) Peripheral Clock 11 Enable Mask */ 301 #define PMC_PCER0_PID11 PMC_PCER0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID11_Msk instead */ 302 #define PMC_PCER0_PID12_Pos 12 /**< (PMC_PCER0) Peripheral Clock 12 Enable Position */ 303 #define PMC_PCER0_PID12_Msk (_U_(0x1) << PMC_PCER0_PID12_Pos) /**< (PMC_PCER0) Peripheral Clock 12 Enable Mask */ 304 #define PMC_PCER0_PID12 PMC_PCER0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID12_Msk instead */ 305 #define PMC_PCER0_PID13_Pos 13 /**< (PMC_PCER0) Peripheral Clock 13 Enable Position */ 306 #define PMC_PCER0_PID13_Msk (_U_(0x1) << PMC_PCER0_PID13_Pos) /**< (PMC_PCER0) Peripheral Clock 13 Enable Mask */ 307 #define PMC_PCER0_PID13 PMC_PCER0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID13_Msk instead */ 308 #define PMC_PCER0_PID14_Pos 14 /**< (PMC_PCER0) Peripheral Clock 14 Enable Position */ 309 #define PMC_PCER0_PID14_Msk (_U_(0x1) << PMC_PCER0_PID14_Pos) /**< (PMC_PCER0) Peripheral Clock 14 Enable Mask */ 310 #define PMC_PCER0_PID14 PMC_PCER0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID14_Msk instead */ 311 #define PMC_PCER0_PID15_Pos 15 /**< (PMC_PCER0) Peripheral Clock 15 Enable Position */ 312 #define PMC_PCER0_PID15_Msk (_U_(0x1) << PMC_PCER0_PID15_Pos) /**< (PMC_PCER0) Peripheral Clock 15 Enable Mask */ 313 #define PMC_PCER0_PID15 PMC_PCER0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID15_Msk instead */ 314 #define PMC_PCER0_PID16_Pos 16 /**< (PMC_PCER0) Peripheral Clock 16 Enable Position */ 315 #define PMC_PCER0_PID16_Msk (_U_(0x1) << PMC_PCER0_PID16_Pos) /**< (PMC_PCER0) Peripheral Clock 16 Enable Mask */ 316 #define PMC_PCER0_PID16 PMC_PCER0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID16_Msk instead */ 317 #define PMC_PCER0_PID17_Pos 17 /**< (PMC_PCER0) Peripheral Clock 17 Enable Position */ 318 #define PMC_PCER0_PID17_Msk (_U_(0x1) << PMC_PCER0_PID17_Pos) /**< (PMC_PCER0) Peripheral Clock 17 Enable Mask */ 319 #define PMC_PCER0_PID17 PMC_PCER0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID17_Msk instead */ 320 #define PMC_PCER0_PID18_Pos 18 /**< (PMC_PCER0) Peripheral Clock 18 Enable Position */ 321 #define PMC_PCER0_PID18_Msk (_U_(0x1) << PMC_PCER0_PID18_Pos) /**< (PMC_PCER0) Peripheral Clock 18 Enable Mask */ 322 #define PMC_PCER0_PID18 PMC_PCER0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID18_Msk instead */ 323 #define PMC_PCER0_PID19_Pos 19 /**< (PMC_PCER0) Peripheral Clock 19 Enable Position */ 324 #define PMC_PCER0_PID19_Msk (_U_(0x1) << PMC_PCER0_PID19_Pos) /**< (PMC_PCER0) Peripheral Clock 19 Enable Mask */ 325 #define PMC_PCER0_PID19 PMC_PCER0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID19_Msk instead */ 326 #define PMC_PCER0_PID20_Pos 20 /**< (PMC_PCER0) Peripheral Clock 20 Enable Position */ 327 #define PMC_PCER0_PID20_Msk (_U_(0x1) << PMC_PCER0_PID20_Pos) /**< (PMC_PCER0) Peripheral Clock 20 Enable Mask */ 328 #define PMC_PCER0_PID20 PMC_PCER0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID20_Msk instead */ 329 #define PMC_PCER0_PID21_Pos 21 /**< (PMC_PCER0) Peripheral Clock 21 Enable Position */ 330 #define PMC_PCER0_PID21_Msk (_U_(0x1) << PMC_PCER0_PID21_Pos) /**< (PMC_PCER0) Peripheral Clock 21 Enable Mask */ 331 #define PMC_PCER0_PID21 PMC_PCER0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID21_Msk instead */ 332 #define PMC_PCER0_PID22_Pos 22 /**< (PMC_PCER0) Peripheral Clock 22 Enable Position */ 333 #define PMC_PCER0_PID22_Msk (_U_(0x1) << PMC_PCER0_PID22_Pos) /**< (PMC_PCER0) Peripheral Clock 22 Enable Mask */ 334 #define PMC_PCER0_PID22 PMC_PCER0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID22_Msk instead */ 335 #define PMC_PCER0_PID23_Pos 23 /**< (PMC_PCER0) Peripheral Clock 23 Enable Position */ 336 #define PMC_PCER0_PID23_Msk (_U_(0x1) << PMC_PCER0_PID23_Pos) /**< (PMC_PCER0) Peripheral Clock 23 Enable Mask */ 337 #define PMC_PCER0_PID23 PMC_PCER0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID23_Msk instead */ 338 #define PMC_PCER0_PID24_Pos 24 /**< (PMC_PCER0) Peripheral Clock 24 Enable Position */ 339 #define PMC_PCER0_PID24_Msk (_U_(0x1) << PMC_PCER0_PID24_Pos) /**< (PMC_PCER0) Peripheral Clock 24 Enable Mask */ 340 #define PMC_PCER0_PID24 PMC_PCER0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID24_Msk instead */ 341 #define PMC_PCER0_PID25_Pos 25 /**< (PMC_PCER0) Peripheral Clock 25 Enable Position */ 342 #define PMC_PCER0_PID25_Msk (_U_(0x1) << PMC_PCER0_PID25_Pos) /**< (PMC_PCER0) Peripheral Clock 25 Enable Mask */ 343 #define PMC_PCER0_PID25 PMC_PCER0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID25_Msk instead */ 344 #define PMC_PCER0_PID26_Pos 26 /**< (PMC_PCER0) Peripheral Clock 26 Enable Position */ 345 #define PMC_PCER0_PID26_Msk (_U_(0x1) << PMC_PCER0_PID26_Pos) /**< (PMC_PCER0) Peripheral Clock 26 Enable Mask */ 346 #define PMC_PCER0_PID26 PMC_PCER0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID26_Msk instead */ 347 #define PMC_PCER0_PID27_Pos 27 /**< (PMC_PCER0) Peripheral Clock 27 Enable Position */ 348 #define PMC_PCER0_PID27_Msk (_U_(0x1) << PMC_PCER0_PID27_Pos) /**< (PMC_PCER0) Peripheral Clock 27 Enable Mask */ 349 #define PMC_PCER0_PID27 PMC_PCER0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID27_Msk instead */ 350 #define PMC_PCER0_PID28_Pos 28 /**< (PMC_PCER0) Peripheral Clock 28 Enable Position */ 351 #define PMC_PCER0_PID28_Msk (_U_(0x1) << PMC_PCER0_PID28_Pos) /**< (PMC_PCER0) Peripheral Clock 28 Enable Mask */ 352 #define PMC_PCER0_PID28 PMC_PCER0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID28_Msk instead */ 353 #define PMC_PCER0_PID29_Pos 29 /**< (PMC_PCER0) Peripheral Clock 29 Enable Position */ 354 #define PMC_PCER0_PID29_Msk (_U_(0x1) << PMC_PCER0_PID29_Pos) /**< (PMC_PCER0) Peripheral Clock 29 Enable Mask */ 355 #define PMC_PCER0_PID29 PMC_PCER0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID29_Msk instead */ 356 #define PMC_PCER0_PID30_Pos 30 /**< (PMC_PCER0) Peripheral Clock 30 Enable Position */ 357 #define PMC_PCER0_PID30_Msk (_U_(0x1) << PMC_PCER0_PID30_Pos) /**< (PMC_PCER0) Peripheral Clock 30 Enable Mask */ 358 #define PMC_PCER0_PID30 PMC_PCER0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID30_Msk instead */ 359 #define PMC_PCER0_PID31_Pos 31 /**< (PMC_PCER0) Peripheral Clock 31 Enable Position */ 360 #define PMC_PCER0_PID31_Msk (_U_(0x1) << PMC_PCER0_PID31_Pos) /**< (PMC_PCER0) Peripheral Clock 31 Enable Mask */ 361 #define PMC_PCER0_PID31 PMC_PCER0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID31_Msk instead */ 362 #define PMC_PCER0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCER0) Register MASK (Use PMC_PCER0_Msk instead) */ 363 #define PMC_PCER0_Msk _U_(0xFFFFFF80) /**< (PMC_PCER0) Register Mask */ 364 365 #define PMC_PCER0_PID_Pos 7 /**< (PMC_PCER0 Position) Peripheral Clock 3x Enable */ 366 #define PMC_PCER0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER0_PID_Pos) /**< (PMC_PCER0 Mask) PID */ 367 #define PMC_PCER0_PID(value) (PMC_PCER0_PID_Msk & ((value) << PMC_PCER0_PID_Pos)) 368 369 /* -------- PMC_PCDR0 : (PMC Offset: 0x14) (/W 32) Peripheral Clock Disable Register 0 -------- */ 370 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 371 #if COMPONENT_TYPEDEF_STYLE == 'N' 372 typedef union { 373 struct { 374 uint32_t :7; /**< bit: 0..6 Reserved */ 375 uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Disable */ 376 uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Disable */ 377 uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Disable */ 378 uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Disable */ 379 uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Disable */ 380 uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Disable */ 381 uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Disable */ 382 uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Disable */ 383 uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Disable */ 384 uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Disable */ 385 uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Disable */ 386 uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Disable */ 387 uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Disable */ 388 uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Disable */ 389 uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Disable */ 390 uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Disable */ 391 uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Disable */ 392 uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Disable */ 393 uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Disable */ 394 uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Disable */ 395 uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Disable */ 396 uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Disable */ 397 uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Disable */ 398 uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Disable */ 399 uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Disable */ 400 } bit; /**< Structure used for bit access */ 401 struct { 402 uint32_t :7; /**< bit: 0..6 Reserved */ 403 uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Disable */ 404 } vec; /**< Structure used for vec access */ 405 uint32_t reg; /**< Type used for register access */ 406 } PMC_PCDR0_Type; 407 #endif 408 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 409 410 #define PMC_PCDR0_OFFSET (0x14) /**< (PMC_PCDR0) Peripheral Clock Disable Register 0 Offset */ 411 412 #define PMC_PCDR0_PID7_Pos 7 /**< (PMC_PCDR0) Peripheral Clock 7 Disable Position */ 413 #define PMC_PCDR0_PID7_Msk (_U_(0x1) << PMC_PCDR0_PID7_Pos) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Mask */ 414 #define PMC_PCDR0_PID7 PMC_PCDR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID7_Msk instead */ 415 #define PMC_PCDR0_PID8_Pos 8 /**< (PMC_PCDR0) Peripheral Clock 8 Disable Position */ 416 #define PMC_PCDR0_PID8_Msk (_U_(0x1) << PMC_PCDR0_PID8_Pos) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Mask */ 417 #define PMC_PCDR0_PID8 PMC_PCDR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID8_Msk instead */ 418 #define PMC_PCDR0_PID9_Pos 9 /**< (PMC_PCDR0) Peripheral Clock 9 Disable Position */ 419 #define PMC_PCDR0_PID9_Msk (_U_(0x1) << PMC_PCDR0_PID9_Pos) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Mask */ 420 #define PMC_PCDR0_PID9 PMC_PCDR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID9_Msk instead */ 421 #define PMC_PCDR0_PID10_Pos 10 /**< (PMC_PCDR0) Peripheral Clock 10 Disable Position */ 422 #define PMC_PCDR0_PID10_Msk (_U_(0x1) << PMC_PCDR0_PID10_Pos) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Mask */ 423 #define PMC_PCDR0_PID10 PMC_PCDR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID10_Msk instead */ 424 #define PMC_PCDR0_PID11_Pos 11 /**< (PMC_PCDR0) Peripheral Clock 11 Disable Position */ 425 #define PMC_PCDR0_PID11_Msk (_U_(0x1) << PMC_PCDR0_PID11_Pos) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Mask */ 426 #define PMC_PCDR0_PID11 PMC_PCDR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID11_Msk instead */ 427 #define PMC_PCDR0_PID12_Pos 12 /**< (PMC_PCDR0) Peripheral Clock 12 Disable Position */ 428 #define PMC_PCDR0_PID12_Msk (_U_(0x1) << PMC_PCDR0_PID12_Pos) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Mask */ 429 #define PMC_PCDR0_PID12 PMC_PCDR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID12_Msk instead */ 430 #define PMC_PCDR0_PID13_Pos 13 /**< (PMC_PCDR0) Peripheral Clock 13 Disable Position */ 431 #define PMC_PCDR0_PID13_Msk (_U_(0x1) << PMC_PCDR0_PID13_Pos) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Mask */ 432 #define PMC_PCDR0_PID13 PMC_PCDR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID13_Msk instead */ 433 #define PMC_PCDR0_PID14_Pos 14 /**< (PMC_PCDR0) Peripheral Clock 14 Disable Position */ 434 #define PMC_PCDR0_PID14_Msk (_U_(0x1) << PMC_PCDR0_PID14_Pos) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Mask */ 435 #define PMC_PCDR0_PID14 PMC_PCDR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID14_Msk instead */ 436 #define PMC_PCDR0_PID15_Pos 15 /**< (PMC_PCDR0) Peripheral Clock 15 Disable Position */ 437 #define PMC_PCDR0_PID15_Msk (_U_(0x1) << PMC_PCDR0_PID15_Pos) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Mask */ 438 #define PMC_PCDR0_PID15 PMC_PCDR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID15_Msk instead */ 439 #define PMC_PCDR0_PID16_Pos 16 /**< (PMC_PCDR0) Peripheral Clock 16 Disable Position */ 440 #define PMC_PCDR0_PID16_Msk (_U_(0x1) << PMC_PCDR0_PID16_Pos) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Mask */ 441 #define PMC_PCDR0_PID16 PMC_PCDR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID16_Msk instead */ 442 #define PMC_PCDR0_PID17_Pos 17 /**< (PMC_PCDR0) Peripheral Clock 17 Disable Position */ 443 #define PMC_PCDR0_PID17_Msk (_U_(0x1) << PMC_PCDR0_PID17_Pos) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Mask */ 444 #define PMC_PCDR0_PID17 PMC_PCDR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID17_Msk instead */ 445 #define PMC_PCDR0_PID18_Pos 18 /**< (PMC_PCDR0) Peripheral Clock 18 Disable Position */ 446 #define PMC_PCDR0_PID18_Msk (_U_(0x1) << PMC_PCDR0_PID18_Pos) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Mask */ 447 #define PMC_PCDR0_PID18 PMC_PCDR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID18_Msk instead */ 448 #define PMC_PCDR0_PID19_Pos 19 /**< (PMC_PCDR0) Peripheral Clock 19 Disable Position */ 449 #define PMC_PCDR0_PID19_Msk (_U_(0x1) << PMC_PCDR0_PID19_Pos) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Mask */ 450 #define PMC_PCDR0_PID19 PMC_PCDR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID19_Msk instead */ 451 #define PMC_PCDR0_PID20_Pos 20 /**< (PMC_PCDR0) Peripheral Clock 20 Disable Position */ 452 #define PMC_PCDR0_PID20_Msk (_U_(0x1) << PMC_PCDR0_PID20_Pos) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Mask */ 453 #define PMC_PCDR0_PID20 PMC_PCDR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID20_Msk instead */ 454 #define PMC_PCDR0_PID21_Pos 21 /**< (PMC_PCDR0) Peripheral Clock 21 Disable Position */ 455 #define PMC_PCDR0_PID21_Msk (_U_(0x1) << PMC_PCDR0_PID21_Pos) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Mask */ 456 #define PMC_PCDR0_PID21 PMC_PCDR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID21_Msk instead */ 457 #define PMC_PCDR0_PID22_Pos 22 /**< (PMC_PCDR0) Peripheral Clock 22 Disable Position */ 458 #define PMC_PCDR0_PID22_Msk (_U_(0x1) << PMC_PCDR0_PID22_Pos) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Mask */ 459 #define PMC_PCDR0_PID22 PMC_PCDR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID22_Msk instead */ 460 #define PMC_PCDR0_PID23_Pos 23 /**< (PMC_PCDR0) Peripheral Clock 23 Disable Position */ 461 #define PMC_PCDR0_PID23_Msk (_U_(0x1) << PMC_PCDR0_PID23_Pos) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Mask */ 462 #define PMC_PCDR0_PID23 PMC_PCDR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID23_Msk instead */ 463 #define PMC_PCDR0_PID24_Pos 24 /**< (PMC_PCDR0) Peripheral Clock 24 Disable Position */ 464 #define PMC_PCDR0_PID24_Msk (_U_(0x1) << PMC_PCDR0_PID24_Pos) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Mask */ 465 #define PMC_PCDR0_PID24 PMC_PCDR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID24_Msk instead */ 466 #define PMC_PCDR0_PID25_Pos 25 /**< (PMC_PCDR0) Peripheral Clock 25 Disable Position */ 467 #define PMC_PCDR0_PID25_Msk (_U_(0x1) << PMC_PCDR0_PID25_Pos) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Mask */ 468 #define PMC_PCDR0_PID25 PMC_PCDR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID25_Msk instead */ 469 #define PMC_PCDR0_PID26_Pos 26 /**< (PMC_PCDR0) Peripheral Clock 26 Disable Position */ 470 #define PMC_PCDR0_PID26_Msk (_U_(0x1) << PMC_PCDR0_PID26_Pos) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Mask */ 471 #define PMC_PCDR0_PID26 PMC_PCDR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID26_Msk instead */ 472 #define PMC_PCDR0_PID27_Pos 27 /**< (PMC_PCDR0) Peripheral Clock 27 Disable Position */ 473 #define PMC_PCDR0_PID27_Msk (_U_(0x1) << PMC_PCDR0_PID27_Pos) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Mask */ 474 #define PMC_PCDR0_PID27 PMC_PCDR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID27_Msk instead */ 475 #define PMC_PCDR0_PID28_Pos 28 /**< (PMC_PCDR0) Peripheral Clock 28 Disable Position */ 476 #define PMC_PCDR0_PID28_Msk (_U_(0x1) << PMC_PCDR0_PID28_Pos) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Mask */ 477 #define PMC_PCDR0_PID28 PMC_PCDR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID28_Msk instead */ 478 #define PMC_PCDR0_PID29_Pos 29 /**< (PMC_PCDR0) Peripheral Clock 29 Disable Position */ 479 #define PMC_PCDR0_PID29_Msk (_U_(0x1) << PMC_PCDR0_PID29_Pos) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Mask */ 480 #define PMC_PCDR0_PID29 PMC_PCDR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID29_Msk instead */ 481 #define PMC_PCDR0_PID30_Pos 30 /**< (PMC_PCDR0) Peripheral Clock 30 Disable Position */ 482 #define PMC_PCDR0_PID30_Msk (_U_(0x1) << PMC_PCDR0_PID30_Pos) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Mask */ 483 #define PMC_PCDR0_PID30 PMC_PCDR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID30_Msk instead */ 484 #define PMC_PCDR0_PID31_Pos 31 /**< (PMC_PCDR0) Peripheral Clock 31 Disable Position */ 485 #define PMC_PCDR0_PID31_Msk (_U_(0x1) << PMC_PCDR0_PID31_Pos) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Mask */ 486 #define PMC_PCDR0_PID31 PMC_PCDR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID31_Msk instead */ 487 #define PMC_PCDR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCDR0) Register MASK (Use PMC_PCDR0_Msk instead) */ 488 #define PMC_PCDR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCDR0) Register Mask */ 489 490 #define PMC_PCDR0_PID_Pos 7 /**< (PMC_PCDR0 Position) Peripheral Clock 3x Disable */ 491 #define PMC_PCDR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR0_PID_Pos) /**< (PMC_PCDR0 Mask) PID */ 492 #define PMC_PCDR0_PID(value) (PMC_PCDR0_PID_Msk & ((value) << PMC_PCDR0_PID_Pos)) 493 494 /* -------- PMC_PCSR0 : (PMC Offset: 0x18) (R/ 32) Peripheral Clock Status Register 0 -------- */ 495 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 496 #if COMPONENT_TYPEDEF_STYLE == 'N' 497 typedef union { 498 struct { 499 uint32_t :7; /**< bit: 0..6 Reserved */ 500 uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Status */ 501 uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Status */ 502 uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Status */ 503 uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Status */ 504 uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Status */ 505 uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Status */ 506 uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Status */ 507 uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Status */ 508 uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Status */ 509 uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Status */ 510 uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Status */ 511 uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Status */ 512 uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Status */ 513 uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Status */ 514 uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Status */ 515 uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Status */ 516 uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Status */ 517 uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Status */ 518 uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Status */ 519 uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Status */ 520 uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Status */ 521 uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Status */ 522 uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Status */ 523 uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Status */ 524 uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Status */ 525 } bit; /**< Structure used for bit access */ 526 struct { 527 uint32_t :7; /**< bit: 0..6 Reserved */ 528 uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Status */ 529 } vec; /**< Structure used for vec access */ 530 uint32_t reg; /**< Type used for register access */ 531 } PMC_PCSR0_Type; 532 #endif 533 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 534 535 #define PMC_PCSR0_OFFSET (0x18) /**< (PMC_PCSR0) Peripheral Clock Status Register 0 Offset */ 536 537 #define PMC_PCSR0_PID7_Pos 7 /**< (PMC_PCSR0) Peripheral Clock 7 Status Position */ 538 #define PMC_PCSR0_PID7_Msk (_U_(0x1) << PMC_PCSR0_PID7_Pos) /**< (PMC_PCSR0) Peripheral Clock 7 Status Mask */ 539 #define PMC_PCSR0_PID7 PMC_PCSR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID7_Msk instead */ 540 #define PMC_PCSR0_PID8_Pos 8 /**< (PMC_PCSR0) Peripheral Clock 8 Status Position */ 541 #define PMC_PCSR0_PID8_Msk (_U_(0x1) << PMC_PCSR0_PID8_Pos) /**< (PMC_PCSR0) Peripheral Clock 8 Status Mask */ 542 #define PMC_PCSR0_PID8 PMC_PCSR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID8_Msk instead */ 543 #define PMC_PCSR0_PID9_Pos 9 /**< (PMC_PCSR0) Peripheral Clock 9 Status Position */ 544 #define PMC_PCSR0_PID9_Msk (_U_(0x1) << PMC_PCSR0_PID9_Pos) /**< (PMC_PCSR0) Peripheral Clock 9 Status Mask */ 545 #define PMC_PCSR0_PID9 PMC_PCSR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID9_Msk instead */ 546 #define PMC_PCSR0_PID10_Pos 10 /**< (PMC_PCSR0) Peripheral Clock 10 Status Position */ 547 #define PMC_PCSR0_PID10_Msk (_U_(0x1) << PMC_PCSR0_PID10_Pos) /**< (PMC_PCSR0) Peripheral Clock 10 Status Mask */ 548 #define PMC_PCSR0_PID10 PMC_PCSR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID10_Msk instead */ 549 #define PMC_PCSR0_PID11_Pos 11 /**< (PMC_PCSR0) Peripheral Clock 11 Status Position */ 550 #define PMC_PCSR0_PID11_Msk (_U_(0x1) << PMC_PCSR0_PID11_Pos) /**< (PMC_PCSR0) Peripheral Clock 11 Status Mask */ 551 #define PMC_PCSR0_PID11 PMC_PCSR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID11_Msk instead */ 552 #define PMC_PCSR0_PID12_Pos 12 /**< (PMC_PCSR0) Peripheral Clock 12 Status Position */ 553 #define PMC_PCSR0_PID12_Msk (_U_(0x1) << PMC_PCSR0_PID12_Pos) /**< (PMC_PCSR0) Peripheral Clock 12 Status Mask */ 554 #define PMC_PCSR0_PID12 PMC_PCSR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID12_Msk instead */ 555 #define PMC_PCSR0_PID13_Pos 13 /**< (PMC_PCSR0) Peripheral Clock 13 Status Position */ 556 #define PMC_PCSR0_PID13_Msk (_U_(0x1) << PMC_PCSR0_PID13_Pos) /**< (PMC_PCSR0) Peripheral Clock 13 Status Mask */ 557 #define PMC_PCSR0_PID13 PMC_PCSR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID13_Msk instead */ 558 #define PMC_PCSR0_PID14_Pos 14 /**< (PMC_PCSR0) Peripheral Clock 14 Status Position */ 559 #define PMC_PCSR0_PID14_Msk (_U_(0x1) << PMC_PCSR0_PID14_Pos) /**< (PMC_PCSR0) Peripheral Clock 14 Status Mask */ 560 #define PMC_PCSR0_PID14 PMC_PCSR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID14_Msk instead */ 561 #define PMC_PCSR0_PID15_Pos 15 /**< (PMC_PCSR0) Peripheral Clock 15 Status Position */ 562 #define PMC_PCSR0_PID15_Msk (_U_(0x1) << PMC_PCSR0_PID15_Pos) /**< (PMC_PCSR0) Peripheral Clock 15 Status Mask */ 563 #define PMC_PCSR0_PID15 PMC_PCSR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID15_Msk instead */ 564 #define PMC_PCSR0_PID16_Pos 16 /**< (PMC_PCSR0) Peripheral Clock 16 Status Position */ 565 #define PMC_PCSR0_PID16_Msk (_U_(0x1) << PMC_PCSR0_PID16_Pos) /**< (PMC_PCSR0) Peripheral Clock 16 Status Mask */ 566 #define PMC_PCSR0_PID16 PMC_PCSR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID16_Msk instead */ 567 #define PMC_PCSR0_PID17_Pos 17 /**< (PMC_PCSR0) Peripheral Clock 17 Status Position */ 568 #define PMC_PCSR0_PID17_Msk (_U_(0x1) << PMC_PCSR0_PID17_Pos) /**< (PMC_PCSR0) Peripheral Clock 17 Status Mask */ 569 #define PMC_PCSR0_PID17 PMC_PCSR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID17_Msk instead */ 570 #define PMC_PCSR0_PID18_Pos 18 /**< (PMC_PCSR0) Peripheral Clock 18 Status Position */ 571 #define PMC_PCSR0_PID18_Msk (_U_(0x1) << PMC_PCSR0_PID18_Pos) /**< (PMC_PCSR0) Peripheral Clock 18 Status Mask */ 572 #define PMC_PCSR0_PID18 PMC_PCSR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID18_Msk instead */ 573 #define PMC_PCSR0_PID19_Pos 19 /**< (PMC_PCSR0) Peripheral Clock 19 Status Position */ 574 #define PMC_PCSR0_PID19_Msk (_U_(0x1) << PMC_PCSR0_PID19_Pos) /**< (PMC_PCSR0) Peripheral Clock 19 Status Mask */ 575 #define PMC_PCSR0_PID19 PMC_PCSR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID19_Msk instead */ 576 #define PMC_PCSR0_PID20_Pos 20 /**< (PMC_PCSR0) Peripheral Clock 20 Status Position */ 577 #define PMC_PCSR0_PID20_Msk (_U_(0x1) << PMC_PCSR0_PID20_Pos) /**< (PMC_PCSR0) Peripheral Clock 20 Status Mask */ 578 #define PMC_PCSR0_PID20 PMC_PCSR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID20_Msk instead */ 579 #define PMC_PCSR0_PID21_Pos 21 /**< (PMC_PCSR0) Peripheral Clock 21 Status Position */ 580 #define PMC_PCSR0_PID21_Msk (_U_(0x1) << PMC_PCSR0_PID21_Pos) /**< (PMC_PCSR0) Peripheral Clock 21 Status Mask */ 581 #define PMC_PCSR0_PID21 PMC_PCSR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID21_Msk instead */ 582 #define PMC_PCSR0_PID22_Pos 22 /**< (PMC_PCSR0) Peripheral Clock 22 Status Position */ 583 #define PMC_PCSR0_PID22_Msk (_U_(0x1) << PMC_PCSR0_PID22_Pos) /**< (PMC_PCSR0) Peripheral Clock 22 Status Mask */ 584 #define PMC_PCSR0_PID22 PMC_PCSR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID22_Msk instead */ 585 #define PMC_PCSR0_PID23_Pos 23 /**< (PMC_PCSR0) Peripheral Clock 23 Status Position */ 586 #define PMC_PCSR0_PID23_Msk (_U_(0x1) << PMC_PCSR0_PID23_Pos) /**< (PMC_PCSR0) Peripheral Clock 23 Status Mask */ 587 #define PMC_PCSR0_PID23 PMC_PCSR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID23_Msk instead */ 588 #define PMC_PCSR0_PID24_Pos 24 /**< (PMC_PCSR0) Peripheral Clock 24 Status Position */ 589 #define PMC_PCSR0_PID24_Msk (_U_(0x1) << PMC_PCSR0_PID24_Pos) /**< (PMC_PCSR0) Peripheral Clock 24 Status Mask */ 590 #define PMC_PCSR0_PID24 PMC_PCSR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID24_Msk instead */ 591 #define PMC_PCSR0_PID25_Pos 25 /**< (PMC_PCSR0) Peripheral Clock 25 Status Position */ 592 #define PMC_PCSR0_PID25_Msk (_U_(0x1) << PMC_PCSR0_PID25_Pos) /**< (PMC_PCSR0) Peripheral Clock 25 Status Mask */ 593 #define PMC_PCSR0_PID25 PMC_PCSR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID25_Msk instead */ 594 #define PMC_PCSR0_PID26_Pos 26 /**< (PMC_PCSR0) Peripheral Clock 26 Status Position */ 595 #define PMC_PCSR0_PID26_Msk (_U_(0x1) << PMC_PCSR0_PID26_Pos) /**< (PMC_PCSR0) Peripheral Clock 26 Status Mask */ 596 #define PMC_PCSR0_PID26 PMC_PCSR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID26_Msk instead */ 597 #define PMC_PCSR0_PID27_Pos 27 /**< (PMC_PCSR0) Peripheral Clock 27 Status Position */ 598 #define PMC_PCSR0_PID27_Msk (_U_(0x1) << PMC_PCSR0_PID27_Pos) /**< (PMC_PCSR0) Peripheral Clock 27 Status Mask */ 599 #define PMC_PCSR0_PID27 PMC_PCSR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID27_Msk instead */ 600 #define PMC_PCSR0_PID28_Pos 28 /**< (PMC_PCSR0) Peripheral Clock 28 Status Position */ 601 #define PMC_PCSR0_PID28_Msk (_U_(0x1) << PMC_PCSR0_PID28_Pos) /**< (PMC_PCSR0) Peripheral Clock 28 Status Mask */ 602 #define PMC_PCSR0_PID28 PMC_PCSR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID28_Msk instead */ 603 #define PMC_PCSR0_PID29_Pos 29 /**< (PMC_PCSR0) Peripheral Clock 29 Status Position */ 604 #define PMC_PCSR0_PID29_Msk (_U_(0x1) << PMC_PCSR0_PID29_Pos) /**< (PMC_PCSR0) Peripheral Clock 29 Status Mask */ 605 #define PMC_PCSR0_PID29 PMC_PCSR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID29_Msk instead */ 606 #define PMC_PCSR0_PID30_Pos 30 /**< (PMC_PCSR0) Peripheral Clock 30 Status Position */ 607 #define PMC_PCSR0_PID30_Msk (_U_(0x1) << PMC_PCSR0_PID30_Pos) /**< (PMC_PCSR0) Peripheral Clock 30 Status Mask */ 608 #define PMC_PCSR0_PID30 PMC_PCSR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID30_Msk instead */ 609 #define PMC_PCSR0_PID31_Pos 31 /**< (PMC_PCSR0) Peripheral Clock 31 Status Position */ 610 #define PMC_PCSR0_PID31_Msk (_U_(0x1) << PMC_PCSR0_PID31_Pos) /**< (PMC_PCSR0) Peripheral Clock 31 Status Mask */ 611 #define PMC_PCSR0_PID31 PMC_PCSR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID31_Msk instead */ 612 #define PMC_PCSR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCSR0) Register MASK (Use PMC_PCSR0_Msk instead) */ 613 #define PMC_PCSR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCSR0) Register Mask */ 614 615 #define PMC_PCSR0_PID_Pos 7 /**< (PMC_PCSR0 Position) Peripheral Clock 3x Status */ 616 #define PMC_PCSR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR0_PID_Pos) /**< (PMC_PCSR0 Mask) PID */ 617 #define PMC_PCSR0_PID(value) (PMC_PCSR0_PID_Msk & ((value) << PMC_PCSR0_PID_Pos)) 618 619 /* -------- CKGR_UCKR : (PMC Offset: 0x1c) (R/W 32) UTMI Clock Register -------- */ 620 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 621 #if COMPONENT_TYPEDEF_STYLE == 'N' 622 typedef union { 623 struct { 624 uint32_t :16; /**< bit: 0..15 Reserved */ 625 uint32_t UPLLEN:1; /**< bit: 16 UTMI PLL Enable */ 626 uint32_t :3; /**< bit: 17..19 Reserved */ 627 uint32_t UPLLCOUNT:4; /**< bit: 20..23 UTMI PLL Start-up Time */ 628 uint32_t :8; /**< bit: 24..31 Reserved */ 629 } bit; /**< Structure used for bit access */ 630 uint32_t reg; /**< Type used for register access */ 631 } CKGR_UCKR_Type; 632 #endif 633 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 634 635 #define CKGR_UCKR_OFFSET (0x1C) /**< (CKGR_UCKR) UTMI Clock Register Offset */ 636 637 #define CKGR_UCKR_UPLLEN_Pos 16 /**< (CKGR_UCKR) UTMI PLL Enable Position */ 638 #define CKGR_UCKR_UPLLEN_Msk (_U_(0x1) << CKGR_UCKR_UPLLEN_Pos) /**< (CKGR_UCKR) UTMI PLL Enable Mask */ 639 #define CKGR_UCKR_UPLLEN CKGR_UCKR_UPLLEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_UCKR_UPLLEN_Msk instead */ 640 #define CKGR_UCKR_UPLLCOUNT_Pos 20 /**< (CKGR_UCKR) UTMI PLL Start-up Time Position */ 641 #define CKGR_UCKR_UPLLCOUNT_Msk (_U_(0xF) << CKGR_UCKR_UPLLCOUNT_Pos) /**< (CKGR_UCKR) UTMI PLL Start-up Time Mask */ 642 #define CKGR_UCKR_UPLLCOUNT(value) (CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)) 643 #define CKGR_UCKR_MASK _U_(0xF10000) /**< \deprecated (CKGR_UCKR) Register MASK (Use CKGR_UCKR_Msk instead) */ 644 #define CKGR_UCKR_Msk _U_(0xF10000) /**< (CKGR_UCKR) Register Mask */ 645 646 647 /* -------- CKGR_MOR : (PMC Offset: 0x20) (R/W 32) Main Oscillator Register -------- */ 648 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 649 #if COMPONENT_TYPEDEF_STYLE == 'N' 650 typedef union { 651 struct { 652 uint32_t MOSCXTEN:1; /**< bit: 0 Main Crystal Oscillator Enable */ 653 uint32_t MOSCXTBY:1; /**< bit: 1 Main Crystal Oscillator Bypass */ 654 uint32_t WAITMODE:1; /**< bit: 2 Wait Mode Command (Write-only) */ 655 uint32_t MOSCRCEN:1; /**< bit: 3 Main RC Oscillator Enable */ 656 uint32_t MOSCRCF:3; /**< bit: 4..6 Main RC Oscillator Frequency Selection */ 657 uint32_t :1; /**< bit: 7 Reserved */ 658 uint32_t MOSCXTST:8; /**< bit: 8..15 Main Crystal Oscillator Startup Time */ 659 uint32_t KEY:8; /**< bit: 16..23 Write Access Password */ 660 uint32_t MOSCSEL:1; /**< bit: 24 Main Clock Oscillator Selection */ 661 uint32_t CFDEN:1; /**< bit: 25 Clock Failure Detector Enable */ 662 uint32_t XT32KFME:1; /**< bit: 26 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ 663 uint32_t :5; /**< bit: 27..31 Reserved */ 664 } bit; /**< Structure used for bit access */ 665 uint32_t reg; /**< Type used for register access */ 666 } CKGR_MOR_Type; 667 #endif 668 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 669 670 #define CKGR_MOR_OFFSET (0x20) /**< (CKGR_MOR) Main Oscillator Register Offset */ 671 672 #define CKGR_MOR_MOSCXTEN_Pos 0 /**< (CKGR_MOR) Main Crystal Oscillator Enable Position */ 673 #define CKGR_MOR_MOSCXTEN_Msk (_U_(0x1) << CKGR_MOR_MOSCXTEN_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Enable Mask */ 674 #define CKGR_MOR_MOSCXTEN CKGR_MOR_MOSCXTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCXTEN_Msk instead */ 675 #define CKGR_MOR_MOSCXTBY_Pos 1 /**< (CKGR_MOR) Main Crystal Oscillator Bypass Position */ 676 #define CKGR_MOR_MOSCXTBY_Msk (_U_(0x1) << CKGR_MOR_MOSCXTBY_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Mask */ 677 #define CKGR_MOR_MOSCXTBY CKGR_MOR_MOSCXTBY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCXTBY_Msk instead */ 678 #define CKGR_MOR_WAITMODE_Pos 2 /**< (CKGR_MOR) Wait Mode Command (Write-only) Position */ 679 #define CKGR_MOR_WAITMODE_Msk (_U_(0x1) << CKGR_MOR_WAITMODE_Pos) /**< (CKGR_MOR) Wait Mode Command (Write-only) Mask */ 680 #define CKGR_MOR_WAITMODE CKGR_MOR_WAITMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_WAITMODE_Msk instead */ 681 #define CKGR_MOR_MOSCRCEN_Pos 3 /**< (CKGR_MOR) Main RC Oscillator Enable Position */ 682 #define CKGR_MOR_MOSCRCEN_Msk (_U_(0x1) << CKGR_MOR_MOSCRCEN_Pos) /**< (CKGR_MOR) Main RC Oscillator Enable Mask */ 683 #define CKGR_MOR_MOSCRCEN CKGR_MOR_MOSCRCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCRCEN_Msk instead */ 684 #define CKGR_MOR_MOSCRCF_Pos 4 /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Position */ 685 #define CKGR_MOR_MOSCRCF_Msk (_U_(0x7) << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Mask */ 686 #define CKGR_MOR_MOSCRCF(value) (CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)) 687 #define CKGR_MOR_MOSCRCF_4_MHz_Val _U_(0x0) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz */ 688 #define CKGR_MOR_MOSCRCF_8_MHz_Val _U_(0x1) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ 689 #define CKGR_MOR_MOSCRCF_12_MHz_Val _U_(0x2) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ 690 #define CKGR_MOR_MOSCRCF_4_MHz (CKGR_MOR_MOSCRCF_4_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz Position */ 691 #define CKGR_MOR_MOSCRCF_8_MHz (CKGR_MOR_MOSCRCF_8_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz Position */ 692 #define CKGR_MOR_MOSCRCF_12_MHz (CKGR_MOR_MOSCRCF_12_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz Position */ 693 #define CKGR_MOR_MOSCXTST_Pos 8 /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Position */ 694 #define CKGR_MOR_MOSCXTST_Msk (_U_(0xFF) << CKGR_MOR_MOSCXTST_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Mask */ 695 #define CKGR_MOR_MOSCXTST(value) (CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)) 696 #define CKGR_MOR_KEY_Pos 16 /**< (CKGR_MOR) Write Access Password Position */ 697 #define CKGR_MOR_KEY_Msk (_U_(0xFF) << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Write Access Password Mask */ 698 #define CKGR_MOR_KEY(value) (CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)) 699 #define CKGR_MOR_KEY_PASSWD_Val _U_(0x37) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 700 #define CKGR_MOR_KEY_PASSWD (CKGR_MOR_KEY_PASSWD_Val << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ 701 #define CKGR_MOR_MOSCSEL_Pos 24 /**< (CKGR_MOR) Main Clock Oscillator Selection Position */ 702 #define CKGR_MOR_MOSCSEL_Msk (_U_(0x1) << CKGR_MOR_MOSCSEL_Pos) /**< (CKGR_MOR) Main Clock Oscillator Selection Mask */ 703 #define CKGR_MOR_MOSCSEL CKGR_MOR_MOSCSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCSEL_Msk instead */ 704 #define CKGR_MOR_CFDEN_Pos 25 /**< (CKGR_MOR) Clock Failure Detector Enable Position */ 705 #define CKGR_MOR_CFDEN_Msk (_U_(0x1) << CKGR_MOR_CFDEN_Pos) /**< (CKGR_MOR) Clock Failure Detector Enable Mask */ 706 #define CKGR_MOR_CFDEN CKGR_MOR_CFDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_CFDEN_Msk instead */ 707 #define CKGR_MOR_XT32KFME_Pos 26 /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Position */ 708 #define CKGR_MOR_XT32KFME_Msk (_U_(0x1) << CKGR_MOR_XT32KFME_Pos) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Mask */ 709 #define CKGR_MOR_XT32KFME CKGR_MOR_XT32KFME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_XT32KFME_Msk instead */ 710 #define CKGR_MOR_MASK _U_(0x7FFFF7F) /**< \deprecated (CKGR_MOR) Register MASK (Use CKGR_MOR_Msk instead) */ 711 #define CKGR_MOR_Msk _U_(0x7FFFF7F) /**< (CKGR_MOR) Register Mask */ 712 713 714 /* -------- CKGR_MCFR : (PMC Offset: 0x24) (R/W 32) Main Clock Frequency Register -------- */ 715 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 716 #if COMPONENT_TYPEDEF_STYLE == 'N' 717 typedef union { 718 struct { 719 uint32_t MAINF:16; /**< bit: 0..15 Main Clock Frequency */ 720 uint32_t MAINFRDY:1; /**< bit: 16 Main Clock Frequency Measure Ready */ 721 uint32_t :3; /**< bit: 17..19 Reserved */ 722 uint32_t RCMEAS:1; /**< bit: 20 RC Oscillator Frequency Measure (write-only) */ 723 uint32_t :3; /**< bit: 21..23 Reserved */ 724 uint32_t CCSS:1; /**< bit: 24 Counter Clock Source Selection */ 725 uint32_t :7; /**< bit: 25..31 Reserved */ 726 } bit; /**< Structure used for bit access */ 727 uint32_t reg; /**< Type used for register access */ 728 } CKGR_MCFR_Type; 729 #endif 730 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 731 732 #define CKGR_MCFR_OFFSET (0x24) /**< (CKGR_MCFR) Main Clock Frequency Register Offset */ 733 734 #define CKGR_MCFR_MAINF_Pos 0 /**< (CKGR_MCFR) Main Clock Frequency Position */ 735 #define CKGR_MCFR_MAINF_Msk (_U_(0xFFFF) << CKGR_MCFR_MAINF_Pos) /**< (CKGR_MCFR) Main Clock Frequency Mask */ 736 #define CKGR_MCFR_MAINF(value) (CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)) 737 #define CKGR_MCFR_MAINFRDY_Pos 16 /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Position */ 738 #define CKGR_MCFR_MAINFRDY_Msk (_U_(0x1) << CKGR_MCFR_MAINFRDY_Pos) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Mask */ 739 #define CKGR_MCFR_MAINFRDY CKGR_MCFR_MAINFRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_MAINFRDY_Msk instead */ 740 #define CKGR_MCFR_RCMEAS_Pos 20 /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Position */ 741 #define CKGR_MCFR_RCMEAS_Msk (_U_(0x1) << CKGR_MCFR_RCMEAS_Pos) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Mask */ 742 #define CKGR_MCFR_RCMEAS CKGR_MCFR_RCMEAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_RCMEAS_Msk instead */ 743 #define CKGR_MCFR_CCSS_Pos 24 /**< (CKGR_MCFR) Counter Clock Source Selection Position */ 744 #define CKGR_MCFR_CCSS_Msk (_U_(0x1) << CKGR_MCFR_CCSS_Pos) /**< (CKGR_MCFR) Counter Clock Source Selection Mask */ 745 #define CKGR_MCFR_CCSS CKGR_MCFR_CCSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_CCSS_Msk instead */ 746 #define CKGR_MCFR_MASK _U_(0x111FFFF) /**< \deprecated (CKGR_MCFR) Register MASK (Use CKGR_MCFR_Msk instead) */ 747 #define CKGR_MCFR_Msk _U_(0x111FFFF) /**< (CKGR_MCFR) Register Mask */ 748 749 750 /* -------- CKGR_PLLAR : (PMC Offset: 0x28) (R/W 32) PLLA Register -------- */ 751 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 752 #if COMPONENT_TYPEDEF_STYLE == 'N' 753 typedef union { 754 struct { 755 uint32_t DIVA:8; /**< bit: 0..7 PLLA Front End Divider */ 756 uint32_t PLLACOUNT:6; /**< bit: 8..13 PLLA Counter */ 757 uint32_t :2; /**< bit: 14..15 Reserved */ 758 uint32_t MULA:11; /**< bit: 16..26 PLLA Multiplier */ 759 uint32_t :2; /**< bit: 27..28 Reserved */ 760 uint32_t ONE:1; /**< bit: 29 Must Be Set to 1 */ 761 uint32_t :2; /**< bit: 30..31 Reserved */ 762 } bit; /**< Structure used for bit access */ 763 uint32_t reg; /**< Type used for register access */ 764 } CKGR_PLLAR_Type; 765 #endif 766 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 767 768 #define CKGR_PLLAR_OFFSET (0x28) /**< (CKGR_PLLAR) PLLA Register Offset */ 769 770 #define CKGR_PLLAR_DIVA_Pos 0 /**< (CKGR_PLLAR) PLLA Front End Divider Position */ 771 #define CKGR_PLLAR_DIVA_Msk (_U_(0xFF) << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) PLLA Front End Divider Mask */ 772 #define CKGR_PLLAR_DIVA(value) (CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)) 773 #define CKGR_PLLAR_DIVA_0_Val _U_(0x0) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ 774 #define CKGR_PLLAR_DIVA_BYPASS_Val _U_(0x1) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ 775 #define CKGR_PLLAR_DIVA_0 (CKGR_PLLAR_DIVA_0_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. Position */ 776 #define CKGR_PLLAR_DIVA_BYPASS (CKGR_PLLAR_DIVA_BYPASS_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. Position */ 777 #define CKGR_PLLAR_PLLACOUNT_Pos 8 /**< (CKGR_PLLAR) PLLA Counter Position */ 778 #define CKGR_PLLAR_PLLACOUNT_Msk (_U_(0x3F) << CKGR_PLLAR_PLLACOUNT_Pos) /**< (CKGR_PLLAR) PLLA Counter Mask */ 779 #define CKGR_PLLAR_PLLACOUNT(value) (CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)) 780 #define CKGR_PLLAR_MULA_Pos 16 /**< (CKGR_PLLAR) PLLA Multiplier Position */ 781 #define CKGR_PLLAR_MULA_Msk (_U_(0x7FF) << CKGR_PLLAR_MULA_Pos) /**< (CKGR_PLLAR) PLLA Multiplier Mask */ 782 #define CKGR_PLLAR_MULA(value) (CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)) 783 #define CKGR_PLLAR_ONE_Pos 29 /**< (CKGR_PLLAR) Must Be Set to 1 Position */ 784 #define CKGR_PLLAR_ONE_Msk (_U_(0x1) << CKGR_PLLAR_ONE_Pos) /**< (CKGR_PLLAR) Must Be Set to 1 Mask */ 785 #define CKGR_PLLAR_ONE CKGR_PLLAR_ONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_PLLAR_ONE_Msk instead */ 786 #define CKGR_PLLAR_MASK _U_(0x27FF3FFF) /**< \deprecated (CKGR_PLLAR) Register MASK (Use CKGR_PLLAR_Msk instead) */ 787 #define CKGR_PLLAR_Msk _U_(0x27FF3FFF) /**< (CKGR_PLLAR) Register Mask */ 788 789 790 /* -------- PMC_MCKR : (PMC Offset: 0x30) (R/W 32) Master Clock Register -------- */ 791 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 792 #if COMPONENT_TYPEDEF_STYLE == 'N' 793 typedef union { 794 struct { 795 uint32_t CSS:2; /**< bit: 0..1 Master Clock Source Selection */ 796 uint32_t :2; /**< bit: 2..3 Reserved */ 797 uint32_t PRES:3; /**< bit: 4..6 Processor Clock Prescaler */ 798 uint32_t :1; /**< bit: 7 Reserved */ 799 uint32_t MDIV:2; /**< bit: 8..9 Master Clock Division */ 800 uint32_t :3; /**< bit: 10..12 Reserved */ 801 uint32_t UPLLDIV2:1; /**< bit: 13 UPLL Divider by 2 */ 802 uint32_t :18; /**< bit: 14..31 Reserved */ 803 } bit; /**< Structure used for bit access */ 804 struct { 805 uint32_t :13; /**< bit: 0..12 Reserved */ 806 uint32_t UPLLDIV:1; /**< bit: 13 UPLL Divider by 2 */ 807 uint32_t :18; /**< bit: 14..31 Reserved */ 808 } vec; /**< Structure used for vec access */ 809 uint32_t reg; /**< Type used for register access */ 810 } PMC_MCKR_Type; 811 #endif 812 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 813 814 #define PMC_MCKR_OFFSET (0x30) /**< (PMC_MCKR) Master Clock Register Offset */ 815 816 #define PMC_MCKR_CSS_Pos 0 /**< (PMC_MCKR) Master Clock Source Selection Position */ 817 #define PMC_MCKR_CSS_Msk (_U_(0x3) << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Master Clock Source Selection Mask */ 818 #define PMC_MCKR_CSS(value) (PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)) 819 #define PMC_MCKR_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_MCKR) Slow Clock is selected */ 820 #define PMC_MCKR_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_MCKR) Main Clock is selected */ 821 #define PMC_MCKR_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_MCKR) PLLA Clock is selected */ 822 #define PMC_MCKR_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_MCKR) Divided UPLL Clock is selected */ 823 #define PMC_MCKR_CSS_SLOW_CLK (PMC_MCKR_CSS_SLOW_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Slow Clock is selected Position */ 824 #define PMC_MCKR_CSS_MAIN_CLK (PMC_MCKR_CSS_MAIN_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Main Clock is selected Position */ 825 #define PMC_MCKR_CSS_PLLA_CLK (PMC_MCKR_CSS_PLLA_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) PLLA Clock is selected Position */ 826 #define PMC_MCKR_CSS_UPLL_CLK (PMC_MCKR_CSS_UPLL_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Divided UPLL Clock is selected Position */ 827 #define PMC_MCKR_PRES_Pos 4 /**< (PMC_MCKR) Processor Clock Prescaler Position */ 828 #define PMC_MCKR_PRES_Msk (_U_(0x7) << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Processor Clock Prescaler Mask */ 829 #define PMC_MCKR_PRES(value) (PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)) 830 #define PMC_MCKR_PRES_CLK_1_Val _U_(0x0) /**< (PMC_MCKR) Selected clock */ 831 #define PMC_MCKR_PRES_CLK_2_Val _U_(0x1) /**< (PMC_MCKR) Selected clock divided by 2 */ 832 #define PMC_MCKR_PRES_CLK_4_Val _U_(0x2) /**< (PMC_MCKR) Selected clock divided by 4 */ 833 #define PMC_MCKR_PRES_CLK_8_Val _U_(0x3) /**< (PMC_MCKR) Selected clock divided by 8 */ 834 #define PMC_MCKR_PRES_CLK_16_Val _U_(0x4) /**< (PMC_MCKR) Selected clock divided by 16 */ 835 #define PMC_MCKR_PRES_CLK_32_Val _U_(0x5) /**< (PMC_MCKR) Selected clock divided by 32 */ 836 #define PMC_MCKR_PRES_CLK_64_Val _U_(0x6) /**< (PMC_MCKR) Selected clock divided by 64 */ 837 #define PMC_MCKR_PRES_CLK_3_Val _U_(0x7) /**< (PMC_MCKR) Selected clock divided by 3 */ 838 #define PMC_MCKR_PRES_CLK_1 (PMC_MCKR_PRES_CLK_1_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock Position */ 839 #define PMC_MCKR_PRES_CLK_2 (PMC_MCKR_PRES_CLK_2_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 2 Position */ 840 #define PMC_MCKR_PRES_CLK_4 (PMC_MCKR_PRES_CLK_4_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 4 Position */ 841 #define PMC_MCKR_PRES_CLK_8 (PMC_MCKR_PRES_CLK_8_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 8 Position */ 842 #define PMC_MCKR_PRES_CLK_16 (PMC_MCKR_PRES_CLK_16_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 16 Position */ 843 #define PMC_MCKR_PRES_CLK_32 (PMC_MCKR_PRES_CLK_32_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 32 Position */ 844 #define PMC_MCKR_PRES_CLK_64 (PMC_MCKR_PRES_CLK_64_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 64 Position */ 845 #define PMC_MCKR_PRES_CLK_3 (PMC_MCKR_PRES_CLK_3_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 3 Position */ 846 #define PMC_MCKR_MDIV_Pos 8 /**< (PMC_MCKR) Master Clock Division Position */ 847 #define PMC_MCKR_MDIV_Msk (_U_(0x3) << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock Division Mask */ 848 #define PMC_MCKR_MDIV(value) (PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)) 849 #define PMC_MCKR_MDIV_EQ_PCK_Val _U_(0x0) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ 850 #define PMC_MCKR_MDIV_PCK_DIV2_Val _U_(0x1) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ 851 #define PMC_MCKR_MDIV_PCK_DIV4_Val _U_(0x2) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ 852 #define PMC_MCKR_MDIV_PCK_DIV3_Val _U_(0x3) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ 853 #define PMC_MCKR_MDIV_EQ_PCK (PMC_MCKR_MDIV_EQ_PCK_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. Position */ 854 #define PMC_MCKR_MDIV_PCK_DIV2 (PMC_MCKR_MDIV_PCK_DIV2_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. Position */ 855 #define PMC_MCKR_MDIV_PCK_DIV4 (PMC_MCKR_MDIV_PCK_DIV4_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. Position */ 856 #define PMC_MCKR_MDIV_PCK_DIV3 (PMC_MCKR_MDIV_PCK_DIV3_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. Position */ 857 #define PMC_MCKR_UPLLDIV2_Pos 13 /**< (PMC_MCKR) UPLL Divider by 2 Position */ 858 #define PMC_MCKR_UPLLDIV2_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV2_Pos) /**< (PMC_MCKR) UPLL Divider by 2 Mask */ 859 #define PMC_MCKR_UPLLDIV2 PMC_MCKR_UPLLDIV2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_MCKR_UPLLDIV2_Msk instead */ 860 #define PMC_MCKR_MASK _U_(0x2373) /**< \deprecated (PMC_MCKR) Register MASK (Use PMC_MCKR_Msk instead) */ 861 #define PMC_MCKR_Msk _U_(0x2373) /**< (PMC_MCKR) Register Mask */ 862 863 #define PMC_MCKR_UPLLDIV_Pos 13 /**< (PMC_MCKR Position) UPLL Divider by 2 */ 864 #define PMC_MCKR_UPLLDIV_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV_Pos) /**< (PMC_MCKR Mask) UPLLDIV */ 865 #define PMC_MCKR_UPLLDIV(value) (PMC_MCKR_UPLLDIV_Msk & ((value) << PMC_MCKR_UPLLDIV_Pos)) 866 867 /* -------- PMC_USB : (PMC Offset: 0x38) (R/W 32) USB Clock Register -------- */ 868 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 869 #if COMPONENT_TYPEDEF_STYLE == 'N' 870 typedef union { 871 struct { 872 uint32_t USBS:1; /**< bit: 0 USB Input Clock Selection */ 873 uint32_t :7; /**< bit: 1..7 Reserved */ 874 uint32_t USBDIV:4; /**< bit: 8..11 Divider for USB_48M */ 875 uint32_t :20; /**< bit: 12..31 Reserved */ 876 } bit; /**< Structure used for bit access */ 877 uint32_t reg; /**< Type used for register access */ 878 } PMC_USB_Type; 879 #endif 880 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 881 882 #define PMC_USB_OFFSET (0x38) /**< (PMC_USB) USB Clock Register Offset */ 883 884 #define PMC_USB_USBS_Pos 0 /**< (PMC_USB) USB Input Clock Selection Position */ 885 #define PMC_USB_USBS_Msk (_U_(0x1) << PMC_USB_USBS_Pos) /**< (PMC_USB) USB Input Clock Selection Mask */ 886 #define PMC_USB_USBS PMC_USB_USBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_USB_USBS_Msk instead */ 887 #define PMC_USB_USBDIV_Pos 8 /**< (PMC_USB) Divider for USB_48M Position */ 888 #define PMC_USB_USBDIV_Msk (_U_(0xF) << PMC_USB_USBDIV_Pos) /**< (PMC_USB) Divider for USB_48M Mask */ 889 #define PMC_USB_USBDIV(value) (PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)) 890 #define PMC_USB_MASK _U_(0xF01) /**< \deprecated (PMC_USB) Register MASK (Use PMC_USB_Msk instead) */ 891 #define PMC_USB_Msk _U_(0xF01) /**< (PMC_USB) Register Mask */ 892 893 894 /* -------- PMC_PCK : (PMC Offset: 0x40) (R/W 32) Programmable Clock Register -------- */ 895 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 896 #if COMPONENT_TYPEDEF_STYLE == 'N' 897 typedef union { 898 struct { 899 uint32_t CSS:3; /**< bit: 0..2 Programmable Clock Source Selection */ 900 uint32_t :1; /**< bit: 3 Reserved */ 901 uint32_t PRES:8; /**< bit: 4..11 Programmable Clock Prescaler */ 902 uint32_t :20; /**< bit: 12..31 Reserved */ 903 } bit; /**< Structure used for bit access */ 904 uint32_t reg; /**< Type used for register access */ 905 } PMC_PCK_Type; 906 #endif 907 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 908 909 #define PMC_PCK_OFFSET (0x40) /**< (PMC_PCK) Programmable Clock Register Offset */ 910 911 #define PMC_PCK_CSS_Pos 0 /**< (PMC_PCK) Programmable Clock Source Selection Position */ 912 #define PMC_PCK_CSS_Msk (_U_(0x7) << PMC_PCK_CSS_Pos) /**< (PMC_PCK) Programmable Clock Source Selection Mask */ 913 #define PMC_PCK_CSS(value) (PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)) 914 #define PMC_PCK_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCK) SLCK is selected */ 915 #define PMC_PCK_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCK) MAINCK is selected */ 916 #define PMC_PCK_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCK) PLLACK is selected */ 917 #define PMC_PCK_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCK) UPLLCKDIV is selected */ 918 #define PMC_PCK_CSS_MCK_Val _U_(0x4) /**< (PMC_PCK) MCK is selected */ 919 #define PMC_PCK_CSS_SLOW_CLK (PMC_PCK_CSS_SLOW_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) SLCK is selected Position */ 920 #define PMC_PCK_CSS_MAIN_CLK (PMC_PCK_CSS_MAIN_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MAINCK is selected Position */ 921 #define PMC_PCK_CSS_PLLA_CLK (PMC_PCK_CSS_PLLA_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) PLLACK is selected Position */ 922 #define PMC_PCK_CSS_UPLL_CLK (PMC_PCK_CSS_UPLL_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) UPLLCKDIV is selected Position */ 923 #define PMC_PCK_CSS_MCK (PMC_PCK_CSS_MCK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MCK is selected Position */ 924 #define PMC_PCK_PRES_Pos 4 /**< (PMC_PCK) Programmable Clock Prescaler Position */ 925 #define PMC_PCK_PRES_Msk (_U_(0xFF) << PMC_PCK_PRES_Pos) /**< (PMC_PCK) Programmable Clock Prescaler Mask */ 926 #define PMC_PCK_PRES(value) (PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)) 927 #define PMC_PCK_MASK _U_(0xFF7) /**< \deprecated (PMC_PCK) Register MASK (Use PMC_PCK_Msk instead) */ 928 #define PMC_PCK_Msk _U_(0xFF7) /**< (PMC_PCK) Register Mask */ 929 930 931 /* -------- PMC_IER : (PMC Offset: 0x60) (/W 32) Interrupt Enable Register -------- */ 932 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 933 #if COMPONENT_TYPEDEF_STYLE == 'N' 934 typedef union { 935 struct { 936 uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Enable */ 937 uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Enable */ 938 uint32_t :1; /**< bit: 2 Reserved */ 939 uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Enable */ 940 uint32_t :2; /**< bit: 4..5 Reserved */ 941 uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Enable */ 942 uint32_t :1; /**< bit: 7 Reserved */ 943 uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Enable */ 944 uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Enable */ 945 uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Enable */ 946 uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Enable */ 947 uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Enable */ 948 uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Enable */ 949 uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Enable */ 950 uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Enable */ 951 uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Enable */ 952 uint32_t MOSCRCS:1; /**< bit: 17 Main RC Oscillator Status Interrupt Enable */ 953 uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Enable */ 954 uint32_t :2; /**< bit: 19..20 Reserved */ 955 uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Enable */ 956 uint32_t :10; /**< bit: 22..31 Reserved */ 957 } bit; /**< Structure used for bit access */ 958 struct { 959 uint32_t :8; /**< bit: 0..7 Reserved */ 960 uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Enable */ 961 uint32_t :16; /**< bit: 16..31 Reserved */ 962 } vec; /**< Structure used for vec access */ 963 uint32_t reg; /**< Type used for register access */ 964 } PMC_IER_Type; 965 #endif 966 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 967 968 #define PMC_IER_OFFSET (0x60) /**< (PMC_IER) Interrupt Enable Register Offset */ 969 970 #define PMC_IER_MOSCXTS_Pos 0 /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Position */ 971 #define PMC_IER_MOSCXTS_Msk (_U_(0x1) << PMC_IER_MOSCXTS_Pos) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Mask */ 972 #define PMC_IER_MOSCXTS PMC_IER_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCXTS_Msk instead */ 973 #define PMC_IER_LOCKA_Pos 1 /**< (PMC_IER) PLLA Lock Interrupt Enable Position */ 974 #define PMC_IER_LOCKA_Msk (_U_(0x1) << PMC_IER_LOCKA_Pos) /**< (PMC_IER) PLLA Lock Interrupt Enable Mask */ 975 #define PMC_IER_LOCKA PMC_IER_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_LOCKA_Msk instead */ 976 #define PMC_IER_MCKRDY_Pos 3 /**< (PMC_IER) Master Clock Ready Interrupt Enable Position */ 977 #define PMC_IER_MCKRDY_Msk (_U_(0x1) << PMC_IER_MCKRDY_Pos) /**< (PMC_IER) Master Clock Ready Interrupt Enable Mask */ 978 #define PMC_IER_MCKRDY PMC_IER_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MCKRDY_Msk instead */ 979 #define PMC_IER_LOCKU_Pos 6 /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Position */ 980 #define PMC_IER_LOCKU_Msk (_U_(0x1) << PMC_IER_LOCKU_Pos) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Mask */ 981 #define PMC_IER_LOCKU PMC_IER_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_LOCKU_Msk instead */ 982 #define PMC_IER_PCKRDY0_Pos 8 /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Position */ 983 #define PMC_IER_PCKRDY0_Msk (_U_(0x1) << PMC_IER_PCKRDY0_Pos) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Mask */ 984 #define PMC_IER_PCKRDY0 PMC_IER_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY0_Msk instead */ 985 #define PMC_IER_PCKRDY1_Pos 9 /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Position */ 986 #define PMC_IER_PCKRDY1_Msk (_U_(0x1) << PMC_IER_PCKRDY1_Pos) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Mask */ 987 #define PMC_IER_PCKRDY1 PMC_IER_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY1_Msk instead */ 988 #define PMC_IER_PCKRDY2_Pos 10 /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Position */ 989 #define PMC_IER_PCKRDY2_Msk (_U_(0x1) << PMC_IER_PCKRDY2_Pos) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Mask */ 990 #define PMC_IER_PCKRDY2 PMC_IER_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY2_Msk instead */ 991 #define PMC_IER_PCKRDY3_Pos 11 /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Position */ 992 #define PMC_IER_PCKRDY3_Msk (_U_(0x1) << PMC_IER_PCKRDY3_Pos) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Mask */ 993 #define PMC_IER_PCKRDY3 PMC_IER_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY3_Msk instead */ 994 #define PMC_IER_PCKRDY4_Pos 12 /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Position */ 995 #define PMC_IER_PCKRDY4_Msk (_U_(0x1) << PMC_IER_PCKRDY4_Pos) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Mask */ 996 #define PMC_IER_PCKRDY4 PMC_IER_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY4_Msk instead */ 997 #define PMC_IER_PCKRDY5_Pos 13 /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Position */ 998 #define PMC_IER_PCKRDY5_Msk (_U_(0x1) << PMC_IER_PCKRDY5_Pos) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Mask */ 999 #define PMC_IER_PCKRDY5 PMC_IER_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY5_Msk instead */ 1000 #define PMC_IER_PCKRDY6_Pos 14 /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Position */ 1001 #define PMC_IER_PCKRDY6_Msk (_U_(0x1) << PMC_IER_PCKRDY6_Pos) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Mask */ 1002 #define PMC_IER_PCKRDY6 PMC_IER_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY6_Msk instead */ 1003 #define PMC_IER_PCKRDY7_Pos 15 /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Position */ 1004 #define PMC_IER_PCKRDY7_Msk (_U_(0x1) << PMC_IER_PCKRDY7_Pos) /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Mask */ 1005 #define PMC_IER_PCKRDY7 PMC_IER_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY7_Msk instead */ 1006 #define PMC_IER_MOSCSELS_Pos 16 /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Position */ 1007 #define PMC_IER_MOSCSELS_Msk (_U_(0x1) << PMC_IER_MOSCSELS_Pos) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Mask */ 1008 #define PMC_IER_MOSCSELS PMC_IER_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCSELS_Msk instead */ 1009 #define PMC_IER_MOSCRCS_Pos 17 /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Position */ 1010 #define PMC_IER_MOSCRCS_Msk (_U_(0x1) << PMC_IER_MOSCRCS_Pos) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Mask */ 1011 #define PMC_IER_MOSCRCS PMC_IER_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCRCS_Msk instead */ 1012 #define PMC_IER_CFDEV_Pos 18 /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Position */ 1013 #define PMC_IER_CFDEV_Msk (_U_(0x1) << PMC_IER_CFDEV_Pos) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Mask */ 1014 #define PMC_IER_CFDEV PMC_IER_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_CFDEV_Msk instead */ 1015 #define PMC_IER_XT32KERR_Pos 21 /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Position */ 1016 #define PMC_IER_XT32KERR_Msk (_U_(0x1) << PMC_IER_XT32KERR_Pos) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Mask */ 1017 #define PMC_IER_XT32KERR PMC_IER_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_XT32KERR_Msk instead */ 1018 #define PMC_IER_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IER) Register MASK (Use PMC_IER_Msk instead) */ 1019 #define PMC_IER_Msk _U_(0x27FF4B) /**< (PMC_IER) Register Mask */ 1020 1021 #define PMC_IER_PCKRDY_Pos 8 /**< (PMC_IER Position) Programmable Clock Ready x Interrupt Enable */ 1022 #define PMC_IER_PCKRDY_Msk (_U_(0xFF) << PMC_IER_PCKRDY_Pos) /**< (PMC_IER Mask) PCKRDY */ 1023 #define PMC_IER_PCKRDY(value) (PMC_IER_PCKRDY_Msk & ((value) << PMC_IER_PCKRDY_Pos)) 1024 1025 /* -------- PMC_IDR : (PMC Offset: 0x64) (/W 32) Interrupt Disable Register -------- */ 1026 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1027 #if COMPONENT_TYPEDEF_STYLE == 'N' 1028 typedef union { 1029 struct { 1030 uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Disable */ 1031 uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Disable */ 1032 uint32_t :1; /**< bit: 2 Reserved */ 1033 uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Disable */ 1034 uint32_t :2; /**< bit: 4..5 Reserved */ 1035 uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Disable */ 1036 uint32_t :1; /**< bit: 7 Reserved */ 1037 uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Disable */ 1038 uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Disable */ 1039 uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Disable */ 1040 uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Disable */ 1041 uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Disable */ 1042 uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Disable */ 1043 uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Disable */ 1044 uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Disable */ 1045 uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Disable */ 1046 uint32_t MOSCRCS:1; /**< bit: 17 Main RC Status Interrupt Disable */ 1047 uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Disable */ 1048 uint32_t :2; /**< bit: 19..20 Reserved */ 1049 uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Disable */ 1050 uint32_t :10; /**< bit: 22..31 Reserved */ 1051 } bit; /**< Structure used for bit access */ 1052 struct { 1053 uint32_t :8; /**< bit: 0..7 Reserved */ 1054 uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Disable */ 1055 uint32_t :16; /**< bit: 16..31 Reserved */ 1056 } vec; /**< Structure used for vec access */ 1057 uint32_t reg; /**< Type used for register access */ 1058 } PMC_IDR_Type; 1059 #endif 1060 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1061 1062 #define PMC_IDR_OFFSET (0x64) /**< (PMC_IDR) Interrupt Disable Register Offset */ 1063 1064 #define PMC_IDR_MOSCXTS_Pos 0 /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Position */ 1065 #define PMC_IDR_MOSCXTS_Msk (_U_(0x1) << PMC_IDR_MOSCXTS_Pos) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Mask */ 1066 #define PMC_IDR_MOSCXTS PMC_IDR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCXTS_Msk instead */ 1067 #define PMC_IDR_LOCKA_Pos 1 /**< (PMC_IDR) PLLA Lock Interrupt Disable Position */ 1068 #define PMC_IDR_LOCKA_Msk (_U_(0x1) << PMC_IDR_LOCKA_Pos) /**< (PMC_IDR) PLLA Lock Interrupt Disable Mask */ 1069 #define PMC_IDR_LOCKA PMC_IDR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_LOCKA_Msk instead */ 1070 #define PMC_IDR_MCKRDY_Pos 3 /**< (PMC_IDR) Master Clock Ready Interrupt Disable Position */ 1071 #define PMC_IDR_MCKRDY_Msk (_U_(0x1) << PMC_IDR_MCKRDY_Pos) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Mask */ 1072 #define PMC_IDR_MCKRDY PMC_IDR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MCKRDY_Msk instead */ 1073 #define PMC_IDR_LOCKU_Pos 6 /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Position */ 1074 #define PMC_IDR_LOCKU_Msk (_U_(0x1) << PMC_IDR_LOCKU_Pos) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Mask */ 1075 #define PMC_IDR_LOCKU PMC_IDR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_LOCKU_Msk instead */ 1076 #define PMC_IDR_PCKRDY0_Pos 8 /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Position */ 1077 #define PMC_IDR_PCKRDY0_Msk (_U_(0x1) << PMC_IDR_PCKRDY0_Pos) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Mask */ 1078 #define PMC_IDR_PCKRDY0 PMC_IDR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY0_Msk instead */ 1079 #define PMC_IDR_PCKRDY1_Pos 9 /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Position */ 1080 #define PMC_IDR_PCKRDY1_Msk (_U_(0x1) << PMC_IDR_PCKRDY1_Pos) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Mask */ 1081 #define PMC_IDR_PCKRDY1 PMC_IDR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY1_Msk instead */ 1082 #define PMC_IDR_PCKRDY2_Pos 10 /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Position */ 1083 #define PMC_IDR_PCKRDY2_Msk (_U_(0x1) << PMC_IDR_PCKRDY2_Pos) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Mask */ 1084 #define PMC_IDR_PCKRDY2 PMC_IDR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY2_Msk instead */ 1085 #define PMC_IDR_PCKRDY3_Pos 11 /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Position */ 1086 #define PMC_IDR_PCKRDY3_Msk (_U_(0x1) << PMC_IDR_PCKRDY3_Pos) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Mask */ 1087 #define PMC_IDR_PCKRDY3 PMC_IDR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY3_Msk instead */ 1088 #define PMC_IDR_PCKRDY4_Pos 12 /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Position */ 1089 #define PMC_IDR_PCKRDY4_Msk (_U_(0x1) << PMC_IDR_PCKRDY4_Pos) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Mask */ 1090 #define PMC_IDR_PCKRDY4 PMC_IDR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY4_Msk instead */ 1091 #define PMC_IDR_PCKRDY5_Pos 13 /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Position */ 1092 #define PMC_IDR_PCKRDY5_Msk (_U_(0x1) << PMC_IDR_PCKRDY5_Pos) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Mask */ 1093 #define PMC_IDR_PCKRDY5 PMC_IDR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY5_Msk instead */ 1094 #define PMC_IDR_PCKRDY6_Pos 14 /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Position */ 1095 #define PMC_IDR_PCKRDY6_Msk (_U_(0x1) << PMC_IDR_PCKRDY6_Pos) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Mask */ 1096 #define PMC_IDR_PCKRDY6 PMC_IDR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY6_Msk instead */ 1097 #define PMC_IDR_PCKRDY7_Pos 15 /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Position */ 1098 #define PMC_IDR_PCKRDY7_Msk (_U_(0x1) << PMC_IDR_PCKRDY7_Pos) /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Mask */ 1099 #define PMC_IDR_PCKRDY7 PMC_IDR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY7_Msk instead */ 1100 #define PMC_IDR_MOSCSELS_Pos 16 /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Position */ 1101 #define PMC_IDR_MOSCSELS_Msk (_U_(0x1) << PMC_IDR_MOSCSELS_Pos) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Mask */ 1102 #define PMC_IDR_MOSCSELS PMC_IDR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCSELS_Msk instead */ 1103 #define PMC_IDR_MOSCRCS_Pos 17 /**< (PMC_IDR) Main RC Status Interrupt Disable Position */ 1104 #define PMC_IDR_MOSCRCS_Msk (_U_(0x1) << PMC_IDR_MOSCRCS_Pos) /**< (PMC_IDR) Main RC Status Interrupt Disable Mask */ 1105 #define PMC_IDR_MOSCRCS PMC_IDR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCRCS_Msk instead */ 1106 #define PMC_IDR_CFDEV_Pos 18 /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Position */ 1107 #define PMC_IDR_CFDEV_Msk (_U_(0x1) << PMC_IDR_CFDEV_Pos) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Mask */ 1108 #define PMC_IDR_CFDEV PMC_IDR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_CFDEV_Msk instead */ 1109 #define PMC_IDR_XT32KERR_Pos 21 /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Position */ 1110 #define PMC_IDR_XT32KERR_Msk (_U_(0x1) << PMC_IDR_XT32KERR_Pos) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Mask */ 1111 #define PMC_IDR_XT32KERR PMC_IDR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_XT32KERR_Msk instead */ 1112 #define PMC_IDR_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IDR) Register MASK (Use PMC_IDR_Msk instead) */ 1113 #define PMC_IDR_Msk _U_(0x27FF4B) /**< (PMC_IDR) Register Mask */ 1114 1115 #define PMC_IDR_PCKRDY_Pos 8 /**< (PMC_IDR Position) Programmable Clock Ready x Interrupt Disable */ 1116 #define PMC_IDR_PCKRDY_Msk (_U_(0xFF) << PMC_IDR_PCKRDY_Pos) /**< (PMC_IDR Mask) PCKRDY */ 1117 #define PMC_IDR_PCKRDY(value) (PMC_IDR_PCKRDY_Msk & ((value) << PMC_IDR_PCKRDY_Pos)) 1118 1119 /* -------- PMC_SR : (PMC Offset: 0x68) (R/ 32) Status Register -------- */ 1120 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1121 #if COMPONENT_TYPEDEF_STYLE == 'N' 1122 typedef union { 1123 struct { 1124 uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status */ 1125 uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Status */ 1126 uint32_t :1; /**< bit: 2 Reserved */ 1127 uint32_t MCKRDY:1; /**< bit: 3 Master Clock Status */ 1128 uint32_t :2; /**< bit: 4..5 Reserved */ 1129 uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Status */ 1130 uint32_t OSCSELS:1; /**< bit: 7 Slow Clock Source Oscillator Selection */ 1131 uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Status */ 1132 uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Status */ 1133 uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Status */ 1134 uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Status */ 1135 uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Status */ 1136 uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Status */ 1137 uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Status */ 1138 uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Status */ 1139 uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status */ 1140 uint32_t MOSCRCS:1; /**< bit: 17 Main RC Oscillator Status */ 1141 uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event */ 1142 uint32_t CFDS:1; /**< bit: 19 Clock Failure Detector Status */ 1143 uint32_t FOS:1; /**< bit: 20 Clock Failure Detector Fault Output Status */ 1144 uint32_t XT32KERR:1; /**< bit: 21 Slow Crystal Oscillator Error */ 1145 uint32_t :10; /**< bit: 22..31 Reserved */ 1146 } bit; /**< Structure used for bit access */ 1147 struct { 1148 uint32_t :8; /**< bit: 0..7 Reserved */ 1149 uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Status */ 1150 uint32_t :16; /**< bit: 16..31 Reserved */ 1151 } vec; /**< Structure used for vec access */ 1152 uint32_t reg; /**< Type used for register access */ 1153 } PMC_SR_Type; 1154 #endif 1155 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1156 1157 #define PMC_SR_OFFSET (0x68) /**< (PMC_SR) Status Register Offset */ 1158 1159 #define PMC_SR_MOSCXTS_Pos 0 /**< (PMC_SR) Main Crystal Oscillator Status Position */ 1160 #define PMC_SR_MOSCXTS_Msk (_U_(0x1) << PMC_SR_MOSCXTS_Pos) /**< (PMC_SR) Main Crystal Oscillator Status Mask */ 1161 #define PMC_SR_MOSCXTS PMC_SR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCXTS_Msk instead */ 1162 #define PMC_SR_LOCKA_Pos 1 /**< (PMC_SR) PLLA Lock Status Position */ 1163 #define PMC_SR_LOCKA_Msk (_U_(0x1) << PMC_SR_LOCKA_Pos) /**< (PMC_SR) PLLA Lock Status Mask */ 1164 #define PMC_SR_LOCKA PMC_SR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_LOCKA_Msk instead */ 1165 #define PMC_SR_MCKRDY_Pos 3 /**< (PMC_SR) Master Clock Status Position */ 1166 #define PMC_SR_MCKRDY_Msk (_U_(0x1) << PMC_SR_MCKRDY_Pos) /**< (PMC_SR) Master Clock Status Mask */ 1167 #define PMC_SR_MCKRDY PMC_SR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MCKRDY_Msk instead */ 1168 #define PMC_SR_LOCKU_Pos 6 /**< (PMC_SR) UTMI PLL Lock Status Position */ 1169 #define PMC_SR_LOCKU_Msk (_U_(0x1) << PMC_SR_LOCKU_Pos) /**< (PMC_SR) UTMI PLL Lock Status Mask */ 1170 #define PMC_SR_LOCKU PMC_SR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_LOCKU_Msk instead */ 1171 #define PMC_SR_OSCSELS_Pos 7 /**< (PMC_SR) Slow Clock Source Oscillator Selection Position */ 1172 #define PMC_SR_OSCSELS_Msk (_U_(0x1) << PMC_SR_OSCSELS_Pos) /**< (PMC_SR) Slow Clock Source Oscillator Selection Mask */ 1173 #define PMC_SR_OSCSELS PMC_SR_OSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_OSCSELS_Msk instead */ 1174 #define PMC_SR_PCKRDY0_Pos 8 /**< (PMC_SR) Programmable Clock Ready 0 Status Position */ 1175 #define PMC_SR_PCKRDY0_Msk (_U_(0x1) << PMC_SR_PCKRDY0_Pos) /**< (PMC_SR) Programmable Clock Ready 0 Status Mask */ 1176 #define PMC_SR_PCKRDY0 PMC_SR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY0_Msk instead */ 1177 #define PMC_SR_PCKRDY1_Pos 9 /**< (PMC_SR) Programmable Clock Ready 1 Status Position */ 1178 #define PMC_SR_PCKRDY1_Msk (_U_(0x1) << PMC_SR_PCKRDY1_Pos) /**< (PMC_SR) Programmable Clock Ready 1 Status Mask */ 1179 #define PMC_SR_PCKRDY1 PMC_SR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY1_Msk instead */ 1180 #define PMC_SR_PCKRDY2_Pos 10 /**< (PMC_SR) Programmable Clock Ready 2 Status Position */ 1181 #define PMC_SR_PCKRDY2_Msk (_U_(0x1) << PMC_SR_PCKRDY2_Pos) /**< (PMC_SR) Programmable Clock Ready 2 Status Mask */ 1182 #define PMC_SR_PCKRDY2 PMC_SR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY2_Msk instead */ 1183 #define PMC_SR_PCKRDY3_Pos 11 /**< (PMC_SR) Programmable Clock Ready 3 Status Position */ 1184 #define PMC_SR_PCKRDY3_Msk (_U_(0x1) << PMC_SR_PCKRDY3_Pos) /**< (PMC_SR) Programmable Clock Ready 3 Status Mask */ 1185 #define PMC_SR_PCKRDY3 PMC_SR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY3_Msk instead */ 1186 #define PMC_SR_PCKRDY4_Pos 12 /**< (PMC_SR) Programmable Clock Ready 4 Status Position */ 1187 #define PMC_SR_PCKRDY4_Msk (_U_(0x1) << PMC_SR_PCKRDY4_Pos) /**< (PMC_SR) Programmable Clock Ready 4 Status Mask */ 1188 #define PMC_SR_PCKRDY4 PMC_SR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY4_Msk instead */ 1189 #define PMC_SR_PCKRDY5_Pos 13 /**< (PMC_SR) Programmable Clock Ready 5 Status Position */ 1190 #define PMC_SR_PCKRDY5_Msk (_U_(0x1) << PMC_SR_PCKRDY5_Pos) /**< (PMC_SR) Programmable Clock Ready 5 Status Mask */ 1191 #define PMC_SR_PCKRDY5 PMC_SR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY5_Msk instead */ 1192 #define PMC_SR_PCKRDY6_Pos 14 /**< (PMC_SR) Programmable Clock Ready 6 Status Position */ 1193 #define PMC_SR_PCKRDY6_Msk (_U_(0x1) << PMC_SR_PCKRDY6_Pos) /**< (PMC_SR) Programmable Clock Ready 6 Status Mask */ 1194 #define PMC_SR_PCKRDY6 PMC_SR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY6_Msk instead */ 1195 #define PMC_SR_PCKRDY7_Pos 15 /**< (PMC_SR) Programmable Clock Ready 7 Status Position */ 1196 #define PMC_SR_PCKRDY7_Msk (_U_(0x1) << PMC_SR_PCKRDY7_Pos) /**< (PMC_SR) Programmable Clock Ready 7 Status Mask */ 1197 #define PMC_SR_PCKRDY7 PMC_SR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY7_Msk instead */ 1198 #define PMC_SR_MOSCSELS_Pos 16 /**< (PMC_SR) Main Clock Source Oscillator Selection Status Position */ 1199 #define PMC_SR_MOSCSELS_Msk (_U_(0x1) << PMC_SR_MOSCSELS_Pos) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Mask */ 1200 #define PMC_SR_MOSCSELS PMC_SR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCSELS_Msk instead */ 1201 #define PMC_SR_MOSCRCS_Pos 17 /**< (PMC_SR) Main RC Oscillator Status Position */ 1202 #define PMC_SR_MOSCRCS_Msk (_U_(0x1) << PMC_SR_MOSCRCS_Pos) /**< (PMC_SR) Main RC Oscillator Status Mask */ 1203 #define PMC_SR_MOSCRCS PMC_SR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCRCS_Msk instead */ 1204 #define PMC_SR_CFDEV_Pos 18 /**< (PMC_SR) Clock Failure Detector Event Position */ 1205 #define PMC_SR_CFDEV_Msk (_U_(0x1) << PMC_SR_CFDEV_Pos) /**< (PMC_SR) Clock Failure Detector Event Mask */ 1206 #define PMC_SR_CFDEV PMC_SR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_CFDEV_Msk instead */ 1207 #define PMC_SR_CFDS_Pos 19 /**< (PMC_SR) Clock Failure Detector Status Position */ 1208 #define PMC_SR_CFDS_Msk (_U_(0x1) << PMC_SR_CFDS_Pos) /**< (PMC_SR) Clock Failure Detector Status Mask */ 1209 #define PMC_SR_CFDS PMC_SR_CFDS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_CFDS_Msk instead */ 1210 #define PMC_SR_FOS_Pos 20 /**< (PMC_SR) Clock Failure Detector Fault Output Status Position */ 1211 #define PMC_SR_FOS_Msk (_U_(0x1) << PMC_SR_FOS_Pos) /**< (PMC_SR) Clock Failure Detector Fault Output Status Mask */ 1212 #define PMC_SR_FOS PMC_SR_FOS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_FOS_Msk instead */ 1213 #define PMC_SR_XT32KERR_Pos 21 /**< (PMC_SR) Slow Crystal Oscillator Error Position */ 1214 #define PMC_SR_XT32KERR_Msk (_U_(0x1) << PMC_SR_XT32KERR_Pos) /**< (PMC_SR) Slow Crystal Oscillator Error Mask */ 1215 #define PMC_SR_XT32KERR PMC_SR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_XT32KERR_Msk instead */ 1216 #define PMC_SR_MASK _U_(0x3FFFCB) /**< \deprecated (PMC_SR) Register MASK (Use PMC_SR_Msk instead) */ 1217 #define PMC_SR_Msk _U_(0x3FFFCB) /**< (PMC_SR) Register Mask */ 1218 1219 #define PMC_SR_PCKRDY_Pos 8 /**< (PMC_SR Position) Programmable Clock Ready x Status */ 1220 #define PMC_SR_PCKRDY_Msk (_U_(0xFF) << PMC_SR_PCKRDY_Pos) /**< (PMC_SR Mask) PCKRDY */ 1221 #define PMC_SR_PCKRDY(value) (PMC_SR_PCKRDY_Msk & ((value) << PMC_SR_PCKRDY_Pos)) 1222 1223 /* -------- PMC_IMR : (PMC Offset: 0x6c) (R/ 32) Interrupt Mask Register -------- */ 1224 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1225 #if COMPONENT_TYPEDEF_STYLE == 'N' 1226 typedef union { 1227 struct { 1228 uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Mask */ 1229 uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Mask */ 1230 uint32_t :1; /**< bit: 2 Reserved */ 1231 uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Mask */ 1232 uint32_t :2; /**< bit: 4..5 Reserved */ 1233 uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Mask */ 1234 uint32_t :1; /**< bit: 7 Reserved */ 1235 uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Mask */ 1236 uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Mask */ 1237 uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Mask */ 1238 uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Mask */ 1239 uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Mask */ 1240 uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Mask */ 1241 uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Mask */ 1242 uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Mask */ 1243 uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Mask */ 1244 uint32_t MOSCRCS:1; /**< bit: 17 Main RC Status Interrupt Mask */ 1245 uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Mask */ 1246 uint32_t :2; /**< bit: 19..20 Reserved */ 1247 uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Mask */ 1248 uint32_t :10; /**< bit: 22..31 Reserved */ 1249 } bit; /**< Structure used for bit access */ 1250 struct { 1251 uint32_t :8; /**< bit: 0..7 Reserved */ 1252 uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Mask */ 1253 uint32_t :16; /**< bit: 16..31 Reserved */ 1254 } vec; /**< Structure used for vec access */ 1255 uint32_t reg; /**< Type used for register access */ 1256 } PMC_IMR_Type; 1257 #endif 1258 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1259 1260 #define PMC_IMR_OFFSET (0x6C) /**< (PMC_IMR) Interrupt Mask Register Offset */ 1261 1262 #define PMC_IMR_MOSCXTS_Pos 0 /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Position */ 1263 #define PMC_IMR_MOSCXTS_Msk (_U_(0x1) << PMC_IMR_MOSCXTS_Pos) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Mask */ 1264 #define PMC_IMR_MOSCXTS PMC_IMR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCXTS_Msk instead */ 1265 #define PMC_IMR_LOCKA_Pos 1 /**< (PMC_IMR) PLLA Lock Interrupt Mask Position */ 1266 #define PMC_IMR_LOCKA_Msk (_U_(0x1) << PMC_IMR_LOCKA_Pos) /**< (PMC_IMR) PLLA Lock Interrupt Mask Mask */ 1267 #define PMC_IMR_LOCKA PMC_IMR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_LOCKA_Msk instead */ 1268 #define PMC_IMR_MCKRDY_Pos 3 /**< (PMC_IMR) Master Clock Ready Interrupt Mask Position */ 1269 #define PMC_IMR_MCKRDY_Msk (_U_(0x1) << PMC_IMR_MCKRDY_Pos) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Mask */ 1270 #define PMC_IMR_MCKRDY PMC_IMR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MCKRDY_Msk instead */ 1271 #define PMC_IMR_LOCKU_Pos 6 /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Position */ 1272 #define PMC_IMR_LOCKU_Msk (_U_(0x1) << PMC_IMR_LOCKU_Pos) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Mask */ 1273 #define PMC_IMR_LOCKU PMC_IMR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_LOCKU_Msk instead */ 1274 #define PMC_IMR_PCKRDY0_Pos 8 /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Position */ 1275 #define PMC_IMR_PCKRDY0_Msk (_U_(0x1) << PMC_IMR_PCKRDY0_Pos) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Mask */ 1276 #define PMC_IMR_PCKRDY0 PMC_IMR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY0_Msk instead */ 1277 #define PMC_IMR_PCKRDY1_Pos 9 /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Position */ 1278 #define PMC_IMR_PCKRDY1_Msk (_U_(0x1) << PMC_IMR_PCKRDY1_Pos) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Mask */ 1279 #define PMC_IMR_PCKRDY1 PMC_IMR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY1_Msk instead */ 1280 #define PMC_IMR_PCKRDY2_Pos 10 /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Position */ 1281 #define PMC_IMR_PCKRDY2_Msk (_U_(0x1) << PMC_IMR_PCKRDY2_Pos) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Mask */ 1282 #define PMC_IMR_PCKRDY2 PMC_IMR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY2_Msk instead */ 1283 #define PMC_IMR_PCKRDY3_Pos 11 /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Position */ 1284 #define PMC_IMR_PCKRDY3_Msk (_U_(0x1) << PMC_IMR_PCKRDY3_Pos) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Mask */ 1285 #define PMC_IMR_PCKRDY3 PMC_IMR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY3_Msk instead */ 1286 #define PMC_IMR_PCKRDY4_Pos 12 /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Position */ 1287 #define PMC_IMR_PCKRDY4_Msk (_U_(0x1) << PMC_IMR_PCKRDY4_Pos) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Mask */ 1288 #define PMC_IMR_PCKRDY4 PMC_IMR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY4_Msk instead */ 1289 #define PMC_IMR_PCKRDY5_Pos 13 /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Position */ 1290 #define PMC_IMR_PCKRDY5_Msk (_U_(0x1) << PMC_IMR_PCKRDY5_Pos) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Mask */ 1291 #define PMC_IMR_PCKRDY5 PMC_IMR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY5_Msk instead */ 1292 #define PMC_IMR_PCKRDY6_Pos 14 /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Position */ 1293 #define PMC_IMR_PCKRDY6_Msk (_U_(0x1) << PMC_IMR_PCKRDY6_Pos) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Mask */ 1294 #define PMC_IMR_PCKRDY6 PMC_IMR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY6_Msk instead */ 1295 #define PMC_IMR_PCKRDY7_Pos 15 /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Position */ 1296 #define PMC_IMR_PCKRDY7_Msk (_U_(0x1) << PMC_IMR_PCKRDY7_Pos) /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Mask */ 1297 #define PMC_IMR_PCKRDY7 PMC_IMR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY7_Msk instead */ 1298 #define PMC_IMR_MOSCSELS_Pos 16 /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Position */ 1299 #define PMC_IMR_MOSCSELS_Msk (_U_(0x1) << PMC_IMR_MOSCSELS_Pos) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Mask */ 1300 #define PMC_IMR_MOSCSELS PMC_IMR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCSELS_Msk instead */ 1301 #define PMC_IMR_MOSCRCS_Pos 17 /**< (PMC_IMR) Main RC Status Interrupt Mask Position */ 1302 #define PMC_IMR_MOSCRCS_Msk (_U_(0x1) << PMC_IMR_MOSCRCS_Pos) /**< (PMC_IMR) Main RC Status Interrupt Mask Mask */ 1303 #define PMC_IMR_MOSCRCS PMC_IMR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCRCS_Msk instead */ 1304 #define PMC_IMR_CFDEV_Pos 18 /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Position */ 1305 #define PMC_IMR_CFDEV_Msk (_U_(0x1) << PMC_IMR_CFDEV_Pos) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Mask */ 1306 #define PMC_IMR_CFDEV PMC_IMR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_CFDEV_Msk instead */ 1307 #define PMC_IMR_XT32KERR_Pos 21 /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Position */ 1308 #define PMC_IMR_XT32KERR_Msk (_U_(0x1) << PMC_IMR_XT32KERR_Pos) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Mask */ 1309 #define PMC_IMR_XT32KERR PMC_IMR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_XT32KERR_Msk instead */ 1310 #define PMC_IMR_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IMR) Register MASK (Use PMC_IMR_Msk instead) */ 1311 #define PMC_IMR_Msk _U_(0x27FF4B) /**< (PMC_IMR) Register Mask */ 1312 1313 #define PMC_IMR_PCKRDY_Pos 8 /**< (PMC_IMR Position) Programmable Clock Ready x Interrupt Mask */ 1314 #define PMC_IMR_PCKRDY_Msk (_U_(0xFF) << PMC_IMR_PCKRDY_Pos) /**< (PMC_IMR Mask) PCKRDY */ 1315 #define PMC_IMR_PCKRDY(value) (PMC_IMR_PCKRDY_Msk & ((value) << PMC_IMR_PCKRDY_Pos)) 1316 1317 /* -------- PMC_FSMR : (PMC Offset: 0x70) (R/W 32) Fast Startup Mode Register -------- */ 1318 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1319 #if COMPONENT_TYPEDEF_STYLE == 'N' 1320 typedef union { 1321 struct { 1322 uint32_t FSTT0:1; /**< bit: 0 Fast Startup Input Enable 0 */ 1323 uint32_t FSTT1:1; /**< bit: 1 Fast Startup Input Enable 1 */ 1324 uint32_t FSTT2:1; /**< bit: 2 Fast Startup Input Enable 2 */ 1325 uint32_t FSTT3:1; /**< bit: 3 Fast Startup Input Enable 3 */ 1326 uint32_t FSTT4:1; /**< bit: 4 Fast Startup Input Enable 4 */ 1327 uint32_t FSTT5:1; /**< bit: 5 Fast Startup Input Enable 5 */ 1328 uint32_t FSTT6:1; /**< bit: 6 Fast Startup Input Enable 6 */ 1329 uint32_t FSTT7:1; /**< bit: 7 Fast Startup Input Enable 7 */ 1330 uint32_t FSTT8:1; /**< bit: 8 Fast Startup Input Enable 8 */ 1331 uint32_t FSTT9:1; /**< bit: 9 Fast Startup Input Enable 9 */ 1332 uint32_t FSTT10:1; /**< bit: 10 Fast Startup Input Enable 10 */ 1333 uint32_t FSTT11:1; /**< bit: 11 Fast Startup Input Enable 11 */ 1334 uint32_t FSTT12:1; /**< bit: 12 Fast Startup Input Enable 12 */ 1335 uint32_t FSTT13:1; /**< bit: 13 Fast Startup Input Enable 13 */ 1336 uint32_t FSTT14:1; /**< bit: 14 Fast Startup Input Enable 14 */ 1337 uint32_t FSTT15:1; /**< bit: 15 Fast Startup Input Enable 15 */ 1338 uint32_t RTTAL:1; /**< bit: 16 RTT Alarm Enable */ 1339 uint32_t RTCAL:1; /**< bit: 17 RTC Alarm Enable */ 1340 uint32_t USBAL:1; /**< bit: 18 USB Alarm Enable */ 1341 uint32_t :1; /**< bit: 19 Reserved */ 1342 uint32_t LPM:1; /**< bit: 20 Low-power Mode */ 1343 uint32_t FLPM:2; /**< bit: 21..22 Flash Low-power Mode */ 1344 uint32_t FFLPM:1; /**< bit: 23 Force Flash Low-power Mode */ 1345 uint32_t :8; /**< bit: 24..31 Reserved */ 1346 } bit; /**< Structure used for bit access */ 1347 struct { 1348 uint32_t FSTT:16; /**< bit: 0..15 Fast Startup Input Enable x */ 1349 uint32_t :16; /**< bit: 16..31 Reserved */ 1350 } vec; /**< Structure used for vec access */ 1351 uint32_t reg; /**< Type used for register access */ 1352 } PMC_FSMR_Type; 1353 #endif 1354 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1355 1356 #define PMC_FSMR_OFFSET (0x70) /**< (PMC_FSMR) Fast Startup Mode Register Offset */ 1357 1358 #define PMC_FSMR_FSTT0_Pos 0 /**< (PMC_FSMR) Fast Startup Input Enable 0 Position */ 1359 #define PMC_FSMR_FSTT0_Msk (_U_(0x1) << PMC_FSMR_FSTT0_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 0 Mask */ 1360 #define PMC_FSMR_FSTT0 PMC_FSMR_FSTT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT0_Msk instead */ 1361 #define PMC_FSMR_FSTT1_Pos 1 /**< (PMC_FSMR) Fast Startup Input Enable 1 Position */ 1362 #define PMC_FSMR_FSTT1_Msk (_U_(0x1) << PMC_FSMR_FSTT1_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 1 Mask */ 1363 #define PMC_FSMR_FSTT1 PMC_FSMR_FSTT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT1_Msk instead */ 1364 #define PMC_FSMR_FSTT2_Pos 2 /**< (PMC_FSMR) Fast Startup Input Enable 2 Position */ 1365 #define PMC_FSMR_FSTT2_Msk (_U_(0x1) << PMC_FSMR_FSTT2_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 2 Mask */ 1366 #define PMC_FSMR_FSTT2 PMC_FSMR_FSTT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT2_Msk instead */ 1367 #define PMC_FSMR_FSTT3_Pos 3 /**< (PMC_FSMR) Fast Startup Input Enable 3 Position */ 1368 #define PMC_FSMR_FSTT3_Msk (_U_(0x1) << PMC_FSMR_FSTT3_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 3 Mask */ 1369 #define PMC_FSMR_FSTT3 PMC_FSMR_FSTT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT3_Msk instead */ 1370 #define PMC_FSMR_FSTT4_Pos 4 /**< (PMC_FSMR) Fast Startup Input Enable 4 Position */ 1371 #define PMC_FSMR_FSTT4_Msk (_U_(0x1) << PMC_FSMR_FSTT4_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 4 Mask */ 1372 #define PMC_FSMR_FSTT4 PMC_FSMR_FSTT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT4_Msk instead */ 1373 #define PMC_FSMR_FSTT5_Pos 5 /**< (PMC_FSMR) Fast Startup Input Enable 5 Position */ 1374 #define PMC_FSMR_FSTT5_Msk (_U_(0x1) << PMC_FSMR_FSTT5_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 5 Mask */ 1375 #define PMC_FSMR_FSTT5 PMC_FSMR_FSTT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT5_Msk instead */ 1376 #define PMC_FSMR_FSTT6_Pos 6 /**< (PMC_FSMR) Fast Startup Input Enable 6 Position */ 1377 #define PMC_FSMR_FSTT6_Msk (_U_(0x1) << PMC_FSMR_FSTT6_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 6 Mask */ 1378 #define PMC_FSMR_FSTT6 PMC_FSMR_FSTT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT6_Msk instead */ 1379 #define PMC_FSMR_FSTT7_Pos 7 /**< (PMC_FSMR) Fast Startup Input Enable 7 Position */ 1380 #define PMC_FSMR_FSTT7_Msk (_U_(0x1) << PMC_FSMR_FSTT7_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 7 Mask */ 1381 #define PMC_FSMR_FSTT7 PMC_FSMR_FSTT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT7_Msk instead */ 1382 #define PMC_FSMR_FSTT8_Pos 8 /**< (PMC_FSMR) Fast Startup Input Enable 8 Position */ 1383 #define PMC_FSMR_FSTT8_Msk (_U_(0x1) << PMC_FSMR_FSTT8_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 8 Mask */ 1384 #define PMC_FSMR_FSTT8 PMC_FSMR_FSTT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT8_Msk instead */ 1385 #define PMC_FSMR_FSTT9_Pos 9 /**< (PMC_FSMR) Fast Startup Input Enable 9 Position */ 1386 #define PMC_FSMR_FSTT9_Msk (_U_(0x1) << PMC_FSMR_FSTT9_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 9 Mask */ 1387 #define PMC_FSMR_FSTT9 PMC_FSMR_FSTT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT9_Msk instead */ 1388 #define PMC_FSMR_FSTT10_Pos 10 /**< (PMC_FSMR) Fast Startup Input Enable 10 Position */ 1389 #define PMC_FSMR_FSTT10_Msk (_U_(0x1) << PMC_FSMR_FSTT10_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 10 Mask */ 1390 #define PMC_FSMR_FSTT10 PMC_FSMR_FSTT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT10_Msk instead */ 1391 #define PMC_FSMR_FSTT11_Pos 11 /**< (PMC_FSMR) Fast Startup Input Enable 11 Position */ 1392 #define PMC_FSMR_FSTT11_Msk (_U_(0x1) << PMC_FSMR_FSTT11_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 11 Mask */ 1393 #define PMC_FSMR_FSTT11 PMC_FSMR_FSTT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT11_Msk instead */ 1394 #define PMC_FSMR_FSTT12_Pos 12 /**< (PMC_FSMR) Fast Startup Input Enable 12 Position */ 1395 #define PMC_FSMR_FSTT12_Msk (_U_(0x1) << PMC_FSMR_FSTT12_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 12 Mask */ 1396 #define PMC_FSMR_FSTT12 PMC_FSMR_FSTT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT12_Msk instead */ 1397 #define PMC_FSMR_FSTT13_Pos 13 /**< (PMC_FSMR) Fast Startup Input Enable 13 Position */ 1398 #define PMC_FSMR_FSTT13_Msk (_U_(0x1) << PMC_FSMR_FSTT13_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 13 Mask */ 1399 #define PMC_FSMR_FSTT13 PMC_FSMR_FSTT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT13_Msk instead */ 1400 #define PMC_FSMR_FSTT14_Pos 14 /**< (PMC_FSMR) Fast Startup Input Enable 14 Position */ 1401 #define PMC_FSMR_FSTT14_Msk (_U_(0x1) << PMC_FSMR_FSTT14_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 14 Mask */ 1402 #define PMC_FSMR_FSTT14 PMC_FSMR_FSTT14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT14_Msk instead */ 1403 #define PMC_FSMR_FSTT15_Pos 15 /**< (PMC_FSMR) Fast Startup Input Enable 15 Position */ 1404 #define PMC_FSMR_FSTT15_Msk (_U_(0x1) << PMC_FSMR_FSTT15_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 15 Mask */ 1405 #define PMC_FSMR_FSTT15 PMC_FSMR_FSTT15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT15_Msk instead */ 1406 #define PMC_FSMR_RTTAL_Pos 16 /**< (PMC_FSMR) RTT Alarm Enable Position */ 1407 #define PMC_FSMR_RTTAL_Msk (_U_(0x1) << PMC_FSMR_RTTAL_Pos) /**< (PMC_FSMR) RTT Alarm Enable Mask */ 1408 #define PMC_FSMR_RTTAL PMC_FSMR_RTTAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_RTTAL_Msk instead */ 1409 #define PMC_FSMR_RTCAL_Pos 17 /**< (PMC_FSMR) RTC Alarm Enable Position */ 1410 #define PMC_FSMR_RTCAL_Msk (_U_(0x1) << PMC_FSMR_RTCAL_Pos) /**< (PMC_FSMR) RTC Alarm Enable Mask */ 1411 #define PMC_FSMR_RTCAL PMC_FSMR_RTCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_RTCAL_Msk instead */ 1412 #define PMC_FSMR_USBAL_Pos 18 /**< (PMC_FSMR) USB Alarm Enable Position */ 1413 #define PMC_FSMR_USBAL_Msk (_U_(0x1) << PMC_FSMR_USBAL_Pos) /**< (PMC_FSMR) USB Alarm Enable Mask */ 1414 #define PMC_FSMR_USBAL PMC_FSMR_USBAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_USBAL_Msk instead */ 1415 #define PMC_FSMR_LPM_Pos 20 /**< (PMC_FSMR) Low-power Mode Position */ 1416 #define PMC_FSMR_LPM_Msk (_U_(0x1) << PMC_FSMR_LPM_Pos) /**< (PMC_FSMR) Low-power Mode Mask */ 1417 #define PMC_FSMR_LPM PMC_FSMR_LPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_LPM_Msk instead */ 1418 #define PMC_FSMR_FLPM_Pos 21 /**< (PMC_FSMR) Flash Low-power Mode Position */ 1419 #define PMC_FSMR_FLPM_Msk (_U_(0x3) << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash Low-power Mode Mask */ 1420 #define PMC_FSMR_FLPM(value) (PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)) 1421 #define PMC_FSMR_FLPM_FLASH_STANDBY_Val _U_(0x0) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ 1422 #define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val _U_(0x1) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ 1423 #define PMC_FSMR_FLPM_FLASH_IDLE_Val _U_(0x2) /**< (PMC_FSMR) Idle mode */ 1424 #define PMC_FSMR_FLPM_FLASH_STANDBY (PMC_FSMR_FLPM_FLASH_STANDBY_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode Position */ 1425 #define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode Position */ 1426 #define PMC_FSMR_FLPM_FLASH_IDLE (PMC_FSMR_FLPM_FLASH_IDLE_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Idle mode Position */ 1427 #define PMC_FSMR_FFLPM_Pos 23 /**< (PMC_FSMR) Force Flash Low-power Mode Position */ 1428 #define PMC_FSMR_FFLPM_Msk (_U_(0x1) << PMC_FSMR_FFLPM_Pos) /**< (PMC_FSMR) Force Flash Low-power Mode Mask */ 1429 #define PMC_FSMR_FFLPM PMC_FSMR_FFLPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FFLPM_Msk instead */ 1430 #define PMC_FSMR_MASK _U_(0xF7FFFF) /**< \deprecated (PMC_FSMR) Register MASK (Use PMC_FSMR_Msk instead) */ 1431 #define PMC_FSMR_Msk _U_(0xF7FFFF) /**< (PMC_FSMR) Register Mask */ 1432 1433 #define PMC_FSMR_FSTT_Pos 0 /**< (PMC_FSMR Position) Fast Startup Input Enable x */ 1434 #define PMC_FSMR_FSTT_Msk (_U_(0xFFFF) << PMC_FSMR_FSTT_Pos) /**< (PMC_FSMR Mask) FSTT */ 1435 #define PMC_FSMR_FSTT(value) (PMC_FSMR_FSTT_Msk & ((value) << PMC_FSMR_FSTT_Pos)) 1436 1437 /* -------- PMC_FSPR : (PMC Offset: 0x74) (R/W 32) Fast Startup Polarity Register -------- */ 1438 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1439 #if COMPONENT_TYPEDEF_STYLE == 'N' 1440 typedef union { 1441 struct { 1442 uint32_t FSTP0:1; /**< bit: 0 Fast Startup Input Polarity 0 */ 1443 uint32_t FSTP1:1; /**< bit: 1 Fast Startup Input Polarity 1 */ 1444 uint32_t FSTP2:1; /**< bit: 2 Fast Startup Input Polarity 2 */ 1445 uint32_t FSTP3:1; /**< bit: 3 Fast Startup Input Polarity 3 */ 1446 uint32_t FSTP4:1; /**< bit: 4 Fast Startup Input Polarity 4 */ 1447 uint32_t FSTP5:1; /**< bit: 5 Fast Startup Input Polarity 5 */ 1448 uint32_t FSTP6:1; /**< bit: 6 Fast Startup Input Polarity 6 */ 1449 uint32_t FSTP7:1; /**< bit: 7 Fast Startup Input Polarity 7 */ 1450 uint32_t FSTP8:1; /**< bit: 8 Fast Startup Input Polarity 8 */ 1451 uint32_t FSTP9:1; /**< bit: 9 Fast Startup Input Polarity 9 */ 1452 uint32_t FSTP10:1; /**< bit: 10 Fast Startup Input Polarity 10 */ 1453 uint32_t FSTP11:1; /**< bit: 11 Fast Startup Input Polarity 11 */ 1454 uint32_t FSTP12:1; /**< bit: 12 Fast Startup Input Polarity 12 */ 1455 uint32_t FSTP13:1; /**< bit: 13 Fast Startup Input Polarity 13 */ 1456 uint32_t FSTP14:1; /**< bit: 14 Fast Startup Input Polarity 14 */ 1457 uint32_t FSTP15:1; /**< bit: 15 Fast Startup Input Polarity 15 */ 1458 uint32_t :16; /**< bit: 16..31 Reserved */ 1459 } bit; /**< Structure used for bit access */ 1460 struct { 1461 uint32_t FSTP:16; /**< bit: 0..15 Fast Startup Input Polarity x5 */ 1462 uint32_t :16; /**< bit: 16..31 Reserved */ 1463 } vec; /**< Structure used for vec access */ 1464 uint32_t reg; /**< Type used for register access */ 1465 } PMC_FSPR_Type; 1466 #endif 1467 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1468 1469 #define PMC_FSPR_OFFSET (0x74) /**< (PMC_FSPR) Fast Startup Polarity Register Offset */ 1470 1471 #define PMC_FSPR_FSTP0_Pos 0 /**< (PMC_FSPR) Fast Startup Input Polarity 0 Position */ 1472 #define PMC_FSPR_FSTP0_Msk (_U_(0x1) << PMC_FSPR_FSTP0_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Mask */ 1473 #define PMC_FSPR_FSTP0 PMC_FSPR_FSTP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP0_Msk instead */ 1474 #define PMC_FSPR_FSTP1_Pos 1 /**< (PMC_FSPR) Fast Startup Input Polarity 1 Position */ 1475 #define PMC_FSPR_FSTP1_Msk (_U_(0x1) << PMC_FSPR_FSTP1_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Mask */ 1476 #define PMC_FSPR_FSTP1 PMC_FSPR_FSTP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP1_Msk instead */ 1477 #define PMC_FSPR_FSTP2_Pos 2 /**< (PMC_FSPR) Fast Startup Input Polarity 2 Position */ 1478 #define PMC_FSPR_FSTP2_Msk (_U_(0x1) << PMC_FSPR_FSTP2_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Mask */ 1479 #define PMC_FSPR_FSTP2 PMC_FSPR_FSTP2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP2_Msk instead */ 1480 #define PMC_FSPR_FSTP3_Pos 3 /**< (PMC_FSPR) Fast Startup Input Polarity 3 Position */ 1481 #define PMC_FSPR_FSTP3_Msk (_U_(0x1) << PMC_FSPR_FSTP3_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Mask */ 1482 #define PMC_FSPR_FSTP3 PMC_FSPR_FSTP3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP3_Msk instead */ 1483 #define PMC_FSPR_FSTP4_Pos 4 /**< (PMC_FSPR) Fast Startup Input Polarity 4 Position */ 1484 #define PMC_FSPR_FSTP4_Msk (_U_(0x1) << PMC_FSPR_FSTP4_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Mask */ 1485 #define PMC_FSPR_FSTP4 PMC_FSPR_FSTP4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP4_Msk instead */ 1486 #define PMC_FSPR_FSTP5_Pos 5 /**< (PMC_FSPR) Fast Startup Input Polarity 5 Position */ 1487 #define PMC_FSPR_FSTP5_Msk (_U_(0x1) << PMC_FSPR_FSTP5_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Mask */ 1488 #define PMC_FSPR_FSTP5 PMC_FSPR_FSTP5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP5_Msk instead */ 1489 #define PMC_FSPR_FSTP6_Pos 6 /**< (PMC_FSPR) Fast Startup Input Polarity 6 Position */ 1490 #define PMC_FSPR_FSTP6_Msk (_U_(0x1) << PMC_FSPR_FSTP6_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Mask */ 1491 #define PMC_FSPR_FSTP6 PMC_FSPR_FSTP6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP6_Msk instead */ 1492 #define PMC_FSPR_FSTP7_Pos 7 /**< (PMC_FSPR) Fast Startup Input Polarity 7 Position */ 1493 #define PMC_FSPR_FSTP7_Msk (_U_(0x1) << PMC_FSPR_FSTP7_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Mask */ 1494 #define PMC_FSPR_FSTP7 PMC_FSPR_FSTP7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP7_Msk instead */ 1495 #define PMC_FSPR_FSTP8_Pos 8 /**< (PMC_FSPR) Fast Startup Input Polarity 8 Position */ 1496 #define PMC_FSPR_FSTP8_Msk (_U_(0x1) << PMC_FSPR_FSTP8_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Mask */ 1497 #define PMC_FSPR_FSTP8 PMC_FSPR_FSTP8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP8_Msk instead */ 1498 #define PMC_FSPR_FSTP9_Pos 9 /**< (PMC_FSPR) Fast Startup Input Polarity 9 Position */ 1499 #define PMC_FSPR_FSTP9_Msk (_U_(0x1) << PMC_FSPR_FSTP9_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Mask */ 1500 #define PMC_FSPR_FSTP9 PMC_FSPR_FSTP9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP9_Msk instead */ 1501 #define PMC_FSPR_FSTP10_Pos 10 /**< (PMC_FSPR) Fast Startup Input Polarity 10 Position */ 1502 #define PMC_FSPR_FSTP10_Msk (_U_(0x1) << PMC_FSPR_FSTP10_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Mask */ 1503 #define PMC_FSPR_FSTP10 PMC_FSPR_FSTP10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP10_Msk instead */ 1504 #define PMC_FSPR_FSTP11_Pos 11 /**< (PMC_FSPR) Fast Startup Input Polarity 11 Position */ 1505 #define PMC_FSPR_FSTP11_Msk (_U_(0x1) << PMC_FSPR_FSTP11_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Mask */ 1506 #define PMC_FSPR_FSTP11 PMC_FSPR_FSTP11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP11_Msk instead */ 1507 #define PMC_FSPR_FSTP12_Pos 12 /**< (PMC_FSPR) Fast Startup Input Polarity 12 Position */ 1508 #define PMC_FSPR_FSTP12_Msk (_U_(0x1) << PMC_FSPR_FSTP12_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Mask */ 1509 #define PMC_FSPR_FSTP12 PMC_FSPR_FSTP12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP12_Msk instead */ 1510 #define PMC_FSPR_FSTP13_Pos 13 /**< (PMC_FSPR) Fast Startup Input Polarity 13 Position */ 1511 #define PMC_FSPR_FSTP13_Msk (_U_(0x1) << PMC_FSPR_FSTP13_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Mask */ 1512 #define PMC_FSPR_FSTP13 PMC_FSPR_FSTP13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP13_Msk instead */ 1513 #define PMC_FSPR_FSTP14_Pos 14 /**< (PMC_FSPR) Fast Startup Input Polarity 14 Position */ 1514 #define PMC_FSPR_FSTP14_Msk (_U_(0x1) << PMC_FSPR_FSTP14_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Mask */ 1515 #define PMC_FSPR_FSTP14 PMC_FSPR_FSTP14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP14_Msk instead */ 1516 #define PMC_FSPR_FSTP15_Pos 15 /**< (PMC_FSPR) Fast Startup Input Polarity 15 Position */ 1517 #define PMC_FSPR_FSTP15_Msk (_U_(0x1) << PMC_FSPR_FSTP15_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Mask */ 1518 #define PMC_FSPR_FSTP15 PMC_FSPR_FSTP15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP15_Msk instead */ 1519 #define PMC_FSPR_MASK _U_(0xFFFF) /**< \deprecated (PMC_FSPR) Register MASK (Use PMC_FSPR_Msk instead) */ 1520 #define PMC_FSPR_Msk _U_(0xFFFF) /**< (PMC_FSPR) Register Mask */ 1521 1522 #define PMC_FSPR_FSTP_Pos 0 /**< (PMC_FSPR Position) Fast Startup Input Polarity x5 */ 1523 #define PMC_FSPR_FSTP_Msk (_U_(0xFFFF) << PMC_FSPR_FSTP_Pos) /**< (PMC_FSPR Mask) FSTP */ 1524 #define PMC_FSPR_FSTP(value) (PMC_FSPR_FSTP_Msk & ((value) << PMC_FSPR_FSTP_Pos)) 1525 1526 /* -------- PMC_FOCR : (PMC Offset: 0x78) (/W 32) Fault Output Clear Register -------- */ 1527 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1528 #if COMPONENT_TYPEDEF_STYLE == 'N' 1529 typedef union { 1530 struct { 1531 uint32_t FOCLR:1; /**< bit: 0 Fault Output Clear */ 1532 uint32_t :31; /**< bit: 1..31 Reserved */ 1533 } bit; /**< Structure used for bit access */ 1534 uint32_t reg; /**< Type used for register access */ 1535 } PMC_FOCR_Type; 1536 #endif 1537 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1538 1539 #define PMC_FOCR_OFFSET (0x78) /**< (PMC_FOCR) Fault Output Clear Register Offset */ 1540 1541 #define PMC_FOCR_FOCLR_Pos 0 /**< (PMC_FOCR) Fault Output Clear Position */ 1542 #define PMC_FOCR_FOCLR_Msk (_U_(0x1) << PMC_FOCR_FOCLR_Pos) /**< (PMC_FOCR) Fault Output Clear Mask */ 1543 #define PMC_FOCR_FOCLR PMC_FOCR_FOCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FOCR_FOCLR_Msk instead */ 1544 #define PMC_FOCR_MASK _U_(0x01) /**< \deprecated (PMC_FOCR) Register MASK (Use PMC_FOCR_Msk instead) */ 1545 #define PMC_FOCR_Msk _U_(0x01) /**< (PMC_FOCR) Register Mask */ 1546 1547 1548 /* -------- PMC_WPMR : (PMC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 1549 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1550 #if COMPONENT_TYPEDEF_STYLE == 'N' 1551 typedef union { 1552 struct { 1553 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 1554 uint32_t :7; /**< bit: 1..7 Reserved */ 1555 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 1556 } bit; /**< Structure used for bit access */ 1557 uint32_t reg; /**< Type used for register access */ 1558 } PMC_WPMR_Type; 1559 #endif 1560 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1561 1562 #define PMC_WPMR_OFFSET (0xE4) /**< (PMC_WPMR) Write Protection Mode Register Offset */ 1563 1564 #define PMC_WPMR_WPEN_Pos 0 /**< (PMC_WPMR) Write Protection Enable Position */ 1565 #define PMC_WPMR_WPEN_Msk (_U_(0x1) << PMC_WPMR_WPEN_Pos) /**< (PMC_WPMR) Write Protection Enable Mask */ 1566 #define PMC_WPMR_WPEN PMC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_WPMR_WPEN_Msk instead */ 1567 #define PMC_WPMR_WPKEY_Pos 8 /**< (PMC_WPMR) Write Protection Key Position */ 1568 #define PMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Write Protection Key Mask */ 1569 #define PMC_WPMR_WPKEY(value) (PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)) 1570 #define PMC_WPMR_WPKEY_PASSWD_Val _U_(0x504D43) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ 1571 #define PMC_WPMR_WPKEY_PASSWD (PMC_WPMR_WPKEY_PASSWD_Val << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ 1572 #define PMC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (PMC_WPMR) Register MASK (Use PMC_WPMR_Msk instead) */ 1573 #define PMC_WPMR_Msk _U_(0xFFFFFF01) /**< (PMC_WPMR) Register Mask */ 1574 1575 1576 /* -------- PMC_WPSR : (PMC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 1577 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1578 #if COMPONENT_TYPEDEF_STYLE == 'N' 1579 typedef union { 1580 struct { 1581 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 1582 uint32_t :7; /**< bit: 1..7 Reserved */ 1583 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 1584 uint32_t :8; /**< bit: 24..31 Reserved */ 1585 } bit; /**< Structure used for bit access */ 1586 uint32_t reg; /**< Type used for register access */ 1587 } PMC_WPSR_Type; 1588 #endif 1589 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1590 1591 #define PMC_WPSR_OFFSET (0xE8) /**< (PMC_WPSR) Write Protection Status Register Offset */ 1592 1593 #define PMC_WPSR_WPVS_Pos 0 /**< (PMC_WPSR) Write Protection Violation Status Position */ 1594 #define PMC_WPSR_WPVS_Msk (_U_(0x1) << PMC_WPSR_WPVS_Pos) /**< (PMC_WPSR) Write Protection Violation Status Mask */ 1595 #define PMC_WPSR_WPVS PMC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_WPSR_WPVS_Msk instead */ 1596 #define PMC_WPSR_WPVSRC_Pos 8 /**< (PMC_WPSR) Write Protection Violation Source Position */ 1597 #define PMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PMC_WPSR_WPVSRC_Pos) /**< (PMC_WPSR) Write Protection Violation Source Mask */ 1598 #define PMC_WPSR_WPVSRC(value) (PMC_WPSR_WPVSRC_Msk & ((value) << PMC_WPSR_WPVSRC_Pos)) 1599 #define PMC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (PMC_WPSR) Register MASK (Use PMC_WPSR_Msk instead) */ 1600 #define PMC_WPSR_Msk _U_(0xFFFF01) /**< (PMC_WPSR) Register Mask */ 1601 1602 1603 /* -------- PMC_PCER1 : (PMC Offset: 0x100) (/W 32) Peripheral Clock Enable Register 1 -------- */ 1604 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1605 #if COMPONENT_TYPEDEF_STYLE == 'N' 1606 typedef union { 1607 struct { 1608 uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Enable */ 1609 uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Enable */ 1610 uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Enable */ 1611 uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Enable */ 1612 uint32_t :1; /**< bit: 4 Reserved */ 1613 uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Enable */ 1614 uint32_t :1; /**< bit: 6 Reserved */ 1615 uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Enable */ 1616 uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Enable */ 1617 uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Enable */ 1618 uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Enable */ 1619 uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Enable */ 1620 uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Enable */ 1621 uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Enable */ 1622 uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Enable */ 1623 uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Enable */ 1624 uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Enable */ 1625 uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Enable */ 1626 uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Enable */ 1627 uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Enable */ 1628 uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Enable */ 1629 uint32_t PID53:1; /**< bit: 21 Peripheral Clock 53 Enable */ 1630 uint32_t :2; /**< bit: 22..23 Reserved */ 1631 uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Enable */ 1632 uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Enable */ 1633 uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Enable */ 1634 uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Enable */ 1635 uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Enable */ 1636 uint32_t :3; /**< bit: 29..31 Reserved */ 1637 } bit; /**< Structure used for bit access */ 1638 struct { 1639 uint32_t PID:25; /**< bit: 0..24 Peripheral Clock 6x Enable */ 1640 uint32_t :7; /**< bit: 25..31 Reserved */ 1641 } vec; /**< Structure used for vec access */ 1642 uint32_t reg; /**< Type used for register access */ 1643 } PMC_PCER1_Type; 1644 #endif 1645 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1646 1647 #define PMC_PCER1_OFFSET (0x100) /**< (PMC_PCER1) Peripheral Clock Enable Register 1 Offset */ 1648 1649 #define PMC_PCER1_PID32_Pos 0 /**< (PMC_PCER1) Peripheral Clock 32 Enable Position */ 1650 #define PMC_PCER1_PID32_Msk (_U_(0x1) << PMC_PCER1_PID32_Pos) /**< (PMC_PCER1) Peripheral Clock 32 Enable Mask */ 1651 #define PMC_PCER1_PID32 PMC_PCER1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID32_Msk instead */ 1652 #define PMC_PCER1_PID33_Pos 1 /**< (PMC_PCER1) Peripheral Clock 33 Enable Position */ 1653 #define PMC_PCER1_PID33_Msk (_U_(0x1) << PMC_PCER1_PID33_Pos) /**< (PMC_PCER1) Peripheral Clock 33 Enable Mask */ 1654 #define PMC_PCER1_PID33 PMC_PCER1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID33_Msk instead */ 1655 #define PMC_PCER1_PID34_Pos 2 /**< (PMC_PCER1) Peripheral Clock 34 Enable Position */ 1656 #define PMC_PCER1_PID34_Msk (_U_(0x1) << PMC_PCER1_PID34_Pos) /**< (PMC_PCER1) Peripheral Clock 34 Enable Mask */ 1657 #define PMC_PCER1_PID34 PMC_PCER1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID34_Msk instead */ 1658 #define PMC_PCER1_PID35_Pos 3 /**< (PMC_PCER1) Peripheral Clock 35 Enable Position */ 1659 #define PMC_PCER1_PID35_Msk (_U_(0x1) << PMC_PCER1_PID35_Pos) /**< (PMC_PCER1) Peripheral Clock 35 Enable Mask */ 1660 #define PMC_PCER1_PID35 PMC_PCER1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID35_Msk instead */ 1661 #define PMC_PCER1_PID37_Pos 5 /**< (PMC_PCER1) Peripheral Clock 37 Enable Position */ 1662 #define PMC_PCER1_PID37_Msk (_U_(0x1) << PMC_PCER1_PID37_Pos) /**< (PMC_PCER1) Peripheral Clock 37 Enable Mask */ 1663 #define PMC_PCER1_PID37 PMC_PCER1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID37_Msk instead */ 1664 #define PMC_PCER1_PID39_Pos 7 /**< (PMC_PCER1) Peripheral Clock 39 Enable Position */ 1665 #define PMC_PCER1_PID39_Msk (_U_(0x1) << PMC_PCER1_PID39_Pos) /**< (PMC_PCER1) Peripheral Clock 39 Enable Mask */ 1666 #define PMC_PCER1_PID39 PMC_PCER1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID39_Msk instead */ 1667 #define PMC_PCER1_PID40_Pos 8 /**< (PMC_PCER1) Peripheral Clock 40 Enable Position */ 1668 #define PMC_PCER1_PID40_Msk (_U_(0x1) << PMC_PCER1_PID40_Pos) /**< (PMC_PCER1) Peripheral Clock 40 Enable Mask */ 1669 #define PMC_PCER1_PID40 PMC_PCER1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID40_Msk instead */ 1670 #define PMC_PCER1_PID41_Pos 9 /**< (PMC_PCER1) Peripheral Clock 41 Enable Position */ 1671 #define PMC_PCER1_PID41_Msk (_U_(0x1) << PMC_PCER1_PID41_Pos) /**< (PMC_PCER1) Peripheral Clock 41 Enable Mask */ 1672 #define PMC_PCER1_PID41 PMC_PCER1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID41_Msk instead */ 1673 #define PMC_PCER1_PID42_Pos 10 /**< (PMC_PCER1) Peripheral Clock 42 Enable Position */ 1674 #define PMC_PCER1_PID42_Msk (_U_(0x1) << PMC_PCER1_PID42_Pos) /**< (PMC_PCER1) Peripheral Clock 42 Enable Mask */ 1675 #define PMC_PCER1_PID42 PMC_PCER1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID42_Msk instead */ 1676 #define PMC_PCER1_PID43_Pos 11 /**< (PMC_PCER1) Peripheral Clock 43 Enable Position */ 1677 #define PMC_PCER1_PID43_Msk (_U_(0x1) << PMC_PCER1_PID43_Pos) /**< (PMC_PCER1) Peripheral Clock 43 Enable Mask */ 1678 #define PMC_PCER1_PID43 PMC_PCER1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID43_Msk instead */ 1679 #define PMC_PCER1_PID44_Pos 12 /**< (PMC_PCER1) Peripheral Clock 44 Enable Position */ 1680 #define PMC_PCER1_PID44_Msk (_U_(0x1) << PMC_PCER1_PID44_Pos) /**< (PMC_PCER1) Peripheral Clock 44 Enable Mask */ 1681 #define PMC_PCER1_PID44 PMC_PCER1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID44_Msk instead */ 1682 #define PMC_PCER1_PID45_Pos 13 /**< (PMC_PCER1) Peripheral Clock 45 Enable Position */ 1683 #define PMC_PCER1_PID45_Msk (_U_(0x1) << PMC_PCER1_PID45_Pos) /**< (PMC_PCER1) Peripheral Clock 45 Enable Mask */ 1684 #define PMC_PCER1_PID45 PMC_PCER1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID45_Msk instead */ 1685 #define PMC_PCER1_PID46_Pos 14 /**< (PMC_PCER1) Peripheral Clock 46 Enable Position */ 1686 #define PMC_PCER1_PID46_Msk (_U_(0x1) << PMC_PCER1_PID46_Pos) /**< (PMC_PCER1) Peripheral Clock 46 Enable Mask */ 1687 #define PMC_PCER1_PID46 PMC_PCER1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID46_Msk instead */ 1688 #define PMC_PCER1_PID47_Pos 15 /**< (PMC_PCER1) Peripheral Clock 47 Enable Position */ 1689 #define PMC_PCER1_PID47_Msk (_U_(0x1) << PMC_PCER1_PID47_Pos) /**< (PMC_PCER1) Peripheral Clock 47 Enable Mask */ 1690 #define PMC_PCER1_PID47 PMC_PCER1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID47_Msk instead */ 1691 #define PMC_PCER1_PID48_Pos 16 /**< (PMC_PCER1) Peripheral Clock 48 Enable Position */ 1692 #define PMC_PCER1_PID48_Msk (_U_(0x1) << PMC_PCER1_PID48_Pos) /**< (PMC_PCER1) Peripheral Clock 48 Enable Mask */ 1693 #define PMC_PCER1_PID48 PMC_PCER1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID48_Msk instead */ 1694 #define PMC_PCER1_PID49_Pos 17 /**< (PMC_PCER1) Peripheral Clock 49 Enable Position */ 1695 #define PMC_PCER1_PID49_Msk (_U_(0x1) << PMC_PCER1_PID49_Pos) /**< (PMC_PCER1) Peripheral Clock 49 Enable Mask */ 1696 #define PMC_PCER1_PID49 PMC_PCER1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID49_Msk instead */ 1697 #define PMC_PCER1_PID50_Pos 18 /**< (PMC_PCER1) Peripheral Clock 50 Enable Position */ 1698 #define PMC_PCER1_PID50_Msk (_U_(0x1) << PMC_PCER1_PID50_Pos) /**< (PMC_PCER1) Peripheral Clock 50 Enable Mask */ 1699 #define PMC_PCER1_PID50 PMC_PCER1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID50_Msk instead */ 1700 #define PMC_PCER1_PID51_Pos 19 /**< (PMC_PCER1) Peripheral Clock 51 Enable Position */ 1701 #define PMC_PCER1_PID51_Msk (_U_(0x1) << PMC_PCER1_PID51_Pos) /**< (PMC_PCER1) Peripheral Clock 51 Enable Mask */ 1702 #define PMC_PCER1_PID51 PMC_PCER1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID51_Msk instead */ 1703 #define PMC_PCER1_PID52_Pos 20 /**< (PMC_PCER1) Peripheral Clock 52 Enable Position */ 1704 #define PMC_PCER1_PID52_Msk (_U_(0x1) << PMC_PCER1_PID52_Pos) /**< (PMC_PCER1) Peripheral Clock 52 Enable Mask */ 1705 #define PMC_PCER1_PID52 PMC_PCER1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID52_Msk instead */ 1706 #define PMC_PCER1_PID53_Pos 21 /**< (PMC_PCER1) Peripheral Clock 53 Enable Position */ 1707 #define PMC_PCER1_PID53_Msk (_U_(0x1) << PMC_PCER1_PID53_Pos) /**< (PMC_PCER1) Peripheral Clock 53 Enable Mask */ 1708 #define PMC_PCER1_PID53 PMC_PCER1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID53_Msk instead */ 1709 #define PMC_PCER1_PID56_Pos 24 /**< (PMC_PCER1) Peripheral Clock 56 Enable Position */ 1710 #define PMC_PCER1_PID56_Msk (_U_(0x1) << PMC_PCER1_PID56_Pos) /**< (PMC_PCER1) Peripheral Clock 56 Enable Mask */ 1711 #define PMC_PCER1_PID56 PMC_PCER1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID56_Msk instead */ 1712 #define PMC_PCER1_PID57_Pos 25 /**< (PMC_PCER1) Peripheral Clock 57 Enable Position */ 1713 #define PMC_PCER1_PID57_Msk (_U_(0x1) << PMC_PCER1_PID57_Pos) /**< (PMC_PCER1) Peripheral Clock 57 Enable Mask */ 1714 #define PMC_PCER1_PID57 PMC_PCER1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID57_Msk instead */ 1715 #define PMC_PCER1_PID58_Pos 26 /**< (PMC_PCER1) Peripheral Clock 58 Enable Position */ 1716 #define PMC_PCER1_PID58_Msk (_U_(0x1) << PMC_PCER1_PID58_Pos) /**< (PMC_PCER1) Peripheral Clock 58 Enable Mask */ 1717 #define PMC_PCER1_PID58 PMC_PCER1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID58_Msk instead */ 1718 #define PMC_PCER1_PID59_Pos 27 /**< (PMC_PCER1) Peripheral Clock 59 Enable Position */ 1719 #define PMC_PCER1_PID59_Msk (_U_(0x1) << PMC_PCER1_PID59_Pos) /**< (PMC_PCER1) Peripheral Clock 59 Enable Mask */ 1720 #define PMC_PCER1_PID59 PMC_PCER1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID59_Msk instead */ 1721 #define PMC_PCER1_PID60_Pos 28 /**< (PMC_PCER1) Peripheral Clock 60 Enable Position */ 1722 #define PMC_PCER1_PID60_Msk (_U_(0x1) << PMC_PCER1_PID60_Pos) /**< (PMC_PCER1) Peripheral Clock 60 Enable Mask */ 1723 #define PMC_PCER1_PID60 PMC_PCER1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID60_Msk instead */ 1724 #define PMC_PCER1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_PCER1) Register MASK (Use PMC_PCER1_Msk instead) */ 1725 #define PMC_PCER1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCER1) Register Mask */ 1726 1727 #define PMC_PCER1_PID_Pos 0 /**< (PMC_PCER1 Position) Peripheral Clock 6x Enable */ 1728 #define PMC_PCER1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER1_PID_Pos) /**< (PMC_PCER1 Mask) PID */ 1729 #define PMC_PCER1_PID(value) (PMC_PCER1_PID_Msk & ((value) << PMC_PCER1_PID_Pos)) 1730 1731 /* -------- PMC_PCDR1 : (PMC Offset: 0x104) (/W 32) Peripheral Clock Disable Register 1 -------- */ 1732 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1733 #if COMPONENT_TYPEDEF_STYLE == 'N' 1734 typedef union { 1735 struct { 1736 uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Disable */ 1737 uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Disable */ 1738 uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Disable */ 1739 uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Disable */ 1740 uint32_t :1; /**< bit: 4 Reserved */ 1741 uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Disable */ 1742 uint32_t :1; /**< bit: 6 Reserved */ 1743 uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Disable */ 1744 uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Disable */ 1745 uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Disable */ 1746 uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Disable */ 1747 uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Disable */ 1748 uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Disable */ 1749 uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Disable */ 1750 uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Disable */ 1751 uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Disable */ 1752 uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Disable */ 1753 uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Disable */ 1754 uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Disable */ 1755 uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Disable */ 1756 uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Disable */ 1757 uint32_t PID53:1; /**< bit: 21 Peripheral Clock 53 Disable */ 1758 uint32_t :2; /**< bit: 22..23 Reserved */ 1759 uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Disable */ 1760 uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Disable */ 1761 uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Disable */ 1762 uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Disable */ 1763 uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Disable */ 1764 uint32_t :3; /**< bit: 29..31 Reserved */ 1765 } bit; /**< Structure used for bit access */ 1766 struct { 1767 uint32_t PID:25; /**< bit: 0..24 Peripheral Clock 6x Disable */ 1768 uint32_t :7; /**< bit: 25..31 Reserved */ 1769 } vec; /**< Structure used for vec access */ 1770 uint32_t reg; /**< Type used for register access */ 1771 } PMC_PCDR1_Type; 1772 #endif 1773 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1774 1775 #define PMC_PCDR1_OFFSET (0x104) /**< (PMC_PCDR1) Peripheral Clock Disable Register 1 Offset */ 1776 1777 #define PMC_PCDR1_PID32_Pos 0 /**< (PMC_PCDR1) Peripheral Clock 32 Disable Position */ 1778 #define PMC_PCDR1_PID32_Msk (_U_(0x1) << PMC_PCDR1_PID32_Pos) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Mask */ 1779 #define PMC_PCDR1_PID32 PMC_PCDR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID32_Msk instead */ 1780 #define PMC_PCDR1_PID33_Pos 1 /**< (PMC_PCDR1) Peripheral Clock 33 Disable Position */ 1781 #define PMC_PCDR1_PID33_Msk (_U_(0x1) << PMC_PCDR1_PID33_Pos) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Mask */ 1782 #define PMC_PCDR1_PID33 PMC_PCDR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID33_Msk instead */ 1783 #define PMC_PCDR1_PID34_Pos 2 /**< (PMC_PCDR1) Peripheral Clock 34 Disable Position */ 1784 #define PMC_PCDR1_PID34_Msk (_U_(0x1) << PMC_PCDR1_PID34_Pos) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Mask */ 1785 #define PMC_PCDR1_PID34 PMC_PCDR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID34_Msk instead */ 1786 #define PMC_PCDR1_PID35_Pos 3 /**< (PMC_PCDR1) Peripheral Clock 35 Disable Position */ 1787 #define PMC_PCDR1_PID35_Msk (_U_(0x1) << PMC_PCDR1_PID35_Pos) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Mask */ 1788 #define PMC_PCDR1_PID35 PMC_PCDR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID35_Msk instead */ 1789 #define PMC_PCDR1_PID37_Pos 5 /**< (PMC_PCDR1) Peripheral Clock 37 Disable Position */ 1790 #define PMC_PCDR1_PID37_Msk (_U_(0x1) << PMC_PCDR1_PID37_Pos) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Mask */ 1791 #define PMC_PCDR1_PID37 PMC_PCDR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID37_Msk instead */ 1792 #define PMC_PCDR1_PID39_Pos 7 /**< (PMC_PCDR1) Peripheral Clock 39 Disable Position */ 1793 #define PMC_PCDR1_PID39_Msk (_U_(0x1) << PMC_PCDR1_PID39_Pos) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Mask */ 1794 #define PMC_PCDR1_PID39 PMC_PCDR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID39_Msk instead */ 1795 #define PMC_PCDR1_PID40_Pos 8 /**< (PMC_PCDR1) Peripheral Clock 40 Disable Position */ 1796 #define PMC_PCDR1_PID40_Msk (_U_(0x1) << PMC_PCDR1_PID40_Pos) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Mask */ 1797 #define PMC_PCDR1_PID40 PMC_PCDR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID40_Msk instead */ 1798 #define PMC_PCDR1_PID41_Pos 9 /**< (PMC_PCDR1) Peripheral Clock 41 Disable Position */ 1799 #define PMC_PCDR1_PID41_Msk (_U_(0x1) << PMC_PCDR1_PID41_Pos) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Mask */ 1800 #define PMC_PCDR1_PID41 PMC_PCDR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID41_Msk instead */ 1801 #define PMC_PCDR1_PID42_Pos 10 /**< (PMC_PCDR1) Peripheral Clock 42 Disable Position */ 1802 #define PMC_PCDR1_PID42_Msk (_U_(0x1) << PMC_PCDR1_PID42_Pos) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Mask */ 1803 #define PMC_PCDR1_PID42 PMC_PCDR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID42_Msk instead */ 1804 #define PMC_PCDR1_PID43_Pos 11 /**< (PMC_PCDR1) Peripheral Clock 43 Disable Position */ 1805 #define PMC_PCDR1_PID43_Msk (_U_(0x1) << PMC_PCDR1_PID43_Pos) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Mask */ 1806 #define PMC_PCDR1_PID43 PMC_PCDR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID43_Msk instead */ 1807 #define PMC_PCDR1_PID44_Pos 12 /**< (PMC_PCDR1) Peripheral Clock 44 Disable Position */ 1808 #define PMC_PCDR1_PID44_Msk (_U_(0x1) << PMC_PCDR1_PID44_Pos) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Mask */ 1809 #define PMC_PCDR1_PID44 PMC_PCDR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID44_Msk instead */ 1810 #define PMC_PCDR1_PID45_Pos 13 /**< (PMC_PCDR1) Peripheral Clock 45 Disable Position */ 1811 #define PMC_PCDR1_PID45_Msk (_U_(0x1) << PMC_PCDR1_PID45_Pos) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Mask */ 1812 #define PMC_PCDR1_PID45 PMC_PCDR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID45_Msk instead */ 1813 #define PMC_PCDR1_PID46_Pos 14 /**< (PMC_PCDR1) Peripheral Clock 46 Disable Position */ 1814 #define PMC_PCDR1_PID46_Msk (_U_(0x1) << PMC_PCDR1_PID46_Pos) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Mask */ 1815 #define PMC_PCDR1_PID46 PMC_PCDR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID46_Msk instead */ 1816 #define PMC_PCDR1_PID47_Pos 15 /**< (PMC_PCDR1) Peripheral Clock 47 Disable Position */ 1817 #define PMC_PCDR1_PID47_Msk (_U_(0x1) << PMC_PCDR1_PID47_Pos) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Mask */ 1818 #define PMC_PCDR1_PID47 PMC_PCDR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID47_Msk instead */ 1819 #define PMC_PCDR1_PID48_Pos 16 /**< (PMC_PCDR1) Peripheral Clock 48 Disable Position */ 1820 #define PMC_PCDR1_PID48_Msk (_U_(0x1) << PMC_PCDR1_PID48_Pos) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Mask */ 1821 #define PMC_PCDR1_PID48 PMC_PCDR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID48_Msk instead */ 1822 #define PMC_PCDR1_PID49_Pos 17 /**< (PMC_PCDR1) Peripheral Clock 49 Disable Position */ 1823 #define PMC_PCDR1_PID49_Msk (_U_(0x1) << PMC_PCDR1_PID49_Pos) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Mask */ 1824 #define PMC_PCDR1_PID49 PMC_PCDR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID49_Msk instead */ 1825 #define PMC_PCDR1_PID50_Pos 18 /**< (PMC_PCDR1) Peripheral Clock 50 Disable Position */ 1826 #define PMC_PCDR1_PID50_Msk (_U_(0x1) << PMC_PCDR1_PID50_Pos) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Mask */ 1827 #define PMC_PCDR1_PID50 PMC_PCDR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID50_Msk instead */ 1828 #define PMC_PCDR1_PID51_Pos 19 /**< (PMC_PCDR1) Peripheral Clock 51 Disable Position */ 1829 #define PMC_PCDR1_PID51_Msk (_U_(0x1) << PMC_PCDR1_PID51_Pos) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Mask */ 1830 #define PMC_PCDR1_PID51 PMC_PCDR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID51_Msk instead */ 1831 #define PMC_PCDR1_PID52_Pos 20 /**< (PMC_PCDR1) Peripheral Clock 52 Disable Position */ 1832 #define PMC_PCDR1_PID52_Msk (_U_(0x1) << PMC_PCDR1_PID52_Pos) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Mask */ 1833 #define PMC_PCDR1_PID52 PMC_PCDR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID52_Msk instead */ 1834 #define PMC_PCDR1_PID53_Pos 21 /**< (PMC_PCDR1) Peripheral Clock 53 Disable Position */ 1835 #define PMC_PCDR1_PID53_Msk (_U_(0x1) << PMC_PCDR1_PID53_Pos) /**< (PMC_PCDR1) Peripheral Clock 53 Disable Mask */ 1836 #define PMC_PCDR1_PID53 PMC_PCDR1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID53_Msk instead */ 1837 #define PMC_PCDR1_PID56_Pos 24 /**< (PMC_PCDR1) Peripheral Clock 56 Disable Position */ 1838 #define PMC_PCDR1_PID56_Msk (_U_(0x1) << PMC_PCDR1_PID56_Pos) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Mask */ 1839 #define PMC_PCDR1_PID56 PMC_PCDR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID56_Msk instead */ 1840 #define PMC_PCDR1_PID57_Pos 25 /**< (PMC_PCDR1) Peripheral Clock 57 Disable Position */ 1841 #define PMC_PCDR1_PID57_Msk (_U_(0x1) << PMC_PCDR1_PID57_Pos) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Mask */ 1842 #define PMC_PCDR1_PID57 PMC_PCDR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID57_Msk instead */ 1843 #define PMC_PCDR1_PID58_Pos 26 /**< (PMC_PCDR1) Peripheral Clock 58 Disable Position */ 1844 #define PMC_PCDR1_PID58_Msk (_U_(0x1) << PMC_PCDR1_PID58_Pos) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Mask */ 1845 #define PMC_PCDR1_PID58 PMC_PCDR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID58_Msk instead */ 1846 #define PMC_PCDR1_PID59_Pos 27 /**< (PMC_PCDR1) Peripheral Clock 59 Disable Position */ 1847 #define PMC_PCDR1_PID59_Msk (_U_(0x1) << PMC_PCDR1_PID59_Pos) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Mask */ 1848 #define PMC_PCDR1_PID59 PMC_PCDR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID59_Msk instead */ 1849 #define PMC_PCDR1_PID60_Pos 28 /**< (PMC_PCDR1) Peripheral Clock 60 Disable Position */ 1850 #define PMC_PCDR1_PID60_Msk (_U_(0x1) << PMC_PCDR1_PID60_Pos) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Mask */ 1851 #define PMC_PCDR1_PID60 PMC_PCDR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID60_Msk instead */ 1852 #define PMC_PCDR1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_PCDR1) Register MASK (Use PMC_PCDR1_Msk instead) */ 1853 #define PMC_PCDR1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCDR1) Register Mask */ 1854 1855 #define PMC_PCDR1_PID_Pos 0 /**< (PMC_PCDR1 Position) Peripheral Clock 6x Disable */ 1856 #define PMC_PCDR1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR1_PID_Pos) /**< (PMC_PCDR1 Mask) PID */ 1857 #define PMC_PCDR1_PID(value) (PMC_PCDR1_PID_Msk & ((value) << PMC_PCDR1_PID_Pos)) 1858 1859 /* -------- PMC_PCSR1 : (PMC Offset: 0x108) (R/ 32) Peripheral Clock Status Register 1 -------- */ 1860 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1861 #if COMPONENT_TYPEDEF_STYLE == 'N' 1862 typedef union { 1863 struct { 1864 uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Status */ 1865 uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Status */ 1866 uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Status */ 1867 uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Status */ 1868 uint32_t :1; /**< bit: 4 Reserved */ 1869 uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Status */ 1870 uint32_t :1; /**< bit: 6 Reserved */ 1871 uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Status */ 1872 uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Status */ 1873 uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Status */ 1874 uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Status */ 1875 uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Status */ 1876 uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Status */ 1877 uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Status */ 1878 uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Status */ 1879 uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Status */ 1880 uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Status */ 1881 uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Status */ 1882 uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Status */ 1883 uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Status */ 1884 uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Status */ 1885 uint32_t PID53:1; /**< bit: 21 Peripheral Clock 53 Status */ 1886 uint32_t :2; /**< bit: 22..23 Reserved */ 1887 uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Status */ 1888 uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Status */ 1889 uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Status */ 1890 uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Status */ 1891 uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Status */ 1892 uint32_t :3; /**< bit: 29..31 Reserved */ 1893 } bit; /**< Structure used for bit access */ 1894 struct { 1895 uint32_t PID:25; /**< bit: 0..24 Peripheral Clock 6x Status */ 1896 uint32_t :7; /**< bit: 25..31 Reserved */ 1897 } vec; /**< Structure used for vec access */ 1898 uint32_t reg; /**< Type used for register access */ 1899 } PMC_PCSR1_Type; 1900 #endif 1901 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1902 1903 #define PMC_PCSR1_OFFSET (0x108) /**< (PMC_PCSR1) Peripheral Clock Status Register 1 Offset */ 1904 1905 #define PMC_PCSR1_PID32_Pos 0 /**< (PMC_PCSR1) Peripheral Clock 32 Status Position */ 1906 #define PMC_PCSR1_PID32_Msk (_U_(0x1) << PMC_PCSR1_PID32_Pos) /**< (PMC_PCSR1) Peripheral Clock 32 Status Mask */ 1907 #define PMC_PCSR1_PID32 PMC_PCSR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID32_Msk instead */ 1908 #define PMC_PCSR1_PID33_Pos 1 /**< (PMC_PCSR1) Peripheral Clock 33 Status Position */ 1909 #define PMC_PCSR1_PID33_Msk (_U_(0x1) << PMC_PCSR1_PID33_Pos) /**< (PMC_PCSR1) Peripheral Clock 33 Status Mask */ 1910 #define PMC_PCSR1_PID33 PMC_PCSR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID33_Msk instead */ 1911 #define PMC_PCSR1_PID34_Pos 2 /**< (PMC_PCSR1) Peripheral Clock 34 Status Position */ 1912 #define PMC_PCSR1_PID34_Msk (_U_(0x1) << PMC_PCSR1_PID34_Pos) /**< (PMC_PCSR1) Peripheral Clock 34 Status Mask */ 1913 #define PMC_PCSR1_PID34 PMC_PCSR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID34_Msk instead */ 1914 #define PMC_PCSR1_PID35_Pos 3 /**< (PMC_PCSR1) Peripheral Clock 35 Status Position */ 1915 #define PMC_PCSR1_PID35_Msk (_U_(0x1) << PMC_PCSR1_PID35_Pos) /**< (PMC_PCSR1) Peripheral Clock 35 Status Mask */ 1916 #define PMC_PCSR1_PID35 PMC_PCSR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID35_Msk instead */ 1917 #define PMC_PCSR1_PID37_Pos 5 /**< (PMC_PCSR1) Peripheral Clock 37 Status Position */ 1918 #define PMC_PCSR1_PID37_Msk (_U_(0x1) << PMC_PCSR1_PID37_Pos) /**< (PMC_PCSR1) Peripheral Clock 37 Status Mask */ 1919 #define PMC_PCSR1_PID37 PMC_PCSR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID37_Msk instead */ 1920 #define PMC_PCSR1_PID39_Pos 7 /**< (PMC_PCSR1) Peripheral Clock 39 Status Position */ 1921 #define PMC_PCSR1_PID39_Msk (_U_(0x1) << PMC_PCSR1_PID39_Pos) /**< (PMC_PCSR1) Peripheral Clock 39 Status Mask */ 1922 #define PMC_PCSR1_PID39 PMC_PCSR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID39_Msk instead */ 1923 #define PMC_PCSR1_PID40_Pos 8 /**< (PMC_PCSR1) Peripheral Clock 40 Status Position */ 1924 #define PMC_PCSR1_PID40_Msk (_U_(0x1) << PMC_PCSR1_PID40_Pos) /**< (PMC_PCSR1) Peripheral Clock 40 Status Mask */ 1925 #define PMC_PCSR1_PID40 PMC_PCSR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID40_Msk instead */ 1926 #define PMC_PCSR1_PID41_Pos 9 /**< (PMC_PCSR1) Peripheral Clock 41 Status Position */ 1927 #define PMC_PCSR1_PID41_Msk (_U_(0x1) << PMC_PCSR1_PID41_Pos) /**< (PMC_PCSR1) Peripheral Clock 41 Status Mask */ 1928 #define PMC_PCSR1_PID41 PMC_PCSR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID41_Msk instead */ 1929 #define PMC_PCSR1_PID42_Pos 10 /**< (PMC_PCSR1) Peripheral Clock 42 Status Position */ 1930 #define PMC_PCSR1_PID42_Msk (_U_(0x1) << PMC_PCSR1_PID42_Pos) /**< (PMC_PCSR1) Peripheral Clock 42 Status Mask */ 1931 #define PMC_PCSR1_PID42 PMC_PCSR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID42_Msk instead */ 1932 #define PMC_PCSR1_PID43_Pos 11 /**< (PMC_PCSR1) Peripheral Clock 43 Status Position */ 1933 #define PMC_PCSR1_PID43_Msk (_U_(0x1) << PMC_PCSR1_PID43_Pos) /**< (PMC_PCSR1) Peripheral Clock 43 Status Mask */ 1934 #define PMC_PCSR1_PID43 PMC_PCSR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID43_Msk instead */ 1935 #define PMC_PCSR1_PID44_Pos 12 /**< (PMC_PCSR1) Peripheral Clock 44 Status Position */ 1936 #define PMC_PCSR1_PID44_Msk (_U_(0x1) << PMC_PCSR1_PID44_Pos) /**< (PMC_PCSR1) Peripheral Clock 44 Status Mask */ 1937 #define PMC_PCSR1_PID44 PMC_PCSR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID44_Msk instead */ 1938 #define PMC_PCSR1_PID45_Pos 13 /**< (PMC_PCSR1) Peripheral Clock 45 Status Position */ 1939 #define PMC_PCSR1_PID45_Msk (_U_(0x1) << PMC_PCSR1_PID45_Pos) /**< (PMC_PCSR1) Peripheral Clock 45 Status Mask */ 1940 #define PMC_PCSR1_PID45 PMC_PCSR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID45_Msk instead */ 1941 #define PMC_PCSR1_PID46_Pos 14 /**< (PMC_PCSR1) Peripheral Clock 46 Status Position */ 1942 #define PMC_PCSR1_PID46_Msk (_U_(0x1) << PMC_PCSR1_PID46_Pos) /**< (PMC_PCSR1) Peripheral Clock 46 Status Mask */ 1943 #define PMC_PCSR1_PID46 PMC_PCSR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID46_Msk instead */ 1944 #define PMC_PCSR1_PID47_Pos 15 /**< (PMC_PCSR1) Peripheral Clock 47 Status Position */ 1945 #define PMC_PCSR1_PID47_Msk (_U_(0x1) << PMC_PCSR1_PID47_Pos) /**< (PMC_PCSR1) Peripheral Clock 47 Status Mask */ 1946 #define PMC_PCSR1_PID47 PMC_PCSR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID47_Msk instead */ 1947 #define PMC_PCSR1_PID48_Pos 16 /**< (PMC_PCSR1) Peripheral Clock 48 Status Position */ 1948 #define PMC_PCSR1_PID48_Msk (_U_(0x1) << PMC_PCSR1_PID48_Pos) /**< (PMC_PCSR1) Peripheral Clock 48 Status Mask */ 1949 #define PMC_PCSR1_PID48 PMC_PCSR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID48_Msk instead */ 1950 #define PMC_PCSR1_PID49_Pos 17 /**< (PMC_PCSR1) Peripheral Clock 49 Status Position */ 1951 #define PMC_PCSR1_PID49_Msk (_U_(0x1) << PMC_PCSR1_PID49_Pos) /**< (PMC_PCSR1) Peripheral Clock 49 Status Mask */ 1952 #define PMC_PCSR1_PID49 PMC_PCSR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID49_Msk instead */ 1953 #define PMC_PCSR1_PID50_Pos 18 /**< (PMC_PCSR1) Peripheral Clock 50 Status Position */ 1954 #define PMC_PCSR1_PID50_Msk (_U_(0x1) << PMC_PCSR1_PID50_Pos) /**< (PMC_PCSR1) Peripheral Clock 50 Status Mask */ 1955 #define PMC_PCSR1_PID50 PMC_PCSR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID50_Msk instead */ 1956 #define PMC_PCSR1_PID51_Pos 19 /**< (PMC_PCSR1) Peripheral Clock 51 Status Position */ 1957 #define PMC_PCSR1_PID51_Msk (_U_(0x1) << PMC_PCSR1_PID51_Pos) /**< (PMC_PCSR1) Peripheral Clock 51 Status Mask */ 1958 #define PMC_PCSR1_PID51 PMC_PCSR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID51_Msk instead */ 1959 #define PMC_PCSR1_PID52_Pos 20 /**< (PMC_PCSR1) Peripheral Clock 52 Status Position */ 1960 #define PMC_PCSR1_PID52_Msk (_U_(0x1) << PMC_PCSR1_PID52_Pos) /**< (PMC_PCSR1) Peripheral Clock 52 Status Mask */ 1961 #define PMC_PCSR1_PID52 PMC_PCSR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID52_Msk instead */ 1962 #define PMC_PCSR1_PID53_Pos 21 /**< (PMC_PCSR1) Peripheral Clock 53 Status Position */ 1963 #define PMC_PCSR1_PID53_Msk (_U_(0x1) << PMC_PCSR1_PID53_Pos) /**< (PMC_PCSR1) Peripheral Clock 53 Status Mask */ 1964 #define PMC_PCSR1_PID53 PMC_PCSR1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID53_Msk instead */ 1965 #define PMC_PCSR1_PID56_Pos 24 /**< (PMC_PCSR1) Peripheral Clock 56 Status Position */ 1966 #define PMC_PCSR1_PID56_Msk (_U_(0x1) << PMC_PCSR1_PID56_Pos) /**< (PMC_PCSR1) Peripheral Clock 56 Status Mask */ 1967 #define PMC_PCSR1_PID56 PMC_PCSR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID56_Msk instead */ 1968 #define PMC_PCSR1_PID57_Pos 25 /**< (PMC_PCSR1) Peripheral Clock 57 Status Position */ 1969 #define PMC_PCSR1_PID57_Msk (_U_(0x1) << PMC_PCSR1_PID57_Pos) /**< (PMC_PCSR1) Peripheral Clock 57 Status Mask */ 1970 #define PMC_PCSR1_PID57 PMC_PCSR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID57_Msk instead */ 1971 #define PMC_PCSR1_PID58_Pos 26 /**< (PMC_PCSR1) Peripheral Clock 58 Status Position */ 1972 #define PMC_PCSR1_PID58_Msk (_U_(0x1) << PMC_PCSR1_PID58_Pos) /**< (PMC_PCSR1) Peripheral Clock 58 Status Mask */ 1973 #define PMC_PCSR1_PID58 PMC_PCSR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID58_Msk instead */ 1974 #define PMC_PCSR1_PID59_Pos 27 /**< (PMC_PCSR1) Peripheral Clock 59 Status Position */ 1975 #define PMC_PCSR1_PID59_Msk (_U_(0x1) << PMC_PCSR1_PID59_Pos) /**< (PMC_PCSR1) Peripheral Clock 59 Status Mask */ 1976 #define PMC_PCSR1_PID59 PMC_PCSR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID59_Msk instead */ 1977 #define PMC_PCSR1_PID60_Pos 28 /**< (PMC_PCSR1) Peripheral Clock 60 Status Position */ 1978 #define PMC_PCSR1_PID60_Msk (_U_(0x1) << PMC_PCSR1_PID60_Pos) /**< (PMC_PCSR1) Peripheral Clock 60 Status Mask */ 1979 #define PMC_PCSR1_PID60 PMC_PCSR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID60_Msk instead */ 1980 #define PMC_PCSR1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_PCSR1) Register MASK (Use PMC_PCSR1_Msk instead) */ 1981 #define PMC_PCSR1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCSR1) Register Mask */ 1982 1983 #define PMC_PCSR1_PID_Pos 0 /**< (PMC_PCSR1 Position) Peripheral Clock 6x Status */ 1984 #define PMC_PCSR1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR1_PID_Pos) /**< (PMC_PCSR1 Mask) PID */ 1985 #define PMC_PCSR1_PID(value) (PMC_PCSR1_PID_Msk & ((value) << PMC_PCSR1_PID_Pos)) 1986 1987 /* -------- PMC_PCR : (PMC Offset: 0x10c) (R/W 32) Peripheral Control Register -------- */ 1988 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1989 #if COMPONENT_TYPEDEF_STYLE == 'N' 1990 typedef union { 1991 struct { 1992 uint32_t PID:7; /**< bit: 0..6 Peripheral ID */ 1993 uint32_t :1; /**< bit: 7 Reserved */ 1994 uint32_t GCLKCSS:3; /**< bit: 8..10 Generic Clock Source Selection */ 1995 uint32_t :1; /**< bit: 11 Reserved */ 1996 uint32_t CMD:1; /**< bit: 12 Command */ 1997 uint32_t :7; /**< bit: 13..19 Reserved */ 1998 uint32_t GCLKDIV:8; /**< bit: 20..27 Generic Clock Division Ratio */ 1999 uint32_t EN:1; /**< bit: 28 Enable */ 2000 uint32_t GCLKEN:1; /**< bit: 29 Generic Clock Enable */ 2001 uint32_t :2; /**< bit: 30..31 Reserved */ 2002 } bit; /**< Structure used for bit access */ 2003 uint32_t reg; /**< Type used for register access */ 2004 } PMC_PCR_Type; 2005 #endif 2006 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2007 2008 #define PMC_PCR_OFFSET (0x10C) /**< (PMC_PCR) Peripheral Control Register Offset */ 2009 2010 #define PMC_PCR_PID_Pos 0 /**< (PMC_PCR) Peripheral ID Position */ 2011 #define PMC_PCR_PID_Msk (_U_(0x7F) << PMC_PCR_PID_Pos) /**< (PMC_PCR) Peripheral ID Mask */ 2012 #define PMC_PCR_PID(value) (PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)) 2013 #define PMC_PCR_GCLKCSS_Pos 8 /**< (PMC_PCR) Generic Clock Source Selection Position */ 2014 #define PMC_PCR_GCLKCSS_Msk (_U_(0x7) << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Generic Clock Source Selection Mask */ 2015 #define PMC_PCR_GCLKCSS(value) (PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)) 2016 #define PMC_PCR_GCLKCSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCR) Slow clock is selected */ 2017 #define PMC_PCR_GCLKCSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCR) Main clock is selected */ 2018 #define PMC_PCR_GCLKCSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCR) PLLACK is selected */ 2019 #define PMC_PCR_GCLKCSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCR) UPLL Clock is selected */ 2020 #define PMC_PCR_GCLKCSS_MCK_CLK_Val _U_(0x4) /**< (PMC_PCR) Master Clock is selected */ 2021 #define PMC_PCR_GCLKCSS_SLOW_CLK (PMC_PCR_GCLKCSS_SLOW_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Slow clock is selected Position */ 2022 #define PMC_PCR_GCLKCSS_MAIN_CLK (PMC_PCR_GCLKCSS_MAIN_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Main clock is selected Position */ 2023 #define PMC_PCR_GCLKCSS_PLLA_CLK (PMC_PCR_GCLKCSS_PLLA_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) PLLACK is selected Position */ 2024 #define PMC_PCR_GCLKCSS_UPLL_CLK (PMC_PCR_GCLKCSS_UPLL_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) UPLL Clock is selected Position */ 2025 #define PMC_PCR_GCLKCSS_MCK_CLK (PMC_PCR_GCLKCSS_MCK_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Master Clock is selected Position */ 2026 #define PMC_PCR_CMD_Pos 12 /**< (PMC_PCR) Command Position */ 2027 #define PMC_PCR_CMD_Msk (_U_(0x1) << PMC_PCR_CMD_Pos) /**< (PMC_PCR) Command Mask */ 2028 #define PMC_PCR_CMD PMC_PCR_CMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_CMD_Msk instead */ 2029 #define PMC_PCR_GCLKDIV_Pos 20 /**< (PMC_PCR) Generic Clock Division Ratio Position */ 2030 #define PMC_PCR_GCLKDIV_Msk (_U_(0xFF) << PMC_PCR_GCLKDIV_Pos) /**< (PMC_PCR) Generic Clock Division Ratio Mask */ 2031 #define PMC_PCR_GCLKDIV(value) (PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)) 2032 #define PMC_PCR_EN_Pos 28 /**< (PMC_PCR) Enable Position */ 2033 #define PMC_PCR_EN_Msk (_U_(0x1) << PMC_PCR_EN_Pos) /**< (PMC_PCR) Enable Mask */ 2034 #define PMC_PCR_EN PMC_PCR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_EN_Msk instead */ 2035 #define PMC_PCR_GCLKEN_Pos 29 /**< (PMC_PCR) Generic Clock Enable Position */ 2036 #define PMC_PCR_GCLKEN_Msk (_U_(0x1) << PMC_PCR_GCLKEN_Pos) /**< (PMC_PCR) Generic Clock Enable Mask */ 2037 #define PMC_PCR_GCLKEN PMC_PCR_GCLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_GCLKEN_Msk instead */ 2038 #define PMC_PCR_MASK _U_(0x3FF0177F) /**< \deprecated (PMC_PCR) Register MASK (Use PMC_PCR_Msk instead) */ 2039 #define PMC_PCR_Msk _U_(0x3FF0177F) /**< (PMC_PCR) Register Mask */ 2040 2041 2042 /* -------- PMC_OCR : (PMC Offset: 0x110) (R/W 32) Oscillator Calibration Register -------- */ 2043 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2044 #if COMPONENT_TYPEDEF_STYLE == 'N' 2045 typedef union { 2046 struct { 2047 uint32_t CAL4:7; /**< bit: 0..6 Main RC Oscillator Calibration Bits for 4 MHz */ 2048 uint32_t SEL4:1; /**< bit: 7 Selection of Main RC Oscillator Calibration Bits for 4 MHz */ 2049 uint32_t CAL8:7; /**< bit: 8..14 Main RC Oscillator Calibration Bits for 8 MHz */ 2050 uint32_t SEL8:1; /**< bit: 15 Selection of Main RC Oscillator Calibration Bits for 8 MHz */ 2051 uint32_t CAL12:7; /**< bit: 16..22 Main RC Oscillator Calibration Bits for 12 MHz */ 2052 uint32_t SEL12:1; /**< bit: 23 Selection of Main RC Oscillator Calibration Bits for 12 MHz */ 2053 uint32_t :8; /**< bit: 24..31 Reserved */ 2054 } bit; /**< Structure used for bit access */ 2055 uint32_t reg; /**< Type used for register access */ 2056 } PMC_OCR_Type; 2057 #endif 2058 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2059 2060 #define PMC_OCR_OFFSET (0x110) /**< (PMC_OCR) Oscillator Calibration Register Offset */ 2061 2062 #define PMC_OCR_CAL4_Pos 0 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Position */ 2063 #define PMC_OCR_CAL4_Msk (_U_(0x7F) << PMC_OCR_CAL4_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Mask */ 2064 #define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)) 2065 #define PMC_OCR_SEL4_Pos 7 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Position */ 2066 #define PMC_OCR_SEL4_Msk (_U_(0x1) << PMC_OCR_SEL4_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Mask */ 2067 #define PMC_OCR_SEL4 PMC_OCR_SEL4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL4_Msk instead */ 2068 #define PMC_OCR_CAL8_Pos 8 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Position */ 2069 #define PMC_OCR_CAL8_Msk (_U_(0x7F) << PMC_OCR_CAL8_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Mask */ 2070 #define PMC_OCR_CAL8(value) (PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)) 2071 #define PMC_OCR_SEL8_Pos 15 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Position */ 2072 #define PMC_OCR_SEL8_Msk (_U_(0x1) << PMC_OCR_SEL8_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Mask */ 2073 #define PMC_OCR_SEL8 PMC_OCR_SEL8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL8_Msk instead */ 2074 #define PMC_OCR_CAL12_Pos 16 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Position */ 2075 #define PMC_OCR_CAL12_Msk (_U_(0x7F) << PMC_OCR_CAL12_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Mask */ 2076 #define PMC_OCR_CAL12(value) (PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)) 2077 #define PMC_OCR_SEL12_Pos 23 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Position */ 2078 #define PMC_OCR_SEL12_Msk (_U_(0x1) << PMC_OCR_SEL12_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Mask */ 2079 #define PMC_OCR_SEL12 PMC_OCR_SEL12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL12_Msk instead */ 2080 #define PMC_OCR_MASK _U_(0xFFFFFF) /**< \deprecated (PMC_OCR) Register MASK (Use PMC_OCR_Msk instead) */ 2081 #define PMC_OCR_Msk _U_(0xFFFFFF) /**< (PMC_OCR) Register Mask */ 2082 2083 2084 /* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) (/W 32) SleepWalking Enable Register 0 -------- */ 2085 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2086 #if COMPONENT_TYPEDEF_STYLE == 'N' 2087 typedef union { 2088 struct { 2089 uint32_t :7; /**< bit: 0..6 Reserved */ 2090 uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Enable */ 2091 uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Enable */ 2092 uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Enable */ 2093 uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Enable */ 2094 uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Enable */ 2095 uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Enable */ 2096 uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Enable */ 2097 uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Enable */ 2098 uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Enable */ 2099 uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Enable */ 2100 uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Enable */ 2101 uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Enable */ 2102 uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Enable */ 2103 uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Enable */ 2104 uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Enable */ 2105 uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Enable */ 2106 uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Enable */ 2107 uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Enable */ 2108 uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Enable */ 2109 uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Enable */ 2110 uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Enable */ 2111 uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Enable */ 2112 uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Enable */ 2113 uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Enable */ 2114 uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Enable */ 2115 } bit; /**< Structure used for bit access */ 2116 struct { 2117 uint32_t :7; /**< bit: 0..6 Reserved */ 2118 uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Enable */ 2119 } vec; /**< Structure used for vec access */ 2120 uint32_t reg; /**< Type used for register access */ 2121 } PMC_SLPWK_ER0_Type; 2122 #endif 2123 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2124 2125 #define PMC_SLPWK_ER0_OFFSET (0x114) /**< (PMC_SLPWK_ER0) SleepWalking Enable Register 0 Offset */ 2126 2127 #define PMC_SLPWK_ER0_PID7_Pos 7 /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Position */ 2128 #define PMC_SLPWK_ER0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID7_Pos) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Mask */ 2129 #define PMC_SLPWK_ER0_PID7 PMC_SLPWK_ER0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID7_Msk instead */ 2130 #define PMC_SLPWK_ER0_PID8_Pos 8 /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Position */ 2131 #define PMC_SLPWK_ER0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID8_Pos) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Mask */ 2132 #define PMC_SLPWK_ER0_PID8 PMC_SLPWK_ER0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID8_Msk instead */ 2133 #define PMC_SLPWK_ER0_PID9_Pos 9 /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Position */ 2134 #define PMC_SLPWK_ER0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID9_Pos) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Mask */ 2135 #define PMC_SLPWK_ER0_PID9 PMC_SLPWK_ER0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID9_Msk instead */ 2136 #define PMC_SLPWK_ER0_PID10_Pos 10 /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Position */ 2137 #define PMC_SLPWK_ER0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID10_Pos) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Mask */ 2138 #define PMC_SLPWK_ER0_PID10 PMC_SLPWK_ER0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID10_Msk instead */ 2139 #define PMC_SLPWK_ER0_PID11_Pos 11 /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Position */ 2140 #define PMC_SLPWK_ER0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID11_Pos) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Mask */ 2141 #define PMC_SLPWK_ER0_PID11 PMC_SLPWK_ER0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID11_Msk instead */ 2142 #define PMC_SLPWK_ER0_PID12_Pos 12 /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Position */ 2143 #define PMC_SLPWK_ER0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID12_Pos) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Mask */ 2144 #define PMC_SLPWK_ER0_PID12 PMC_SLPWK_ER0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID12_Msk instead */ 2145 #define PMC_SLPWK_ER0_PID13_Pos 13 /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Position */ 2146 #define PMC_SLPWK_ER0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID13_Pos) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Mask */ 2147 #define PMC_SLPWK_ER0_PID13 PMC_SLPWK_ER0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID13_Msk instead */ 2148 #define PMC_SLPWK_ER0_PID14_Pos 14 /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Position */ 2149 #define PMC_SLPWK_ER0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID14_Pos) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Mask */ 2150 #define PMC_SLPWK_ER0_PID14 PMC_SLPWK_ER0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID14_Msk instead */ 2151 #define PMC_SLPWK_ER0_PID15_Pos 15 /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Position */ 2152 #define PMC_SLPWK_ER0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID15_Pos) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Mask */ 2153 #define PMC_SLPWK_ER0_PID15 PMC_SLPWK_ER0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID15_Msk instead */ 2154 #define PMC_SLPWK_ER0_PID16_Pos 16 /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Position */ 2155 #define PMC_SLPWK_ER0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID16_Pos) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Mask */ 2156 #define PMC_SLPWK_ER0_PID16 PMC_SLPWK_ER0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID16_Msk instead */ 2157 #define PMC_SLPWK_ER0_PID17_Pos 17 /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Position */ 2158 #define PMC_SLPWK_ER0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID17_Pos) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Mask */ 2159 #define PMC_SLPWK_ER0_PID17 PMC_SLPWK_ER0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID17_Msk instead */ 2160 #define PMC_SLPWK_ER0_PID18_Pos 18 /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Position */ 2161 #define PMC_SLPWK_ER0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID18_Pos) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Mask */ 2162 #define PMC_SLPWK_ER0_PID18 PMC_SLPWK_ER0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID18_Msk instead */ 2163 #define PMC_SLPWK_ER0_PID19_Pos 19 /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Position */ 2164 #define PMC_SLPWK_ER0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID19_Pos) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Mask */ 2165 #define PMC_SLPWK_ER0_PID19 PMC_SLPWK_ER0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID19_Msk instead */ 2166 #define PMC_SLPWK_ER0_PID20_Pos 20 /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Position */ 2167 #define PMC_SLPWK_ER0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID20_Pos) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Mask */ 2168 #define PMC_SLPWK_ER0_PID20 PMC_SLPWK_ER0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID20_Msk instead */ 2169 #define PMC_SLPWK_ER0_PID21_Pos 21 /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Position */ 2170 #define PMC_SLPWK_ER0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID21_Pos) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Mask */ 2171 #define PMC_SLPWK_ER0_PID21 PMC_SLPWK_ER0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID21_Msk instead */ 2172 #define PMC_SLPWK_ER0_PID22_Pos 22 /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Position */ 2173 #define PMC_SLPWK_ER0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID22_Pos) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Mask */ 2174 #define PMC_SLPWK_ER0_PID22 PMC_SLPWK_ER0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID22_Msk instead */ 2175 #define PMC_SLPWK_ER0_PID23_Pos 23 /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Position */ 2176 #define PMC_SLPWK_ER0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID23_Pos) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Mask */ 2177 #define PMC_SLPWK_ER0_PID23 PMC_SLPWK_ER0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID23_Msk instead */ 2178 #define PMC_SLPWK_ER0_PID24_Pos 24 /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Position */ 2179 #define PMC_SLPWK_ER0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID24_Pos) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Mask */ 2180 #define PMC_SLPWK_ER0_PID24 PMC_SLPWK_ER0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID24_Msk instead */ 2181 #define PMC_SLPWK_ER0_PID25_Pos 25 /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Position */ 2182 #define PMC_SLPWK_ER0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID25_Pos) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Mask */ 2183 #define PMC_SLPWK_ER0_PID25 PMC_SLPWK_ER0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID25_Msk instead */ 2184 #define PMC_SLPWK_ER0_PID26_Pos 26 /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Position */ 2185 #define PMC_SLPWK_ER0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID26_Pos) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Mask */ 2186 #define PMC_SLPWK_ER0_PID26 PMC_SLPWK_ER0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID26_Msk instead */ 2187 #define PMC_SLPWK_ER0_PID27_Pos 27 /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Position */ 2188 #define PMC_SLPWK_ER0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID27_Pos) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Mask */ 2189 #define PMC_SLPWK_ER0_PID27 PMC_SLPWK_ER0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID27_Msk instead */ 2190 #define PMC_SLPWK_ER0_PID28_Pos 28 /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Position */ 2191 #define PMC_SLPWK_ER0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID28_Pos) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Mask */ 2192 #define PMC_SLPWK_ER0_PID28 PMC_SLPWK_ER0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID28_Msk instead */ 2193 #define PMC_SLPWK_ER0_PID29_Pos 29 /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Position */ 2194 #define PMC_SLPWK_ER0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID29_Pos) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Mask */ 2195 #define PMC_SLPWK_ER0_PID29 PMC_SLPWK_ER0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID29_Msk instead */ 2196 #define PMC_SLPWK_ER0_PID30_Pos 30 /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Position */ 2197 #define PMC_SLPWK_ER0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID30_Pos) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Mask */ 2198 #define PMC_SLPWK_ER0_PID30 PMC_SLPWK_ER0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID30_Msk instead */ 2199 #define PMC_SLPWK_ER0_PID31_Pos 31 /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Position */ 2200 #define PMC_SLPWK_ER0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID31_Pos) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Mask */ 2201 #define PMC_SLPWK_ER0_PID31 PMC_SLPWK_ER0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID31_Msk instead */ 2202 #define PMC_SLPWK_ER0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_ER0) Register MASK (Use PMC_SLPWK_ER0_Msk instead) */ 2203 #define PMC_SLPWK_ER0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ER0) Register Mask */ 2204 2205 #define PMC_SLPWK_ER0_PID_Pos 7 /**< (PMC_SLPWK_ER0 Position) Peripheral 3x SleepWalking Enable */ 2206 #define PMC_SLPWK_ER0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER0_PID_Pos) /**< (PMC_SLPWK_ER0 Mask) PID */ 2207 #define PMC_SLPWK_ER0_PID(value) (PMC_SLPWK_ER0_PID_Msk & ((value) << PMC_SLPWK_ER0_PID_Pos)) 2208 2209 /* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) (/W 32) SleepWalking Disable Register 0 -------- */ 2210 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2211 #if COMPONENT_TYPEDEF_STYLE == 'N' 2212 typedef union { 2213 struct { 2214 uint32_t :7; /**< bit: 0..6 Reserved */ 2215 uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Disable */ 2216 uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Disable */ 2217 uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Disable */ 2218 uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Disable */ 2219 uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Disable */ 2220 uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Disable */ 2221 uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Disable */ 2222 uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Disable */ 2223 uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Disable */ 2224 uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Disable */ 2225 uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Disable */ 2226 uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Disable */ 2227 uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Disable */ 2228 uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Disable */ 2229 uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Disable */ 2230 uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Disable */ 2231 uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Disable */ 2232 uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Disable */ 2233 uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Disable */ 2234 uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Disable */ 2235 uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Disable */ 2236 uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Disable */ 2237 uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Disable */ 2238 uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Disable */ 2239 uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Disable */ 2240 } bit; /**< Structure used for bit access */ 2241 struct { 2242 uint32_t :7; /**< bit: 0..6 Reserved */ 2243 uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Disable */ 2244 } vec; /**< Structure used for vec access */ 2245 uint32_t reg; /**< Type used for register access */ 2246 } PMC_SLPWK_DR0_Type; 2247 #endif 2248 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2249 2250 #define PMC_SLPWK_DR0_OFFSET (0x118) /**< (PMC_SLPWK_DR0) SleepWalking Disable Register 0 Offset */ 2251 2252 #define PMC_SLPWK_DR0_PID7_Pos 7 /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Position */ 2253 #define PMC_SLPWK_DR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID7_Pos) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Mask */ 2254 #define PMC_SLPWK_DR0_PID7 PMC_SLPWK_DR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID7_Msk instead */ 2255 #define PMC_SLPWK_DR0_PID8_Pos 8 /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Position */ 2256 #define PMC_SLPWK_DR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID8_Pos) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Mask */ 2257 #define PMC_SLPWK_DR0_PID8 PMC_SLPWK_DR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID8_Msk instead */ 2258 #define PMC_SLPWK_DR0_PID9_Pos 9 /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Position */ 2259 #define PMC_SLPWK_DR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID9_Pos) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Mask */ 2260 #define PMC_SLPWK_DR0_PID9 PMC_SLPWK_DR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID9_Msk instead */ 2261 #define PMC_SLPWK_DR0_PID10_Pos 10 /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Position */ 2262 #define PMC_SLPWK_DR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID10_Pos) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Mask */ 2263 #define PMC_SLPWK_DR0_PID10 PMC_SLPWK_DR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID10_Msk instead */ 2264 #define PMC_SLPWK_DR0_PID11_Pos 11 /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Position */ 2265 #define PMC_SLPWK_DR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID11_Pos) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Mask */ 2266 #define PMC_SLPWK_DR0_PID11 PMC_SLPWK_DR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID11_Msk instead */ 2267 #define PMC_SLPWK_DR0_PID12_Pos 12 /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Position */ 2268 #define PMC_SLPWK_DR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID12_Pos) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Mask */ 2269 #define PMC_SLPWK_DR0_PID12 PMC_SLPWK_DR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID12_Msk instead */ 2270 #define PMC_SLPWK_DR0_PID13_Pos 13 /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Position */ 2271 #define PMC_SLPWK_DR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID13_Pos) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Mask */ 2272 #define PMC_SLPWK_DR0_PID13 PMC_SLPWK_DR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID13_Msk instead */ 2273 #define PMC_SLPWK_DR0_PID14_Pos 14 /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Position */ 2274 #define PMC_SLPWK_DR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID14_Pos) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Mask */ 2275 #define PMC_SLPWK_DR0_PID14 PMC_SLPWK_DR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID14_Msk instead */ 2276 #define PMC_SLPWK_DR0_PID15_Pos 15 /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Position */ 2277 #define PMC_SLPWK_DR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID15_Pos) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Mask */ 2278 #define PMC_SLPWK_DR0_PID15 PMC_SLPWK_DR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID15_Msk instead */ 2279 #define PMC_SLPWK_DR0_PID16_Pos 16 /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Position */ 2280 #define PMC_SLPWK_DR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID16_Pos) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Mask */ 2281 #define PMC_SLPWK_DR0_PID16 PMC_SLPWK_DR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID16_Msk instead */ 2282 #define PMC_SLPWK_DR0_PID17_Pos 17 /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Position */ 2283 #define PMC_SLPWK_DR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID17_Pos) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Mask */ 2284 #define PMC_SLPWK_DR0_PID17 PMC_SLPWK_DR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID17_Msk instead */ 2285 #define PMC_SLPWK_DR0_PID18_Pos 18 /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Position */ 2286 #define PMC_SLPWK_DR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID18_Pos) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Mask */ 2287 #define PMC_SLPWK_DR0_PID18 PMC_SLPWK_DR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID18_Msk instead */ 2288 #define PMC_SLPWK_DR0_PID19_Pos 19 /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Position */ 2289 #define PMC_SLPWK_DR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID19_Pos) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Mask */ 2290 #define PMC_SLPWK_DR0_PID19 PMC_SLPWK_DR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID19_Msk instead */ 2291 #define PMC_SLPWK_DR0_PID20_Pos 20 /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Position */ 2292 #define PMC_SLPWK_DR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID20_Pos) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Mask */ 2293 #define PMC_SLPWK_DR0_PID20 PMC_SLPWK_DR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID20_Msk instead */ 2294 #define PMC_SLPWK_DR0_PID21_Pos 21 /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Position */ 2295 #define PMC_SLPWK_DR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID21_Pos) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Mask */ 2296 #define PMC_SLPWK_DR0_PID21 PMC_SLPWK_DR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID21_Msk instead */ 2297 #define PMC_SLPWK_DR0_PID22_Pos 22 /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Position */ 2298 #define PMC_SLPWK_DR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID22_Pos) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Mask */ 2299 #define PMC_SLPWK_DR0_PID22 PMC_SLPWK_DR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID22_Msk instead */ 2300 #define PMC_SLPWK_DR0_PID23_Pos 23 /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Position */ 2301 #define PMC_SLPWK_DR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID23_Pos) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Mask */ 2302 #define PMC_SLPWK_DR0_PID23 PMC_SLPWK_DR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID23_Msk instead */ 2303 #define PMC_SLPWK_DR0_PID24_Pos 24 /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Position */ 2304 #define PMC_SLPWK_DR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID24_Pos) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Mask */ 2305 #define PMC_SLPWK_DR0_PID24 PMC_SLPWK_DR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID24_Msk instead */ 2306 #define PMC_SLPWK_DR0_PID25_Pos 25 /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Position */ 2307 #define PMC_SLPWK_DR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID25_Pos) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Mask */ 2308 #define PMC_SLPWK_DR0_PID25 PMC_SLPWK_DR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID25_Msk instead */ 2309 #define PMC_SLPWK_DR0_PID26_Pos 26 /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Position */ 2310 #define PMC_SLPWK_DR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID26_Pos) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Mask */ 2311 #define PMC_SLPWK_DR0_PID26 PMC_SLPWK_DR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID26_Msk instead */ 2312 #define PMC_SLPWK_DR0_PID27_Pos 27 /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Position */ 2313 #define PMC_SLPWK_DR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID27_Pos) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Mask */ 2314 #define PMC_SLPWK_DR0_PID27 PMC_SLPWK_DR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID27_Msk instead */ 2315 #define PMC_SLPWK_DR0_PID28_Pos 28 /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Position */ 2316 #define PMC_SLPWK_DR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID28_Pos) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Mask */ 2317 #define PMC_SLPWK_DR0_PID28 PMC_SLPWK_DR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID28_Msk instead */ 2318 #define PMC_SLPWK_DR0_PID29_Pos 29 /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Position */ 2319 #define PMC_SLPWK_DR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID29_Pos) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Mask */ 2320 #define PMC_SLPWK_DR0_PID29 PMC_SLPWK_DR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID29_Msk instead */ 2321 #define PMC_SLPWK_DR0_PID30_Pos 30 /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Position */ 2322 #define PMC_SLPWK_DR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID30_Pos) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Mask */ 2323 #define PMC_SLPWK_DR0_PID30 PMC_SLPWK_DR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID30_Msk instead */ 2324 #define PMC_SLPWK_DR0_PID31_Pos 31 /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Position */ 2325 #define PMC_SLPWK_DR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID31_Pos) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Mask */ 2326 #define PMC_SLPWK_DR0_PID31 PMC_SLPWK_DR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID31_Msk instead */ 2327 #define PMC_SLPWK_DR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_DR0) Register MASK (Use PMC_SLPWK_DR0_Msk instead) */ 2328 #define PMC_SLPWK_DR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_DR0) Register Mask */ 2329 2330 #define PMC_SLPWK_DR0_PID_Pos 7 /**< (PMC_SLPWK_DR0 Position) Peripheral 3x SleepWalking Disable */ 2331 #define PMC_SLPWK_DR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR0_PID_Pos) /**< (PMC_SLPWK_DR0 Mask) PID */ 2332 #define PMC_SLPWK_DR0_PID(value) (PMC_SLPWK_DR0_PID_Msk & ((value) << PMC_SLPWK_DR0_PID_Pos)) 2333 2334 /* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11c) (R/ 32) SleepWalking Status Register 0 -------- */ 2335 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2336 #if COMPONENT_TYPEDEF_STYLE == 'N' 2337 typedef union { 2338 struct { 2339 uint32_t :7; /**< bit: 0..6 Reserved */ 2340 uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Status */ 2341 uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Status */ 2342 uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Status */ 2343 uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Status */ 2344 uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Status */ 2345 uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Status */ 2346 uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Status */ 2347 uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Status */ 2348 uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Status */ 2349 uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Status */ 2350 uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Status */ 2351 uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Status */ 2352 uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Status */ 2353 uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Status */ 2354 uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Status */ 2355 uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Status */ 2356 uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Status */ 2357 uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Status */ 2358 uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Status */ 2359 uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Status */ 2360 uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Status */ 2361 uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Status */ 2362 uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Status */ 2363 uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Status */ 2364 uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Status */ 2365 } bit; /**< Structure used for bit access */ 2366 struct { 2367 uint32_t :7; /**< bit: 0..6 Reserved */ 2368 uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Status */ 2369 } vec; /**< Structure used for vec access */ 2370 uint32_t reg; /**< Type used for register access */ 2371 } PMC_SLPWK_SR0_Type; 2372 #endif 2373 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2374 2375 #define PMC_SLPWK_SR0_OFFSET (0x11C) /**< (PMC_SLPWK_SR0) SleepWalking Status Register 0 Offset */ 2376 2377 #define PMC_SLPWK_SR0_PID7_Pos 7 /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Position */ 2378 #define PMC_SLPWK_SR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID7_Pos) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Mask */ 2379 #define PMC_SLPWK_SR0_PID7 PMC_SLPWK_SR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID7_Msk instead */ 2380 #define PMC_SLPWK_SR0_PID8_Pos 8 /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Position */ 2381 #define PMC_SLPWK_SR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID8_Pos) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Mask */ 2382 #define PMC_SLPWK_SR0_PID8 PMC_SLPWK_SR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID8_Msk instead */ 2383 #define PMC_SLPWK_SR0_PID9_Pos 9 /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Position */ 2384 #define PMC_SLPWK_SR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID9_Pos) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Mask */ 2385 #define PMC_SLPWK_SR0_PID9 PMC_SLPWK_SR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID9_Msk instead */ 2386 #define PMC_SLPWK_SR0_PID10_Pos 10 /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Position */ 2387 #define PMC_SLPWK_SR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID10_Pos) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Mask */ 2388 #define PMC_SLPWK_SR0_PID10 PMC_SLPWK_SR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID10_Msk instead */ 2389 #define PMC_SLPWK_SR0_PID11_Pos 11 /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Position */ 2390 #define PMC_SLPWK_SR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID11_Pos) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Mask */ 2391 #define PMC_SLPWK_SR0_PID11 PMC_SLPWK_SR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID11_Msk instead */ 2392 #define PMC_SLPWK_SR0_PID12_Pos 12 /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Position */ 2393 #define PMC_SLPWK_SR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID12_Pos) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Mask */ 2394 #define PMC_SLPWK_SR0_PID12 PMC_SLPWK_SR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID12_Msk instead */ 2395 #define PMC_SLPWK_SR0_PID13_Pos 13 /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Position */ 2396 #define PMC_SLPWK_SR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID13_Pos) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Mask */ 2397 #define PMC_SLPWK_SR0_PID13 PMC_SLPWK_SR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID13_Msk instead */ 2398 #define PMC_SLPWK_SR0_PID14_Pos 14 /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Position */ 2399 #define PMC_SLPWK_SR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID14_Pos) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Mask */ 2400 #define PMC_SLPWK_SR0_PID14 PMC_SLPWK_SR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID14_Msk instead */ 2401 #define PMC_SLPWK_SR0_PID15_Pos 15 /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Position */ 2402 #define PMC_SLPWK_SR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID15_Pos) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Mask */ 2403 #define PMC_SLPWK_SR0_PID15 PMC_SLPWK_SR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID15_Msk instead */ 2404 #define PMC_SLPWK_SR0_PID16_Pos 16 /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Position */ 2405 #define PMC_SLPWK_SR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID16_Pos) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Mask */ 2406 #define PMC_SLPWK_SR0_PID16 PMC_SLPWK_SR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID16_Msk instead */ 2407 #define PMC_SLPWK_SR0_PID17_Pos 17 /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Position */ 2408 #define PMC_SLPWK_SR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID17_Pos) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Mask */ 2409 #define PMC_SLPWK_SR0_PID17 PMC_SLPWK_SR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID17_Msk instead */ 2410 #define PMC_SLPWK_SR0_PID18_Pos 18 /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Position */ 2411 #define PMC_SLPWK_SR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID18_Pos) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Mask */ 2412 #define PMC_SLPWK_SR0_PID18 PMC_SLPWK_SR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID18_Msk instead */ 2413 #define PMC_SLPWK_SR0_PID19_Pos 19 /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Position */ 2414 #define PMC_SLPWK_SR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID19_Pos) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Mask */ 2415 #define PMC_SLPWK_SR0_PID19 PMC_SLPWK_SR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID19_Msk instead */ 2416 #define PMC_SLPWK_SR0_PID20_Pos 20 /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Position */ 2417 #define PMC_SLPWK_SR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID20_Pos) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Mask */ 2418 #define PMC_SLPWK_SR0_PID20 PMC_SLPWK_SR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID20_Msk instead */ 2419 #define PMC_SLPWK_SR0_PID21_Pos 21 /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Position */ 2420 #define PMC_SLPWK_SR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID21_Pos) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Mask */ 2421 #define PMC_SLPWK_SR0_PID21 PMC_SLPWK_SR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID21_Msk instead */ 2422 #define PMC_SLPWK_SR0_PID22_Pos 22 /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Position */ 2423 #define PMC_SLPWK_SR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID22_Pos) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Mask */ 2424 #define PMC_SLPWK_SR0_PID22 PMC_SLPWK_SR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID22_Msk instead */ 2425 #define PMC_SLPWK_SR0_PID23_Pos 23 /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Position */ 2426 #define PMC_SLPWK_SR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID23_Pos) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Mask */ 2427 #define PMC_SLPWK_SR0_PID23 PMC_SLPWK_SR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID23_Msk instead */ 2428 #define PMC_SLPWK_SR0_PID24_Pos 24 /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Position */ 2429 #define PMC_SLPWK_SR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID24_Pos) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Mask */ 2430 #define PMC_SLPWK_SR0_PID24 PMC_SLPWK_SR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID24_Msk instead */ 2431 #define PMC_SLPWK_SR0_PID25_Pos 25 /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Position */ 2432 #define PMC_SLPWK_SR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID25_Pos) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Mask */ 2433 #define PMC_SLPWK_SR0_PID25 PMC_SLPWK_SR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID25_Msk instead */ 2434 #define PMC_SLPWK_SR0_PID26_Pos 26 /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Position */ 2435 #define PMC_SLPWK_SR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID26_Pos) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Mask */ 2436 #define PMC_SLPWK_SR0_PID26 PMC_SLPWK_SR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID26_Msk instead */ 2437 #define PMC_SLPWK_SR0_PID27_Pos 27 /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Position */ 2438 #define PMC_SLPWK_SR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID27_Pos) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Mask */ 2439 #define PMC_SLPWK_SR0_PID27 PMC_SLPWK_SR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID27_Msk instead */ 2440 #define PMC_SLPWK_SR0_PID28_Pos 28 /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Position */ 2441 #define PMC_SLPWK_SR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID28_Pos) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Mask */ 2442 #define PMC_SLPWK_SR0_PID28 PMC_SLPWK_SR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID28_Msk instead */ 2443 #define PMC_SLPWK_SR0_PID29_Pos 29 /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Position */ 2444 #define PMC_SLPWK_SR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID29_Pos) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Mask */ 2445 #define PMC_SLPWK_SR0_PID29 PMC_SLPWK_SR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID29_Msk instead */ 2446 #define PMC_SLPWK_SR0_PID30_Pos 30 /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Position */ 2447 #define PMC_SLPWK_SR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID30_Pos) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Mask */ 2448 #define PMC_SLPWK_SR0_PID30 PMC_SLPWK_SR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID30_Msk instead */ 2449 #define PMC_SLPWK_SR0_PID31_Pos 31 /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Position */ 2450 #define PMC_SLPWK_SR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID31_Pos) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Mask */ 2451 #define PMC_SLPWK_SR0_PID31 PMC_SLPWK_SR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID31_Msk instead */ 2452 #define PMC_SLPWK_SR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_SR0) Register MASK (Use PMC_SLPWK_SR0_Msk instead) */ 2453 #define PMC_SLPWK_SR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_SR0) Register Mask */ 2454 2455 #define PMC_SLPWK_SR0_PID_Pos 7 /**< (PMC_SLPWK_SR0 Position) Peripheral 3x SleepWalking Status */ 2456 #define PMC_SLPWK_SR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR0_PID_Pos) /**< (PMC_SLPWK_SR0 Mask) PID */ 2457 #define PMC_SLPWK_SR0_PID(value) (PMC_SLPWK_SR0_PID_Msk & ((value) << PMC_SLPWK_SR0_PID_Pos)) 2458 2459 /* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) (R/ 32) SleepWalking Activity Status Register 0 -------- */ 2460 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2461 #if COMPONENT_TYPEDEF_STYLE == 'N' 2462 typedef union { 2463 struct { 2464 uint32_t :7; /**< bit: 0..6 Reserved */ 2465 uint32_t PID7:1; /**< bit: 7 Peripheral 7 Activity Status */ 2466 uint32_t PID8:1; /**< bit: 8 Peripheral 8 Activity Status */ 2467 uint32_t PID9:1; /**< bit: 9 Peripheral 9 Activity Status */ 2468 uint32_t PID10:1; /**< bit: 10 Peripheral 10 Activity Status */ 2469 uint32_t PID11:1; /**< bit: 11 Peripheral 11 Activity Status */ 2470 uint32_t PID12:1; /**< bit: 12 Peripheral 12 Activity Status */ 2471 uint32_t PID13:1; /**< bit: 13 Peripheral 13 Activity Status */ 2472 uint32_t PID14:1; /**< bit: 14 Peripheral 14 Activity Status */ 2473 uint32_t PID15:1; /**< bit: 15 Peripheral 15 Activity Status */ 2474 uint32_t PID16:1; /**< bit: 16 Peripheral 16 Activity Status */ 2475 uint32_t PID17:1; /**< bit: 17 Peripheral 17 Activity Status */ 2476 uint32_t PID18:1; /**< bit: 18 Peripheral 18 Activity Status */ 2477 uint32_t PID19:1; /**< bit: 19 Peripheral 19 Activity Status */ 2478 uint32_t PID20:1; /**< bit: 20 Peripheral 20 Activity Status */ 2479 uint32_t PID21:1; /**< bit: 21 Peripheral 21 Activity Status */ 2480 uint32_t PID22:1; /**< bit: 22 Peripheral 22 Activity Status */ 2481 uint32_t PID23:1; /**< bit: 23 Peripheral 23 Activity Status */ 2482 uint32_t PID24:1; /**< bit: 24 Peripheral 24 Activity Status */ 2483 uint32_t PID25:1; /**< bit: 25 Peripheral 25 Activity Status */ 2484 uint32_t PID26:1; /**< bit: 26 Peripheral 26 Activity Status */ 2485 uint32_t PID27:1; /**< bit: 27 Peripheral 27 Activity Status */ 2486 uint32_t PID28:1; /**< bit: 28 Peripheral 28 Activity Status */ 2487 uint32_t PID29:1; /**< bit: 29 Peripheral 29 Activity Status */ 2488 uint32_t PID30:1; /**< bit: 30 Peripheral 30 Activity Status */ 2489 uint32_t PID31:1; /**< bit: 31 Peripheral 31 Activity Status */ 2490 } bit; /**< Structure used for bit access */ 2491 struct { 2492 uint32_t :7; /**< bit: 0..6 Reserved */ 2493 uint32_t PID:25; /**< bit: 7..31 Peripheral 3x Activity Status */ 2494 } vec; /**< Structure used for vec access */ 2495 uint32_t reg; /**< Type used for register access */ 2496 } PMC_SLPWK_ASR0_Type; 2497 #endif 2498 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2499 2500 #define PMC_SLPWK_ASR0_OFFSET (0x120) /**< (PMC_SLPWK_ASR0) SleepWalking Activity Status Register 0 Offset */ 2501 2502 #define PMC_SLPWK_ASR0_PID7_Pos 7 /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Position */ 2503 #define PMC_SLPWK_ASR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID7_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Mask */ 2504 #define PMC_SLPWK_ASR0_PID7 PMC_SLPWK_ASR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID7_Msk instead */ 2505 #define PMC_SLPWK_ASR0_PID8_Pos 8 /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Position */ 2506 #define PMC_SLPWK_ASR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID8_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Mask */ 2507 #define PMC_SLPWK_ASR0_PID8 PMC_SLPWK_ASR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID8_Msk instead */ 2508 #define PMC_SLPWK_ASR0_PID9_Pos 9 /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Position */ 2509 #define PMC_SLPWK_ASR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID9_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Mask */ 2510 #define PMC_SLPWK_ASR0_PID9 PMC_SLPWK_ASR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID9_Msk instead */ 2511 #define PMC_SLPWK_ASR0_PID10_Pos 10 /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Position */ 2512 #define PMC_SLPWK_ASR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID10_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Mask */ 2513 #define PMC_SLPWK_ASR0_PID10 PMC_SLPWK_ASR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID10_Msk instead */ 2514 #define PMC_SLPWK_ASR0_PID11_Pos 11 /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Position */ 2515 #define PMC_SLPWK_ASR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID11_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Mask */ 2516 #define PMC_SLPWK_ASR0_PID11 PMC_SLPWK_ASR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID11_Msk instead */ 2517 #define PMC_SLPWK_ASR0_PID12_Pos 12 /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Position */ 2518 #define PMC_SLPWK_ASR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID12_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Mask */ 2519 #define PMC_SLPWK_ASR0_PID12 PMC_SLPWK_ASR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID12_Msk instead */ 2520 #define PMC_SLPWK_ASR0_PID13_Pos 13 /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Position */ 2521 #define PMC_SLPWK_ASR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID13_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Mask */ 2522 #define PMC_SLPWK_ASR0_PID13 PMC_SLPWK_ASR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID13_Msk instead */ 2523 #define PMC_SLPWK_ASR0_PID14_Pos 14 /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Position */ 2524 #define PMC_SLPWK_ASR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID14_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Mask */ 2525 #define PMC_SLPWK_ASR0_PID14 PMC_SLPWK_ASR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID14_Msk instead */ 2526 #define PMC_SLPWK_ASR0_PID15_Pos 15 /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Position */ 2527 #define PMC_SLPWK_ASR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID15_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Mask */ 2528 #define PMC_SLPWK_ASR0_PID15 PMC_SLPWK_ASR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID15_Msk instead */ 2529 #define PMC_SLPWK_ASR0_PID16_Pos 16 /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Position */ 2530 #define PMC_SLPWK_ASR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID16_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Mask */ 2531 #define PMC_SLPWK_ASR0_PID16 PMC_SLPWK_ASR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID16_Msk instead */ 2532 #define PMC_SLPWK_ASR0_PID17_Pos 17 /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Position */ 2533 #define PMC_SLPWK_ASR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID17_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Mask */ 2534 #define PMC_SLPWK_ASR0_PID17 PMC_SLPWK_ASR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID17_Msk instead */ 2535 #define PMC_SLPWK_ASR0_PID18_Pos 18 /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Position */ 2536 #define PMC_SLPWK_ASR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID18_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Mask */ 2537 #define PMC_SLPWK_ASR0_PID18 PMC_SLPWK_ASR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID18_Msk instead */ 2538 #define PMC_SLPWK_ASR0_PID19_Pos 19 /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Position */ 2539 #define PMC_SLPWK_ASR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID19_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Mask */ 2540 #define PMC_SLPWK_ASR0_PID19 PMC_SLPWK_ASR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID19_Msk instead */ 2541 #define PMC_SLPWK_ASR0_PID20_Pos 20 /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Position */ 2542 #define PMC_SLPWK_ASR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID20_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Mask */ 2543 #define PMC_SLPWK_ASR0_PID20 PMC_SLPWK_ASR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID20_Msk instead */ 2544 #define PMC_SLPWK_ASR0_PID21_Pos 21 /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Position */ 2545 #define PMC_SLPWK_ASR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID21_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Mask */ 2546 #define PMC_SLPWK_ASR0_PID21 PMC_SLPWK_ASR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID21_Msk instead */ 2547 #define PMC_SLPWK_ASR0_PID22_Pos 22 /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Position */ 2548 #define PMC_SLPWK_ASR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID22_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Mask */ 2549 #define PMC_SLPWK_ASR0_PID22 PMC_SLPWK_ASR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID22_Msk instead */ 2550 #define PMC_SLPWK_ASR0_PID23_Pos 23 /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Position */ 2551 #define PMC_SLPWK_ASR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID23_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Mask */ 2552 #define PMC_SLPWK_ASR0_PID23 PMC_SLPWK_ASR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID23_Msk instead */ 2553 #define PMC_SLPWK_ASR0_PID24_Pos 24 /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Position */ 2554 #define PMC_SLPWK_ASR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID24_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Mask */ 2555 #define PMC_SLPWK_ASR0_PID24 PMC_SLPWK_ASR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID24_Msk instead */ 2556 #define PMC_SLPWK_ASR0_PID25_Pos 25 /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Position */ 2557 #define PMC_SLPWK_ASR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID25_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Mask */ 2558 #define PMC_SLPWK_ASR0_PID25 PMC_SLPWK_ASR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID25_Msk instead */ 2559 #define PMC_SLPWK_ASR0_PID26_Pos 26 /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Position */ 2560 #define PMC_SLPWK_ASR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID26_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Mask */ 2561 #define PMC_SLPWK_ASR0_PID26 PMC_SLPWK_ASR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID26_Msk instead */ 2562 #define PMC_SLPWK_ASR0_PID27_Pos 27 /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Position */ 2563 #define PMC_SLPWK_ASR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID27_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Mask */ 2564 #define PMC_SLPWK_ASR0_PID27 PMC_SLPWK_ASR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID27_Msk instead */ 2565 #define PMC_SLPWK_ASR0_PID28_Pos 28 /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Position */ 2566 #define PMC_SLPWK_ASR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID28_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Mask */ 2567 #define PMC_SLPWK_ASR0_PID28 PMC_SLPWK_ASR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID28_Msk instead */ 2568 #define PMC_SLPWK_ASR0_PID29_Pos 29 /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Position */ 2569 #define PMC_SLPWK_ASR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID29_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Mask */ 2570 #define PMC_SLPWK_ASR0_PID29 PMC_SLPWK_ASR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID29_Msk instead */ 2571 #define PMC_SLPWK_ASR0_PID30_Pos 30 /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Position */ 2572 #define PMC_SLPWK_ASR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID30_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Mask */ 2573 #define PMC_SLPWK_ASR0_PID30 PMC_SLPWK_ASR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID30_Msk instead */ 2574 #define PMC_SLPWK_ASR0_PID31_Pos 31 /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Position */ 2575 #define PMC_SLPWK_ASR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID31_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Mask */ 2576 #define PMC_SLPWK_ASR0_PID31 PMC_SLPWK_ASR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID31_Msk instead */ 2577 #define PMC_SLPWK_ASR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_ASR0) Register MASK (Use PMC_SLPWK_ASR0_Msk instead) */ 2578 #define PMC_SLPWK_ASR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ASR0) Register Mask */ 2579 2580 #define PMC_SLPWK_ASR0_PID_Pos 7 /**< (PMC_SLPWK_ASR0 Position) Peripheral 3x Activity Status */ 2581 #define PMC_SLPWK_ASR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR0_PID_Pos) /**< (PMC_SLPWK_ASR0 Mask) PID */ 2582 #define PMC_SLPWK_ASR0_PID(value) (PMC_SLPWK_ASR0_PID_Msk & ((value) << PMC_SLPWK_ASR0_PID_Pos)) 2583 2584 /* -------- PMC_PMMR : (PMC Offset: 0x130) (R/W 32) PLL Maximum Multiplier Value Register -------- */ 2585 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2586 #if COMPONENT_TYPEDEF_STYLE == 'N' 2587 typedef union { 2588 struct { 2589 uint32_t PLLA_MMAX:11; /**< bit: 0..10 PLLA Maximum Allowed Multiplier Value */ 2590 uint32_t :21; /**< bit: 11..31 Reserved */ 2591 } bit; /**< Structure used for bit access */ 2592 uint32_t reg; /**< Type used for register access */ 2593 } PMC_PMMR_Type; 2594 #endif 2595 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2596 2597 #define PMC_PMMR_OFFSET (0x130) /**< (PMC_PMMR) PLL Maximum Multiplier Value Register Offset */ 2598 2599 #define PMC_PMMR_PLLA_MMAX_Pos 0 /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Position */ 2600 #define PMC_PMMR_PLLA_MMAX_Msk (_U_(0x7FF) << PMC_PMMR_PLLA_MMAX_Pos) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Mask */ 2601 #define PMC_PMMR_PLLA_MMAX(value) (PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)) 2602 #define PMC_PMMR_MASK _U_(0x7FF) /**< \deprecated (PMC_PMMR) Register MASK (Use PMC_PMMR_Msk instead) */ 2603 #define PMC_PMMR_Msk _U_(0x7FF) /**< (PMC_PMMR) Register Mask */ 2604 2605 2606 /* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x134) (/W 32) SleepWalking Enable Register 1 -------- */ 2607 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2608 #if COMPONENT_TYPEDEF_STYLE == 'N' 2609 typedef union { 2610 struct { 2611 uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Enable */ 2612 uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Enable */ 2613 uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Enable */ 2614 uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Enable */ 2615 uint32_t :1; /**< bit: 4 Reserved */ 2616 uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Enable */ 2617 uint32_t :1; /**< bit: 6 Reserved */ 2618 uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Enable */ 2619 uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Enable */ 2620 uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Enable */ 2621 uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Enable */ 2622 uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Enable */ 2623 uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Enable */ 2624 uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Enable */ 2625 uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Enable */ 2626 uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Enable */ 2627 uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Enable */ 2628 uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Enable */ 2629 uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Enable */ 2630 uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Enable */ 2631 uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Enable */ 2632 uint32_t PID53:1; /**< bit: 21 Peripheral 53 SleepWalking Enable */ 2633 uint32_t :2; /**< bit: 22..23 Reserved */ 2634 uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Enable */ 2635 uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Enable */ 2636 uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Enable */ 2637 uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Enable */ 2638 uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Enable */ 2639 uint32_t :3; /**< bit: 29..31 Reserved */ 2640 } bit; /**< Structure used for bit access */ 2641 struct { 2642 uint32_t PID:25; /**< bit: 0..24 Peripheral 6x SleepWalking Enable */ 2643 uint32_t :7; /**< bit: 25..31 Reserved */ 2644 } vec; /**< Structure used for vec access */ 2645 uint32_t reg; /**< Type used for register access */ 2646 } PMC_SLPWK_ER1_Type; 2647 #endif 2648 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2649 2650 #define PMC_SLPWK_ER1_OFFSET (0x134) /**< (PMC_SLPWK_ER1) SleepWalking Enable Register 1 Offset */ 2651 2652 #define PMC_SLPWK_ER1_PID32_Pos 0 /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Position */ 2653 #define PMC_SLPWK_ER1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID32_Pos) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Mask */ 2654 #define PMC_SLPWK_ER1_PID32 PMC_SLPWK_ER1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID32_Msk instead */ 2655 #define PMC_SLPWK_ER1_PID33_Pos 1 /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Position */ 2656 #define PMC_SLPWK_ER1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID33_Pos) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Mask */ 2657 #define PMC_SLPWK_ER1_PID33 PMC_SLPWK_ER1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID33_Msk instead */ 2658 #define PMC_SLPWK_ER1_PID34_Pos 2 /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Position */ 2659 #define PMC_SLPWK_ER1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID34_Pos) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Mask */ 2660 #define PMC_SLPWK_ER1_PID34 PMC_SLPWK_ER1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID34_Msk instead */ 2661 #define PMC_SLPWK_ER1_PID35_Pos 3 /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Position */ 2662 #define PMC_SLPWK_ER1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID35_Pos) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Mask */ 2663 #define PMC_SLPWK_ER1_PID35 PMC_SLPWK_ER1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID35_Msk instead */ 2664 #define PMC_SLPWK_ER1_PID37_Pos 5 /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Position */ 2665 #define PMC_SLPWK_ER1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID37_Pos) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Mask */ 2666 #define PMC_SLPWK_ER1_PID37 PMC_SLPWK_ER1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID37_Msk instead */ 2667 #define PMC_SLPWK_ER1_PID39_Pos 7 /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Position */ 2668 #define PMC_SLPWK_ER1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID39_Pos) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Mask */ 2669 #define PMC_SLPWK_ER1_PID39 PMC_SLPWK_ER1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID39_Msk instead */ 2670 #define PMC_SLPWK_ER1_PID40_Pos 8 /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Position */ 2671 #define PMC_SLPWK_ER1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID40_Pos) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Mask */ 2672 #define PMC_SLPWK_ER1_PID40 PMC_SLPWK_ER1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID40_Msk instead */ 2673 #define PMC_SLPWK_ER1_PID41_Pos 9 /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Position */ 2674 #define PMC_SLPWK_ER1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID41_Pos) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Mask */ 2675 #define PMC_SLPWK_ER1_PID41 PMC_SLPWK_ER1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID41_Msk instead */ 2676 #define PMC_SLPWK_ER1_PID42_Pos 10 /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Position */ 2677 #define PMC_SLPWK_ER1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID42_Pos) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Mask */ 2678 #define PMC_SLPWK_ER1_PID42 PMC_SLPWK_ER1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID42_Msk instead */ 2679 #define PMC_SLPWK_ER1_PID43_Pos 11 /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Position */ 2680 #define PMC_SLPWK_ER1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID43_Pos) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Mask */ 2681 #define PMC_SLPWK_ER1_PID43 PMC_SLPWK_ER1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID43_Msk instead */ 2682 #define PMC_SLPWK_ER1_PID44_Pos 12 /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Position */ 2683 #define PMC_SLPWK_ER1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID44_Pos) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Mask */ 2684 #define PMC_SLPWK_ER1_PID44 PMC_SLPWK_ER1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID44_Msk instead */ 2685 #define PMC_SLPWK_ER1_PID45_Pos 13 /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Position */ 2686 #define PMC_SLPWK_ER1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID45_Pos) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Mask */ 2687 #define PMC_SLPWK_ER1_PID45 PMC_SLPWK_ER1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID45_Msk instead */ 2688 #define PMC_SLPWK_ER1_PID46_Pos 14 /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Position */ 2689 #define PMC_SLPWK_ER1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID46_Pos) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Mask */ 2690 #define PMC_SLPWK_ER1_PID46 PMC_SLPWK_ER1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID46_Msk instead */ 2691 #define PMC_SLPWK_ER1_PID47_Pos 15 /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Position */ 2692 #define PMC_SLPWK_ER1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID47_Pos) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Mask */ 2693 #define PMC_SLPWK_ER1_PID47 PMC_SLPWK_ER1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID47_Msk instead */ 2694 #define PMC_SLPWK_ER1_PID48_Pos 16 /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Position */ 2695 #define PMC_SLPWK_ER1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID48_Pos) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Mask */ 2696 #define PMC_SLPWK_ER1_PID48 PMC_SLPWK_ER1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID48_Msk instead */ 2697 #define PMC_SLPWK_ER1_PID49_Pos 17 /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Position */ 2698 #define PMC_SLPWK_ER1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID49_Pos) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Mask */ 2699 #define PMC_SLPWK_ER1_PID49 PMC_SLPWK_ER1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID49_Msk instead */ 2700 #define PMC_SLPWK_ER1_PID50_Pos 18 /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Position */ 2701 #define PMC_SLPWK_ER1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID50_Pos) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Mask */ 2702 #define PMC_SLPWK_ER1_PID50 PMC_SLPWK_ER1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID50_Msk instead */ 2703 #define PMC_SLPWK_ER1_PID51_Pos 19 /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Position */ 2704 #define PMC_SLPWK_ER1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID51_Pos) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Mask */ 2705 #define PMC_SLPWK_ER1_PID51 PMC_SLPWK_ER1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID51_Msk instead */ 2706 #define PMC_SLPWK_ER1_PID52_Pos 20 /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Position */ 2707 #define PMC_SLPWK_ER1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID52_Pos) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Mask */ 2708 #define PMC_SLPWK_ER1_PID52 PMC_SLPWK_ER1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID52_Msk instead */ 2709 #define PMC_SLPWK_ER1_PID53_Pos 21 /**< (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable Position */ 2710 #define PMC_SLPWK_ER1_PID53_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID53_Pos) /**< (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable Mask */ 2711 #define PMC_SLPWK_ER1_PID53 PMC_SLPWK_ER1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID53_Msk instead */ 2712 #define PMC_SLPWK_ER1_PID56_Pos 24 /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Position */ 2713 #define PMC_SLPWK_ER1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID56_Pos) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Mask */ 2714 #define PMC_SLPWK_ER1_PID56 PMC_SLPWK_ER1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID56_Msk instead */ 2715 #define PMC_SLPWK_ER1_PID57_Pos 25 /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Position */ 2716 #define PMC_SLPWK_ER1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID57_Pos) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Mask */ 2717 #define PMC_SLPWK_ER1_PID57 PMC_SLPWK_ER1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID57_Msk instead */ 2718 #define PMC_SLPWK_ER1_PID58_Pos 26 /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Position */ 2719 #define PMC_SLPWK_ER1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID58_Pos) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Mask */ 2720 #define PMC_SLPWK_ER1_PID58 PMC_SLPWK_ER1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID58_Msk instead */ 2721 #define PMC_SLPWK_ER1_PID59_Pos 27 /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Position */ 2722 #define PMC_SLPWK_ER1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID59_Pos) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Mask */ 2723 #define PMC_SLPWK_ER1_PID59 PMC_SLPWK_ER1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID59_Msk instead */ 2724 #define PMC_SLPWK_ER1_PID60_Pos 28 /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Position */ 2725 #define PMC_SLPWK_ER1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID60_Pos) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Mask */ 2726 #define PMC_SLPWK_ER1_PID60 PMC_SLPWK_ER1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID60_Msk instead */ 2727 #define PMC_SLPWK_ER1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_SLPWK_ER1) Register MASK (Use PMC_SLPWK_ER1_Msk instead) */ 2728 #define PMC_SLPWK_ER1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_ER1) Register Mask */ 2729 2730 #define PMC_SLPWK_ER1_PID_Pos 0 /**< (PMC_SLPWK_ER1 Position) Peripheral 6x SleepWalking Enable */ 2731 #define PMC_SLPWK_ER1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER1_PID_Pos) /**< (PMC_SLPWK_ER1 Mask) PID */ 2732 #define PMC_SLPWK_ER1_PID(value) (PMC_SLPWK_ER1_PID_Msk & ((value) << PMC_SLPWK_ER1_PID_Pos)) 2733 2734 /* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x138) (/W 32) SleepWalking Disable Register 1 -------- */ 2735 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2736 #if COMPONENT_TYPEDEF_STYLE == 'N' 2737 typedef union { 2738 struct { 2739 uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Disable */ 2740 uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Disable */ 2741 uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Disable */ 2742 uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Disable */ 2743 uint32_t :1; /**< bit: 4 Reserved */ 2744 uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Disable */ 2745 uint32_t :1; /**< bit: 6 Reserved */ 2746 uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Disable */ 2747 uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Disable */ 2748 uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Disable */ 2749 uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Disable */ 2750 uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Disable */ 2751 uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Disable */ 2752 uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Disable */ 2753 uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Disable */ 2754 uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Disable */ 2755 uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Disable */ 2756 uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Disable */ 2757 uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Disable */ 2758 uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Disable */ 2759 uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Disable */ 2760 uint32_t PID53:1; /**< bit: 21 Peripheral 53 SleepWalking Disable */ 2761 uint32_t :2; /**< bit: 22..23 Reserved */ 2762 uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Disable */ 2763 uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Disable */ 2764 uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Disable */ 2765 uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Disable */ 2766 uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Disable */ 2767 uint32_t :3; /**< bit: 29..31 Reserved */ 2768 } bit; /**< Structure used for bit access */ 2769 struct { 2770 uint32_t PID:25; /**< bit: 0..24 Peripheral 6x SleepWalking Disable */ 2771 uint32_t :7; /**< bit: 25..31 Reserved */ 2772 } vec; /**< Structure used for vec access */ 2773 uint32_t reg; /**< Type used for register access */ 2774 } PMC_SLPWK_DR1_Type; 2775 #endif 2776 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2777 2778 #define PMC_SLPWK_DR1_OFFSET (0x138) /**< (PMC_SLPWK_DR1) SleepWalking Disable Register 1 Offset */ 2779 2780 #define PMC_SLPWK_DR1_PID32_Pos 0 /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Position */ 2781 #define PMC_SLPWK_DR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID32_Pos) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Mask */ 2782 #define PMC_SLPWK_DR1_PID32 PMC_SLPWK_DR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID32_Msk instead */ 2783 #define PMC_SLPWK_DR1_PID33_Pos 1 /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Position */ 2784 #define PMC_SLPWK_DR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID33_Pos) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Mask */ 2785 #define PMC_SLPWK_DR1_PID33 PMC_SLPWK_DR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID33_Msk instead */ 2786 #define PMC_SLPWK_DR1_PID34_Pos 2 /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Position */ 2787 #define PMC_SLPWK_DR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID34_Pos) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Mask */ 2788 #define PMC_SLPWK_DR1_PID34 PMC_SLPWK_DR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID34_Msk instead */ 2789 #define PMC_SLPWK_DR1_PID35_Pos 3 /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Position */ 2790 #define PMC_SLPWK_DR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID35_Pos) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Mask */ 2791 #define PMC_SLPWK_DR1_PID35 PMC_SLPWK_DR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID35_Msk instead */ 2792 #define PMC_SLPWK_DR1_PID37_Pos 5 /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Position */ 2793 #define PMC_SLPWK_DR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID37_Pos) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Mask */ 2794 #define PMC_SLPWK_DR1_PID37 PMC_SLPWK_DR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID37_Msk instead */ 2795 #define PMC_SLPWK_DR1_PID39_Pos 7 /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Position */ 2796 #define PMC_SLPWK_DR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID39_Pos) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Mask */ 2797 #define PMC_SLPWK_DR1_PID39 PMC_SLPWK_DR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID39_Msk instead */ 2798 #define PMC_SLPWK_DR1_PID40_Pos 8 /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Position */ 2799 #define PMC_SLPWK_DR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID40_Pos) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Mask */ 2800 #define PMC_SLPWK_DR1_PID40 PMC_SLPWK_DR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID40_Msk instead */ 2801 #define PMC_SLPWK_DR1_PID41_Pos 9 /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Position */ 2802 #define PMC_SLPWK_DR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID41_Pos) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Mask */ 2803 #define PMC_SLPWK_DR1_PID41 PMC_SLPWK_DR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID41_Msk instead */ 2804 #define PMC_SLPWK_DR1_PID42_Pos 10 /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Position */ 2805 #define PMC_SLPWK_DR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID42_Pos) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Mask */ 2806 #define PMC_SLPWK_DR1_PID42 PMC_SLPWK_DR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID42_Msk instead */ 2807 #define PMC_SLPWK_DR1_PID43_Pos 11 /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Position */ 2808 #define PMC_SLPWK_DR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID43_Pos) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Mask */ 2809 #define PMC_SLPWK_DR1_PID43 PMC_SLPWK_DR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID43_Msk instead */ 2810 #define PMC_SLPWK_DR1_PID44_Pos 12 /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Position */ 2811 #define PMC_SLPWK_DR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID44_Pos) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Mask */ 2812 #define PMC_SLPWK_DR1_PID44 PMC_SLPWK_DR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID44_Msk instead */ 2813 #define PMC_SLPWK_DR1_PID45_Pos 13 /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Position */ 2814 #define PMC_SLPWK_DR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID45_Pos) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Mask */ 2815 #define PMC_SLPWK_DR1_PID45 PMC_SLPWK_DR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID45_Msk instead */ 2816 #define PMC_SLPWK_DR1_PID46_Pos 14 /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Position */ 2817 #define PMC_SLPWK_DR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID46_Pos) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Mask */ 2818 #define PMC_SLPWK_DR1_PID46 PMC_SLPWK_DR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID46_Msk instead */ 2819 #define PMC_SLPWK_DR1_PID47_Pos 15 /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Position */ 2820 #define PMC_SLPWK_DR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID47_Pos) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Mask */ 2821 #define PMC_SLPWK_DR1_PID47 PMC_SLPWK_DR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID47_Msk instead */ 2822 #define PMC_SLPWK_DR1_PID48_Pos 16 /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Position */ 2823 #define PMC_SLPWK_DR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID48_Pos) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Mask */ 2824 #define PMC_SLPWK_DR1_PID48 PMC_SLPWK_DR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID48_Msk instead */ 2825 #define PMC_SLPWK_DR1_PID49_Pos 17 /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Position */ 2826 #define PMC_SLPWK_DR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID49_Pos) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Mask */ 2827 #define PMC_SLPWK_DR1_PID49 PMC_SLPWK_DR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID49_Msk instead */ 2828 #define PMC_SLPWK_DR1_PID50_Pos 18 /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Position */ 2829 #define PMC_SLPWK_DR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID50_Pos) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Mask */ 2830 #define PMC_SLPWK_DR1_PID50 PMC_SLPWK_DR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID50_Msk instead */ 2831 #define PMC_SLPWK_DR1_PID51_Pos 19 /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Position */ 2832 #define PMC_SLPWK_DR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID51_Pos) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Mask */ 2833 #define PMC_SLPWK_DR1_PID51 PMC_SLPWK_DR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID51_Msk instead */ 2834 #define PMC_SLPWK_DR1_PID52_Pos 20 /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Position */ 2835 #define PMC_SLPWK_DR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID52_Pos) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Mask */ 2836 #define PMC_SLPWK_DR1_PID52 PMC_SLPWK_DR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID52_Msk instead */ 2837 #define PMC_SLPWK_DR1_PID53_Pos 21 /**< (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable Position */ 2838 #define PMC_SLPWK_DR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID53_Pos) /**< (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable Mask */ 2839 #define PMC_SLPWK_DR1_PID53 PMC_SLPWK_DR1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID53_Msk instead */ 2840 #define PMC_SLPWK_DR1_PID56_Pos 24 /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Position */ 2841 #define PMC_SLPWK_DR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID56_Pos) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Mask */ 2842 #define PMC_SLPWK_DR1_PID56 PMC_SLPWK_DR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID56_Msk instead */ 2843 #define PMC_SLPWK_DR1_PID57_Pos 25 /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Position */ 2844 #define PMC_SLPWK_DR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID57_Pos) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Mask */ 2845 #define PMC_SLPWK_DR1_PID57 PMC_SLPWK_DR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID57_Msk instead */ 2846 #define PMC_SLPWK_DR1_PID58_Pos 26 /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Position */ 2847 #define PMC_SLPWK_DR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID58_Pos) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Mask */ 2848 #define PMC_SLPWK_DR1_PID58 PMC_SLPWK_DR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID58_Msk instead */ 2849 #define PMC_SLPWK_DR1_PID59_Pos 27 /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Position */ 2850 #define PMC_SLPWK_DR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID59_Pos) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Mask */ 2851 #define PMC_SLPWK_DR1_PID59 PMC_SLPWK_DR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID59_Msk instead */ 2852 #define PMC_SLPWK_DR1_PID60_Pos 28 /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Position */ 2853 #define PMC_SLPWK_DR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID60_Pos) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Mask */ 2854 #define PMC_SLPWK_DR1_PID60 PMC_SLPWK_DR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID60_Msk instead */ 2855 #define PMC_SLPWK_DR1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_SLPWK_DR1) Register MASK (Use PMC_SLPWK_DR1_Msk instead) */ 2856 #define PMC_SLPWK_DR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_DR1) Register Mask */ 2857 2858 #define PMC_SLPWK_DR1_PID_Pos 0 /**< (PMC_SLPWK_DR1 Position) Peripheral 6x SleepWalking Disable */ 2859 #define PMC_SLPWK_DR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR1_PID_Pos) /**< (PMC_SLPWK_DR1 Mask) PID */ 2860 #define PMC_SLPWK_DR1_PID(value) (PMC_SLPWK_DR1_PID_Msk & ((value) << PMC_SLPWK_DR1_PID_Pos)) 2861 2862 /* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x13c) (R/ 32) SleepWalking Status Register 1 -------- */ 2863 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2864 #if COMPONENT_TYPEDEF_STYLE == 'N' 2865 typedef union { 2866 struct { 2867 uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Status */ 2868 uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Status */ 2869 uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Status */ 2870 uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Status */ 2871 uint32_t :1; /**< bit: 4 Reserved */ 2872 uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Status */ 2873 uint32_t :1; /**< bit: 6 Reserved */ 2874 uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Status */ 2875 uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Status */ 2876 uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Status */ 2877 uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Status */ 2878 uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Status */ 2879 uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Status */ 2880 uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Status */ 2881 uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Status */ 2882 uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Status */ 2883 uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Status */ 2884 uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Status */ 2885 uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Status */ 2886 uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Status */ 2887 uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Status */ 2888 uint32_t PID53:1; /**< bit: 21 Peripheral 53 SleepWalking Status */ 2889 uint32_t :2; /**< bit: 22..23 Reserved */ 2890 uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Status */ 2891 uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Status */ 2892 uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Status */ 2893 uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Status */ 2894 uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Status */ 2895 uint32_t :3; /**< bit: 29..31 Reserved */ 2896 } bit; /**< Structure used for bit access */ 2897 struct { 2898 uint32_t PID:25; /**< bit: 0..24 Peripheral 6x SleepWalking Status */ 2899 uint32_t :7; /**< bit: 25..31 Reserved */ 2900 } vec; /**< Structure used for vec access */ 2901 uint32_t reg; /**< Type used for register access */ 2902 } PMC_SLPWK_SR1_Type; 2903 #endif 2904 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2905 2906 #define PMC_SLPWK_SR1_OFFSET (0x13C) /**< (PMC_SLPWK_SR1) SleepWalking Status Register 1 Offset */ 2907 2908 #define PMC_SLPWK_SR1_PID32_Pos 0 /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Position */ 2909 #define PMC_SLPWK_SR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID32_Pos) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Mask */ 2910 #define PMC_SLPWK_SR1_PID32 PMC_SLPWK_SR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID32_Msk instead */ 2911 #define PMC_SLPWK_SR1_PID33_Pos 1 /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Position */ 2912 #define PMC_SLPWK_SR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID33_Pos) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Mask */ 2913 #define PMC_SLPWK_SR1_PID33 PMC_SLPWK_SR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID33_Msk instead */ 2914 #define PMC_SLPWK_SR1_PID34_Pos 2 /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Position */ 2915 #define PMC_SLPWK_SR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID34_Pos) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Mask */ 2916 #define PMC_SLPWK_SR1_PID34 PMC_SLPWK_SR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID34_Msk instead */ 2917 #define PMC_SLPWK_SR1_PID35_Pos 3 /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Position */ 2918 #define PMC_SLPWK_SR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID35_Pos) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Mask */ 2919 #define PMC_SLPWK_SR1_PID35 PMC_SLPWK_SR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID35_Msk instead */ 2920 #define PMC_SLPWK_SR1_PID37_Pos 5 /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Position */ 2921 #define PMC_SLPWK_SR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID37_Pos) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Mask */ 2922 #define PMC_SLPWK_SR1_PID37 PMC_SLPWK_SR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID37_Msk instead */ 2923 #define PMC_SLPWK_SR1_PID39_Pos 7 /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Position */ 2924 #define PMC_SLPWK_SR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID39_Pos) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Mask */ 2925 #define PMC_SLPWK_SR1_PID39 PMC_SLPWK_SR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID39_Msk instead */ 2926 #define PMC_SLPWK_SR1_PID40_Pos 8 /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Position */ 2927 #define PMC_SLPWK_SR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID40_Pos) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Mask */ 2928 #define PMC_SLPWK_SR1_PID40 PMC_SLPWK_SR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID40_Msk instead */ 2929 #define PMC_SLPWK_SR1_PID41_Pos 9 /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Position */ 2930 #define PMC_SLPWK_SR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID41_Pos) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Mask */ 2931 #define PMC_SLPWK_SR1_PID41 PMC_SLPWK_SR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID41_Msk instead */ 2932 #define PMC_SLPWK_SR1_PID42_Pos 10 /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Position */ 2933 #define PMC_SLPWK_SR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID42_Pos) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Mask */ 2934 #define PMC_SLPWK_SR1_PID42 PMC_SLPWK_SR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID42_Msk instead */ 2935 #define PMC_SLPWK_SR1_PID43_Pos 11 /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Position */ 2936 #define PMC_SLPWK_SR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID43_Pos) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Mask */ 2937 #define PMC_SLPWK_SR1_PID43 PMC_SLPWK_SR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID43_Msk instead */ 2938 #define PMC_SLPWK_SR1_PID44_Pos 12 /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Position */ 2939 #define PMC_SLPWK_SR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID44_Pos) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Mask */ 2940 #define PMC_SLPWK_SR1_PID44 PMC_SLPWK_SR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID44_Msk instead */ 2941 #define PMC_SLPWK_SR1_PID45_Pos 13 /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Position */ 2942 #define PMC_SLPWK_SR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID45_Pos) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Mask */ 2943 #define PMC_SLPWK_SR1_PID45 PMC_SLPWK_SR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID45_Msk instead */ 2944 #define PMC_SLPWK_SR1_PID46_Pos 14 /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Position */ 2945 #define PMC_SLPWK_SR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID46_Pos) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Mask */ 2946 #define PMC_SLPWK_SR1_PID46 PMC_SLPWK_SR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID46_Msk instead */ 2947 #define PMC_SLPWK_SR1_PID47_Pos 15 /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Position */ 2948 #define PMC_SLPWK_SR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID47_Pos) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Mask */ 2949 #define PMC_SLPWK_SR1_PID47 PMC_SLPWK_SR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID47_Msk instead */ 2950 #define PMC_SLPWK_SR1_PID48_Pos 16 /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Position */ 2951 #define PMC_SLPWK_SR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID48_Pos) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Mask */ 2952 #define PMC_SLPWK_SR1_PID48 PMC_SLPWK_SR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID48_Msk instead */ 2953 #define PMC_SLPWK_SR1_PID49_Pos 17 /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Position */ 2954 #define PMC_SLPWK_SR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID49_Pos) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Mask */ 2955 #define PMC_SLPWK_SR1_PID49 PMC_SLPWK_SR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID49_Msk instead */ 2956 #define PMC_SLPWK_SR1_PID50_Pos 18 /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Position */ 2957 #define PMC_SLPWK_SR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID50_Pos) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Mask */ 2958 #define PMC_SLPWK_SR1_PID50 PMC_SLPWK_SR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID50_Msk instead */ 2959 #define PMC_SLPWK_SR1_PID51_Pos 19 /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Position */ 2960 #define PMC_SLPWK_SR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID51_Pos) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Mask */ 2961 #define PMC_SLPWK_SR1_PID51 PMC_SLPWK_SR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID51_Msk instead */ 2962 #define PMC_SLPWK_SR1_PID52_Pos 20 /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Position */ 2963 #define PMC_SLPWK_SR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID52_Pos) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Mask */ 2964 #define PMC_SLPWK_SR1_PID52 PMC_SLPWK_SR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID52_Msk instead */ 2965 #define PMC_SLPWK_SR1_PID53_Pos 21 /**< (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status Position */ 2966 #define PMC_SLPWK_SR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID53_Pos) /**< (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status Mask */ 2967 #define PMC_SLPWK_SR1_PID53 PMC_SLPWK_SR1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID53_Msk instead */ 2968 #define PMC_SLPWK_SR1_PID56_Pos 24 /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Position */ 2969 #define PMC_SLPWK_SR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID56_Pos) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Mask */ 2970 #define PMC_SLPWK_SR1_PID56 PMC_SLPWK_SR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID56_Msk instead */ 2971 #define PMC_SLPWK_SR1_PID57_Pos 25 /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Position */ 2972 #define PMC_SLPWK_SR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID57_Pos) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Mask */ 2973 #define PMC_SLPWK_SR1_PID57 PMC_SLPWK_SR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID57_Msk instead */ 2974 #define PMC_SLPWK_SR1_PID58_Pos 26 /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Position */ 2975 #define PMC_SLPWK_SR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID58_Pos) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Mask */ 2976 #define PMC_SLPWK_SR1_PID58 PMC_SLPWK_SR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID58_Msk instead */ 2977 #define PMC_SLPWK_SR1_PID59_Pos 27 /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Position */ 2978 #define PMC_SLPWK_SR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID59_Pos) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Mask */ 2979 #define PMC_SLPWK_SR1_PID59 PMC_SLPWK_SR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID59_Msk instead */ 2980 #define PMC_SLPWK_SR1_PID60_Pos 28 /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Position */ 2981 #define PMC_SLPWK_SR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID60_Pos) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Mask */ 2982 #define PMC_SLPWK_SR1_PID60 PMC_SLPWK_SR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID60_Msk instead */ 2983 #define PMC_SLPWK_SR1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_SLPWK_SR1) Register MASK (Use PMC_SLPWK_SR1_Msk instead) */ 2984 #define PMC_SLPWK_SR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_SR1) Register Mask */ 2985 2986 #define PMC_SLPWK_SR1_PID_Pos 0 /**< (PMC_SLPWK_SR1 Position) Peripheral 6x SleepWalking Status */ 2987 #define PMC_SLPWK_SR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR1_PID_Pos) /**< (PMC_SLPWK_SR1 Mask) PID */ 2988 #define PMC_SLPWK_SR1_PID(value) (PMC_SLPWK_SR1_PID_Msk & ((value) << PMC_SLPWK_SR1_PID_Pos)) 2989 2990 /* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x140) (R/ 32) SleepWalking Activity Status Register 1 -------- */ 2991 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2992 #if COMPONENT_TYPEDEF_STYLE == 'N' 2993 typedef union { 2994 struct { 2995 uint32_t PID32:1; /**< bit: 0 Peripheral 32 Activity Status */ 2996 uint32_t PID33:1; /**< bit: 1 Peripheral 33 Activity Status */ 2997 uint32_t PID34:1; /**< bit: 2 Peripheral 34 Activity Status */ 2998 uint32_t PID35:1; /**< bit: 3 Peripheral 35 Activity Status */ 2999 uint32_t :1; /**< bit: 4 Reserved */ 3000 uint32_t PID37:1; /**< bit: 5 Peripheral 37 Activity Status */ 3001 uint32_t :1; /**< bit: 6 Reserved */ 3002 uint32_t PID39:1; /**< bit: 7 Peripheral 39 Activity Status */ 3003 uint32_t PID40:1; /**< bit: 8 Peripheral 40 Activity Status */ 3004 uint32_t PID41:1; /**< bit: 9 Peripheral 41 Activity Status */ 3005 uint32_t PID42:1; /**< bit: 10 Peripheral 42 Activity Status */ 3006 uint32_t PID43:1; /**< bit: 11 Peripheral 43 Activity Status */ 3007 uint32_t PID44:1; /**< bit: 12 Peripheral 44 Activity Status */ 3008 uint32_t PID45:1; /**< bit: 13 Peripheral 45 Activity Status */ 3009 uint32_t PID46:1; /**< bit: 14 Peripheral 46 Activity Status */ 3010 uint32_t PID47:1; /**< bit: 15 Peripheral 47 Activity Status */ 3011 uint32_t PID48:1; /**< bit: 16 Peripheral 48 Activity Status */ 3012 uint32_t PID49:1; /**< bit: 17 Peripheral 49 Activity Status */ 3013 uint32_t PID50:1; /**< bit: 18 Peripheral 50 Activity Status */ 3014 uint32_t PID51:1; /**< bit: 19 Peripheral 51 Activity Status */ 3015 uint32_t PID52:1; /**< bit: 20 Peripheral 52 Activity Status */ 3016 uint32_t PID53:1; /**< bit: 21 Peripheral 53 Activity Status */ 3017 uint32_t :2; /**< bit: 22..23 Reserved */ 3018 uint32_t PID56:1; /**< bit: 24 Peripheral 56 Activity Status */ 3019 uint32_t PID57:1; /**< bit: 25 Peripheral 57 Activity Status */ 3020 uint32_t PID58:1; /**< bit: 26 Peripheral 58 Activity Status */ 3021 uint32_t PID59:1; /**< bit: 27 Peripheral 59 Activity Status */ 3022 uint32_t PID60:1; /**< bit: 28 Peripheral 60 Activity Status */ 3023 uint32_t :3; /**< bit: 29..31 Reserved */ 3024 } bit; /**< Structure used for bit access */ 3025 struct { 3026 uint32_t PID:25; /**< bit: 0..24 Peripheral 6x Activity Status */ 3027 uint32_t :7; /**< bit: 25..31 Reserved */ 3028 } vec; /**< Structure used for vec access */ 3029 uint32_t reg; /**< Type used for register access */ 3030 } PMC_SLPWK_ASR1_Type; 3031 #endif 3032 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3033 3034 #define PMC_SLPWK_ASR1_OFFSET (0x140) /**< (PMC_SLPWK_ASR1) SleepWalking Activity Status Register 1 Offset */ 3035 3036 #define PMC_SLPWK_ASR1_PID32_Pos 0 /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Position */ 3037 #define PMC_SLPWK_ASR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID32_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Mask */ 3038 #define PMC_SLPWK_ASR1_PID32 PMC_SLPWK_ASR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID32_Msk instead */ 3039 #define PMC_SLPWK_ASR1_PID33_Pos 1 /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Position */ 3040 #define PMC_SLPWK_ASR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID33_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Mask */ 3041 #define PMC_SLPWK_ASR1_PID33 PMC_SLPWK_ASR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID33_Msk instead */ 3042 #define PMC_SLPWK_ASR1_PID34_Pos 2 /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Position */ 3043 #define PMC_SLPWK_ASR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID34_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Mask */ 3044 #define PMC_SLPWK_ASR1_PID34 PMC_SLPWK_ASR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID34_Msk instead */ 3045 #define PMC_SLPWK_ASR1_PID35_Pos 3 /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Position */ 3046 #define PMC_SLPWK_ASR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID35_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Mask */ 3047 #define PMC_SLPWK_ASR1_PID35 PMC_SLPWK_ASR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID35_Msk instead */ 3048 #define PMC_SLPWK_ASR1_PID37_Pos 5 /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Position */ 3049 #define PMC_SLPWK_ASR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID37_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Mask */ 3050 #define PMC_SLPWK_ASR1_PID37 PMC_SLPWK_ASR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID37_Msk instead */ 3051 #define PMC_SLPWK_ASR1_PID39_Pos 7 /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Position */ 3052 #define PMC_SLPWK_ASR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID39_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Mask */ 3053 #define PMC_SLPWK_ASR1_PID39 PMC_SLPWK_ASR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID39_Msk instead */ 3054 #define PMC_SLPWK_ASR1_PID40_Pos 8 /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Position */ 3055 #define PMC_SLPWK_ASR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID40_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Mask */ 3056 #define PMC_SLPWK_ASR1_PID40 PMC_SLPWK_ASR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID40_Msk instead */ 3057 #define PMC_SLPWK_ASR1_PID41_Pos 9 /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Position */ 3058 #define PMC_SLPWK_ASR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID41_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Mask */ 3059 #define PMC_SLPWK_ASR1_PID41 PMC_SLPWK_ASR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID41_Msk instead */ 3060 #define PMC_SLPWK_ASR1_PID42_Pos 10 /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Position */ 3061 #define PMC_SLPWK_ASR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID42_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Mask */ 3062 #define PMC_SLPWK_ASR1_PID42 PMC_SLPWK_ASR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID42_Msk instead */ 3063 #define PMC_SLPWK_ASR1_PID43_Pos 11 /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Position */ 3064 #define PMC_SLPWK_ASR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID43_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Mask */ 3065 #define PMC_SLPWK_ASR1_PID43 PMC_SLPWK_ASR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID43_Msk instead */ 3066 #define PMC_SLPWK_ASR1_PID44_Pos 12 /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Position */ 3067 #define PMC_SLPWK_ASR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID44_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Mask */ 3068 #define PMC_SLPWK_ASR1_PID44 PMC_SLPWK_ASR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID44_Msk instead */ 3069 #define PMC_SLPWK_ASR1_PID45_Pos 13 /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Position */ 3070 #define PMC_SLPWK_ASR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID45_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Mask */ 3071 #define PMC_SLPWK_ASR1_PID45 PMC_SLPWK_ASR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID45_Msk instead */ 3072 #define PMC_SLPWK_ASR1_PID46_Pos 14 /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Position */ 3073 #define PMC_SLPWK_ASR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID46_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Mask */ 3074 #define PMC_SLPWK_ASR1_PID46 PMC_SLPWK_ASR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID46_Msk instead */ 3075 #define PMC_SLPWK_ASR1_PID47_Pos 15 /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Position */ 3076 #define PMC_SLPWK_ASR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID47_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Mask */ 3077 #define PMC_SLPWK_ASR1_PID47 PMC_SLPWK_ASR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID47_Msk instead */ 3078 #define PMC_SLPWK_ASR1_PID48_Pos 16 /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Position */ 3079 #define PMC_SLPWK_ASR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID48_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Mask */ 3080 #define PMC_SLPWK_ASR1_PID48 PMC_SLPWK_ASR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID48_Msk instead */ 3081 #define PMC_SLPWK_ASR1_PID49_Pos 17 /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Position */ 3082 #define PMC_SLPWK_ASR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID49_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Mask */ 3083 #define PMC_SLPWK_ASR1_PID49 PMC_SLPWK_ASR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID49_Msk instead */ 3084 #define PMC_SLPWK_ASR1_PID50_Pos 18 /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Position */ 3085 #define PMC_SLPWK_ASR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID50_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Mask */ 3086 #define PMC_SLPWK_ASR1_PID50 PMC_SLPWK_ASR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID50_Msk instead */ 3087 #define PMC_SLPWK_ASR1_PID51_Pos 19 /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Position */ 3088 #define PMC_SLPWK_ASR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID51_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Mask */ 3089 #define PMC_SLPWK_ASR1_PID51 PMC_SLPWK_ASR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID51_Msk instead */ 3090 #define PMC_SLPWK_ASR1_PID52_Pos 20 /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Position */ 3091 #define PMC_SLPWK_ASR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID52_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Mask */ 3092 #define PMC_SLPWK_ASR1_PID52 PMC_SLPWK_ASR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID52_Msk instead */ 3093 #define PMC_SLPWK_ASR1_PID53_Pos 21 /**< (PMC_SLPWK_ASR1) Peripheral 53 Activity Status Position */ 3094 #define PMC_SLPWK_ASR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID53_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 53 Activity Status Mask */ 3095 #define PMC_SLPWK_ASR1_PID53 PMC_SLPWK_ASR1_PID53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID53_Msk instead */ 3096 #define PMC_SLPWK_ASR1_PID56_Pos 24 /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Position */ 3097 #define PMC_SLPWK_ASR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID56_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Mask */ 3098 #define PMC_SLPWK_ASR1_PID56 PMC_SLPWK_ASR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID56_Msk instead */ 3099 #define PMC_SLPWK_ASR1_PID57_Pos 25 /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Position */ 3100 #define PMC_SLPWK_ASR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID57_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Mask */ 3101 #define PMC_SLPWK_ASR1_PID57 PMC_SLPWK_ASR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID57_Msk instead */ 3102 #define PMC_SLPWK_ASR1_PID58_Pos 26 /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Position */ 3103 #define PMC_SLPWK_ASR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID58_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Mask */ 3104 #define PMC_SLPWK_ASR1_PID58 PMC_SLPWK_ASR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID58_Msk instead */ 3105 #define PMC_SLPWK_ASR1_PID59_Pos 27 /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Position */ 3106 #define PMC_SLPWK_ASR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID59_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Mask */ 3107 #define PMC_SLPWK_ASR1_PID59 PMC_SLPWK_ASR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID59_Msk instead */ 3108 #define PMC_SLPWK_ASR1_PID60_Pos 28 /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Position */ 3109 #define PMC_SLPWK_ASR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID60_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Mask */ 3110 #define PMC_SLPWK_ASR1_PID60 PMC_SLPWK_ASR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID60_Msk instead */ 3111 #define PMC_SLPWK_ASR1_MASK _U_(0x1F3FFFAF) /**< \deprecated (PMC_SLPWK_ASR1) Register MASK (Use PMC_SLPWK_ASR1_Msk instead) */ 3112 #define PMC_SLPWK_ASR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_ASR1) Register Mask */ 3113 3114 #define PMC_SLPWK_ASR1_PID_Pos 0 /**< (PMC_SLPWK_ASR1 Position) Peripheral 6x Activity Status */ 3115 #define PMC_SLPWK_ASR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR1_PID_Pos) /**< (PMC_SLPWK_ASR1 Mask) PID */ 3116 #define PMC_SLPWK_ASR1_PID(value) (PMC_SLPWK_ASR1_PID_Msk & ((value) << PMC_SLPWK_ASR1_PID_Pos)) 3117 3118 /* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x144) (R/ 32) SleepWalking Activity In Progress Register -------- */ 3119 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3120 #if COMPONENT_TYPEDEF_STYLE == 'N' 3121 typedef union { 3122 struct { 3123 uint32_t AIP:1; /**< bit: 0 Activity In Progress */ 3124 uint32_t :31; /**< bit: 1..31 Reserved */ 3125 } bit; /**< Structure used for bit access */ 3126 uint32_t reg; /**< Type used for register access */ 3127 } PMC_SLPWK_AIPR_Type; 3128 #endif 3129 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3130 3131 #define PMC_SLPWK_AIPR_OFFSET (0x144) /**< (PMC_SLPWK_AIPR) SleepWalking Activity In Progress Register Offset */ 3132 3133 #define PMC_SLPWK_AIPR_AIP_Pos 0 /**< (PMC_SLPWK_AIPR) Activity In Progress Position */ 3134 #define PMC_SLPWK_AIPR_AIP_Msk (_U_(0x1) << PMC_SLPWK_AIPR_AIP_Pos) /**< (PMC_SLPWK_AIPR) Activity In Progress Mask */ 3135 #define PMC_SLPWK_AIPR_AIP PMC_SLPWK_AIPR_AIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_AIPR_AIP_Msk instead */ 3136 #define PMC_SLPWK_AIPR_MASK _U_(0x01) /**< \deprecated (PMC_SLPWK_AIPR) Register MASK (Use PMC_SLPWK_AIPR_Msk instead) */ 3137 #define PMC_SLPWK_AIPR_Msk _U_(0x01) /**< (PMC_SLPWK_AIPR) Register Mask */ 3138 3139 3140 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3141 #if COMPONENT_TYPEDEF_STYLE == 'R' 3142 /** \brief PMC hardware registers */ 3143 typedef struct { 3144 __O uint32_t PMC_SCER; /**< (PMC Offset: 0x00) System Clock Enable Register */ 3145 __O uint32_t PMC_SCDR; /**< (PMC Offset: 0x04) System Clock Disable Register */ 3146 __I uint32_t PMC_SCSR; /**< (PMC Offset: 0x08) System Clock Status Register */ 3147 __I uint8_t Reserved1[4]; 3148 __O uint32_t PMC_PCER0; /**< (PMC Offset: 0x10) Peripheral Clock Enable Register 0 */ 3149 __O uint32_t PMC_PCDR0; /**< (PMC Offset: 0x14) Peripheral Clock Disable Register 0 */ 3150 __I uint32_t PMC_PCSR0; /**< (PMC Offset: 0x18) Peripheral Clock Status Register 0 */ 3151 __IO uint32_t CKGR_UCKR; /**< (PMC Offset: 0x1C) UTMI Clock Register */ 3152 __IO uint32_t CKGR_MOR; /**< (PMC Offset: 0x20) Main Oscillator Register */ 3153 __IO uint32_t CKGR_MCFR; /**< (PMC Offset: 0x24) Main Clock Frequency Register */ 3154 __IO uint32_t CKGR_PLLAR; /**< (PMC Offset: 0x28) PLLA Register */ 3155 __I uint8_t Reserved2[4]; 3156 __IO uint32_t PMC_MCKR; /**< (PMC Offset: 0x30) Master Clock Register */ 3157 __I uint8_t Reserved3[4]; 3158 __IO uint32_t PMC_USB; /**< (PMC Offset: 0x38) USB Clock Register */ 3159 __I uint8_t Reserved4[4]; 3160 __IO uint32_t PMC_PCK[8]; /**< (PMC Offset: 0x40) Programmable Clock Register */ 3161 __O uint32_t PMC_IER; /**< (PMC Offset: 0x60) Interrupt Enable Register */ 3162 __O uint32_t PMC_IDR; /**< (PMC Offset: 0x64) Interrupt Disable Register */ 3163 __I uint32_t PMC_SR; /**< (PMC Offset: 0x68) Status Register */ 3164 __I uint32_t PMC_IMR; /**< (PMC Offset: 0x6C) Interrupt Mask Register */ 3165 __IO uint32_t PMC_FSMR; /**< (PMC Offset: 0x70) Fast Startup Mode Register */ 3166 __IO uint32_t PMC_FSPR; /**< (PMC Offset: 0x74) Fast Startup Polarity Register */ 3167 __O uint32_t PMC_FOCR; /**< (PMC Offset: 0x78) Fault Output Clear Register */ 3168 __I uint8_t Reserved5[104]; 3169 __IO uint32_t PMC_WPMR; /**< (PMC Offset: 0xE4) Write Protection Mode Register */ 3170 __I uint32_t PMC_WPSR; /**< (PMC Offset: 0xE8) Write Protection Status Register */ 3171 __I uint8_t Reserved6[20]; 3172 __O uint32_t PMC_PCER1; /**< (PMC Offset: 0x100) Peripheral Clock Enable Register 1 */ 3173 __O uint32_t PMC_PCDR1; /**< (PMC Offset: 0x104) Peripheral Clock Disable Register 1 */ 3174 __I uint32_t PMC_PCSR1; /**< (PMC Offset: 0x108) Peripheral Clock Status Register 1 */ 3175 __IO uint32_t PMC_PCR; /**< (PMC Offset: 0x10C) Peripheral Control Register */ 3176 __IO uint32_t PMC_OCR; /**< (PMC Offset: 0x110) Oscillator Calibration Register */ 3177 __O uint32_t PMC_SLPWK_ER0; /**< (PMC Offset: 0x114) SleepWalking Enable Register 0 */ 3178 __O uint32_t PMC_SLPWK_DR0; /**< (PMC Offset: 0x118) SleepWalking Disable Register 0 */ 3179 __I uint32_t PMC_SLPWK_SR0; /**< (PMC Offset: 0x11C) SleepWalking Status Register 0 */ 3180 __I uint32_t PMC_SLPWK_ASR0; /**< (PMC Offset: 0x120) SleepWalking Activity Status Register 0 */ 3181 __I uint8_t Reserved7[12]; 3182 __IO uint32_t PMC_PMMR; /**< (PMC Offset: 0x130) PLL Maximum Multiplier Value Register */ 3183 __O uint32_t PMC_SLPWK_ER1; /**< (PMC Offset: 0x134) SleepWalking Enable Register 1 */ 3184 __O uint32_t PMC_SLPWK_DR1; /**< (PMC Offset: 0x138) SleepWalking Disable Register 1 */ 3185 __I uint32_t PMC_SLPWK_SR1; /**< (PMC Offset: 0x13C) SleepWalking Status Register 1 */ 3186 __I uint32_t PMC_SLPWK_ASR1; /**< (PMC Offset: 0x140) SleepWalking Activity Status Register 1 */ 3187 __I uint32_t PMC_SLPWK_AIPR; /**< (PMC Offset: 0x144) SleepWalking Activity In Progress Register */ 3188 } Pmc; 3189 3190 #elif COMPONENT_TYPEDEF_STYLE == 'N' 3191 /** \brief PMC hardware registers */ 3192 typedef struct { 3193 __O PMC_SCER_Type PMC_SCER; /**< Offset: 0x00 ( /W 32) System Clock Enable Register */ 3194 __O PMC_SCDR_Type PMC_SCDR; /**< Offset: 0x04 ( /W 32) System Clock Disable Register */ 3195 __I PMC_SCSR_Type PMC_SCSR; /**< Offset: 0x08 (R/ 32) System Clock Status Register */ 3196 __I uint8_t Reserved1[4]; 3197 __O PMC_PCER0_Type PMC_PCER0; /**< Offset: 0x10 ( /W 32) Peripheral Clock Enable Register 0 */ 3198 __O PMC_PCDR0_Type PMC_PCDR0; /**< Offset: 0x14 ( /W 32) Peripheral Clock Disable Register 0 */ 3199 __I PMC_PCSR0_Type PMC_PCSR0; /**< Offset: 0x18 (R/ 32) Peripheral Clock Status Register 0 */ 3200 __IO CKGR_UCKR_Type CKGR_UCKR; /**< Offset: 0x1C (R/W 32) UTMI Clock Register */ 3201 __IO CKGR_MOR_Type CKGR_MOR; /**< Offset: 0x20 (R/W 32) Main Oscillator Register */ 3202 __IO CKGR_MCFR_Type CKGR_MCFR; /**< Offset: 0x24 (R/W 32) Main Clock Frequency Register */ 3203 __IO CKGR_PLLAR_Type CKGR_PLLAR; /**< Offset: 0x28 (R/W 32) PLLA Register */ 3204 __I uint8_t Reserved2[4]; 3205 __IO PMC_MCKR_Type PMC_MCKR; /**< Offset: 0x30 (R/W 32) Master Clock Register */ 3206 __I uint8_t Reserved3[4]; 3207 __IO PMC_USB_Type PMC_USB; /**< Offset: 0x38 (R/W 32) USB Clock Register */ 3208 __I uint8_t Reserved4[4]; 3209 __IO PMC_PCK_Type PMC_PCK[8]; /**< Offset: 0x40 (R/W 32) Programmable Clock Register */ 3210 __O PMC_IER_Type PMC_IER; /**< Offset: 0x60 ( /W 32) Interrupt Enable Register */ 3211 __O PMC_IDR_Type PMC_IDR; /**< Offset: 0x64 ( /W 32) Interrupt Disable Register */ 3212 __I PMC_SR_Type PMC_SR; /**< Offset: 0x68 (R/ 32) Status Register */ 3213 __I PMC_IMR_Type PMC_IMR; /**< Offset: 0x6C (R/ 32) Interrupt Mask Register */ 3214 __IO PMC_FSMR_Type PMC_FSMR; /**< Offset: 0x70 (R/W 32) Fast Startup Mode Register */ 3215 __IO PMC_FSPR_Type PMC_FSPR; /**< Offset: 0x74 (R/W 32) Fast Startup Polarity Register */ 3216 __O PMC_FOCR_Type PMC_FOCR; /**< Offset: 0x78 ( /W 32) Fault Output Clear Register */ 3217 __I uint8_t Reserved5[104]; 3218 __IO PMC_WPMR_Type PMC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 3219 __I PMC_WPSR_Type PMC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 3220 __I uint8_t Reserved6[20]; 3221 __O PMC_PCER1_Type PMC_PCER1; /**< Offset: 0x100 ( /W 32) Peripheral Clock Enable Register 1 */ 3222 __O PMC_PCDR1_Type PMC_PCDR1; /**< Offset: 0x104 ( /W 32) Peripheral Clock Disable Register 1 */ 3223 __I PMC_PCSR1_Type PMC_PCSR1; /**< Offset: 0x108 (R/ 32) Peripheral Clock Status Register 1 */ 3224 __IO PMC_PCR_Type PMC_PCR; /**< Offset: 0x10C (R/W 32) Peripheral Control Register */ 3225 __IO PMC_OCR_Type PMC_OCR; /**< Offset: 0x110 (R/W 32) Oscillator Calibration Register */ 3226 __O PMC_SLPWK_ER0_Type PMC_SLPWK_ER0; /**< Offset: 0x114 ( /W 32) SleepWalking Enable Register 0 */ 3227 __O PMC_SLPWK_DR0_Type PMC_SLPWK_DR0; /**< Offset: 0x118 ( /W 32) SleepWalking Disable Register 0 */ 3228 __I PMC_SLPWK_SR0_Type PMC_SLPWK_SR0; /**< Offset: 0x11C (R/ 32) SleepWalking Status Register 0 */ 3229 __I PMC_SLPWK_ASR0_Type PMC_SLPWK_ASR0; /**< Offset: 0x120 (R/ 32) SleepWalking Activity Status Register 0 */ 3230 __I uint8_t Reserved7[12]; 3231 __IO PMC_PMMR_Type PMC_PMMR; /**< Offset: 0x130 (R/W 32) PLL Maximum Multiplier Value Register */ 3232 __O PMC_SLPWK_ER1_Type PMC_SLPWK_ER1; /**< Offset: 0x134 ( /W 32) SleepWalking Enable Register 1 */ 3233 __O PMC_SLPWK_DR1_Type PMC_SLPWK_DR1; /**< Offset: 0x138 ( /W 32) SleepWalking Disable Register 1 */ 3234 __I PMC_SLPWK_SR1_Type PMC_SLPWK_SR1; /**< Offset: 0x13C (R/ 32) SleepWalking Status Register 1 */ 3235 __I PMC_SLPWK_ASR1_Type PMC_SLPWK_ASR1; /**< Offset: 0x140 (R/ 32) SleepWalking Activity Status Register 1 */ 3236 __I PMC_SLPWK_AIPR_Type PMC_SLPWK_AIPR; /**< Offset: 0x144 (R/ 32) SleepWalking Activity In Progress Register */ 3237 } Pmc; 3238 3239 #else /* COMPONENT_TYPEDEF_STYLE */ 3240 #error Unknown component typedef style 3241 #endif /* COMPONENT_TYPEDEF_STYLE */ 3242 3243 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3244 /** @} end of Power Management Controller */ 3245 3246 #endif /* _SAMV71_PMC_COMPONENT_H_ */ 3247
