1 /** 2 * \file 3 * 4 * \brief Component description for MLB 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_MLB_COMPONENT_H_ 32 #define _SAMV71_MLB_COMPONENT_H_ 33 #define _SAMV71_MLB_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 MediaLB 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR MLB */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define MLB_11287 /**< (MLB) Module ID */ 46 #define REV_MLB E /**< (MLB) Module revision */ 47 48 /* -------- MLB_MLBC0 : (MLB Offset: 0x00) (R/W 32) MediaLB Control 0 Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t MLBEN:1; /**< bit: 0 MediaLB Enable */ 54 uint32_t :1; /**< bit: 1 Reserved */ 55 uint32_t MLBCLK:3; /**< bit: 2..4 MLBCLK (MediaLB clock) Speed Select */ 56 uint32_t ZERO:1; /**< bit: 5 Must be Written to 0 */ 57 uint32_t :1; /**< bit: 6 Reserved */ 58 uint32_t MLBLK:1; /**< bit: 7 MediaLB Lock Status (read-only) */ 59 uint32_t :4; /**< bit: 8..11 Reserved */ 60 uint32_t ASYRETRY:1; /**< bit: 12 Asynchronous Tx Packet Retry */ 61 uint32_t :1; /**< bit: 13 Reserved */ 62 uint32_t CTLRETRY:1; /**< bit: 14 Control Tx Packet Retry */ 63 uint32_t FCNT:3; /**< bit: 15..17 The number of frames per sub-buffer for synchronous channels */ 64 uint32_t :14; /**< bit: 18..31 Reserved */ 65 } bit; /**< Structure used for bit access */ 66 uint32_t reg; /**< Type used for register access */ 67 } MLB_MLBC0_Type; 68 #endif 69 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define MLB_MLBC0_OFFSET (0x00) /**< (MLB_MLBC0) MediaLB Control 0 Register Offset */ 72 73 #define MLB_MLBC0_MLBEN_Pos 0 /**< (MLB_MLBC0) MediaLB Enable Position */ 74 #define MLB_MLBC0_MLBEN_Msk (_U_(0x1) << MLB_MLBC0_MLBEN_Pos) /**< (MLB_MLBC0) MediaLB Enable Mask */ 75 #define MLB_MLBC0_MLBEN MLB_MLBC0_MLBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC0_MLBEN_Msk instead */ 76 #define MLB_MLBC0_MLBCLK_Pos 2 /**< (MLB_MLBC0) MLBCLK (MediaLB clock) Speed Select Position */ 77 #define MLB_MLBC0_MLBCLK_Msk (_U_(0x7) << MLB_MLBC0_MLBCLK_Pos) /**< (MLB_MLBC0) MLBCLK (MediaLB clock) Speed Select Mask */ 78 #define MLB_MLBC0_MLBCLK(value) (MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos)) 79 #define MLB_MLBC0_MLBCLK_256_FS_Val _U_(0x0) /**< (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ 80 #define MLB_MLBC0_MLBCLK_512_FS_Val _U_(0x1) /**< (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ 81 #define MLB_MLBC0_MLBCLK_1024_FS_Val _U_(0x2) /**< (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ 82 #define MLB_MLBC0_MLBCLK_256_FS (MLB_MLBC0_MLBCLK_256_FS_Val << MLB_MLBC0_MLBCLK_Pos) /**< (MLB_MLBC0) 256xFs (for MLBPEN = 0) Position */ 83 #define MLB_MLBC0_MLBCLK_512_FS (MLB_MLBC0_MLBCLK_512_FS_Val << MLB_MLBC0_MLBCLK_Pos) /**< (MLB_MLBC0) 512xFs (for MLBPEN = 0) Position */ 84 #define MLB_MLBC0_MLBCLK_1024_FS (MLB_MLBC0_MLBCLK_1024_FS_Val << MLB_MLBC0_MLBCLK_Pos) /**< (MLB_MLBC0) 1024xFs (for MLBPEN = 0) Position */ 85 #define MLB_MLBC0_ZERO_Pos 5 /**< (MLB_MLBC0) Must be Written to 0 Position */ 86 #define MLB_MLBC0_ZERO_Msk (_U_(0x1) << MLB_MLBC0_ZERO_Pos) /**< (MLB_MLBC0) Must be Written to 0 Mask */ 87 #define MLB_MLBC0_ZERO MLB_MLBC0_ZERO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC0_ZERO_Msk instead */ 88 #define MLB_MLBC0_MLBLK_Pos 7 /**< (MLB_MLBC0) MediaLB Lock Status (read-only) Position */ 89 #define MLB_MLBC0_MLBLK_Msk (_U_(0x1) << MLB_MLBC0_MLBLK_Pos) /**< (MLB_MLBC0) MediaLB Lock Status (read-only) Mask */ 90 #define MLB_MLBC0_MLBLK MLB_MLBC0_MLBLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC0_MLBLK_Msk instead */ 91 #define MLB_MLBC0_ASYRETRY_Pos 12 /**< (MLB_MLBC0) Asynchronous Tx Packet Retry Position */ 92 #define MLB_MLBC0_ASYRETRY_Msk (_U_(0x1) << MLB_MLBC0_ASYRETRY_Pos) /**< (MLB_MLBC0) Asynchronous Tx Packet Retry Mask */ 93 #define MLB_MLBC0_ASYRETRY MLB_MLBC0_ASYRETRY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC0_ASYRETRY_Msk instead */ 94 #define MLB_MLBC0_CTLRETRY_Pos 14 /**< (MLB_MLBC0) Control Tx Packet Retry Position */ 95 #define MLB_MLBC0_CTLRETRY_Msk (_U_(0x1) << MLB_MLBC0_CTLRETRY_Pos) /**< (MLB_MLBC0) Control Tx Packet Retry Mask */ 96 #define MLB_MLBC0_CTLRETRY MLB_MLBC0_CTLRETRY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC0_CTLRETRY_Msk instead */ 97 #define MLB_MLBC0_FCNT_Pos 15 /**< (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels Position */ 98 #define MLB_MLBC0_FCNT_Msk (_U_(0x7) << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels Mask */ 99 #define MLB_MLBC0_FCNT(value) (MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos)) 100 #define MLB_MLBC0_FCNT_1_FRAME_Val _U_(0x0) /**< (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ 101 #define MLB_MLBC0_FCNT_2_FRAMES_Val _U_(0x1) /**< (MLB_MLBC0) 2 frames per sub-buffer */ 102 #define MLB_MLBC0_FCNT_4_FRAMES_Val _U_(0x2) /**< (MLB_MLBC0) 4 frames per sub-buffer */ 103 #define MLB_MLBC0_FCNT_8_FRAMES_Val _U_(0x3) /**< (MLB_MLBC0) 8 frames per sub-buffer */ 104 #define MLB_MLBC0_FCNT_16_FRAMES_Val _U_(0x4) /**< (MLB_MLBC0) 16 frames per sub-buffer */ 105 #define MLB_MLBC0_FCNT_32_FRAMES_Val _U_(0x5) /**< (MLB_MLBC0) 32 frames per sub-buffer */ 106 #define MLB_MLBC0_FCNT_64_FRAMES_Val _U_(0x6) /**< (MLB_MLBC0) 64 frames per sub-buffer */ 107 #define MLB_MLBC0_FCNT_1_FRAME (MLB_MLBC0_FCNT_1_FRAME_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) Position */ 108 #define MLB_MLBC0_FCNT_2_FRAMES (MLB_MLBC0_FCNT_2_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 2 frames per sub-buffer Position */ 109 #define MLB_MLBC0_FCNT_4_FRAMES (MLB_MLBC0_FCNT_4_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 4 frames per sub-buffer Position */ 110 #define MLB_MLBC0_FCNT_8_FRAMES (MLB_MLBC0_FCNT_8_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 8 frames per sub-buffer Position */ 111 #define MLB_MLBC0_FCNT_16_FRAMES (MLB_MLBC0_FCNT_16_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 16 frames per sub-buffer Position */ 112 #define MLB_MLBC0_FCNT_32_FRAMES (MLB_MLBC0_FCNT_32_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 32 frames per sub-buffer Position */ 113 #define MLB_MLBC0_FCNT_64_FRAMES (MLB_MLBC0_FCNT_64_FRAMES_Val << MLB_MLBC0_FCNT_Pos) /**< (MLB_MLBC0) 64 frames per sub-buffer Position */ 114 #define MLB_MLBC0_MASK _U_(0x3D0BD) /**< \deprecated (MLB_MLBC0) Register MASK (Use MLB_MLBC0_Msk instead) */ 115 #define MLB_MLBC0_Msk _U_(0x3D0BD) /**< (MLB_MLBC0) Register Mask */ 116 117 118 /* -------- MLB_MS0 : (MLB Offset: 0x0c) (R/W 32) MediaLB Channel Status 0 Register -------- */ 119 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 120 #if COMPONENT_TYPEDEF_STYLE == 'N' 121 typedef union { 122 struct { 123 uint32_t MCS:32; /**< bit: 0..31 MediaLB Channel Status [31:0] (cleared by writing a 0) */ 124 } bit; /**< Structure used for bit access */ 125 uint32_t reg; /**< Type used for register access */ 126 } MLB_MS0_Type; 127 #endif 128 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 #define MLB_MS0_OFFSET (0x0C) /**< (MLB_MS0) MediaLB Channel Status 0 Register Offset */ 131 132 #define MLB_MS0_MCS_Pos 0 /**< (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) Position */ 133 #define MLB_MS0_MCS_Msk (_U_(0xFFFFFFFF) << MLB_MS0_MCS_Pos) /**< (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) Mask */ 134 #define MLB_MS0_MCS(value) (MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos)) 135 #define MLB_MS0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_MS0) Register MASK (Use MLB_MS0_Msk instead) */ 136 #define MLB_MS0_Msk _U_(0xFFFFFFFF) /**< (MLB_MS0) Register Mask */ 137 138 139 /* -------- MLB_MS1 : (MLB Offset: 0x14) (R/W 32) MediaLB Channel Status1 Register -------- */ 140 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 141 #if COMPONENT_TYPEDEF_STYLE == 'N' 142 typedef union { 143 struct { 144 uint32_t MCS:32; /**< bit: 0..31 MediaLB Channel Status [63:32] (cleared by writing a 0) */ 145 } bit; /**< Structure used for bit access */ 146 uint32_t reg; /**< Type used for register access */ 147 } MLB_MS1_Type; 148 #endif 149 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 150 151 #define MLB_MS1_OFFSET (0x14) /**< (MLB_MS1) MediaLB Channel Status1 Register Offset */ 152 153 #define MLB_MS1_MCS_Pos 0 /**< (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) Position */ 154 #define MLB_MS1_MCS_Msk (_U_(0xFFFFFFFF) << MLB_MS1_MCS_Pos) /**< (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) Mask */ 155 #define MLB_MS1_MCS(value) (MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos)) 156 #define MLB_MS1_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_MS1) Register MASK (Use MLB_MS1_Msk instead) */ 157 #define MLB_MS1_Msk _U_(0xFFFFFFFF) /**< (MLB_MS1) Register Mask */ 158 159 160 /* -------- MLB_MSS : (MLB Offset: 0x20) (R/W 32) MediaLB System Status Register -------- */ 161 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 162 #if COMPONENT_TYPEDEF_STYLE == 'N' 163 typedef union { 164 struct { 165 uint32_t RSTSYSCMD:1; /**< bit: 0 Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ 166 uint32_t LKSYSCMD:1; /**< bit: 1 Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ 167 uint32_t ULKSYSCMD:1; /**< bit: 2 Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ 168 uint32_t CSSYSCMD:1; /**< bit: 3 Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ 169 uint32_t SWSYSCMD:1; /**< bit: 4 Software System Command Detected in the System Quadlet (cleared by writing a 0) */ 170 uint32_t SERVREQ:1; /**< bit: 5 Service Request Enabled */ 171 uint32_t :26; /**< bit: 6..31 Reserved */ 172 } bit; /**< Structure used for bit access */ 173 uint32_t reg; /**< Type used for register access */ 174 } MLB_MSS_Type; 175 #endif 176 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 #define MLB_MSS_OFFSET (0x20) /**< (MLB_MSS) MediaLB System Status Register Offset */ 179 180 #define MLB_MSS_RSTSYSCMD_Pos 0 /**< (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) Position */ 181 #define MLB_MSS_RSTSYSCMD_Msk (_U_(0x1) << MLB_MSS_RSTSYSCMD_Pos) /**< (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) Mask */ 182 #define MLB_MSS_RSTSYSCMD MLB_MSS_RSTSYSCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_RSTSYSCMD_Msk instead */ 183 #define MLB_MSS_LKSYSCMD_Pos 1 /**< (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) Position */ 184 #define MLB_MSS_LKSYSCMD_Msk (_U_(0x1) << MLB_MSS_LKSYSCMD_Pos) /**< (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) Mask */ 185 #define MLB_MSS_LKSYSCMD MLB_MSS_LKSYSCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_LKSYSCMD_Msk instead */ 186 #define MLB_MSS_ULKSYSCMD_Pos 2 /**< (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) Position */ 187 #define MLB_MSS_ULKSYSCMD_Msk (_U_(0x1) << MLB_MSS_ULKSYSCMD_Pos) /**< (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) Mask */ 188 #define MLB_MSS_ULKSYSCMD MLB_MSS_ULKSYSCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_ULKSYSCMD_Msk instead */ 189 #define MLB_MSS_CSSYSCMD_Pos 3 /**< (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) Position */ 190 #define MLB_MSS_CSSYSCMD_Msk (_U_(0x1) << MLB_MSS_CSSYSCMD_Pos) /**< (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) Mask */ 191 #define MLB_MSS_CSSYSCMD MLB_MSS_CSSYSCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_CSSYSCMD_Msk instead */ 192 #define MLB_MSS_SWSYSCMD_Pos 4 /**< (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) Position */ 193 #define MLB_MSS_SWSYSCMD_Msk (_U_(0x1) << MLB_MSS_SWSYSCMD_Pos) /**< (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) Mask */ 194 #define MLB_MSS_SWSYSCMD MLB_MSS_SWSYSCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_SWSYSCMD_Msk instead */ 195 #define MLB_MSS_SERVREQ_Pos 5 /**< (MLB_MSS) Service Request Enabled Position */ 196 #define MLB_MSS_SERVREQ_Msk (_U_(0x1) << MLB_MSS_SERVREQ_Pos) /**< (MLB_MSS) Service Request Enabled Mask */ 197 #define MLB_MSS_SERVREQ MLB_MSS_SERVREQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MSS_SERVREQ_Msk instead */ 198 #define MLB_MSS_MASK _U_(0x3F) /**< \deprecated (MLB_MSS) Register MASK (Use MLB_MSS_Msk instead) */ 199 #define MLB_MSS_Msk _U_(0x3F) /**< (MLB_MSS) Register Mask */ 200 201 202 /* -------- MLB_MSD : (MLB Offset: 0x24) (R/ 32) MediaLB System Data Register -------- */ 203 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 204 #if COMPONENT_TYPEDEF_STYLE == 'N' 205 typedef union { 206 struct { 207 uint32_t SD0:8; /**< bit: 0..7 System Data (Byte 0) */ 208 uint32_t SD1:8; /**< bit: 8..15 System Data (Byte 1) */ 209 uint32_t SD2:8; /**< bit: 16..23 System Data (Byte 2) */ 210 uint32_t SD3:8; /**< bit: 24..31 System Data (Byte 3) */ 211 } bit; /**< Structure used for bit access */ 212 uint32_t reg; /**< Type used for register access */ 213 } MLB_MSD_Type; 214 #endif 215 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 #define MLB_MSD_OFFSET (0x24) /**< (MLB_MSD) MediaLB System Data Register Offset */ 218 219 #define MLB_MSD_SD0_Pos 0 /**< (MLB_MSD) System Data (Byte 0) Position */ 220 #define MLB_MSD_SD0_Msk (_U_(0xFF) << MLB_MSD_SD0_Pos) /**< (MLB_MSD) System Data (Byte 0) Mask */ 221 #define MLB_MSD_SD0(value) (MLB_MSD_SD0_Msk & ((value) << MLB_MSD_SD0_Pos)) 222 #define MLB_MSD_SD1_Pos 8 /**< (MLB_MSD) System Data (Byte 1) Position */ 223 #define MLB_MSD_SD1_Msk (_U_(0xFF) << MLB_MSD_SD1_Pos) /**< (MLB_MSD) System Data (Byte 1) Mask */ 224 #define MLB_MSD_SD1(value) (MLB_MSD_SD1_Msk & ((value) << MLB_MSD_SD1_Pos)) 225 #define MLB_MSD_SD2_Pos 16 /**< (MLB_MSD) System Data (Byte 2) Position */ 226 #define MLB_MSD_SD2_Msk (_U_(0xFF) << MLB_MSD_SD2_Pos) /**< (MLB_MSD) System Data (Byte 2) Mask */ 227 #define MLB_MSD_SD2(value) (MLB_MSD_SD2_Msk & ((value) << MLB_MSD_SD2_Pos)) 228 #define MLB_MSD_SD3_Pos 24 /**< (MLB_MSD) System Data (Byte 3) Position */ 229 #define MLB_MSD_SD3_Msk (_U_(0xFF) << MLB_MSD_SD3_Pos) /**< (MLB_MSD) System Data (Byte 3) Mask */ 230 #define MLB_MSD_SD3(value) (MLB_MSD_SD3_Msk & ((value) << MLB_MSD_SD3_Pos)) 231 #define MLB_MSD_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_MSD) Register MASK (Use MLB_MSD_Msk instead) */ 232 #define MLB_MSD_Msk _U_(0xFFFFFFFF) /**< (MLB_MSD) Register Mask */ 233 234 235 /* -------- MLB_MIEN : (MLB Offset: 0x2c) (R/W 32) MediaLB Interrupt Enable Register -------- */ 236 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 237 #if COMPONENT_TYPEDEF_STYLE == 'N' 238 typedef union { 239 struct { 240 uint32_t ISOC_PE:1; /**< bit: 0 Isochronous Rx Protocol Error Enable */ 241 uint32_t ISOC_BUFO:1; /**< bit: 1 Isochronous Rx Buffer Overflow Enable */ 242 uint32_t :14; /**< bit: 2..15 Reserved */ 243 uint32_t SYNC_PE:1; /**< bit: 16 Synchronous Protocol Error Enable */ 244 uint32_t ARX_DONE:1; /**< bit: 17 Asynchronous Rx Done Enable */ 245 uint32_t ARX_PE:1; /**< bit: 18 Asynchronous Rx Protocol Error Enable */ 246 uint32_t ARX_BREAK:1; /**< bit: 19 Asynchronous Rx Break Enable */ 247 uint32_t ATX_DONE:1; /**< bit: 20 Asynchronous Tx Packet Done Enable */ 248 uint32_t ATX_PE:1; /**< bit: 21 Asynchronous Tx Protocol Error Enable */ 249 uint32_t ATX_BREAK:1; /**< bit: 22 Asynchronous Tx Break Enable */ 250 uint32_t :1; /**< bit: 23 Reserved */ 251 uint32_t CRX_DONE:1; /**< bit: 24 Control Rx Packet Done Enable */ 252 uint32_t CRX_PE:1; /**< bit: 25 Control Rx Protocol Error Enable */ 253 uint32_t CRX_BREAK:1; /**< bit: 26 Control Rx Break Enable */ 254 uint32_t CTX_DONE:1; /**< bit: 27 Control Tx Packet Done Enable */ 255 uint32_t CTX_PE:1; /**< bit: 28 Control Tx Protocol Error Enable */ 256 uint32_t CTX_BREAK:1; /**< bit: 29 Control Tx Break Enable */ 257 uint32_t :2; /**< bit: 30..31 Reserved */ 258 } bit; /**< Structure used for bit access */ 259 uint32_t reg; /**< Type used for register access */ 260 } MLB_MIEN_Type; 261 #endif 262 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 263 264 #define MLB_MIEN_OFFSET (0x2C) /**< (MLB_MIEN) MediaLB Interrupt Enable Register Offset */ 265 266 #define MLB_MIEN_ISOC_PE_Pos 0 /**< (MLB_MIEN) Isochronous Rx Protocol Error Enable Position */ 267 #define MLB_MIEN_ISOC_PE_Msk (_U_(0x1) << MLB_MIEN_ISOC_PE_Pos) /**< (MLB_MIEN) Isochronous Rx Protocol Error Enable Mask */ 268 #define MLB_MIEN_ISOC_PE MLB_MIEN_ISOC_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ISOC_PE_Msk instead */ 269 #define MLB_MIEN_ISOC_BUFO_Pos 1 /**< (MLB_MIEN) Isochronous Rx Buffer Overflow Enable Position */ 270 #define MLB_MIEN_ISOC_BUFO_Msk (_U_(0x1) << MLB_MIEN_ISOC_BUFO_Pos) /**< (MLB_MIEN) Isochronous Rx Buffer Overflow Enable Mask */ 271 #define MLB_MIEN_ISOC_BUFO MLB_MIEN_ISOC_BUFO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ISOC_BUFO_Msk instead */ 272 #define MLB_MIEN_SYNC_PE_Pos 16 /**< (MLB_MIEN) Synchronous Protocol Error Enable Position */ 273 #define MLB_MIEN_SYNC_PE_Msk (_U_(0x1) << MLB_MIEN_SYNC_PE_Pos) /**< (MLB_MIEN) Synchronous Protocol Error Enable Mask */ 274 #define MLB_MIEN_SYNC_PE MLB_MIEN_SYNC_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_SYNC_PE_Msk instead */ 275 #define MLB_MIEN_ARX_DONE_Pos 17 /**< (MLB_MIEN) Asynchronous Rx Done Enable Position */ 276 #define MLB_MIEN_ARX_DONE_Msk (_U_(0x1) << MLB_MIEN_ARX_DONE_Pos) /**< (MLB_MIEN) Asynchronous Rx Done Enable Mask */ 277 #define MLB_MIEN_ARX_DONE MLB_MIEN_ARX_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ARX_DONE_Msk instead */ 278 #define MLB_MIEN_ARX_PE_Pos 18 /**< (MLB_MIEN) Asynchronous Rx Protocol Error Enable Position */ 279 #define MLB_MIEN_ARX_PE_Msk (_U_(0x1) << MLB_MIEN_ARX_PE_Pos) /**< (MLB_MIEN) Asynchronous Rx Protocol Error Enable Mask */ 280 #define MLB_MIEN_ARX_PE MLB_MIEN_ARX_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ARX_PE_Msk instead */ 281 #define MLB_MIEN_ARX_BREAK_Pos 19 /**< (MLB_MIEN) Asynchronous Rx Break Enable Position */ 282 #define MLB_MIEN_ARX_BREAK_Msk (_U_(0x1) << MLB_MIEN_ARX_BREAK_Pos) /**< (MLB_MIEN) Asynchronous Rx Break Enable Mask */ 283 #define MLB_MIEN_ARX_BREAK MLB_MIEN_ARX_BREAK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ARX_BREAK_Msk instead */ 284 #define MLB_MIEN_ATX_DONE_Pos 20 /**< (MLB_MIEN) Asynchronous Tx Packet Done Enable Position */ 285 #define MLB_MIEN_ATX_DONE_Msk (_U_(0x1) << MLB_MIEN_ATX_DONE_Pos) /**< (MLB_MIEN) Asynchronous Tx Packet Done Enable Mask */ 286 #define MLB_MIEN_ATX_DONE MLB_MIEN_ATX_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ATX_DONE_Msk instead */ 287 #define MLB_MIEN_ATX_PE_Pos 21 /**< (MLB_MIEN) Asynchronous Tx Protocol Error Enable Position */ 288 #define MLB_MIEN_ATX_PE_Msk (_U_(0x1) << MLB_MIEN_ATX_PE_Pos) /**< (MLB_MIEN) Asynchronous Tx Protocol Error Enable Mask */ 289 #define MLB_MIEN_ATX_PE MLB_MIEN_ATX_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ATX_PE_Msk instead */ 290 #define MLB_MIEN_ATX_BREAK_Pos 22 /**< (MLB_MIEN) Asynchronous Tx Break Enable Position */ 291 #define MLB_MIEN_ATX_BREAK_Msk (_U_(0x1) << MLB_MIEN_ATX_BREAK_Pos) /**< (MLB_MIEN) Asynchronous Tx Break Enable Mask */ 292 #define MLB_MIEN_ATX_BREAK MLB_MIEN_ATX_BREAK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_ATX_BREAK_Msk instead */ 293 #define MLB_MIEN_CRX_DONE_Pos 24 /**< (MLB_MIEN) Control Rx Packet Done Enable Position */ 294 #define MLB_MIEN_CRX_DONE_Msk (_U_(0x1) << MLB_MIEN_CRX_DONE_Pos) /**< (MLB_MIEN) Control Rx Packet Done Enable Mask */ 295 #define MLB_MIEN_CRX_DONE MLB_MIEN_CRX_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CRX_DONE_Msk instead */ 296 #define MLB_MIEN_CRX_PE_Pos 25 /**< (MLB_MIEN) Control Rx Protocol Error Enable Position */ 297 #define MLB_MIEN_CRX_PE_Msk (_U_(0x1) << MLB_MIEN_CRX_PE_Pos) /**< (MLB_MIEN) Control Rx Protocol Error Enable Mask */ 298 #define MLB_MIEN_CRX_PE MLB_MIEN_CRX_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CRX_PE_Msk instead */ 299 #define MLB_MIEN_CRX_BREAK_Pos 26 /**< (MLB_MIEN) Control Rx Break Enable Position */ 300 #define MLB_MIEN_CRX_BREAK_Msk (_U_(0x1) << MLB_MIEN_CRX_BREAK_Pos) /**< (MLB_MIEN) Control Rx Break Enable Mask */ 301 #define MLB_MIEN_CRX_BREAK MLB_MIEN_CRX_BREAK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CRX_BREAK_Msk instead */ 302 #define MLB_MIEN_CTX_DONE_Pos 27 /**< (MLB_MIEN) Control Tx Packet Done Enable Position */ 303 #define MLB_MIEN_CTX_DONE_Msk (_U_(0x1) << MLB_MIEN_CTX_DONE_Pos) /**< (MLB_MIEN) Control Tx Packet Done Enable Mask */ 304 #define MLB_MIEN_CTX_DONE MLB_MIEN_CTX_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CTX_DONE_Msk instead */ 305 #define MLB_MIEN_CTX_PE_Pos 28 /**< (MLB_MIEN) Control Tx Protocol Error Enable Position */ 306 #define MLB_MIEN_CTX_PE_Msk (_U_(0x1) << MLB_MIEN_CTX_PE_Pos) /**< (MLB_MIEN) Control Tx Protocol Error Enable Mask */ 307 #define MLB_MIEN_CTX_PE MLB_MIEN_CTX_PE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CTX_PE_Msk instead */ 308 #define MLB_MIEN_CTX_BREAK_Pos 29 /**< (MLB_MIEN) Control Tx Break Enable Position */ 309 #define MLB_MIEN_CTX_BREAK_Msk (_U_(0x1) << MLB_MIEN_CTX_BREAK_Pos) /**< (MLB_MIEN) Control Tx Break Enable Mask */ 310 #define MLB_MIEN_CTX_BREAK MLB_MIEN_CTX_BREAK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MIEN_CTX_BREAK_Msk instead */ 311 #define MLB_MIEN_MASK _U_(0x3F7F0003) /**< \deprecated (MLB_MIEN) Register MASK (Use MLB_MIEN_Msk instead) */ 312 #define MLB_MIEN_Msk _U_(0x3F7F0003) /**< (MLB_MIEN) Register Mask */ 313 314 315 /* -------- MLB_MLBC1 : (MLB Offset: 0x3c) (R/W 32) MediaLB Control 1 Register -------- */ 316 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 317 #if COMPONENT_TYPEDEF_STYLE == 'N' 318 typedef union { 319 struct { 320 uint32_t :6; /**< bit: 0..5 Reserved */ 321 uint32_t LOCK:1; /**< bit: 6 MediaLB Lock Error Status (cleared by writing a 0) */ 322 uint32_t CLKM:1; /**< bit: 7 MediaLB Clock Missing Status (cleared by writing a 0) */ 323 uint32_t NDA:8; /**< bit: 8..15 Node Device Address */ 324 uint32_t :16; /**< bit: 16..31 Reserved */ 325 } bit; /**< Structure used for bit access */ 326 uint32_t reg; /**< Type used for register access */ 327 } MLB_MLBC1_Type; 328 #endif 329 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 330 331 #define MLB_MLBC1_OFFSET (0x3C) /**< (MLB_MLBC1) MediaLB Control 1 Register Offset */ 332 333 #define MLB_MLBC1_LOCK_Pos 6 /**< (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) Position */ 334 #define MLB_MLBC1_LOCK_Msk (_U_(0x1) << MLB_MLBC1_LOCK_Pos) /**< (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) Mask */ 335 #define MLB_MLBC1_LOCK MLB_MLBC1_LOCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC1_LOCK_Msk instead */ 336 #define MLB_MLBC1_CLKM_Pos 7 /**< (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) Position */ 337 #define MLB_MLBC1_CLKM_Msk (_U_(0x1) << MLB_MLBC1_CLKM_Pos) /**< (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) Mask */ 338 #define MLB_MLBC1_CLKM MLB_MLBC1_CLKM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MLBC1_CLKM_Msk instead */ 339 #define MLB_MLBC1_NDA_Pos 8 /**< (MLB_MLBC1) Node Device Address Position */ 340 #define MLB_MLBC1_NDA_Msk (_U_(0xFF) << MLB_MLBC1_NDA_Pos) /**< (MLB_MLBC1) Node Device Address Mask */ 341 #define MLB_MLBC1_NDA(value) (MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos)) 342 #define MLB_MLBC1_MASK _U_(0xFFC0) /**< \deprecated (MLB_MLBC1) Register MASK (Use MLB_MLBC1_Msk instead) */ 343 #define MLB_MLBC1_Msk _U_(0xFFC0) /**< (MLB_MLBC1) Register Mask */ 344 345 346 /* -------- MLB_HCTL : (MLB Offset: 0x80) (R/W 32) HBI Control Register -------- */ 347 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 348 #if COMPONENT_TYPEDEF_STYLE == 'N' 349 typedef union { 350 struct { 351 uint32_t RST0:1; /**< bit: 0 Address Generation Unit 0 Software Reset */ 352 uint32_t RST1:1; /**< bit: 1 Address Generation Unit 1 Software Reset */ 353 uint32_t :13; /**< bit: 2..14 Reserved */ 354 uint32_t EN:1; /**< bit: 15 HBI Enable */ 355 uint32_t :16; /**< bit: 16..31 Reserved */ 356 } bit; /**< Structure used for bit access */ 357 struct { 358 uint32_t RST:2; /**< bit: 0..1 Address Generation Unit x Software Reset */ 359 uint32_t :30; /**< bit: 2..31 Reserved */ 360 } vec; /**< Structure used for vec access */ 361 uint32_t reg; /**< Type used for register access */ 362 } MLB_HCTL_Type; 363 #endif 364 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 365 366 #define MLB_HCTL_OFFSET (0x80) /**< (MLB_HCTL) HBI Control Register Offset */ 367 368 #define MLB_HCTL_RST0_Pos 0 /**< (MLB_HCTL) Address Generation Unit 0 Software Reset Position */ 369 #define MLB_HCTL_RST0_Msk (_U_(0x1) << MLB_HCTL_RST0_Pos) /**< (MLB_HCTL) Address Generation Unit 0 Software Reset Mask */ 370 #define MLB_HCTL_RST0 MLB_HCTL_RST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_HCTL_RST0_Msk instead */ 371 #define MLB_HCTL_RST1_Pos 1 /**< (MLB_HCTL) Address Generation Unit 1 Software Reset Position */ 372 #define MLB_HCTL_RST1_Msk (_U_(0x1) << MLB_HCTL_RST1_Pos) /**< (MLB_HCTL) Address Generation Unit 1 Software Reset Mask */ 373 #define MLB_HCTL_RST1 MLB_HCTL_RST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_HCTL_RST1_Msk instead */ 374 #define MLB_HCTL_EN_Pos 15 /**< (MLB_HCTL) HBI Enable Position */ 375 #define MLB_HCTL_EN_Msk (_U_(0x1) << MLB_HCTL_EN_Pos) /**< (MLB_HCTL) HBI Enable Mask */ 376 #define MLB_HCTL_EN MLB_HCTL_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_HCTL_EN_Msk instead */ 377 #define MLB_HCTL_MASK _U_(0x8003) /**< \deprecated (MLB_HCTL) Register MASK (Use MLB_HCTL_Msk instead) */ 378 #define MLB_HCTL_Msk _U_(0x8003) /**< (MLB_HCTL) Register Mask */ 379 380 #define MLB_HCTL_RST_Pos 0 /**< (MLB_HCTL Position) Address Generation Unit x Software Reset */ 381 #define MLB_HCTL_RST_Msk (_U_(0x3) << MLB_HCTL_RST_Pos) /**< (MLB_HCTL Mask) RST */ 382 #define MLB_HCTL_RST(value) (MLB_HCTL_RST_Msk & ((value) << MLB_HCTL_RST_Pos)) 383 384 /* -------- MLB_HCMR : (MLB Offset: 0x88) (R/W 32) HBI Channel Mask 0 Register 0 -------- */ 385 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 386 #if COMPONENT_TYPEDEF_STYLE == 'N' 387 typedef union { 388 struct { 389 uint32_t CHM:32; /**< bit: 0..31 Bitwise Channel Mask Bit [31:0] */ 390 } bit; /**< Structure used for bit access */ 391 uint32_t reg; /**< Type used for register access */ 392 } MLB_HCMR_Type; 393 #endif 394 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 396 #define MLB_HCMR_OFFSET (0x88) /**< (MLB_HCMR) HBI Channel Mask 0 Register 0 Offset */ 397 398 #define MLB_HCMR_CHM_Pos 0 /**< (MLB_HCMR) Bitwise Channel Mask Bit [31:0] Position */ 399 #define MLB_HCMR_CHM_Msk (_U_(0xFFFFFFFF) << MLB_HCMR_CHM_Pos) /**< (MLB_HCMR) Bitwise Channel Mask Bit [31:0] Mask */ 400 #define MLB_HCMR_CHM(value) (MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos)) 401 #define MLB_HCMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_HCMR) Register MASK (Use MLB_HCMR_Msk instead) */ 402 #define MLB_HCMR_Msk _U_(0xFFFFFFFF) /**< (MLB_HCMR) Register Mask */ 403 404 405 /* -------- MLB_HCER : (MLB Offset: 0x90) (R/ 32) HBI Channel Error 0 Register 0 -------- */ 406 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 407 #if COMPONENT_TYPEDEF_STYLE == 'N' 408 typedef union { 409 struct { 410 uint32_t CERR:32; /**< bit: 0..31 Bitwise Channel Error Bit [31:0] */ 411 } bit; /**< Structure used for bit access */ 412 uint32_t reg; /**< Type used for register access */ 413 } MLB_HCER_Type; 414 #endif 415 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 416 417 #define MLB_HCER_OFFSET (0x90) /**< (MLB_HCER) HBI Channel Error 0 Register 0 Offset */ 418 419 #define MLB_HCER_CERR_Pos 0 /**< (MLB_HCER) Bitwise Channel Error Bit [31:0] Position */ 420 #define MLB_HCER_CERR_Msk (_U_(0xFFFFFFFF) << MLB_HCER_CERR_Pos) /**< (MLB_HCER) Bitwise Channel Error Bit [31:0] Mask */ 421 #define MLB_HCER_CERR(value) (MLB_HCER_CERR_Msk & ((value) << MLB_HCER_CERR_Pos)) 422 #define MLB_HCER_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_HCER) Register MASK (Use MLB_HCER_Msk instead) */ 423 #define MLB_HCER_Msk _U_(0xFFFFFFFF) /**< (MLB_HCER) Register Mask */ 424 425 426 /* -------- MLB_HCBR : (MLB Offset: 0x98) (R/ 32) HBI Channel Busy 0 Register 0 -------- */ 427 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 428 #if COMPONENT_TYPEDEF_STYLE == 'N' 429 typedef union { 430 struct { 431 uint32_t CHB:32; /**< bit: 0..31 Bitwise Channel Busy Bit [31:0] */ 432 } bit; /**< Structure used for bit access */ 433 uint32_t reg; /**< Type used for register access */ 434 } MLB_HCBR_Type; 435 #endif 436 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define MLB_HCBR_OFFSET (0x98) /**< (MLB_HCBR) HBI Channel Busy 0 Register 0 Offset */ 439 440 #define MLB_HCBR_CHB_Pos 0 /**< (MLB_HCBR) Bitwise Channel Busy Bit [31:0] Position */ 441 #define MLB_HCBR_CHB_Msk (_U_(0xFFFFFFFF) << MLB_HCBR_CHB_Pos) /**< (MLB_HCBR) Bitwise Channel Busy Bit [31:0] Mask */ 442 #define MLB_HCBR_CHB(value) (MLB_HCBR_CHB_Msk & ((value) << MLB_HCBR_CHB_Pos)) 443 #define MLB_HCBR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_HCBR) Register MASK (Use MLB_HCBR_Msk instead) */ 444 #define MLB_HCBR_Msk _U_(0xFFFFFFFF) /**< (MLB_HCBR) Register Mask */ 445 446 447 /* -------- MLB_MDAT : (MLB Offset: 0xc0) (R/W 32) MIF Data 0 Register 0 -------- */ 448 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 449 #if COMPONENT_TYPEDEF_STYLE == 'N' 450 typedef union { 451 struct { 452 uint32_t DATA:32; /**< bit: 0..31 CRT or DBR Data */ 453 } bit; /**< Structure used for bit access */ 454 uint32_t reg; /**< Type used for register access */ 455 } MLB_MDAT_Type; 456 #endif 457 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 458 459 #define MLB_MDAT_OFFSET (0xC0) /**< (MLB_MDAT) MIF Data 0 Register 0 Offset */ 460 461 #define MLB_MDAT_DATA_Pos 0 /**< (MLB_MDAT) CRT or DBR Data Position */ 462 #define MLB_MDAT_DATA_Msk (_U_(0xFFFFFFFF) << MLB_MDAT_DATA_Pos) /**< (MLB_MDAT) CRT or DBR Data Mask */ 463 #define MLB_MDAT_DATA(value) (MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos)) 464 #define MLB_MDAT_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_MDAT) Register MASK (Use MLB_MDAT_Msk instead) */ 465 #define MLB_MDAT_Msk _U_(0xFFFFFFFF) /**< (MLB_MDAT) Register Mask */ 466 467 468 /* -------- MLB_MDWE : (MLB Offset: 0xd0) (R/W 32) MIF Data Write Enable 0 Register 0 -------- */ 469 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 470 #if COMPONENT_TYPEDEF_STYLE == 'N' 471 typedef union { 472 struct { 473 uint32_t MASK:32; /**< bit: 0..31 Bitwise Write Enable for CTR Data - bits[31:0] */ 474 } bit; /**< Structure used for bit access */ 475 uint32_t reg; /**< Type used for register access */ 476 } MLB_MDWE_Type; 477 #endif 478 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 479 480 #define MLB_MDWE_OFFSET (0xD0) /**< (MLB_MDWE) MIF Data Write Enable 0 Register 0 Offset */ 481 482 #define MLB_MDWE_MASK_Pos 0 /**< (MLB_MDWE) Bitwise Write Enable for CTR Data - bits[31:0] Position */ 483 #define MLB_MDWE_MASK_Msk (_U_(0xFFFFFFFF) << MLB_MDWE_MASK_Pos) /**< (MLB_MDWE) Bitwise Write Enable for CTR Data - bits[31:0] Mask */ 484 #define MLB_MDWE_MASK(value) (MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos)) 485 #define MLB_MDWE_Msk _U_(0xFFFFFFFF) /**< (MLB_MDWE) Register Mask */ 486 487 488 /* -------- MLB_MCTL : (MLB Offset: 0xe0) (R/W 32) MIF Control Register -------- */ 489 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 490 #if COMPONENT_TYPEDEF_STYLE == 'N' 491 typedef union { 492 struct { 493 uint32_t XCMP:1; /**< bit: 0 Transfer Complete (Write 0 to Clear) */ 494 uint32_t :31; /**< bit: 1..31 Reserved */ 495 } bit; /**< Structure used for bit access */ 496 uint32_t reg; /**< Type used for register access */ 497 } MLB_MCTL_Type; 498 #endif 499 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 500 501 #define MLB_MCTL_OFFSET (0xE0) /**< (MLB_MCTL) MIF Control Register Offset */ 502 503 #define MLB_MCTL_XCMP_Pos 0 /**< (MLB_MCTL) Transfer Complete (Write 0 to Clear) Position */ 504 #define MLB_MCTL_XCMP_Msk (_U_(0x1) << MLB_MCTL_XCMP_Pos) /**< (MLB_MCTL) Transfer Complete (Write 0 to Clear) Mask */ 505 #define MLB_MCTL_XCMP MLB_MCTL_XCMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MCTL_XCMP_Msk instead */ 506 #define MLB_MCTL_MASK _U_(0x01) /**< \deprecated (MLB_MCTL) Register MASK (Use MLB_MCTL_Msk instead) */ 507 #define MLB_MCTL_Msk _U_(0x01) /**< (MLB_MCTL) Register Mask */ 508 509 510 /* -------- MLB_MADR : (MLB Offset: 0xe4) (R/W 32) MIF Address Register -------- */ 511 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 512 #if COMPONENT_TYPEDEF_STYLE == 'N' 513 typedef union { 514 struct { 515 uint32_t ADDR:14; /**< bit: 0..13 CTR or DBR Address */ 516 uint32_t :16; /**< bit: 14..29 Reserved */ 517 uint32_t TB:1; /**< bit: 30 Target Location Bit */ 518 uint32_t WNR:1; /**< bit: 31 Write-Not-Read Selection */ 519 } bit; /**< Structure used for bit access */ 520 uint32_t reg; /**< Type used for register access */ 521 } MLB_MADR_Type; 522 #endif 523 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 525 #define MLB_MADR_OFFSET (0xE4) /**< (MLB_MADR) MIF Address Register Offset */ 526 527 #define MLB_MADR_ADDR_Pos 0 /**< (MLB_MADR) CTR or DBR Address Position */ 528 #define MLB_MADR_ADDR_Msk (_U_(0x3FFF) << MLB_MADR_ADDR_Pos) /**< (MLB_MADR) CTR or DBR Address Mask */ 529 #define MLB_MADR_ADDR(value) (MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos)) 530 #define MLB_MADR_TB_Pos 30 /**< (MLB_MADR) Target Location Bit Position */ 531 #define MLB_MADR_TB_Msk (_U_(0x1) << MLB_MADR_TB_Pos) /**< (MLB_MADR) Target Location Bit Mask */ 532 #define MLB_MADR_TB MLB_MADR_TB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MADR_TB_Msk instead */ 533 #define MLB_MADR_TB_CTR_Val _U_(0x0) /**< (MLB_MADR) Selects CTR */ 534 #define MLB_MADR_TB_DBR_Val _U_(0x1) /**< (MLB_MADR) Selects DBR */ 535 #define MLB_MADR_TB_CTR (MLB_MADR_TB_CTR_Val << MLB_MADR_TB_Pos) /**< (MLB_MADR) Selects CTR Position */ 536 #define MLB_MADR_TB_DBR (MLB_MADR_TB_DBR_Val << MLB_MADR_TB_Pos) /**< (MLB_MADR) Selects DBR Position */ 537 #define MLB_MADR_WNR_Pos 31 /**< (MLB_MADR) Write-Not-Read Selection Position */ 538 #define MLB_MADR_WNR_Msk (_U_(0x1) << MLB_MADR_WNR_Pos) /**< (MLB_MADR) Write-Not-Read Selection Mask */ 539 #define MLB_MADR_WNR MLB_MADR_WNR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_MADR_WNR_Msk instead */ 540 #define MLB_MADR_MASK _U_(0xC0003FFF) /**< \deprecated (MLB_MADR) Register MASK (Use MLB_MADR_Msk instead) */ 541 #define MLB_MADR_Msk _U_(0xC0003FFF) /**< (MLB_MADR) Register Mask */ 542 543 544 /* -------- MLB_ACTL : (MLB Offset: 0x3c0) (R/W 32) AHB Control Register -------- */ 545 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 546 #if COMPONENT_TYPEDEF_STYLE == 'N' 547 typedef union { 548 struct { 549 uint32_t SCE:1; /**< bit: 0 Software Clear Enable */ 550 uint32_t SMX:1; /**< bit: 1 AHB Interrupt Mux Enable */ 551 uint32_t DMA_MODE:1; /**< bit: 2 DMA Mode */ 552 uint32_t :1; /**< bit: 3 Reserved */ 553 uint32_t MPB:1; /**< bit: 4 DMA Packet Buffering Mode */ 554 uint32_t :27; /**< bit: 5..31 Reserved */ 555 } bit; /**< Structure used for bit access */ 556 uint32_t reg; /**< Type used for register access */ 557 } MLB_ACTL_Type; 558 #endif 559 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 560 561 #define MLB_ACTL_OFFSET (0x3C0) /**< (MLB_ACTL) AHB Control Register Offset */ 562 563 #define MLB_ACTL_SCE_Pos 0 /**< (MLB_ACTL) Software Clear Enable Position */ 564 #define MLB_ACTL_SCE_Msk (_U_(0x1) << MLB_ACTL_SCE_Pos) /**< (MLB_ACTL) Software Clear Enable Mask */ 565 #define MLB_ACTL_SCE MLB_ACTL_SCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_ACTL_SCE_Msk instead */ 566 #define MLB_ACTL_SMX_Pos 1 /**< (MLB_ACTL) AHB Interrupt Mux Enable Position */ 567 #define MLB_ACTL_SMX_Msk (_U_(0x1) << MLB_ACTL_SMX_Pos) /**< (MLB_ACTL) AHB Interrupt Mux Enable Mask */ 568 #define MLB_ACTL_SMX MLB_ACTL_SMX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_ACTL_SMX_Msk instead */ 569 #define MLB_ACTL_DMA_MODE_Pos 2 /**< (MLB_ACTL) DMA Mode Position */ 570 #define MLB_ACTL_DMA_MODE_Msk (_U_(0x1) << MLB_ACTL_DMA_MODE_Pos) /**< (MLB_ACTL) DMA Mode Mask */ 571 #define MLB_ACTL_DMA_MODE MLB_ACTL_DMA_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_ACTL_DMA_MODE_Msk instead */ 572 #define MLB_ACTL_MPB_Pos 4 /**< (MLB_ACTL) DMA Packet Buffering Mode Position */ 573 #define MLB_ACTL_MPB_Msk (_U_(0x1) << MLB_ACTL_MPB_Pos) /**< (MLB_ACTL) DMA Packet Buffering Mode Mask */ 574 #define MLB_ACTL_MPB MLB_ACTL_MPB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MLB_ACTL_MPB_Msk instead */ 575 #define MLB_ACTL_MPB_SINGLE_PACKET_Val _U_(0x0) /**< (MLB_ACTL) Single-packet mode */ 576 #define MLB_ACTL_MPB_MULTIPLE_PACKET_Val _U_(0x1) /**< (MLB_ACTL) Multiple-packet mode */ 577 #define MLB_ACTL_MPB_SINGLE_PACKET (MLB_ACTL_MPB_SINGLE_PACKET_Val << MLB_ACTL_MPB_Pos) /**< (MLB_ACTL) Single-packet mode Position */ 578 #define MLB_ACTL_MPB_MULTIPLE_PACKET (MLB_ACTL_MPB_MULTIPLE_PACKET_Val << MLB_ACTL_MPB_Pos) /**< (MLB_ACTL) Multiple-packet mode Position */ 579 #define MLB_ACTL_MASK _U_(0x17) /**< \deprecated (MLB_ACTL) Register MASK (Use MLB_ACTL_Msk instead) */ 580 #define MLB_ACTL_Msk _U_(0x17) /**< (MLB_ACTL) Register Mask */ 581 582 583 /* -------- MLB_ACSR : (MLB Offset: 0x3d0) (R/W 32) AHB Channel Status 0 Register 0 -------- */ 584 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 585 #if COMPONENT_TYPEDEF_STYLE == 'N' 586 typedef union { 587 struct { 588 uint32_t CHS:32; /**< bit: 0..31 Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ 589 } bit; /**< Structure used for bit access */ 590 uint32_t reg; /**< Type used for register access */ 591 } MLB_ACSR_Type; 592 #endif 593 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 594 595 #define MLB_ACSR_OFFSET (0x3D0) /**< (MLB_ACSR) AHB Channel Status 0 Register 0 Offset */ 596 597 #define MLB_ACSR_CHS_Pos 0 /**< (MLB_ACSR) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) Position */ 598 #define MLB_ACSR_CHS_Msk (_U_(0xFFFFFFFF) << MLB_ACSR_CHS_Pos) /**< (MLB_ACSR) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) Mask */ 599 #define MLB_ACSR_CHS(value) (MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos)) 600 #define MLB_ACSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_ACSR) Register MASK (Use MLB_ACSR_Msk instead) */ 601 #define MLB_ACSR_Msk _U_(0xFFFFFFFF) /**< (MLB_ACSR) Register Mask */ 602 603 604 /* -------- MLB_ACMR : (MLB Offset: 0x3d8) (R/W 32) AHB Channel Mask 0 Register 0 -------- */ 605 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 606 #if COMPONENT_TYPEDEF_STYLE == 'N' 607 typedef union { 608 struct { 609 uint32_t CHM:32; /**< bit: 0..31 Bitwise Channel Mask Bits 31 to 0 */ 610 } bit; /**< Structure used for bit access */ 611 uint32_t reg; /**< Type used for register access */ 612 } MLB_ACMR_Type; 613 #endif 614 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 615 616 #define MLB_ACMR_OFFSET (0x3D8) /**< (MLB_ACMR) AHB Channel Mask 0 Register 0 Offset */ 617 618 #define MLB_ACMR_CHM_Pos 0 /**< (MLB_ACMR) Bitwise Channel Mask Bits 31 to 0 Position */ 619 #define MLB_ACMR_CHM_Msk (_U_(0xFFFFFFFF) << MLB_ACMR_CHM_Pos) /**< (MLB_ACMR) Bitwise Channel Mask Bits 31 to 0 Mask */ 620 #define MLB_ACMR_CHM(value) (MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos)) 621 #define MLB_ACMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MLB_ACMR) Register MASK (Use MLB_ACMR_Msk instead) */ 622 #define MLB_ACMR_Msk _U_(0xFFFFFFFF) /**< (MLB_ACMR) Register Mask */ 623 624 625 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 626 #if COMPONENT_TYPEDEF_STYLE == 'R' 627 /** \brief MLB hardware registers */ 628 typedef struct { 629 __IO uint32_t MLB_MLBC0; /**< (MLB Offset: 0x00) MediaLB Control 0 Register */ 630 __I uint8_t Reserved1[8]; 631 __IO uint32_t MLB_MS0; /**< (MLB Offset: 0x0C) MediaLB Channel Status 0 Register */ 632 __I uint8_t Reserved2[4]; 633 __IO uint32_t MLB_MS1; /**< (MLB Offset: 0x14) MediaLB Channel Status1 Register */ 634 __I uint8_t Reserved3[8]; 635 __IO uint32_t MLB_MSS; /**< (MLB Offset: 0x20) MediaLB System Status Register */ 636 __I uint32_t MLB_MSD; /**< (MLB Offset: 0x24) MediaLB System Data Register */ 637 __I uint8_t Reserved4[4]; 638 __IO uint32_t MLB_MIEN; /**< (MLB Offset: 0x2C) MediaLB Interrupt Enable Register */ 639 __I uint8_t Reserved5[12]; 640 __IO uint32_t MLB_MLBC1; /**< (MLB Offset: 0x3C) MediaLB Control 1 Register */ 641 __I uint8_t Reserved6[64]; 642 __IO uint32_t MLB_HCTL; /**< (MLB Offset: 0x80) HBI Control Register */ 643 __I uint8_t Reserved7[4]; 644 __IO uint32_t MLB_HCMR[2]; /**< (MLB Offset: 0x88) HBI Channel Mask 0 Register 0 */ 645 __I uint32_t MLB_HCER[2]; /**< (MLB Offset: 0x90) HBI Channel Error 0 Register 0 */ 646 __I uint32_t MLB_HCBR[2]; /**< (MLB Offset: 0x98) HBI Channel Busy 0 Register 0 */ 647 __I uint8_t Reserved8[32]; 648 __IO uint32_t MLB_MDAT[4]; /**< (MLB Offset: 0xC0) MIF Data 0 Register 0 */ 649 __IO uint32_t MLB_MDWE[4]; /**< (MLB Offset: 0xD0) MIF Data Write Enable 0 Register 0 */ 650 __IO uint32_t MLB_MCTL; /**< (MLB Offset: 0xE0) MIF Control Register */ 651 __IO uint32_t MLB_MADR; /**< (MLB Offset: 0xE4) MIF Address Register */ 652 __I uint8_t Reserved9[728]; 653 __IO uint32_t MLB_ACTL; /**< (MLB Offset: 0x3C0) AHB Control Register */ 654 __I uint8_t Reserved10[12]; 655 __IO uint32_t MLB_ACSR[2]; /**< (MLB Offset: 0x3D0) AHB Channel Status 0 Register 0 */ 656 __IO uint32_t MLB_ACMR[2]; /**< (MLB Offset: 0x3D8) AHB Channel Mask 0 Register 0 */ 657 } Mlb; 658 659 #elif COMPONENT_TYPEDEF_STYLE == 'N' 660 /** \brief MLB hardware registers */ 661 typedef struct { 662 __IO MLB_MLBC0_Type MLB_MLBC0; /**< Offset: 0x00 (R/W 32) MediaLB Control 0 Register */ 663 __I uint8_t Reserved1[8]; 664 __IO MLB_MS0_Type MLB_MS0; /**< Offset: 0x0C (R/W 32) MediaLB Channel Status 0 Register */ 665 __I uint8_t Reserved2[4]; 666 __IO MLB_MS1_Type MLB_MS1; /**< Offset: 0x14 (R/W 32) MediaLB Channel Status1 Register */ 667 __I uint8_t Reserved3[8]; 668 __IO MLB_MSS_Type MLB_MSS; /**< Offset: 0x20 (R/W 32) MediaLB System Status Register */ 669 __I MLB_MSD_Type MLB_MSD; /**< Offset: 0x24 (R/ 32) MediaLB System Data Register */ 670 __I uint8_t Reserved4[4]; 671 __IO MLB_MIEN_Type MLB_MIEN; /**< Offset: 0x2C (R/W 32) MediaLB Interrupt Enable Register */ 672 __I uint8_t Reserved5[12]; 673 __IO MLB_MLBC1_Type MLB_MLBC1; /**< Offset: 0x3C (R/W 32) MediaLB Control 1 Register */ 674 __I uint8_t Reserved6[64]; 675 __IO MLB_HCTL_Type MLB_HCTL; /**< Offset: 0x80 (R/W 32) HBI Control Register */ 676 __I uint8_t Reserved7[4]; 677 __IO MLB_HCMR_Type MLB_HCMR[2]; /**< Offset: 0x88 (R/W 32) HBI Channel Mask 0 Register 0 */ 678 __I MLB_HCER_Type MLB_HCER[2]; /**< Offset: 0x90 (R/ 32) HBI Channel Error 0 Register 0 */ 679 __I MLB_HCBR_Type MLB_HCBR[2]; /**< Offset: 0x98 (R/ 32) HBI Channel Busy 0 Register 0 */ 680 __I uint8_t Reserved8[32]; 681 __IO MLB_MDAT_Type MLB_MDAT[4]; /**< Offset: 0xC0 (R/W 32) MIF Data 0 Register 0 */ 682 __IO MLB_MDWE_Type MLB_MDWE[4]; /**< Offset: 0xD0 (R/W 32) MIF Data Write Enable 0 Register 0 */ 683 __IO MLB_MCTL_Type MLB_MCTL; /**< Offset: 0xE0 (R/W 32) MIF Control Register */ 684 __IO MLB_MADR_Type MLB_MADR; /**< Offset: 0xE4 (R/W 32) MIF Address Register */ 685 __I uint8_t Reserved9[728]; 686 __IO MLB_ACTL_Type MLB_ACTL; /**< Offset: 0x3C0 (R/W 32) AHB Control Register */ 687 __I uint8_t Reserved10[12]; 688 __IO MLB_ACSR_Type MLB_ACSR[2]; /**< Offset: 0x3D0 (R/W 32) AHB Channel Status 0 Register 0 */ 689 __IO MLB_ACMR_Type MLB_ACMR[2]; /**< Offset: 0x3D8 (R/W 32) AHB Channel Mask 0 Register 0 */ 690 } Mlb; 691 692 #else /* COMPONENT_TYPEDEF_STYLE */ 693 #error Unknown component typedef style 694 #endif /* COMPONENT_TYPEDEF_STYLE */ 695 696 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 697 /** @} end of MediaLB */ 698 699 #endif /* _SAMV71_MLB_COMPONENT_H_ */ 700
