1 /** 2 * \file 3 * 4 * \brief Component description for I2SC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_I2SC_COMPONENT_H_ 32 #define _SAMV71_I2SC_COMPONENT_H_ 33 #define _SAMV71_I2SC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Inter-IC Sound Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR I2SC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define I2SC_11241 /**< (I2SC) Module ID */ 46 #define REV_I2SC N /**< (I2SC) Module revision */ 47 48 /* -------- I2SC_CR : (I2SC Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t RXEN:1; /**< bit: 0 Receiver Enable */ 54 uint32_t RXDIS:1; /**< bit: 1 Receiver Disable */ 55 uint32_t CKEN:1; /**< bit: 2 Clocks Enable */ 56 uint32_t CKDIS:1; /**< bit: 3 Clocks Disable */ 57 uint32_t TXEN:1; /**< bit: 4 Transmitter Enable */ 58 uint32_t TXDIS:1; /**< bit: 5 Transmitter Disable */ 59 uint32_t :1; /**< bit: 6 Reserved */ 60 uint32_t SWRST:1; /**< bit: 7 Software Reset */ 61 uint32_t :24; /**< bit: 8..31 Reserved */ 62 } bit; /**< Structure used for bit access */ 63 uint32_t reg; /**< Type used for register access */ 64 } I2SC_CR_Type; 65 #endif 66 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 #define I2SC_CR_OFFSET (0x00) /**< (I2SC_CR) Control Register Offset */ 69 70 #define I2SC_CR_RXEN_Pos 0 /**< (I2SC_CR) Receiver Enable Position */ 71 #define I2SC_CR_RXEN_Msk (_U_(0x1) << I2SC_CR_RXEN_Pos) /**< (I2SC_CR) Receiver Enable Mask */ 72 #define I2SC_CR_RXEN I2SC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXEN_Msk instead */ 73 #define I2SC_CR_RXDIS_Pos 1 /**< (I2SC_CR) Receiver Disable Position */ 74 #define I2SC_CR_RXDIS_Msk (_U_(0x1) << I2SC_CR_RXDIS_Pos) /**< (I2SC_CR) Receiver Disable Mask */ 75 #define I2SC_CR_RXDIS I2SC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXDIS_Msk instead */ 76 #define I2SC_CR_CKEN_Pos 2 /**< (I2SC_CR) Clocks Enable Position */ 77 #define I2SC_CR_CKEN_Msk (_U_(0x1) << I2SC_CR_CKEN_Pos) /**< (I2SC_CR) Clocks Enable Mask */ 78 #define I2SC_CR_CKEN I2SC_CR_CKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKEN_Msk instead */ 79 #define I2SC_CR_CKDIS_Pos 3 /**< (I2SC_CR) Clocks Disable Position */ 80 #define I2SC_CR_CKDIS_Msk (_U_(0x1) << I2SC_CR_CKDIS_Pos) /**< (I2SC_CR) Clocks Disable Mask */ 81 #define I2SC_CR_CKDIS I2SC_CR_CKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKDIS_Msk instead */ 82 #define I2SC_CR_TXEN_Pos 4 /**< (I2SC_CR) Transmitter Enable Position */ 83 #define I2SC_CR_TXEN_Msk (_U_(0x1) << I2SC_CR_TXEN_Pos) /**< (I2SC_CR) Transmitter Enable Mask */ 84 #define I2SC_CR_TXEN I2SC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXEN_Msk instead */ 85 #define I2SC_CR_TXDIS_Pos 5 /**< (I2SC_CR) Transmitter Disable Position */ 86 #define I2SC_CR_TXDIS_Msk (_U_(0x1) << I2SC_CR_TXDIS_Pos) /**< (I2SC_CR) Transmitter Disable Mask */ 87 #define I2SC_CR_TXDIS I2SC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXDIS_Msk instead */ 88 #define I2SC_CR_SWRST_Pos 7 /**< (I2SC_CR) Software Reset Position */ 89 #define I2SC_CR_SWRST_Msk (_U_(0x1) << I2SC_CR_SWRST_Pos) /**< (I2SC_CR) Software Reset Mask */ 90 #define I2SC_CR_SWRST I2SC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_SWRST_Msk instead */ 91 #define I2SC_CR_MASK _U_(0xBF) /**< \deprecated (I2SC_CR) Register MASK (Use I2SC_CR_Msk instead) */ 92 #define I2SC_CR_Msk _U_(0xBF) /**< (I2SC_CR) Register Mask */ 93 94 95 /* -------- I2SC_MR : (I2SC Offset: 0x04) (R/W 32) Mode Register -------- */ 96 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 97 #if COMPONENT_TYPEDEF_STYLE == 'N' 98 typedef union { 99 struct { 100 uint32_t MODE:1; /**< bit: 0 Inter-IC Sound Controller Mode */ 101 uint32_t :1; /**< bit: 1 Reserved */ 102 uint32_t DATALENGTH:3; /**< bit: 2..4 Data Word Length */ 103 uint32_t :3; /**< bit: 5..7 Reserved */ 104 uint32_t RXMONO:1; /**< bit: 8 Receive Mono */ 105 uint32_t RXDMA:1; /**< bit: 9 Single or Multiple DMA Controller Channels for Receiver */ 106 uint32_t RXLOOP:1; /**< bit: 10 Loopback Test Mode */ 107 uint32_t :1; /**< bit: 11 Reserved */ 108 uint32_t TXMONO:1; /**< bit: 12 Transmit Mono */ 109 uint32_t TXDMA:1; /**< bit: 13 Single or Multiple DMA Controller Channels for Transmitter */ 110 uint32_t TXSAME:1; /**< bit: 14 Transmit Data when Underrun */ 111 uint32_t :1; /**< bit: 15 Reserved */ 112 uint32_t IMCKDIV:6; /**< bit: 16..21 Selected Clock to I2SC Master Clock Ratio */ 113 uint32_t :2; /**< bit: 22..23 Reserved */ 114 uint32_t IMCKFS:6; /**< bit: 24..29 Master Clock to fs Ratio */ 115 uint32_t IMCKMODE:1; /**< bit: 30 Master Clock Mode */ 116 uint32_t IWS:1; /**< bit: 31 I2SC_WS Slot Width */ 117 } bit; /**< Structure used for bit access */ 118 uint32_t reg; /**< Type used for register access */ 119 } I2SC_MR_Type; 120 #endif 121 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #define I2SC_MR_OFFSET (0x04) /**< (I2SC_MR) Mode Register Offset */ 124 125 #define I2SC_MR_MODE_Pos 0 /**< (I2SC_MR) Inter-IC Sound Controller Mode Position */ 126 #define I2SC_MR_MODE_Msk (_U_(0x1) << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Inter-IC Sound Controller Mode Mask */ 127 #define I2SC_MR_MODE I2SC_MR_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_MODE_Msk instead */ 128 #define I2SC_MR_MODE_SLAVE_Val _U_(0x0) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. */ 129 #define I2SC_MR_MODE_MASTER_Val _U_(0x1) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. */ 130 #define I2SC_MR_MODE_SLAVE (I2SC_MR_MODE_SLAVE_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. Position */ 131 #define I2SC_MR_MODE_MASTER (I2SC_MR_MODE_MASTER_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. Position */ 132 #define I2SC_MR_DATALENGTH_Pos 2 /**< (I2SC_MR) Data Word Length Position */ 133 #define I2SC_MR_DATALENGTH_Msk (_U_(0x7) << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data Word Length Mask */ 134 #define I2SC_MR_DATALENGTH(value) (I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)) 135 #define I2SC_MR_DATALENGTH_32_BITS_Val _U_(0x0) /**< (I2SC_MR) Data length is set to 32 bits */ 136 #define I2SC_MR_DATALENGTH_24_BITS_Val _U_(0x1) /**< (I2SC_MR) Data length is set to 24 bits */ 137 #define I2SC_MR_DATALENGTH_20_BITS_Val _U_(0x2) /**< (I2SC_MR) Data length is set to 20 bits */ 138 #define I2SC_MR_DATALENGTH_18_BITS_Val _U_(0x3) /**< (I2SC_MR) Data length is set to 18 bits */ 139 #define I2SC_MR_DATALENGTH_16_BITS_Val _U_(0x4) /**< (I2SC_MR) Data length is set to 16 bits */ 140 #define I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val _U_(0x5) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ 141 #define I2SC_MR_DATALENGTH_8_BITS_Val _U_(0x6) /**< (I2SC_MR) Data length is set to 8 bits */ 142 #define I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val _U_(0x7) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ 143 #define I2SC_MR_DATALENGTH_32_BITS (I2SC_MR_DATALENGTH_32_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 32 bits Position */ 144 #define I2SC_MR_DATALENGTH_24_BITS (I2SC_MR_DATALENGTH_24_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 24 bits Position */ 145 #define I2SC_MR_DATALENGTH_20_BITS (I2SC_MR_DATALENGTH_20_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 20 bits Position */ 146 #define I2SC_MR_DATALENGTH_18_BITS (I2SC_MR_DATALENGTH_18_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 18 bits Position */ 147 #define I2SC_MR_DATALENGTH_16_BITS (I2SC_MR_DATALENGTH_16_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16 bits Position */ 148 #define I2SC_MR_DATALENGTH_16_BITS_COMPACT (I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. Position */ 149 #define I2SC_MR_DATALENGTH_8_BITS (I2SC_MR_DATALENGTH_8_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8 bits Position */ 150 #define I2SC_MR_DATALENGTH_8_BITS_COMPACT (I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. Position */ 151 #define I2SC_MR_RXMONO_Pos 8 /**< (I2SC_MR) Receive Mono Position */ 152 #define I2SC_MR_RXMONO_Msk (_U_(0x1) << I2SC_MR_RXMONO_Pos) /**< (I2SC_MR) Receive Mono Mask */ 153 #define I2SC_MR_RXMONO I2SC_MR_RXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXMONO_Msk instead */ 154 #define I2SC_MR_RXDMA_Pos 9 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Position */ 155 #define I2SC_MR_RXDMA_Msk (_U_(0x1) << I2SC_MR_RXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Mask */ 156 #define I2SC_MR_RXDMA I2SC_MR_RXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXDMA_Msk instead */ 157 #define I2SC_MR_RXLOOP_Pos 10 /**< (I2SC_MR) Loopback Test Mode Position */ 158 #define I2SC_MR_RXLOOP_Msk (_U_(0x1) << I2SC_MR_RXLOOP_Pos) /**< (I2SC_MR) Loopback Test Mode Mask */ 159 #define I2SC_MR_RXLOOP I2SC_MR_RXLOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXLOOP_Msk instead */ 160 #define I2SC_MR_TXMONO_Pos 12 /**< (I2SC_MR) Transmit Mono Position */ 161 #define I2SC_MR_TXMONO_Msk (_U_(0x1) << I2SC_MR_TXMONO_Pos) /**< (I2SC_MR) Transmit Mono Mask */ 162 #define I2SC_MR_TXMONO I2SC_MR_TXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXMONO_Msk instead */ 163 #define I2SC_MR_TXDMA_Pos 13 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Position */ 164 #define I2SC_MR_TXDMA_Msk (_U_(0x1) << I2SC_MR_TXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Mask */ 165 #define I2SC_MR_TXDMA I2SC_MR_TXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXDMA_Msk instead */ 166 #define I2SC_MR_TXSAME_Pos 14 /**< (I2SC_MR) Transmit Data when Underrun Position */ 167 #define I2SC_MR_TXSAME_Msk (_U_(0x1) << I2SC_MR_TXSAME_Pos) /**< (I2SC_MR) Transmit Data when Underrun Mask */ 168 #define I2SC_MR_TXSAME I2SC_MR_TXSAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXSAME_Msk instead */ 169 #define I2SC_MR_IMCKDIV_Pos 16 /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Position */ 170 #define I2SC_MR_IMCKDIV_Msk (_U_(0x3F) << I2SC_MR_IMCKDIV_Pos) /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Mask */ 171 #define I2SC_MR_IMCKDIV(value) (I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)) 172 #define I2SC_MR_IMCKFS_Pos 24 /**< (I2SC_MR) Master Clock to fs Ratio Position */ 173 #define I2SC_MR_IMCKFS_Msk (_U_(0x3F) << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Master Clock to fs Ratio Mask */ 174 #define I2SC_MR_IMCKFS(value) (I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)) 175 #define I2SC_MR_IMCKFS_M2SF32_Val _U_(0x0) /**< (I2SC_MR) Sample frequency ratio set to 32 */ 176 #define I2SC_MR_IMCKFS_M2SF64_Val _U_(0x1) /**< (I2SC_MR) Sample frequency ratio set to 64 */ 177 #define I2SC_MR_IMCKFS_M2SF96_Val _U_(0x2) /**< (I2SC_MR) Sample frequency ratio set to 96 */ 178 #define I2SC_MR_IMCKFS_M2SF128_Val _U_(0x3) /**< (I2SC_MR) Sample frequency ratio set to 128 */ 179 #define I2SC_MR_IMCKFS_M2SF192_Val _U_(0x5) /**< (I2SC_MR) Sample frequency ratio set to 192 */ 180 #define I2SC_MR_IMCKFS_M2SF256_Val _U_(0x7) /**< (I2SC_MR) Sample frequency ratio set to 256 */ 181 #define I2SC_MR_IMCKFS_M2SF384_Val _U_(0xB) /**< (I2SC_MR) Sample frequency ratio set to 384 */ 182 #define I2SC_MR_IMCKFS_M2SF512_Val _U_(0xF) /**< (I2SC_MR) Sample frequency ratio set to 512 */ 183 #define I2SC_MR_IMCKFS_M2SF768_Val _U_(0x17) /**< (I2SC_MR) Sample frequency ratio set to 768 */ 184 #define I2SC_MR_IMCKFS_M2SF1024_Val _U_(0x1F) /**< (I2SC_MR) Sample frequency ratio set to 1024 */ 185 #define I2SC_MR_IMCKFS_M2SF1536_Val _U_(0x2F) /**< (I2SC_MR) Sample frequency ratio set to 1536 */ 186 #define I2SC_MR_IMCKFS_M2SF2048_Val _U_(0x3F) /**< (I2SC_MR) Sample frequency ratio set to 2048 */ 187 #define I2SC_MR_IMCKFS_M2SF32 (I2SC_MR_IMCKFS_M2SF32_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 32 Position */ 188 #define I2SC_MR_IMCKFS_M2SF64 (I2SC_MR_IMCKFS_M2SF64_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 64 Position */ 189 #define I2SC_MR_IMCKFS_M2SF96 (I2SC_MR_IMCKFS_M2SF96_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 96 Position */ 190 #define I2SC_MR_IMCKFS_M2SF128 (I2SC_MR_IMCKFS_M2SF128_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 128 Position */ 191 #define I2SC_MR_IMCKFS_M2SF192 (I2SC_MR_IMCKFS_M2SF192_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 192 Position */ 192 #define I2SC_MR_IMCKFS_M2SF256 (I2SC_MR_IMCKFS_M2SF256_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 256 Position */ 193 #define I2SC_MR_IMCKFS_M2SF384 (I2SC_MR_IMCKFS_M2SF384_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 384 Position */ 194 #define I2SC_MR_IMCKFS_M2SF512 (I2SC_MR_IMCKFS_M2SF512_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 512 Position */ 195 #define I2SC_MR_IMCKFS_M2SF768 (I2SC_MR_IMCKFS_M2SF768_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 768 Position */ 196 #define I2SC_MR_IMCKFS_M2SF1024 (I2SC_MR_IMCKFS_M2SF1024_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1024 Position */ 197 #define I2SC_MR_IMCKFS_M2SF1536 (I2SC_MR_IMCKFS_M2SF1536_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1536 Position */ 198 #define I2SC_MR_IMCKFS_M2SF2048 (I2SC_MR_IMCKFS_M2SF2048_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 2048 Position */ 199 #define I2SC_MR_IMCKMODE_Pos 30 /**< (I2SC_MR) Master Clock Mode Position */ 200 #define I2SC_MR_IMCKMODE_Msk (_U_(0x1) << I2SC_MR_IMCKMODE_Pos) /**< (I2SC_MR) Master Clock Mode Mask */ 201 #define I2SC_MR_IMCKMODE I2SC_MR_IMCKMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IMCKMODE_Msk instead */ 202 #define I2SC_MR_IWS_Pos 31 /**< (I2SC_MR) I2SC_WS Slot Width Position */ 203 #define I2SC_MR_IWS_Msk (_U_(0x1) << I2SC_MR_IWS_Pos) /**< (I2SC_MR) I2SC_WS Slot Width Mask */ 204 #define I2SC_MR_IWS I2SC_MR_IWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IWS_Msk instead */ 205 #define I2SC_MR_MASK _U_(0xFF3F771D) /**< \deprecated (I2SC_MR) Register MASK (Use I2SC_MR_Msk instead) */ 206 #define I2SC_MR_Msk _U_(0xFF3F771D) /**< (I2SC_MR) Register Mask */ 207 208 209 /* -------- I2SC_SR : (I2SC Offset: 0x08) (R/ 32) Status Register -------- */ 210 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 211 #if COMPONENT_TYPEDEF_STYLE == 'N' 212 typedef union { 213 struct { 214 uint32_t RXEN:1; /**< bit: 0 Receiver Enabled */ 215 uint32_t RXRDY:1; /**< bit: 1 Receive Ready */ 216 uint32_t RXOR:1; /**< bit: 2 Receive Overrun */ 217 uint32_t :1; /**< bit: 3 Reserved */ 218 uint32_t TXEN:1; /**< bit: 4 Transmitter Enabled */ 219 uint32_t TXRDY:1; /**< bit: 5 Transmit Ready */ 220 uint32_t TXUR:1; /**< bit: 6 Transmit Underrun */ 221 uint32_t :1; /**< bit: 7 Reserved */ 222 uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Channel */ 223 uint32_t :10; /**< bit: 10..19 Reserved */ 224 uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Channel */ 225 uint32_t :10; /**< bit: 22..31 Reserved */ 226 } bit; /**< Structure used for bit access */ 227 uint32_t reg; /**< Type used for register access */ 228 } I2SC_SR_Type; 229 #endif 230 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 231 232 #define I2SC_SR_OFFSET (0x08) /**< (I2SC_SR) Status Register Offset */ 233 234 #define I2SC_SR_RXEN_Pos 0 /**< (I2SC_SR) Receiver Enabled Position */ 235 #define I2SC_SR_RXEN_Msk (_U_(0x1) << I2SC_SR_RXEN_Pos) /**< (I2SC_SR) Receiver Enabled Mask */ 236 #define I2SC_SR_RXEN I2SC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXEN_Msk instead */ 237 #define I2SC_SR_RXRDY_Pos 1 /**< (I2SC_SR) Receive Ready Position */ 238 #define I2SC_SR_RXRDY_Msk (_U_(0x1) << I2SC_SR_RXRDY_Pos) /**< (I2SC_SR) Receive Ready Mask */ 239 #define I2SC_SR_RXRDY I2SC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXRDY_Msk instead */ 240 #define I2SC_SR_RXOR_Pos 2 /**< (I2SC_SR) Receive Overrun Position */ 241 #define I2SC_SR_RXOR_Msk (_U_(0x1) << I2SC_SR_RXOR_Pos) /**< (I2SC_SR) Receive Overrun Mask */ 242 #define I2SC_SR_RXOR I2SC_SR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXOR_Msk instead */ 243 #define I2SC_SR_TXEN_Pos 4 /**< (I2SC_SR) Transmitter Enabled Position */ 244 #define I2SC_SR_TXEN_Msk (_U_(0x1) << I2SC_SR_TXEN_Pos) /**< (I2SC_SR) Transmitter Enabled Mask */ 245 #define I2SC_SR_TXEN I2SC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXEN_Msk instead */ 246 #define I2SC_SR_TXRDY_Pos 5 /**< (I2SC_SR) Transmit Ready Position */ 247 #define I2SC_SR_TXRDY_Msk (_U_(0x1) << I2SC_SR_TXRDY_Pos) /**< (I2SC_SR) Transmit Ready Mask */ 248 #define I2SC_SR_TXRDY I2SC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXRDY_Msk instead */ 249 #define I2SC_SR_TXUR_Pos 6 /**< (I2SC_SR) Transmit Underrun Position */ 250 #define I2SC_SR_TXUR_Msk (_U_(0x1) << I2SC_SR_TXUR_Pos) /**< (I2SC_SR) Transmit Underrun Mask */ 251 #define I2SC_SR_TXUR I2SC_SR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXUR_Msk instead */ 252 #define I2SC_SR_RXORCH_Pos 8 /**< (I2SC_SR) Receive Overrun Channel Position */ 253 #define I2SC_SR_RXORCH_Msk (_U_(0x3) << I2SC_SR_RXORCH_Pos) /**< (I2SC_SR) Receive Overrun Channel Mask */ 254 #define I2SC_SR_RXORCH(value) (I2SC_SR_RXORCH_Msk & ((value) << I2SC_SR_RXORCH_Pos)) 255 #define I2SC_SR_TXURCH_Pos 20 /**< (I2SC_SR) Transmit Underrun Channel Position */ 256 #define I2SC_SR_TXURCH_Msk (_U_(0x3) << I2SC_SR_TXURCH_Pos) /**< (I2SC_SR) Transmit Underrun Channel Mask */ 257 #define I2SC_SR_TXURCH(value) (I2SC_SR_TXURCH_Msk & ((value) << I2SC_SR_TXURCH_Pos)) 258 #define I2SC_SR_MASK _U_(0x300377) /**< \deprecated (I2SC_SR) Register MASK (Use I2SC_SR_Msk instead) */ 259 #define I2SC_SR_Msk _U_(0x300377) /**< (I2SC_SR) Register Mask */ 260 261 262 /* -------- I2SC_SCR : (I2SC Offset: 0x0c) (/W 32) Status Clear Register -------- */ 263 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 264 #if COMPONENT_TYPEDEF_STYLE == 'N' 265 typedef union { 266 struct { 267 uint32_t :2; /**< bit: 0..1 Reserved */ 268 uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Clear */ 269 uint32_t :3; /**< bit: 3..5 Reserved */ 270 uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Clear */ 271 uint32_t :1; /**< bit: 7 Reserved */ 272 uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Clear */ 273 uint32_t :10; /**< bit: 10..19 Reserved */ 274 uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Clear */ 275 uint32_t :10; /**< bit: 22..31 Reserved */ 276 } bit; /**< Structure used for bit access */ 277 uint32_t reg; /**< Type used for register access */ 278 } I2SC_SCR_Type; 279 #endif 280 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define I2SC_SCR_OFFSET (0x0C) /**< (I2SC_SCR) Status Clear Register Offset */ 283 284 #define I2SC_SCR_RXOR_Pos 2 /**< (I2SC_SCR) Receive Overrun Status Clear Position */ 285 #define I2SC_SCR_RXOR_Msk (_U_(0x1) << I2SC_SCR_RXOR_Pos) /**< (I2SC_SCR) Receive Overrun Status Clear Mask */ 286 #define I2SC_SCR_RXOR I2SC_SCR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_RXOR_Msk instead */ 287 #define I2SC_SCR_TXUR_Pos 6 /**< (I2SC_SCR) Transmit Underrun Status Clear Position */ 288 #define I2SC_SCR_TXUR_Msk (_U_(0x1) << I2SC_SCR_TXUR_Pos) /**< (I2SC_SCR) Transmit Underrun Status Clear Mask */ 289 #define I2SC_SCR_TXUR I2SC_SCR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_TXUR_Msk instead */ 290 #define I2SC_SCR_RXORCH_Pos 8 /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Position */ 291 #define I2SC_SCR_RXORCH_Msk (_U_(0x3) << I2SC_SCR_RXORCH_Pos) /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Mask */ 292 #define I2SC_SCR_RXORCH(value) (I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)) 293 #define I2SC_SCR_TXURCH_Pos 20 /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Position */ 294 #define I2SC_SCR_TXURCH_Msk (_U_(0x3) << I2SC_SCR_TXURCH_Pos) /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Mask */ 295 #define I2SC_SCR_TXURCH(value) (I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)) 296 #define I2SC_SCR_MASK _U_(0x300344) /**< \deprecated (I2SC_SCR) Register MASK (Use I2SC_SCR_Msk instead) */ 297 #define I2SC_SCR_Msk _U_(0x300344) /**< (I2SC_SCR) Register Mask */ 298 299 300 /* -------- I2SC_SSR : (I2SC Offset: 0x10) (/W 32) Status Set Register -------- */ 301 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 302 #if COMPONENT_TYPEDEF_STYLE == 'N' 303 typedef union { 304 struct { 305 uint32_t :2; /**< bit: 0..1 Reserved */ 306 uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Set */ 307 uint32_t :3; /**< bit: 3..5 Reserved */ 308 uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Set */ 309 uint32_t :1; /**< bit: 7 Reserved */ 310 uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Set */ 311 uint32_t :10; /**< bit: 10..19 Reserved */ 312 uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Set */ 313 uint32_t :10; /**< bit: 22..31 Reserved */ 314 } bit; /**< Structure used for bit access */ 315 uint32_t reg; /**< Type used for register access */ 316 } I2SC_SSR_Type; 317 #endif 318 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 319 320 #define I2SC_SSR_OFFSET (0x10) /**< (I2SC_SSR) Status Set Register Offset */ 321 322 #define I2SC_SSR_RXOR_Pos 2 /**< (I2SC_SSR) Receive Overrun Status Set Position */ 323 #define I2SC_SSR_RXOR_Msk (_U_(0x1) << I2SC_SSR_RXOR_Pos) /**< (I2SC_SSR) Receive Overrun Status Set Mask */ 324 #define I2SC_SSR_RXOR I2SC_SSR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_RXOR_Msk instead */ 325 #define I2SC_SSR_TXUR_Pos 6 /**< (I2SC_SSR) Transmit Underrun Status Set Position */ 326 #define I2SC_SSR_TXUR_Msk (_U_(0x1) << I2SC_SSR_TXUR_Pos) /**< (I2SC_SSR) Transmit Underrun Status Set Mask */ 327 #define I2SC_SSR_TXUR I2SC_SSR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_TXUR_Msk instead */ 328 #define I2SC_SSR_RXORCH_Pos 8 /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Position */ 329 #define I2SC_SSR_RXORCH_Msk (_U_(0x3) << I2SC_SSR_RXORCH_Pos) /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Mask */ 330 #define I2SC_SSR_RXORCH(value) (I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)) 331 #define I2SC_SSR_TXURCH_Pos 20 /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Position */ 332 #define I2SC_SSR_TXURCH_Msk (_U_(0x3) << I2SC_SSR_TXURCH_Pos) /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Mask */ 333 #define I2SC_SSR_TXURCH(value) (I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)) 334 #define I2SC_SSR_MASK _U_(0x300344) /**< \deprecated (I2SC_SSR) Register MASK (Use I2SC_SSR_Msk instead) */ 335 #define I2SC_SSR_Msk _U_(0x300344) /**< (I2SC_SSR) Register Mask */ 336 337 338 /* -------- I2SC_IER : (I2SC Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ 339 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 340 #if COMPONENT_TYPEDEF_STYLE == 'N' 341 typedef union { 342 struct { 343 uint32_t :1; /**< bit: 0 Reserved */ 344 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Enable */ 345 uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Enable */ 346 uint32_t :2; /**< bit: 3..4 Reserved */ 347 uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Enable */ 348 uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Enable */ 349 uint32_t :25; /**< bit: 7..31 Reserved */ 350 } bit; /**< Structure used for bit access */ 351 uint32_t reg; /**< Type used for register access */ 352 } I2SC_IER_Type; 353 #endif 354 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 355 356 #define I2SC_IER_OFFSET (0x14) /**< (I2SC_IER) Interrupt Enable Register Offset */ 357 358 #define I2SC_IER_RXRDY_Pos 1 /**< (I2SC_IER) Receiver Ready Interrupt Enable Position */ 359 #define I2SC_IER_RXRDY_Msk (_U_(0x1) << I2SC_IER_RXRDY_Pos) /**< (I2SC_IER) Receiver Ready Interrupt Enable Mask */ 360 #define I2SC_IER_RXRDY I2SC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXRDY_Msk instead */ 361 #define I2SC_IER_RXOR_Pos 2 /**< (I2SC_IER) Receiver Overrun Interrupt Enable Position */ 362 #define I2SC_IER_RXOR_Msk (_U_(0x1) << I2SC_IER_RXOR_Pos) /**< (I2SC_IER) Receiver Overrun Interrupt Enable Mask */ 363 #define I2SC_IER_RXOR I2SC_IER_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXOR_Msk instead */ 364 #define I2SC_IER_TXRDY_Pos 5 /**< (I2SC_IER) Transmit Ready Interrupt Enable Position */ 365 #define I2SC_IER_TXRDY_Msk (_U_(0x1) << I2SC_IER_TXRDY_Pos) /**< (I2SC_IER) Transmit Ready Interrupt Enable Mask */ 366 #define I2SC_IER_TXRDY I2SC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXRDY_Msk instead */ 367 #define I2SC_IER_TXUR_Pos 6 /**< (I2SC_IER) Transmit Underflow Interrupt Enable Position */ 368 #define I2SC_IER_TXUR_Msk (_U_(0x1) << I2SC_IER_TXUR_Pos) /**< (I2SC_IER) Transmit Underflow Interrupt Enable Mask */ 369 #define I2SC_IER_TXUR I2SC_IER_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXUR_Msk instead */ 370 #define I2SC_IER_MASK _U_(0x66) /**< \deprecated (I2SC_IER) Register MASK (Use I2SC_IER_Msk instead) */ 371 #define I2SC_IER_Msk _U_(0x66) /**< (I2SC_IER) Register Mask */ 372 373 374 /* -------- I2SC_IDR : (I2SC Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ 375 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 376 #if COMPONENT_TYPEDEF_STYLE == 'N' 377 typedef union { 378 struct { 379 uint32_t :1; /**< bit: 0 Reserved */ 380 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ 381 uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */ 382 uint32_t :2; /**< bit: 3..4 Reserved */ 383 uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */ 384 uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */ 385 uint32_t :25; /**< bit: 7..31 Reserved */ 386 } bit; /**< Structure used for bit access */ 387 uint32_t reg; /**< Type used for register access */ 388 } I2SC_IDR_Type; 389 #endif 390 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 391 392 #define I2SC_IDR_OFFSET (0x18) /**< (I2SC_IDR) Interrupt Disable Register Offset */ 393 394 #define I2SC_IDR_RXRDY_Pos 1 /**< (I2SC_IDR) Receiver Ready Interrupt Disable Position */ 395 #define I2SC_IDR_RXRDY_Msk (_U_(0x1) << I2SC_IDR_RXRDY_Pos) /**< (I2SC_IDR) Receiver Ready Interrupt Disable Mask */ 396 #define I2SC_IDR_RXRDY I2SC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXRDY_Msk instead */ 397 #define I2SC_IDR_RXOR_Pos 2 /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Position */ 398 #define I2SC_IDR_RXOR_Msk (_U_(0x1) << I2SC_IDR_RXOR_Pos) /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Mask */ 399 #define I2SC_IDR_RXOR I2SC_IDR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXOR_Msk instead */ 400 #define I2SC_IDR_TXRDY_Pos 5 /**< (I2SC_IDR) Transmit Ready Interrupt Disable Position */ 401 #define I2SC_IDR_TXRDY_Msk (_U_(0x1) << I2SC_IDR_TXRDY_Pos) /**< (I2SC_IDR) Transmit Ready Interrupt Disable Mask */ 402 #define I2SC_IDR_TXRDY I2SC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXRDY_Msk instead */ 403 #define I2SC_IDR_TXUR_Pos 6 /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Position */ 404 #define I2SC_IDR_TXUR_Msk (_U_(0x1) << I2SC_IDR_TXUR_Pos) /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Mask */ 405 #define I2SC_IDR_TXUR I2SC_IDR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXUR_Msk instead */ 406 #define I2SC_IDR_MASK _U_(0x66) /**< \deprecated (I2SC_IDR) Register MASK (Use I2SC_IDR_Msk instead) */ 407 #define I2SC_IDR_Msk _U_(0x66) /**< (I2SC_IDR) Register Mask */ 408 409 410 /* -------- I2SC_IMR : (I2SC Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ 411 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 412 #if COMPONENT_TYPEDEF_STYLE == 'N' 413 typedef union { 414 struct { 415 uint32_t :1; /**< bit: 0 Reserved */ 416 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ 417 uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */ 418 uint32_t :2; /**< bit: 3..4 Reserved */ 419 uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */ 420 uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */ 421 uint32_t :25; /**< bit: 7..31 Reserved */ 422 } bit; /**< Structure used for bit access */ 423 uint32_t reg; /**< Type used for register access */ 424 } I2SC_IMR_Type; 425 #endif 426 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 427 428 #define I2SC_IMR_OFFSET (0x1C) /**< (I2SC_IMR) Interrupt Mask Register Offset */ 429 430 #define I2SC_IMR_RXRDY_Pos 1 /**< (I2SC_IMR) Receiver Ready Interrupt Disable Position */ 431 #define I2SC_IMR_RXRDY_Msk (_U_(0x1) << I2SC_IMR_RXRDY_Pos) /**< (I2SC_IMR) Receiver Ready Interrupt Disable Mask */ 432 #define I2SC_IMR_RXRDY I2SC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXRDY_Msk instead */ 433 #define I2SC_IMR_RXOR_Pos 2 /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Position */ 434 #define I2SC_IMR_RXOR_Msk (_U_(0x1) << I2SC_IMR_RXOR_Pos) /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Mask */ 435 #define I2SC_IMR_RXOR I2SC_IMR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXOR_Msk instead */ 436 #define I2SC_IMR_TXRDY_Pos 5 /**< (I2SC_IMR) Transmit Ready Interrupt Disable Position */ 437 #define I2SC_IMR_TXRDY_Msk (_U_(0x1) << I2SC_IMR_TXRDY_Pos) /**< (I2SC_IMR) Transmit Ready Interrupt Disable Mask */ 438 #define I2SC_IMR_TXRDY I2SC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXRDY_Msk instead */ 439 #define I2SC_IMR_TXUR_Pos 6 /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Position */ 440 #define I2SC_IMR_TXUR_Msk (_U_(0x1) << I2SC_IMR_TXUR_Pos) /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Mask */ 441 #define I2SC_IMR_TXUR I2SC_IMR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXUR_Msk instead */ 442 #define I2SC_IMR_MASK _U_(0x66) /**< \deprecated (I2SC_IMR) Register MASK (Use I2SC_IMR_Msk instead) */ 443 #define I2SC_IMR_Msk _U_(0x66) /**< (I2SC_IMR) Register Mask */ 444 445 446 /* -------- I2SC_RHR : (I2SC Offset: 0x20) (R/ 32) Receiver Holding Register -------- */ 447 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 448 #if COMPONENT_TYPEDEF_STYLE == 'N' 449 typedef union { 450 struct { 451 uint32_t RHR:32; /**< bit: 0..31 Receiver Holding Register */ 452 } bit; /**< Structure used for bit access */ 453 uint32_t reg; /**< Type used for register access */ 454 } I2SC_RHR_Type; 455 #endif 456 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 457 458 #define I2SC_RHR_OFFSET (0x20) /**< (I2SC_RHR) Receiver Holding Register Offset */ 459 460 #define I2SC_RHR_RHR_Pos 0 /**< (I2SC_RHR) Receiver Holding Register Position */ 461 #define I2SC_RHR_RHR_Msk (_U_(0xFFFFFFFF) << I2SC_RHR_RHR_Pos) /**< (I2SC_RHR) Receiver Holding Register Mask */ 462 #define I2SC_RHR_RHR(value) (I2SC_RHR_RHR_Msk & ((value) << I2SC_RHR_RHR_Pos)) 463 #define I2SC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_RHR) Register MASK (Use I2SC_RHR_Msk instead) */ 464 #define I2SC_RHR_Msk _U_(0xFFFFFFFF) /**< (I2SC_RHR) Register Mask */ 465 466 467 /* -------- I2SC_THR : (I2SC Offset: 0x24) (/W 32) Transmitter Holding Register -------- */ 468 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 469 #if COMPONENT_TYPEDEF_STYLE == 'N' 470 typedef union { 471 struct { 472 uint32_t THR:32; /**< bit: 0..31 Transmitter Holding Register */ 473 } bit; /**< Structure used for bit access */ 474 uint32_t reg; /**< Type used for register access */ 475 } I2SC_THR_Type; 476 #endif 477 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 479 #define I2SC_THR_OFFSET (0x24) /**< (I2SC_THR) Transmitter Holding Register Offset */ 480 481 #define I2SC_THR_THR_Pos 0 /**< (I2SC_THR) Transmitter Holding Register Position */ 482 #define I2SC_THR_THR_Msk (_U_(0xFFFFFFFF) << I2SC_THR_THR_Pos) /**< (I2SC_THR) Transmitter Holding Register Mask */ 483 #define I2SC_THR_THR(value) (I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)) 484 #define I2SC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_THR) Register MASK (Use I2SC_THR_Msk instead) */ 485 #define I2SC_THR_Msk _U_(0xFFFFFFFF) /**< (I2SC_THR) Register Mask */ 486 487 488 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 489 #if COMPONENT_TYPEDEF_STYLE == 'R' 490 /** \brief I2SC hardware registers */ 491 typedef struct { 492 __O uint32_t I2SC_CR; /**< (I2SC Offset: 0x00) Control Register */ 493 __IO uint32_t I2SC_MR; /**< (I2SC Offset: 0x04) Mode Register */ 494 __I uint32_t I2SC_SR; /**< (I2SC Offset: 0x08) Status Register */ 495 __O uint32_t I2SC_SCR; /**< (I2SC Offset: 0x0C) Status Clear Register */ 496 __O uint32_t I2SC_SSR; /**< (I2SC Offset: 0x10) Status Set Register */ 497 __O uint32_t I2SC_IER; /**< (I2SC Offset: 0x14) Interrupt Enable Register */ 498 __O uint32_t I2SC_IDR; /**< (I2SC Offset: 0x18) Interrupt Disable Register */ 499 __I uint32_t I2SC_IMR; /**< (I2SC Offset: 0x1C) Interrupt Mask Register */ 500 __I uint32_t I2SC_RHR; /**< (I2SC Offset: 0x20) Receiver Holding Register */ 501 __O uint32_t I2SC_THR; /**< (I2SC Offset: 0x24) Transmitter Holding Register */ 502 } I2sc; 503 504 #elif COMPONENT_TYPEDEF_STYLE == 'N' 505 /** \brief I2SC hardware registers */ 506 typedef struct { 507 __O I2SC_CR_Type I2SC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 508 __IO I2SC_MR_Type I2SC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 509 __I I2SC_SR_Type I2SC_SR; /**< Offset: 0x08 (R/ 32) Status Register */ 510 __O I2SC_SCR_Type I2SC_SCR; /**< Offset: 0x0C ( /W 32) Status Clear Register */ 511 __O I2SC_SSR_Type I2SC_SSR; /**< Offset: 0x10 ( /W 32) Status Set Register */ 512 __O I2SC_IER_Type I2SC_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ 513 __O I2SC_IDR_Type I2SC_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ 514 __I I2SC_IMR_Type I2SC_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ 515 __I I2SC_RHR_Type I2SC_RHR; /**< Offset: 0x20 (R/ 32) Receiver Holding Register */ 516 __O I2SC_THR_Type I2SC_THR; /**< Offset: 0x24 ( /W 32) Transmitter Holding Register */ 517 } I2sc; 518 519 #else /* COMPONENT_TYPEDEF_STYLE */ 520 #error Unknown component typedef style 521 #endif /* COMPONENT_TYPEDEF_STYLE */ 522 523 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 /** @} end of Inter-IC Sound Controller */ 525 526 #endif /* _SAMV71_I2SC_COMPONENT_H_ */ 527
