1 /** 2 * \file 3 * 4 * \brief Component description for AES 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_AES_COMPONENT_H_ 32 #define _SAMV71_AES_COMPONENT_H_ 33 #define _SAMV71_AES_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Advanced Encryption Standard 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR AES */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define AES_6149 /**< (AES) Module ID */ 46 #define REV_AES W /**< (AES) Module revision */ 47 48 /* -------- AES_CR : (AES Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t START:1; /**< bit: 0 Start Processing */ 54 uint32_t :7; /**< bit: 1..7 Reserved */ 55 uint32_t SWRST:1; /**< bit: 8 Software Reset */ 56 uint32_t :7; /**< bit: 9..15 Reserved */ 57 uint32_t LOADSEED:1; /**< bit: 16 Random Number Generator Seed Loading */ 58 uint32_t :15; /**< bit: 17..31 Reserved */ 59 } bit; /**< Structure used for bit access */ 60 uint32_t reg; /**< Type used for register access */ 61 } AES_CR_Type; 62 #endif 63 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define AES_CR_OFFSET (0x00) /**< (AES_CR) Control Register Offset */ 66 67 #define AES_CR_START_Pos 0 /**< (AES_CR) Start Processing Position */ 68 #define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */ 69 #define AES_CR_START AES_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_START_Msk instead */ 70 #define AES_CR_SWRST_Pos 8 /**< (AES_CR) Software Reset Position */ 71 #define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */ 72 #define AES_CR_SWRST AES_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_SWRST_Msk instead */ 73 #define AES_CR_LOADSEED_Pos 16 /**< (AES_CR) Random Number Generator Seed Loading Position */ 74 #define AES_CR_LOADSEED_Msk (_U_(0x1) << AES_CR_LOADSEED_Pos) /**< (AES_CR) Random Number Generator Seed Loading Mask */ 75 #define AES_CR_LOADSEED AES_CR_LOADSEED_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_LOADSEED_Msk instead */ 76 #define AES_CR_MASK _U_(0x10101) /**< \deprecated (AES_CR) Register MASK (Use AES_CR_Msk instead) */ 77 #define AES_CR_Msk _U_(0x10101) /**< (AES_CR) Register Mask */ 78 79 80 /* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */ 81 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 82 #if COMPONENT_TYPEDEF_STYLE == 'N' 83 typedef union { 84 struct { 85 uint32_t CIPHER:1; /**< bit: 0 Processing Mode */ 86 uint32_t GTAGEN:1; /**< bit: 1 GCM Automatic Tag Generation Enable */ 87 uint32_t :1; /**< bit: 2 Reserved */ 88 uint32_t DUALBUFF:1; /**< bit: 3 Dual Input Buffer */ 89 uint32_t PROCDLY:4; /**< bit: 4..7 Processing Delay */ 90 uint32_t SMOD:2; /**< bit: 8..9 Start Mode */ 91 uint32_t KEYSIZE:2; /**< bit: 10..11 Key Size */ 92 uint32_t OPMOD:3; /**< bit: 12..14 Operating Mode */ 93 uint32_t LOD:1; /**< bit: 15 Last Output Data Mode */ 94 uint32_t CFBS:3; /**< bit: 16..18 Cipher Feedback Data Size */ 95 uint32_t :1; /**< bit: 19 Reserved */ 96 uint32_t CKEY:4; /**< bit: 20..23 Countermeasure Key */ 97 uint32_t :8; /**< bit: 24..31 Reserved */ 98 } bit; /**< Structure used for bit access */ 99 uint32_t reg; /**< Type used for register access */ 100 } AES_MR_Type; 101 #endif 102 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define AES_MR_OFFSET (0x04) /**< (AES_MR) Mode Register Offset */ 105 106 #define AES_MR_CIPHER_Pos 0 /**< (AES_MR) Processing Mode Position */ 107 #define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */ 108 #define AES_MR_CIPHER AES_MR_CIPHER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CIPHER_Msk instead */ 109 #define AES_MR_GTAGEN_Pos 1 /**< (AES_MR) GCM Automatic Tag Generation Enable Position */ 110 #define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */ 111 #define AES_MR_GTAGEN AES_MR_GTAGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_GTAGEN_Msk instead */ 112 #define AES_MR_DUALBUFF_Pos 3 /**< (AES_MR) Dual Input Buffer Position */ 113 #define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */ 114 #define AES_MR_DUALBUFF AES_MR_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_DUALBUFF_Msk instead */ 115 #define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ 116 #define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ 117 #define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */ 118 #define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */ 119 #define AES_MR_PROCDLY_Pos 4 /**< (AES_MR) Processing Delay Position */ 120 #define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */ 121 #define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)) 122 #define AES_MR_SMOD_Pos 8 /**< (AES_MR) Start Mode Position */ 123 #define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */ 124 #define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)) 125 #define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */ 126 #define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */ 127 #define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ 128 #define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */ 129 #define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */ 130 #define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */ 131 #define AES_MR_KEYSIZE_Pos 10 /**< (AES_MR) Key Size Position */ 132 #define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */ 133 #define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)) 134 #define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */ 135 #define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */ 136 #define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */ 137 #define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */ 138 #define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */ 139 #define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */ 140 #define AES_MR_OPMOD_Pos 12 /**< (AES_MR) Operating Mode Position */ 141 #define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */ 142 #define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)) 143 #define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */ 144 #define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */ 145 #define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */ 146 #define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */ 147 #define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */ 148 #define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */ 149 #define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */ 150 #define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */ 151 #define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */ 152 #define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */ 153 #define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */ 154 #define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */ 155 #define AES_MR_LOD_Pos 15 /**< (AES_MR) Last Output Data Mode Position */ 156 #define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */ 157 #define AES_MR_LOD AES_MR_LOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_LOD_Msk instead */ 158 #define AES_MR_CFBS_Pos 16 /**< (AES_MR) Cipher Feedback Data Size Position */ 159 #define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */ 160 #define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)) 161 #define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */ 162 #define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */ 163 #define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */ 164 #define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */ 165 #define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */ 166 #define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */ 167 #define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */ 168 #define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */ 169 #define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */ 170 #define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */ 171 #define AES_MR_CKEY_Pos 20 /**< (AES_MR) Countermeasure Key Position */ 172 #define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */ 173 #define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)) 174 #define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ 175 #define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */ 176 #define AES_MR_MASK _U_(0xF7FFFB) /**< \deprecated (AES_MR) Register MASK (Use AES_MR_Msk instead) */ 177 #define AES_MR_Msk _U_(0xF7FFFB) /**< (AES_MR) Register Mask */ 178 179 180 /* -------- AES_IER : (AES Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ 181 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 182 #if COMPONENT_TYPEDEF_STYLE == 'N' 183 typedef union { 184 struct { 185 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */ 186 uint32_t :7; /**< bit: 1..7 Reserved */ 187 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Enable */ 188 uint32_t :7; /**< bit: 9..15 Reserved */ 189 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Enable */ 190 uint32_t :15; /**< bit: 17..31 Reserved */ 191 } bit; /**< Structure used for bit access */ 192 uint32_t reg; /**< Type used for register access */ 193 } AES_IER_Type; 194 #endif 195 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 196 197 #define AES_IER_OFFSET (0x10) /**< (AES_IER) Interrupt Enable Register Offset */ 198 199 #define AES_IER_DATRDY_Pos 0 /**< (AES_IER) Data Ready Interrupt Enable Position */ 200 #define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */ 201 #define AES_IER_DATRDY AES_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_DATRDY_Msk instead */ 202 #define AES_IER_URAD_Pos 8 /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */ 203 #define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */ 204 #define AES_IER_URAD AES_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_URAD_Msk instead */ 205 #define AES_IER_TAGRDY_Pos 16 /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */ 206 #define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */ 207 #define AES_IER_TAGRDY AES_IER_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_TAGRDY_Msk instead */ 208 #define AES_IER_MASK _U_(0x10101) /**< \deprecated (AES_IER) Register MASK (Use AES_IER_Msk instead) */ 209 #define AES_IER_Msk _U_(0x10101) /**< (AES_IER) Register Mask */ 210 211 212 /* -------- AES_IDR : (AES Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ 213 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 214 #if COMPONENT_TYPEDEF_STYLE == 'N' 215 typedef union { 216 struct { 217 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */ 218 uint32_t :7; /**< bit: 1..7 Reserved */ 219 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Disable */ 220 uint32_t :7; /**< bit: 9..15 Reserved */ 221 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Disable */ 222 uint32_t :15; /**< bit: 17..31 Reserved */ 223 } bit; /**< Structure used for bit access */ 224 uint32_t reg; /**< Type used for register access */ 225 } AES_IDR_Type; 226 #endif 227 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 228 229 #define AES_IDR_OFFSET (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */ 230 231 #define AES_IDR_DATRDY_Pos 0 /**< (AES_IDR) Data Ready Interrupt Disable Position */ 232 #define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */ 233 #define AES_IDR_DATRDY AES_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_DATRDY_Msk instead */ 234 #define AES_IDR_URAD_Pos 8 /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */ 235 #define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */ 236 #define AES_IDR_URAD AES_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_URAD_Msk instead */ 237 #define AES_IDR_TAGRDY_Pos 16 /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */ 238 #define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */ 239 #define AES_IDR_TAGRDY AES_IDR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_TAGRDY_Msk instead */ 240 #define AES_IDR_MASK _U_(0x10101) /**< \deprecated (AES_IDR) Register MASK (Use AES_IDR_Msk instead) */ 241 #define AES_IDR_Msk _U_(0x10101) /**< (AES_IDR) Register Mask */ 242 243 244 /* -------- AES_IMR : (AES Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 245 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 246 #if COMPONENT_TYPEDEF_STYLE == 'N' 247 typedef union { 248 struct { 249 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */ 250 uint32_t :7; /**< bit: 1..7 Reserved */ 251 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Mask */ 252 uint32_t :7; /**< bit: 9..15 Reserved */ 253 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Mask */ 254 uint32_t :15; /**< bit: 17..31 Reserved */ 255 } bit; /**< Structure used for bit access */ 256 uint32_t reg; /**< Type used for register access */ 257 } AES_IMR_Type; 258 #endif 259 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define AES_IMR_OFFSET (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */ 262 263 #define AES_IMR_DATRDY_Pos 0 /**< (AES_IMR) Data Ready Interrupt Mask Position */ 264 #define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */ 265 #define AES_IMR_DATRDY AES_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_DATRDY_Msk instead */ 266 #define AES_IMR_URAD_Pos 8 /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */ 267 #define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */ 268 #define AES_IMR_URAD AES_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_URAD_Msk instead */ 269 #define AES_IMR_TAGRDY_Pos 16 /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */ 270 #define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */ 271 #define AES_IMR_TAGRDY AES_IMR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_TAGRDY_Msk instead */ 272 #define AES_IMR_MASK _U_(0x10101) /**< \deprecated (AES_IMR) Register MASK (Use AES_IMR_Msk instead) */ 273 #define AES_IMR_Msk _U_(0x10101) /**< (AES_IMR) Register Mask */ 274 275 276 /* -------- AES_ISR : (AES Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ 277 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 278 #if COMPONENT_TYPEDEF_STYLE == 'N' 279 typedef union { 280 struct { 281 uint32_t DATRDY:1; /**< bit: 0 Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ 282 uint32_t :7; /**< bit: 1..7 Reserved */ 283 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ 284 uint32_t :3; /**< bit: 9..11 Reserved */ 285 uint32_t URAT:4; /**< bit: 12..15 Unspecified Register Access (cleared by writing SWRST in AES_CR) */ 286 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready */ 287 uint32_t :15; /**< bit: 17..31 Reserved */ 288 } bit; /**< Structure used for bit access */ 289 uint32_t reg; /**< Type used for register access */ 290 } AES_ISR_Type; 291 #endif 292 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 293 294 #define AES_ISR_OFFSET (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */ 295 296 #define AES_ISR_DATRDY_Pos 0 /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */ 297 #define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */ 298 #define AES_ISR_DATRDY AES_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_DATRDY_Msk instead */ 299 #define AES_ISR_URAD_Pos 8 /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */ 300 #define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */ 301 #define AES_ISR_URAD AES_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_URAD_Msk instead */ 302 #define AES_ISR_URAT_Pos 12 /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */ 303 #define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */ 304 #define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos)) 305 #define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ 306 #define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */ 307 #define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */ 308 #define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */ 309 #define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */ 310 #define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */ 311 #define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */ 312 #define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */ 313 #define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */ 314 #define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */ 315 #define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */ 316 #define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */ 317 #define AES_ISR_TAGRDY_Pos 16 /**< (AES_ISR) GCM Tag Ready Position */ 318 #define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */ 319 #define AES_ISR_TAGRDY AES_ISR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_TAGRDY_Msk instead */ 320 #define AES_ISR_MASK _U_(0x1F101) /**< \deprecated (AES_ISR) Register MASK (Use AES_ISR_Msk instead) */ 321 #define AES_ISR_Msk _U_(0x1F101) /**< (AES_ISR) Register Mask */ 322 323 324 /* -------- AES_KEYWR : (AES Offset: 0x20) (/W 32) Key Word Register -------- */ 325 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 326 #if COMPONENT_TYPEDEF_STYLE == 'N' 327 typedef union { 328 struct { 329 uint32_t KEYW:32; /**< bit: 0..31 Key Word */ 330 } bit; /**< Structure used for bit access */ 331 uint32_t reg; /**< Type used for register access */ 332 } AES_KEYWR_Type; 333 #endif 334 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 335 336 #define AES_KEYWR_OFFSET (0x20) /**< (AES_KEYWR) Key Word Register Offset */ 337 338 #define AES_KEYWR_KEYW_Pos 0 /**< (AES_KEYWR) Key Word Position */ 339 #define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */ 340 #define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)) 341 #define AES_KEYWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_KEYWR) Register MASK (Use AES_KEYWR_Msk instead) */ 342 #define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */ 343 344 345 /* -------- AES_IDATAR : (AES Offset: 0x40) (/W 32) Input Data Register -------- */ 346 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 347 #if COMPONENT_TYPEDEF_STYLE == 'N' 348 typedef union { 349 struct { 350 uint32_t IDATA:32; /**< bit: 0..31 Input Data Word */ 351 } bit; /**< Structure used for bit access */ 352 uint32_t reg; /**< Type used for register access */ 353 } AES_IDATAR_Type; 354 #endif 355 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 356 357 #define AES_IDATAR_OFFSET (0x40) /**< (AES_IDATAR) Input Data Register Offset */ 358 359 #define AES_IDATAR_IDATA_Pos 0 /**< (AES_IDATAR) Input Data Word Position */ 360 #define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */ 361 #define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)) 362 #define AES_IDATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IDATAR) Register MASK (Use AES_IDATAR_Msk instead) */ 363 #define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */ 364 365 366 /* -------- AES_ODATAR : (AES Offset: 0x50) (R/ 32) Output Data Register -------- */ 367 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 368 #if COMPONENT_TYPEDEF_STYLE == 'N' 369 typedef union { 370 struct { 371 uint32_t ODATA:32; /**< bit: 0..31 Output Data */ 372 } bit; /**< Structure used for bit access */ 373 uint32_t reg; /**< Type used for register access */ 374 } AES_ODATAR_Type; 375 #endif 376 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 #define AES_ODATAR_OFFSET (0x50) /**< (AES_ODATAR) Output Data Register Offset */ 379 380 #define AES_ODATAR_ODATA_Pos 0 /**< (AES_ODATAR) Output Data Position */ 381 #define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */ 382 #define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos)) 383 #define AES_ODATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_ODATAR) Register MASK (Use AES_ODATAR_Msk instead) */ 384 #define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */ 385 386 387 /* -------- AES_IVR : (AES Offset: 0x60) (/W 32) Initialization Vector Register -------- */ 388 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 389 #if COMPONENT_TYPEDEF_STYLE == 'N' 390 typedef union { 391 struct { 392 uint32_t IV:32; /**< bit: 0..31 Initialization Vector */ 393 } bit; /**< Structure used for bit access */ 394 uint32_t reg; /**< Type used for register access */ 395 } AES_IVR_Type; 396 #endif 397 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 398 399 #define AES_IVR_OFFSET (0x60) /**< (AES_IVR) Initialization Vector Register Offset */ 400 401 #define AES_IVR_IV_Pos 0 /**< (AES_IVR) Initialization Vector Position */ 402 #define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */ 403 #define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)) 404 #define AES_IVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IVR) Register MASK (Use AES_IVR_Msk instead) */ 405 #define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */ 406 407 408 /* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */ 409 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 410 #if COMPONENT_TYPEDEF_STYLE == 'N' 411 typedef union { 412 struct { 413 uint32_t AADLEN:32; /**< bit: 0..31 Additional Authenticated Data Length */ 414 } bit; /**< Structure used for bit access */ 415 uint32_t reg; /**< Type used for register access */ 416 } AES_AADLENR_Type; 417 #endif 418 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 419 420 #define AES_AADLENR_OFFSET (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */ 421 422 #define AES_AADLENR_AADLEN_Pos 0 /**< (AES_AADLENR) Additional Authenticated Data Length Position */ 423 #define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */ 424 #define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)) 425 #define AES_AADLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_AADLENR) Register MASK (Use AES_AADLENR_Msk instead) */ 426 #define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */ 427 428 429 /* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */ 430 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 431 #if COMPONENT_TYPEDEF_STYLE == 'N' 432 typedef union { 433 struct { 434 uint32_t CLEN:32; /**< bit: 0..31 Plaintext/Ciphertext Length */ 435 } bit; /**< Structure used for bit access */ 436 uint32_t reg; /**< Type used for register access */ 437 } AES_CLENR_Type; 438 #endif 439 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 440 441 #define AES_CLENR_OFFSET (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */ 442 443 #define AES_CLENR_CLEN_Pos 0 /**< (AES_CLENR) Plaintext/Ciphertext Length Position */ 444 #define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */ 445 #define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)) 446 #define AES_CLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CLENR) Register MASK (Use AES_CLENR_Msk instead) */ 447 #define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */ 448 449 450 /* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register -------- */ 451 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 452 #if COMPONENT_TYPEDEF_STYLE == 'N' 453 typedef union { 454 struct { 455 uint32_t GHASH:32; /**< bit: 0..31 Intermediate GCM Hash Word x */ 456 } bit; /**< Structure used for bit access */ 457 uint32_t reg; /**< Type used for register access */ 458 } AES_GHASHR_Type; 459 #endif 460 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define AES_GHASHR_OFFSET (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register Offset */ 463 464 #define AES_GHASHR_GHASH_Pos 0 /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */ 465 #define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */ 466 #define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)) 467 #define AES_GHASHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GHASHR) Register MASK (Use AES_GHASHR_Msk instead) */ 468 #define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */ 469 470 471 /* -------- AES_TAGR : (AES Offset: 0x88) (R/ 32) GCM Authentication Tag Word Register -------- */ 472 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 473 #if COMPONENT_TYPEDEF_STYLE == 'N' 474 typedef union { 475 struct { 476 uint32_t TAG:32; /**< bit: 0..31 GCM Authentication Tag x */ 477 } bit; /**< Structure used for bit access */ 478 uint32_t reg; /**< Type used for register access */ 479 } AES_TAGR_Type; 480 #endif 481 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 482 483 #define AES_TAGR_OFFSET (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register Offset */ 484 485 #define AES_TAGR_TAG_Pos 0 /**< (AES_TAGR) GCM Authentication Tag x Position */ 486 #define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */ 487 #define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos)) 488 #define AES_TAGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_TAGR) Register MASK (Use AES_TAGR_Msk instead) */ 489 #define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */ 490 491 492 /* -------- AES_CTRR : (AES Offset: 0x98) (R/ 32) GCM Encryption Counter Value Register -------- */ 493 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 494 #if COMPONENT_TYPEDEF_STYLE == 'N' 495 typedef union { 496 struct { 497 uint32_t CTR:32; /**< bit: 0..31 GCM Encryption Counter */ 498 } bit; /**< Structure used for bit access */ 499 uint32_t reg; /**< Type used for register access */ 500 } AES_CTRR_Type; 501 #endif 502 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 503 504 #define AES_CTRR_OFFSET (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */ 505 506 #define AES_CTRR_CTR_Pos 0 /**< (AES_CTRR) GCM Encryption Counter Position */ 507 #define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */ 508 #define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos)) 509 #define AES_CTRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CTRR) Register MASK (Use AES_CTRR_Msk instead) */ 510 #define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */ 511 512 513 /* -------- AES_GCMHR : (AES Offset: 0x9c) (R/W 32) GCM H Word Register -------- */ 514 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 515 #if COMPONENT_TYPEDEF_STYLE == 'N' 516 typedef union { 517 struct { 518 uint32_t H:32; /**< bit: 0..31 GCM H Word x */ 519 } bit; /**< Structure used for bit access */ 520 uint32_t reg; /**< Type used for register access */ 521 } AES_GCMHR_Type; 522 #endif 523 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 525 #define AES_GCMHR_OFFSET (0x9C) /**< (AES_GCMHR) GCM H Word Register Offset */ 526 527 #define AES_GCMHR_H_Pos 0 /**< (AES_GCMHR) GCM H Word x Position */ 528 #define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */ 529 #define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)) 530 #define AES_GCMHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GCMHR) Register MASK (Use AES_GCMHR_Msk instead) */ 531 #define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */ 532 533 534 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 535 #if COMPONENT_TYPEDEF_STYLE == 'R' 536 /** \brief AES hardware registers */ 537 typedef struct { 538 __O uint32_t AES_CR; /**< (AES Offset: 0x00) Control Register */ 539 __IO uint32_t AES_MR; /**< (AES Offset: 0x04) Mode Register */ 540 __I uint8_t Reserved1[8]; 541 __O uint32_t AES_IER; /**< (AES Offset: 0x10) Interrupt Enable Register */ 542 __O uint32_t AES_IDR; /**< (AES Offset: 0x14) Interrupt Disable Register */ 543 __I uint32_t AES_IMR; /**< (AES Offset: 0x18) Interrupt Mask Register */ 544 __I uint32_t AES_ISR; /**< (AES Offset: 0x1C) Interrupt Status Register */ 545 __O uint32_t AES_KEYWR[8]; /**< (AES Offset: 0x20) Key Word Register */ 546 __O uint32_t AES_IDATAR[4]; /**< (AES Offset: 0x40) Input Data Register */ 547 __I uint32_t AES_ODATAR[4]; /**< (AES Offset: 0x50) Output Data Register */ 548 __O uint32_t AES_IVR[4]; /**< (AES Offset: 0x60) Initialization Vector Register */ 549 __IO uint32_t AES_AADLENR; /**< (AES Offset: 0x70) Additional Authenticated Data Length Register */ 550 __IO uint32_t AES_CLENR; /**< (AES Offset: 0x74) Plaintext/Ciphertext Length Register */ 551 __IO uint32_t AES_GHASHR[4]; /**< (AES Offset: 0x78) GCM Intermediate Hash Word Register */ 552 __I uint32_t AES_TAGR[4]; /**< (AES Offset: 0x88) GCM Authentication Tag Word Register */ 553 __I uint32_t AES_CTRR; /**< (AES Offset: 0x98) GCM Encryption Counter Value Register */ 554 __IO uint32_t AES_GCMHR[4]; /**< (AES Offset: 0x9C) GCM H Word Register */ 555 } Aes; 556 557 #elif COMPONENT_TYPEDEF_STYLE == 'N' 558 /** \brief AES hardware registers */ 559 typedef struct { 560 __O AES_CR_Type AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 561 __IO AES_MR_Type AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 562 __I uint8_t Reserved1[8]; 563 __O AES_IER_Type AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ 564 __O AES_IDR_Type AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ 565 __I AES_IMR_Type AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ 566 __I AES_ISR_Type AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ 567 __O AES_KEYWR_Type AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register */ 568 __O AES_IDATAR_Type AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register */ 569 __I AES_ODATAR_Type AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register */ 570 __O AES_IVR_Type AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register */ 571 __IO AES_AADLENR_Type AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */ 572 __IO AES_CLENR_Type AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */ 573 __IO AES_GHASHR_Type AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register */ 574 __I AES_TAGR_Type AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register */ 575 __I AES_CTRR_Type AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */ 576 __IO AES_GCMHR_Type AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register */ 577 } Aes; 578 579 #else /* COMPONENT_TYPEDEF_STYLE */ 580 #error Unknown component typedef style 581 #endif /* COMPONENT_TYPEDEF_STYLE */ 582 583 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 584 /** @} end of Advanced Encryption Standard */ 585 586 #endif /* _SAMV71_AES_COMPONENT_H_ */ 587
