1 /** 2 * \file 3 * 4 * \brief Instance description for USBHS 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_USBHS_INSTANCE_H_ 32 #define _SAMV71_USBHS_INSTANCE_H_ 33 34 /* ========== Register definition for USBHS peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_USBHS_DEVDMANXTDSC0 (0x40038310) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 0 */ 38 #define REG_USBHS_DEVDMAADDRESS0 (0x40038314) /**< (USBHS) Device DMA Channel Address Register (n = 1) 0 */ 39 #define REG_USBHS_DEVDMACONTROL0 (0x40038318) /**< (USBHS) Device DMA Channel Control Register (n = 1) 0 */ 40 #define REG_USBHS_DEVDMASTATUS0 (0x4003831C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 0 */ 41 #define REG_USBHS_DEVDMANXTDSC1 (0x40038320) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 1 */ 42 #define REG_USBHS_DEVDMAADDRESS1 (0x40038324) /**< (USBHS) Device DMA Channel Address Register (n = 1) 1 */ 43 #define REG_USBHS_DEVDMACONTROL1 (0x40038328) /**< (USBHS) Device DMA Channel Control Register (n = 1) 1 */ 44 #define REG_USBHS_DEVDMASTATUS1 (0x4003832C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 1 */ 45 #define REG_USBHS_DEVDMANXTDSC2 (0x40038330) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 2 */ 46 #define REG_USBHS_DEVDMAADDRESS2 (0x40038334) /**< (USBHS) Device DMA Channel Address Register (n = 1) 2 */ 47 #define REG_USBHS_DEVDMACONTROL2 (0x40038338) /**< (USBHS) Device DMA Channel Control Register (n = 1) 2 */ 48 #define REG_USBHS_DEVDMASTATUS2 (0x4003833C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 2 */ 49 #define REG_USBHS_DEVDMANXTDSC3 (0x40038340) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 3 */ 50 #define REG_USBHS_DEVDMAADDRESS3 (0x40038344) /**< (USBHS) Device DMA Channel Address Register (n = 1) 3 */ 51 #define REG_USBHS_DEVDMACONTROL3 (0x40038348) /**< (USBHS) Device DMA Channel Control Register (n = 1) 3 */ 52 #define REG_USBHS_DEVDMASTATUS3 (0x4003834C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 3 */ 53 #define REG_USBHS_DEVDMANXTDSC4 (0x40038350) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 4 */ 54 #define REG_USBHS_DEVDMAADDRESS4 (0x40038354) /**< (USBHS) Device DMA Channel Address Register (n = 1) 4 */ 55 #define REG_USBHS_DEVDMACONTROL4 (0x40038358) /**< (USBHS) Device DMA Channel Control Register (n = 1) 4 */ 56 #define REG_USBHS_DEVDMASTATUS4 (0x4003835C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 4 */ 57 #define REG_USBHS_DEVDMANXTDSC5 (0x40038360) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 5 */ 58 #define REG_USBHS_DEVDMAADDRESS5 (0x40038364) /**< (USBHS) Device DMA Channel Address Register (n = 1) 5 */ 59 #define REG_USBHS_DEVDMACONTROL5 (0x40038368) /**< (USBHS) Device DMA Channel Control Register (n = 1) 5 */ 60 #define REG_USBHS_DEVDMASTATUS5 (0x4003836C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 5 */ 61 #define REG_USBHS_DEVDMANXTDSC6 (0x40038370) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 6 */ 62 #define REG_USBHS_DEVDMAADDRESS6 (0x40038374) /**< (USBHS) Device DMA Channel Address Register (n = 1) 6 */ 63 #define REG_USBHS_DEVDMACONTROL6 (0x40038378) /**< (USBHS) Device DMA Channel Control Register (n = 1) 6 */ 64 #define REG_USBHS_DEVDMASTATUS6 (0x4003837C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 6 */ 65 #define REG_USBHS_HSTDMANXTDSC0 (0x40038710) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 0 */ 66 #define REG_USBHS_HSTDMAADDRESS0 (0x40038714) /**< (USBHS) Host DMA Channel Address Register (n = 1) 0 */ 67 #define REG_USBHS_HSTDMACONTROL0 (0x40038718) /**< (USBHS) Host DMA Channel Control Register (n = 1) 0 */ 68 #define REG_USBHS_HSTDMASTATUS0 (0x4003871C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 0 */ 69 #define REG_USBHS_HSTDMANXTDSC1 (0x40038720) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 1 */ 70 #define REG_USBHS_HSTDMAADDRESS1 (0x40038724) /**< (USBHS) Host DMA Channel Address Register (n = 1) 1 */ 71 #define REG_USBHS_HSTDMACONTROL1 (0x40038728) /**< (USBHS) Host DMA Channel Control Register (n = 1) 1 */ 72 #define REG_USBHS_HSTDMASTATUS1 (0x4003872C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 1 */ 73 #define REG_USBHS_HSTDMANXTDSC2 (0x40038730) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 2 */ 74 #define REG_USBHS_HSTDMAADDRESS2 (0x40038734) /**< (USBHS) Host DMA Channel Address Register (n = 1) 2 */ 75 #define REG_USBHS_HSTDMACONTROL2 (0x40038738) /**< (USBHS) Host DMA Channel Control Register (n = 1) 2 */ 76 #define REG_USBHS_HSTDMASTATUS2 (0x4003873C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 2 */ 77 #define REG_USBHS_HSTDMANXTDSC3 (0x40038740) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 3 */ 78 #define REG_USBHS_HSTDMAADDRESS3 (0x40038744) /**< (USBHS) Host DMA Channel Address Register (n = 1) 3 */ 79 #define REG_USBHS_HSTDMACONTROL3 (0x40038748) /**< (USBHS) Host DMA Channel Control Register (n = 1) 3 */ 80 #define REG_USBHS_HSTDMASTATUS3 (0x4003874C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 3 */ 81 #define REG_USBHS_HSTDMANXTDSC4 (0x40038750) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 4 */ 82 #define REG_USBHS_HSTDMAADDRESS4 (0x40038754) /**< (USBHS) Host DMA Channel Address Register (n = 1) 4 */ 83 #define REG_USBHS_HSTDMACONTROL4 (0x40038758) /**< (USBHS) Host DMA Channel Control Register (n = 1) 4 */ 84 #define REG_USBHS_HSTDMASTATUS4 (0x4003875C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 4 */ 85 #define REG_USBHS_HSTDMANXTDSC5 (0x40038760) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 5 */ 86 #define REG_USBHS_HSTDMAADDRESS5 (0x40038764) /**< (USBHS) Host DMA Channel Address Register (n = 1) 5 */ 87 #define REG_USBHS_HSTDMACONTROL5 (0x40038768) /**< (USBHS) Host DMA Channel Control Register (n = 1) 5 */ 88 #define REG_USBHS_HSTDMASTATUS5 (0x4003876C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 5 */ 89 #define REG_USBHS_HSTDMANXTDSC6 (0x40038770) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 6 */ 90 #define REG_USBHS_HSTDMAADDRESS6 (0x40038774) /**< (USBHS) Host DMA Channel Address Register (n = 1) 6 */ 91 #define REG_USBHS_HSTDMACONTROL6 (0x40038778) /**< (USBHS) Host DMA Channel Control Register (n = 1) 6 */ 92 #define REG_USBHS_HSTDMASTATUS6 (0x4003877C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 6 */ 93 #define REG_USBHS_DEVCTRL (0x40038000) /**< (USBHS) Device General Control Register */ 94 #define REG_USBHS_DEVISR (0x40038004) /**< (USBHS) Device Global Interrupt Status Register */ 95 #define REG_USBHS_DEVICR (0x40038008) /**< (USBHS) Device Global Interrupt Clear Register */ 96 #define REG_USBHS_DEVIFR (0x4003800C) /**< (USBHS) Device Global Interrupt Set Register */ 97 #define REG_USBHS_DEVIMR (0x40038010) /**< (USBHS) Device Global Interrupt Mask Register */ 98 #define REG_USBHS_DEVIDR (0x40038014) /**< (USBHS) Device Global Interrupt Disable Register */ 99 #define REG_USBHS_DEVIER (0x40038018) /**< (USBHS) Device Global Interrupt Enable Register */ 100 #define REG_USBHS_DEVEPT (0x4003801C) /**< (USBHS) Device Endpoint Register */ 101 #define REG_USBHS_DEVFNUM (0x40038020) /**< (USBHS) Device Frame Number Register */ 102 #define REG_USBHS_DEVEPTCFG (0x40038100) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */ 103 #define REG_USBHS_DEVEPTCFG0 (0x40038100) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */ 104 #define REG_USBHS_DEVEPTCFG1 (0x40038104) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 1 */ 105 #define REG_USBHS_DEVEPTCFG2 (0x40038108) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 2 */ 106 #define REG_USBHS_DEVEPTCFG3 (0x4003810C) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 3 */ 107 #define REG_USBHS_DEVEPTCFG4 (0x40038110) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 4 */ 108 #define REG_USBHS_DEVEPTCFG5 (0x40038114) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 5 */ 109 #define REG_USBHS_DEVEPTCFG6 (0x40038118) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 6 */ 110 #define REG_USBHS_DEVEPTCFG7 (0x4003811C) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 7 */ 111 #define REG_USBHS_DEVEPTCFG8 (0x40038120) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 8 */ 112 #define REG_USBHS_DEVEPTCFG9 (0x40038124) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 9 */ 113 #define REG_USBHS_DEVEPTISR (0x40038130) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */ 114 #define REG_USBHS_DEVEPTISR0 (0x40038130) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */ 115 #define REG_USBHS_DEVEPTISR1 (0x40038134) /**< (USBHS) Device Endpoint Status Register (n = 0) 1 */ 116 #define REG_USBHS_DEVEPTISR2 (0x40038138) /**< (USBHS) Device Endpoint Status Register (n = 0) 2 */ 117 #define REG_USBHS_DEVEPTISR3 (0x4003813C) /**< (USBHS) Device Endpoint Status Register (n = 0) 3 */ 118 #define REG_USBHS_DEVEPTISR4 (0x40038140) /**< (USBHS) Device Endpoint Status Register (n = 0) 4 */ 119 #define REG_USBHS_DEVEPTISR5 (0x40038144) /**< (USBHS) Device Endpoint Status Register (n = 0) 5 */ 120 #define REG_USBHS_DEVEPTISR6 (0x40038148) /**< (USBHS) Device Endpoint Status Register (n = 0) 6 */ 121 #define REG_USBHS_DEVEPTISR7 (0x4003814C) /**< (USBHS) Device Endpoint Status Register (n = 0) 7 */ 122 #define REG_USBHS_DEVEPTISR8 (0x40038150) /**< (USBHS) Device Endpoint Status Register (n = 0) 8 */ 123 #define REG_USBHS_DEVEPTISR9 (0x40038154) /**< (USBHS) Device Endpoint Status Register (n = 0) 9 */ 124 #define REG_USBHS_DEVEPTICR (0x40038160) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */ 125 #define REG_USBHS_DEVEPTICR0 (0x40038160) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */ 126 #define REG_USBHS_DEVEPTICR1 (0x40038164) /**< (USBHS) Device Endpoint Clear Register (n = 0) 1 */ 127 #define REG_USBHS_DEVEPTICR2 (0x40038168) /**< (USBHS) Device Endpoint Clear Register (n = 0) 2 */ 128 #define REG_USBHS_DEVEPTICR3 (0x4003816C) /**< (USBHS) Device Endpoint Clear Register (n = 0) 3 */ 129 #define REG_USBHS_DEVEPTICR4 (0x40038170) /**< (USBHS) Device Endpoint Clear Register (n = 0) 4 */ 130 #define REG_USBHS_DEVEPTICR5 (0x40038174) /**< (USBHS) Device Endpoint Clear Register (n = 0) 5 */ 131 #define REG_USBHS_DEVEPTICR6 (0x40038178) /**< (USBHS) Device Endpoint Clear Register (n = 0) 6 */ 132 #define REG_USBHS_DEVEPTICR7 (0x4003817C) /**< (USBHS) Device Endpoint Clear Register (n = 0) 7 */ 133 #define REG_USBHS_DEVEPTICR8 (0x40038180) /**< (USBHS) Device Endpoint Clear Register (n = 0) 8 */ 134 #define REG_USBHS_DEVEPTICR9 (0x40038184) /**< (USBHS) Device Endpoint Clear Register (n = 0) 9 */ 135 #define REG_USBHS_DEVEPTIFR (0x40038190) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */ 136 #define REG_USBHS_DEVEPTIFR0 (0x40038190) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */ 137 #define REG_USBHS_DEVEPTIFR1 (0x40038194) /**< (USBHS) Device Endpoint Set Register (n = 0) 1 */ 138 #define REG_USBHS_DEVEPTIFR2 (0x40038198) /**< (USBHS) Device Endpoint Set Register (n = 0) 2 */ 139 #define REG_USBHS_DEVEPTIFR3 (0x4003819C) /**< (USBHS) Device Endpoint Set Register (n = 0) 3 */ 140 #define REG_USBHS_DEVEPTIFR4 (0x400381A0) /**< (USBHS) Device Endpoint Set Register (n = 0) 4 */ 141 #define REG_USBHS_DEVEPTIFR5 (0x400381A4) /**< (USBHS) Device Endpoint Set Register (n = 0) 5 */ 142 #define REG_USBHS_DEVEPTIFR6 (0x400381A8) /**< (USBHS) Device Endpoint Set Register (n = 0) 6 */ 143 #define REG_USBHS_DEVEPTIFR7 (0x400381AC) /**< (USBHS) Device Endpoint Set Register (n = 0) 7 */ 144 #define REG_USBHS_DEVEPTIFR8 (0x400381B0) /**< (USBHS) Device Endpoint Set Register (n = 0) 8 */ 145 #define REG_USBHS_DEVEPTIFR9 (0x400381B4) /**< (USBHS) Device Endpoint Set Register (n = 0) 9 */ 146 #define REG_USBHS_DEVEPTIMR (0x400381C0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */ 147 #define REG_USBHS_DEVEPTIMR0 (0x400381C0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */ 148 #define REG_USBHS_DEVEPTIMR1 (0x400381C4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 1 */ 149 #define REG_USBHS_DEVEPTIMR2 (0x400381C8) /**< (USBHS) Device Endpoint Mask Register (n = 0) 2 */ 150 #define REG_USBHS_DEVEPTIMR3 (0x400381CC) /**< (USBHS) Device Endpoint Mask Register (n = 0) 3 */ 151 #define REG_USBHS_DEVEPTIMR4 (0x400381D0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 4 */ 152 #define REG_USBHS_DEVEPTIMR5 (0x400381D4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 5 */ 153 #define REG_USBHS_DEVEPTIMR6 (0x400381D8) /**< (USBHS) Device Endpoint Mask Register (n = 0) 6 */ 154 #define REG_USBHS_DEVEPTIMR7 (0x400381DC) /**< (USBHS) Device Endpoint Mask Register (n = 0) 7 */ 155 #define REG_USBHS_DEVEPTIMR8 (0x400381E0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 8 */ 156 #define REG_USBHS_DEVEPTIMR9 (0x400381E4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 9 */ 157 #define REG_USBHS_DEVEPTIER (0x400381F0) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */ 158 #define REG_USBHS_DEVEPTIER0 (0x400381F0) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */ 159 #define REG_USBHS_DEVEPTIER1 (0x400381F4) /**< (USBHS) Device Endpoint Enable Register (n = 0) 1 */ 160 #define REG_USBHS_DEVEPTIER2 (0x400381F8) /**< (USBHS) Device Endpoint Enable Register (n = 0) 2 */ 161 #define REG_USBHS_DEVEPTIER3 (0x400381FC) /**< (USBHS) Device Endpoint Enable Register (n = 0) 3 */ 162 #define REG_USBHS_DEVEPTIER4 (0x40038200) /**< (USBHS) Device Endpoint Enable Register (n = 0) 4 */ 163 #define REG_USBHS_DEVEPTIER5 (0x40038204) /**< (USBHS) Device Endpoint Enable Register (n = 0) 5 */ 164 #define REG_USBHS_DEVEPTIER6 (0x40038208) /**< (USBHS) Device Endpoint Enable Register (n = 0) 6 */ 165 #define REG_USBHS_DEVEPTIER7 (0x4003820C) /**< (USBHS) Device Endpoint Enable Register (n = 0) 7 */ 166 #define REG_USBHS_DEVEPTIER8 (0x40038210) /**< (USBHS) Device Endpoint Enable Register (n = 0) 8 */ 167 #define REG_USBHS_DEVEPTIER9 (0x40038214) /**< (USBHS) Device Endpoint Enable Register (n = 0) 9 */ 168 #define REG_USBHS_DEVEPTIDR (0x40038220) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */ 169 #define REG_USBHS_DEVEPTIDR0 (0x40038220) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */ 170 #define REG_USBHS_DEVEPTIDR1 (0x40038224) /**< (USBHS) Device Endpoint Disable Register (n = 0) 1 */ 171 #define REG_USBHS_DEVEPTIDR2 (0x40038228) /**< (USBHS) Device Endpoint Disable Register (n = 0) 2 */ 172 #define REG_USBHS_DEVEPTIDR3 (0x4003822C) /**< (USBHS) Device Endpoint Disable Register (n = 0) 3 */ 173 #define REG_USBHS_DEVEPTIDR4 (0x40038230) /**< (USBHS) Device Endpoint Disable Register (n = 0) 4 */ 174 #define REG_USBHS_DEVEPTIDR5 (0x40038234) /**< (USBHS) Device Endpoint Disable Register (n = 0) 5 */ 175 #define REG_USBHS_DEVEPTIDR6 (0x40038238) /**< (USBHS) Device Endpoint Disable Register (n = 0) 6 */ 176 #define REG_USBHS_DEVEPTIDR7 (0x4003823C) /**< (USBHS) Device Endpoint Disable Register (n = 0) 7 */ 177 #define REG_USBHS_DEVEPTIDR8 (0x40038240) /**< (USBHS) Device Endpoint Disable Register (n = 0) 8 */ 178 #define REG_USBHS_DEVEPTIDR9 (0x40038244) /**< (USBHS) Device Endpoint Disable Register (n = 0) 9 */ 179 #define REG_USBHS_HSTCTRL (0x40038400) /**< (USBHS) Host General Control Register */ 180 #define REG_USBHS_HSTISR (0x40038404) /**< (USBHS) Host Global Interrupt Status Register */ 181 #define REG_USBHS_HSTICR (0x40038408) /**< (USBHS) Host Global Interrupt Clear Register */ 182 #define REG_USBHS_HSTIFR (0x4003840C) /**< (USBHS) Host Global Interrupt Set Register */ 183 #define REG_USBHS_HSTIMR (0x40038410) /**< (USBHS) Host Global Interrupt Mask Register */ 184 #define REG_USBHS_HSTIDR (0x40038414) /**< (USBHS) Host Global Interrupt Disable Register */ 185 #define REG_USBHS_HSTIER (0x40038418) /**< (USBHS) Host Global Interrupt Enable Register */ 186 #define REG_USBHS_HSTPIP (0x4003841C) /**< (USBHS) Host Pipe Register */ 187 #define REG_USBHS_HSTFNUM (0x40038420) /**< (USBHS) Host Frame Number Register */ 188 #define REG_USBHS_HSTADDR1 (0x40038424) /**< (USBHS) Host Address 1 Register */ 189 #define REG_USBHS_HSTADDR2 (0x40038428) /**< (USBHS) Host Address 2 Register */ 190 #define REG_USBHS_HSTADDR3 (0x4003842C) /**< (USBHS) Host Address 3 Register */ 191 #define REG_USBHS_HSTPIPCFG (0x40038500) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */ 192 #define REG_USBHS_HSTPIPCFG0 (0x40038500) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */ 193 #define REG_USBHS_HSTPIPCFG1 (0x40038504) /**< (USBHS) Host Pipe Configuration Register (n = 0) 1 */ 194 #define REG_USBHS_HSTPIPCFG2 (0x40038508) /**< (USBHS) Host Pipe Configuration Register (n = 0) 2 */ 195 #define REG_USBHS_HSTPIPCFG3 (0x4003850C) /**< (USBHS) Host Pipe Configuration Register (n = 0) 3 */ 196 #define REG_USBHS_HSTPIPCFG4 (0x40038510) /**< (USBHS) Host Pipe Configuration Register (n = 0) 4 */ 197 #define REG_USBHS_HSTPIPCFG5 (0x40038514) /**< (USBHS) Host Pipe Configuration Register (n = 0) 5 */ 198 #define REG_USBHS_HSTPIPCFG6 (0x40038518) /**< (USBHS) Host Pipe Configuration Register (n = 0) 6 */ 199 #define REG_USBHS_HSTPIPCFG7 (0x4003851C) /**< (USBHS) Host Pipe Configuration Register (n = 0) 7 */ 200 #define REG_USBHS_HSTPIPCFG8 (0x40038520) /**< (USBHS) Host Pipe Configuration Register (n = 0) 8 */ 201 #define REG_USBHS_HSTPIPCFG9 (0x40038524) /**< (USBHS) Host Pipe Configuration Register (n = 0) 9 */ 202 #define REG_USBHS_HSTPIPISR (0x40038530) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */ 203 #define REG_USBHS_HSTPIPISR0 (0x40038530) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */ 204 #define REG_USBHS_HSTPIPISR1 (0x40038534) /**< (USBHS) Host Pipe Status Register (n = 0) 1 */ 205 #define REG_USBHS_HSTPIPISR2 (0x40038538) /**< (USBHS) Host Pipe Status Register (n = 0) 2 */ 206 #define REG_USBHS_HSTPIPISR3 (0x4003853C) /**< (USBHS) Host Pipe Status Register (n = 0) 3 */ 207 #define REG_USBHS_HSTPIPISR4 (0x40038540) /**< (USBHS) Host Pipe Status Register (n = 0) 4 */ 208 #define REG_USBHS_HSTPIPISR5 (0x40038544) /**< (USBHS) Host Pipe Status Register (n = 0) 5 */ 209 #define REG_USBHS_HSTPIPISR6 (0x40038548) /**< (USBHS) Host Pipe Status Register (n = 0) 6 */ 210 #define REG_USBHS_HSTPIPISR7 (0x4003854C) /**< (USBHS) Host Pipe Status Register (n = 0) 7 */ 211 #define REG_USBHS_HSTPIPISR8 (0x40038550) /**< (USBHS) Host Pipe Status Register (n = 0) 8 */ 212 #define REG_USBHS_HSTPIPISR9 (0x40038554) /**< (USBHS) Host Pipe Status Register (n = 0) 9 */ 213 #define REG_USBHS_HSTPIPICR (0x40038560) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */ 214 #define REG_USBHS_HSTPIPICR0 (0x40038560) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */ 215 #define REG_USBHS_HSTPIPICR1 (0x40038564) /**< (USBHS) Host Pipe Clear Register (n = 0) 1 */ 216 #define REG_USBHS_HSTPIPICR2 (0x40038568) /**< (USBHS) Host Pipe Clear Register (n = 0) 2 */ 217 #define REG_USBHS_HSTPIPICR3 (0x4003856C) /**< (USBHS) Host Pipe Clear Register (n = 0) 3 */ 218 #define REG_USBHS_HSTPIPICR4 (0x40038570) /**< (USBHS) Host Pipe Clear Register (n = 0) 4 */ 219 #define REG_USBHS_HSTPIPICR5 (0x40038574) /**< (USBHS) Host Pipe Clear Register (n = 0) 5 */ 220 #define REG_USBHS_HSTPIPICR6 (0x40038578) /**< (USBHS) Host Pipe Clear Register (n = 0) 6 */ 221 #define REG_USBHS_HSTPIPICR7 (0x4003857C) /**< (USBHS) Host Pipe Clear Register (n = 0) 7 */ 222 #define REG_USBHS_HSTPIPICR8 (0x40038580) /**< (USBHS) Host Pipe Clear Register (n = 0) 8 */ 223 #define REG_USBHS_HSTPIPICR9 (0x40038584) /**< (USBHS) Host Pipe Clear Register (n = 0) 9 */ 224 #define REG_USBHS_HSTPIPIFR (0x40038590) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */ 225 #define REG_USBHS_HSTPIPIFR0 (0x40038590) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */ 226 #define REG_USBHS_HSTPIPIFR1 (0x40038594) /**< (USBHS) Host Pipe Set Register (n = 0) 1 */ 227 #define REG_USBHS_HSTPIPIFR2 (0x40038598) /**< (USBHS) Host Pipe Set Register (n = 0) 2 */ 228 #define REG_USBHS_HSTPIPIFR3 (0x4003859C) /**< (USBHS) Host Pipe Set Register (n = 0) 3 */ 229 #define REG_USBHS_HSTPIPIFR4 (0x400385A0) /**< (USBHS) Host Pipe Set Register (n = 0) 4 */ 230 #define REG_USBHS_HSTPIPIFR5 (0x400385A4) /**< (USBHS) Host Pipe Set Register (n = 0) 5 */ 231 #define REG_USBHS_HSTPIPIFR6 (0x400385A8) /**< (USBHS) Host Pipe Set Register (n = 0) 6 */ 232 #define REG_USBHS_HSTPIPIFR7 (0x400385AC) /**< (USBHS) Host Pipe Set Register (n = 0) 7 */ 233 #define REG_USBHS_HSTPIPIFR8 (0x400385B0) /**< (USBHS) Host Pipe Set Register (n = 0) 8 */ 234 #define REG_USBHS_HSTPIPIFR9 (0x400385B4) /**< (USBHS) Host Pipe Set Register (n = 0) 9 */ 235 #define REG_USBHS_HSTPIPIMR (0x400385C0) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */ 236 #define REG_USBHS_HSTPIPIMR0 (0x400385C0) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */ 237 #define REG_USBHS_HSTPIPIMR1 (0x400385C4) /**< (USBHS) Host Pipe Mask Register (n = 0) 1 */ 238 #define REG_USBHS_HSTPIPIMR2 (0x400385C8) /**< (USBHS) Host Pipe Mask Register (n = 0) 2 */ 239 #define REG_USBHS_HSTPIPIMR3 (0x400385CC) /**< (USBHS) Host Pipe Mask Register (n = 0) 3 */ 240 #define REG_USBHS_HSTPIPIMR4 (0x400385D0) /**< (USBHS) Host Pipe Mask Register (n = 0) 4 */ 241 #define REG_USBHS_HSTPIPIMR5 (0x400385D4) /**< (USBHS) Host Pipe Mask Register (n = 0) 5 */ 242 #define REG_USBHS_HSTPIPIMR6 (0x400385D8) /**< (USBHS) Host Pipe Mask Register (n = 0) 6 */ 243 #define REG_USBHS_HSTPIPIMR7 (0x400385DC) /**< (USBHS) Host Pipe Mask Register (n = 0) 7 */ 244 #define REG_USBHS_HSTPIPIMR8 (0x400385E0) /**< (USBHS) Host Pipe Mask Register (n = 0) 8 */ 245 #define REG_USBHS_HSTPIPIMR9 (0x400385E4) /**< (USBHS) Host Pipe Mask Register (n = 0) 9 */ 246 #define REG_USBHS_HSTPIPIER (0x400385F0) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */ 247 #define REG_USBHS_HSTPIPIER0 (0x400385F0) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */ 248 #define REG_USBHS_HSTPIPIER1 (0x400385F4) /**< (USBHS) Host Pipe Enable Register (n = 0) 1 */ 249 #define REG_USBHS_HSTPIPIER2 (0x400385F8) /**< (USBHS) Host Pipe Enable Register (n = 0) 2 */ 250 #define REG_USBHS_HSTPIPIER3 (0x400385FC) /**< (USBHS) Host Pipe Enable Register (n = 0) 3 */ 251 #define REG_USBHS_HSTPIPIER4 (0x40038600) /**< (USBHS) Host Pipe Enable Register (n = 0) 4 */ 252 #define REG_USBHS_HSTPIPIER5 (0x40038604) /**< (USBHS) Host Pipe Enable Register (n = 0) 5 */ 253 #define REG_USBHS_HSTPIPIER6 (0x40038608) /**< (USBHS) Host Pipe Enable Register (n = 0) 6 */ 254 #define REG_USBHS_HSTPIPIER7 (0x4003860C) /**< (USBHS) Host Pipe Enable Register (n = 0) 7 */ 255 #define REG_USBHS_HSTPIPIER8 (0x40038610) /**< (USBHS) Host Pipe Enable Register (n = 0) 8 */ 256 #define REG_USBHS_HSTPIPIER9 (0x40038614) /**< (USBHS) Host Pipe Enable Register (n = 0) 9 */ 257 #define REG_USBHS_HSTPIPIDR (0x40038620) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */ 258 #define REG_USBHS_HSTPIPIDR0 (0x40038620) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */ 259 #define REG_USBHS_HSTPIPIDR1 (0x40038624) /**< (USBHS) Host Pipe Disable Register (n = 0) 1 */ 260 #define REG_USBHS_HSTPIPIDR2 (0x40038628) /**< (USBHS) Host Pipe Disable Register (n = 0) 2 */ 261 #define REG_USBHS_HSTPIPIDR3 (0x4003862C) /**< (USBHS) Host Pipe Disable Register (n = 0) 3 */ 262 #define REG_USBHS_HSTPIPIDR4 (0x40038630) /**< (USBHS) Host Pipe Disable Register (n = 0) 4 */ 263 #define REG_USBHS_HSTPIPIDR5 (0x40038634) /**< (USBHS) Host Pipe Disable Register (n = 0) 5 */ 264 #define REG_USBHS_HSTPIPIDR6 (0x40038638) /**< (USBHS) Host Pipe Disable Register (n = 0) 6 */ 265 #define REG_USBHS_HSTPIPIDR7 (0x4003863C) /**< (USBHS) Host Pipe Disable Register (n = 0) 7 */ 266 #define REG_USBHS_HSTPIPIDR8 (0x40038640) /**< (USBHS) Host Pipe Disable Register (n = 0) 8 */ 267 #define REG_USBHS_HSTPIPIDR9 (0x40038644) /**< (USBHS) Host Pipe Disable Register (n = 0) 9 */ 268 #define REG_USBHS_HSTPIPINRQ (0x40038650) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */ 269 #define REG_USBHS_HSTPIPINRQ0 (0x40038650) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */ 270 #define REG_USBHS_HSTPIPINRQ1 (0x40038654) /**< (USBHS) Host Pipe IN Request Register (n = 0) 1 */ 271 #define REG_USBHS_HSTPIPINRQ2 (0x40038658) /**< (USBHS) Host Pipe IN Request Register (n = 0) 2 */ 272 #define REG_USBHS_HSTPIPINRQ3 (0x4003865C) /**< (USBHS) Host Pipe IN Request Register (n = 0) 3 */ 273 #define REG_USBHS_HSTPIPINRQ4 (0x40038660) /**< (USBHS) Host Pipe IN Request Register (n = 0) 4 */ 274 #define REG_USBHS_HSTPIPINRQ5 (0x40038664) /**< (USBHS) Host Pipe IN Request Register (n = 0) 5 */ 275 #define REG_USBHS_HSTPIPINRQ6 (0x40038668) /**< (USBHS) Host Pipe IN Request Register (n = 0) 6 */ 276 #define REG_USBHS_HSTPIPINRQ7 (0x4003866C) /**< (USBHS) Host Pipe IN Request Register (n = 0) 7 */ 277 #define REG_USBHS_HSTPIPINRQ8 (0x40038670) /**< (USBHS) Host Pipe IN Request Register (n = 0) 8 */ 278 #define REG_USBHS_HSTPIPINRQ9 (0x40038674) /**< (USBHS) Host Pipe IN Request Register (n = 0) 9 */ 279 #define REG_USBHS_HSTPIPERR (0x40038680) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */ 280 #define REG_USBHS_HSTPIPERR0 (0x40038680) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */ 281 #define REG_USBHS_HSTPIPERR1 (0x40038684) /**< (USBHS) Host Pipe Error Register (n = 0) 1 */ 282 #define REG_USBHS_HSTPIPERR2 (0x40038688) /**< (USBHS) Host Pipe Error Register (n = 0) 2 */ 283 #define REG_USBHS_HSTPIPERR3 (0x4003868C) /**< (USBHS) Host Pipe Error Register (n = 0) 3 */ 284 #define REG_USBHS_HSTPIPERR4 (0x40038690) /**< (USBHS) Host Pipe Error Register (n = 0) 4 */ 285 #define REG_USBHS_HSTPIPERR5 (0x40038694) /**< (USBHS) Host Pipe Error Register (n = 0) 5 */ 286 #define REG_USBHS_HSTPIPERR6 (0x40038698) /**< (USBHS) Host Pipe Error Register (n = 0) 6 */ 287 #define REG_USBHS_HSTPIPERR7 (0x4003869C) /**< (USBHS) Host Pipe Error Register (n = 0) 7 */ 288 #define REG_USBHS_HSTPIPERR8 (0x400386A0) /**< (USBHS) Host Pipe Error Register (n = 0) 8 */ 289 #define REG_USBHS_HSTPIPERR9 (0x400386A4) /**< (USBHS) Host Pipe Error Register (n = 0) 9 */ 290 #define REG_USBHS_CTRL (0x40038800) /**< (USBHS) General Control Register */ 291 #define REG_USBHS_SR (0x40038804) /**< (USBHS) General Status Register */ 292 #define REG_USBHS_SCR (0x40038808) /**< (USBHS) General Status Clear Register */ 293 #define REG_USBHS_SFR (0x4003880C) /**< (USBHS) General Status Set Register */ 294 #define REG_USBHS_TSTA1 (0x40038810) /**< (USBHS) General Test A1 Register */ 295 #define REG_USBHS_TSTA2 (0x40038814) /**< (USBHS) General Test A2 Register */ 296 #define REG_USBHS_VERSION (0x40038818) /**< (USBHS) General Version Register */ 297 #define REG_USBHS_FSM (0x4003882C) /**< (USBHS) General Finite State Machine Register */ 298 299 #else 300 301 #define REG_USBHS_DEVDMANXTDSC0 (*(__IO uint32_t*)0x40038310U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 0 */ 302 #define REG_USBHS_DEVDMAADDRESS0 (*(__IO uint32_t*)0x40038314U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 0 */ 303 #define REG_USBHS_DEVDMACONTROL0 (*(__IO uint32_t*)0x40038318U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 0 */ 304 #define REG_USBHS_DEVDMASTATUS0 (*(__IO uint32_t*)0x4003831CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 0 */ 305 #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038320U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 1 */ 306 #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038324U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 1 */ 307 #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038328U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 1 */ 308 #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003832CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 1 */ 309 #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038330U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 2 */ 310 #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038334U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 2 */ 311 #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038338U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 2 */ 312 #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003833CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 2 */ 313 #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038340U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 3 */ 314 #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038344U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 3 */ 315 #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038348U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 3 */ 316 #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003834CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 3 */ 317 #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038350U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 4 */ 318 #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038354U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 4 */ 319 #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038358U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 4 */ 320 #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003835CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 4 */ 321 #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038360U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 5 */ 322 #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038364U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 5 */ 323 #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038368U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 5 */ 324 #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003836CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 5 */ 325 #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038370U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 6 */ 326 #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038374U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 6 */ 327 #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038378U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 6 */ 328 #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003837CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 6 */ 329 #define REG_USBHS_HSTDMANXTDSC0 (*(__IO uint32_t*)0x40038710U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 0 */ 330 #define REG_USBHS_HSTDMAADDRESS0 (*(__IO uint32_t*)0x40038714U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 0 */ 331 #define REG_USBHS_HSTDMACONTROL0 (*(__IO uint32_t*)0x40038718U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 0 */ 332 #define REG_USBHS_HSTDMASTATUS0 (*(__IO uint32_t*)0x4003871CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 0 */ 333 #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038720U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 1 */ 334 #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038724U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 1 */ 335 #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038728U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 1 */ 336 #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003872CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 1 */ 337 #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038730U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 2 */ 338 #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038734U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 2 */ 339 #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038738U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 2 */ 340 #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003873CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 2 */ 341 #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038740U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 3 */ 342 #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038744U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 3 */ 343 #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038748U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 3 */ 344 #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003874CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 3 */ 345 #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038750U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 4 */ 346 #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038754U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 4 */ 347 #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038758U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 4 */ 348 #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003875CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 4 */ 349 #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038760U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 5 */ 350 #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038764U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 5 */ 351 #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038768U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 5 */ 352 #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003876CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 5 */ 353 #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038770U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 6 */ 354 #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038774U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 6 */ 355 #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038778U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 6 */ 356 #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003877CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 6 */ 357 #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< (USBHS) Device General Control Register */ 358 #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< (USBHS) Device Global Interrupt Status Register */ 359 #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< (USBHS) Device Global Interrupt Clear Register */ 360 #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< (USBHS) Device Global Interrupt Set Register */ 361 #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< (USBHS) Device Global Interrupt Mask Register */ 362 #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< (USBHS) Device Global Interrupt Disable Register */ 363 #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< (USBHS) Device Global Interrupt Enable Register */ 364 #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< (USBHS) Device Endpoint Register */ 365 #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< (USBHS) Device Frame Number Register */ 366 #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */ 367 #define REG_USBHS_DEVEPTCFG0 (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */ 368 #define REG_USBHS_DEVEPTCFG1 (*(__IO uint32_t*)0x40038104U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 1 */ 369 #define REG_USBHS_DEVEPTCFG2 (*(__IO uint32_t*)0x40038108U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 2 */ 370 #define REG_USBHS_DEVEPTCFG3 (*(__IO uint32_t*)0x4003810CU) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 3 */ 371 #define REG_USBHS_DEVEPTCFG4 (*(__IO uint32_t*)0x40038110U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 4 */ 372 #define REG_USBHS_DEVEPTCFG5 (*(__IO uint32_t*)0x40038114U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 5 */ 373 #define REG_USBHS_DEVEPTCFG6 (*(__IO uint32_t*)0x40038118U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 6 */ 374 #define REG_USBHS_DEVEPTCFG7 (*(__IO uint32_t*)0x4003811CU) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 7 */ 375 #define REG_USBHS_DEVEPTCFG8 (*(__IO uint32_t*)0x40038120U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 8 */ 376 #define REG_USBHS_DEVEPTCFG9 (*(__IO uint32_t*)0x40038124U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 9 */ 377 #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */ 378 #define REG_USBHS_DEVEPTISR0 (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */ 379 #define REG_USBHS_DEVEPTISR1 (*(__I uint32_t*)0x40038134U) /**< (USBHS) Device Endpoint Status Register (n = 0) 1 */ 380 #define REG_USBHS_DEVEPTISR2 (*(__I uint32_t*)0x40038138U) /**< (USBHS) Device Endpoint Status Register (n = 0) 2 */ 381 #define REG_USBHS_DEVEPTISR3 (*(__I uint32_t*)0x4003813CU) /**< (USBHS) Device Endpoint Status Register (n = 0) 3 */ 382 #define REG_USBHS_DEVEPTISR4 (*(__I uint32_t*)0x40038140U) /**< (USBHS) Device Endpoint Status Register (n = 0) 4 */ 383 #define REG_USBHS_DEVEPTISR5 (*(__I uint32_t*)0x40038144U) /**< (USBHS) Device Endpoint Status Register (n = 0) 5 */ 384 #define REG_USBHS_DEVEPTISR6 (*(__I uint32_t*)0x40038148U) /**< (USBHS) Device Endpoint Status Register (n = 0) 6 */ 385 #define REG_USBHS_DEVEPTISR7 (*(__I uint32_t*)0x4003814CU) /**< (USBHS) Device Endpoint Status Register (n = 0) 7 */ 386 #define REG_USBHS_DEVEPTISR8 (*(__I uint32_t*)0x40038150U) /**< (USBHS) Device Endpoint Status Register (n = 0) 8 */ 387 #define REG_USBHS_DEVEPTISR9 (*(__I uint32_t*)0x40038154U) /**< (USBHS) Device Endpoint Status Register (n = 0) 9 */ 388 #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */ 389 #define REG_USBHS_DEVEPTICR0 (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */ 390 #define REG_USBHS_DEVEPTICR1 (*(__O uint32_t*)0x40038164U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 1 */ 391 #define REG_USBHS_DEVEPTICR2 (*(__O uint32_t*)0x40038168U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 2 */ 392 #define REG_USBHS_DEVEPTICR3 (*(__O uint32_t*)0x4003816CU) /**< (USBHS) Device Endpoint Clear Register (n = 0) 3 */ 393 #define REG_USBHS_DEVEPTICR4 (*(__O uint32_t*)0x40038170U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 4 */ 394 #define REG_USBHS_DEVEPTICR5 (*(__O uint32_t*)0x40038174U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 5 */ 395 #define REG_USBHS_DEVEPTICR6 (*(__O uint32_t*)0x40038178U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 6 */ 396 #define REG_USBHS_DEVEPTICR7 (*(__O uint32_t*)0x4003817CU) /**< (USBHS) Device Endpoint Clear Register (n = 0) 7 */ 397 #define REG_USBHS_DEVEPTICR8 (*(__O uint32_t*)0x40038180U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 8 */ 398 #define REG_USBHS_DEVEPTICR9 (*(__O uint32_t*)0x40038184U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 9 */ 399 #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */ 400 #define REG_USBHS_DEVEPTIFR0 (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */ 401 #define REG_USBHS_DEVEPTIFR1 (*(__O uint32_t*)0x40038194U) /**< (USBHS) Device Endpoint Set Register (n = 0) 1 */ 402 #define REG_USBHS_DEVEPTIFR2 (*(__O uint32_t*)0x40038198U) /**< (USBHS) Device Endpoint Set Register (n = 0) 2 */ 403 #define REG_USBHS_DEVEPTIFR3 (*(__O uint32_t*)0x4003819CU) /**< (USBHS) Device Endpoint Set Register (n = 0) 3 */ 404 #define REG_USBHS_DEVEPTIFR4 (*(__O uint32_t*)0x400381A0U) /**< (USBHS) Device Endpoint Set Register (n = 0) 4 */ 405 #define REG_USBHS_DEVEPTIFR5 (*(__O uint32_t*)0x400381A4U) /**< (USBHS) Device Endpoint Set Register (n = 0) 5 */ 406 #define REG_USBHS_DEVEPTIFR6 (*(__O uint32_t*)0x400381A8U) /**< (USBHS) Device Endpoint Set Register (n = 0) 6 */ 407 #define REG_USBHS_DEVEPTIFR7 (*(__O uint32_t*)0x400381ACU) /**< (USBHS) Device Endpoint Set Register (n = 0) 7 */ 408 #define REG_USBHS_DEVEPTIFR8 (*(__O uint32_t*)0x400381B0U) /**< (USBHS) Device Endpoint Set Register (n = 0) 8 */ 409 #define REG_USBHS_DEVEPTIFR9 (*(__O uint32_t*)0x400381B4U) /**< (USBHS) Device Endpoint Set Register (n = 0) 9 */ 410 #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */ 411 #define REG_USBHS_DEVEPTIMR0 (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */ 412 #define REG_USBHS_DEVEPTIMR1 (*(__I uint32_t*)0x400381C4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 1 */ 413 #define REG_USBHS_DEVEPTIMR2 (*(__I uint32_t*)0x400381C8U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 2 */ 414 #define REG_USBHS_DEVEPTIMR3 (*(__I uint32_t*)0x400381CCU) /**< (USBHS) Device Endpoint Mask Register (n = 0) 3 */ 415 #define REG_USBHS_DEVEPTIMR4 (*(__I uint32_t*)0x400381D0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 4 */ 416 #define REG_USBHS_DEVEPTIMR5 (*(__I uint32_t*)0x400381D4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 5 */ 417 #define REG_USBHS_DEVEPTIMR6 (*(__I uint32_t*)0x400381D8U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 6 */ 418 #define REG_USBHS_DEVEPTIMR7 (*(__I uint32_t*)0x400381DCU) /**< (USBHS) Device Endpoint Mask Register (n = 0) 7 */ 419 #define REG_USBHS_DEVEPTIMR8 (*(__I uint32_t*)0x400381E0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 8 */ 420 #define REG_USBHS_DEVEPTIMR9 (*(__I uint32_t*)0x400381E4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 9 */ 421 #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */ 422 #define REG_USBHS_DEVEPTIER0 (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */ 423 #define REG_USBHS_DEVEPTIER1 (*(__O uint32_t*)0x400381F4U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 1 */ 424 #define REG_USBHS_DEVEPTIER2 (*(__O uint32_t*)0x400381F8U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 2 */ 425 #define REG_USBHS_DEVEPTIER3 (*(__O uint32_t*)0x400381FCU) /**< (USBHS) Device Endpoint Enable Register (n = 0) 3 */ 426 #define REG_USBHS_DEVEPTIER4 (*(__O uint32_t*)0x40038200U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 4 */ 427 #define REG_USBHS_DEVEPTIER5 (*(__O uint32_t*)0x40038204U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 5 */ 428 #define REG_USBHS_DEVEPTIER6 (*(__O uint32_t*)0x40038208U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 6 */ 429 #define REG_USBHS_DEVEPTIER7 (*(__O uint32_t*)0x4003820CU) /**< (USBHS) Device Endpoint Enable Register (n = 0) 7 */ 430 #define REG_USBHS_DEVEPTIER8 (*(__O uint32_t*)0x40038210U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 8 */ 431 #define REG_USBHS_DEVEPTIER9 (*(__O uint32_t*)0x40038214U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 9 */ 432 #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */ 433 #define REG_USBHS_DEVEPTIDR0 (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */ 434 #define REG_USBHS_DEVEPTIDR1 (*(__O uint32_t*)0x40038224U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 1 */ 435 #define REG_USBHS_DEVEPTIDR2 (*(__O uint32_t*)0x40038228U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 2 */ 436 #define REG_USBHS_DEVEPTIDR3 (*(__O uint32_t*)0x4003822CU) /**< (USBHS) Device Endpoint Disable Register (n = 0) 3 */ 437 #define REG_USBHS_DEVEPTIDR4 (*(__O uint32_t*)0x40038230U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 4 */ 438 #define REG_USBHS_DEVEPTIDR5 (*(__O uint32_t*)0x40038234U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 5 */ 439 #define REG_USBHS_DEVEPTIDR6 (*(__O uint32_t*)0x40038238U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 6 */ 440 #define REG_USBHS_DEVEPTIDR7 (*(__O uint32_t*)0x4003823CU) /**< (USBHS) Device Endpoint Disable Register (n = 0) 7 */ 441 #define REG_USBHS_DEVEPTIDR8 (*(__O uint32_t*)0x40038240U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 8 */ 442 #define REG_USBHS_DEVEPTIDR9 (*(__O uint32_t*)0x40038244U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 9 */ 443 #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< (USBHS) Host General Control Register */ 444 #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< (USBHS) Host Global Interrupt Status Register */ 445 #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< (USBHS) Host Global Interrupt Clear Register */ 446 #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< (USBHS) Host Global Interrupt Set Register */ 447 #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< (USBHS) Host Global Interrupt Mask Register */ 448 #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< (USBHS) Host Global Interrupt Disable Register */ 449 #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< (USBHS) Host Global Interrupt Enable Register */ 450 #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< (USBHS) Host Pipe Register */ 451 #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< (USBHS) Host Frame Number Register */ 452 #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< (USBHS) Host Address 1 Register */ 453 #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< (USBHS) Host Address 2 Register */ 454 #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< (USBHS) Host Address 3 Register */ 455 #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */ 456 #define REG_USBHS_HSTPIPCFG0 (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */ 457 #define REG_USBHS_HSTPIPCFG1 (*(__IO uint32_t*)0x40038504U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 1 */ 458 #define REG_USBHS_HSTPIPCFG2 (*(__IO uint32_t*)0x40038508U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 2 */ 459 #define REG_USBHS_HSTPIPCFG3 (*(__IO uint32_t*)0x4003850CU) /**< (USBHS) Host Pipe Configuration Register (n = 0) 3 */ 460 #define REG_USBHS_HSTPIPCFG4 (*(__IO uint32_t*)0x40038510U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 4 */ 461 #define REG_USBHS_HSTPIPCFG5 (*(__IO uint32_t*)0x40038514U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 5 */ 462 #define REG_USBHS_HSTPIPCFG6 (*(__IO uint32_t*)0x40038518U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 6 */ 463 #define REG_USBHS_HSTPIPCFG7 (*(__IO uint32_t*)0x4003851CU) /**< (USBHS) Host Pipe Configuration Register (n = 0) 7 */ 464 #define REG_USBHS_HSTPIPCFG8 (*(__IO uint32_t*)0x40038520U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 8 */ 465 #define REG_USBHS_HSTPIPCFG9 (*(__IO uint32_t*)0x40038524U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 9 */ 466 #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */ 467 #define REG_USBHS_HSTPIPISR0 (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */ 468 #define REG_USBHS_HSTPIPISR1 (*(__I uint32_t*)0x40038534U) /**< (USBHS) Host Pipe Status Register (n = 0) 1 */ 469 #define REG_USBHS_HSTPIPISR2 (*(__I uint32_t*)0x40038538U) /**< (USBHS) Host Pipe Status Register (n = 0) 2 */ 470 #define REG_USBHS_HSTPIPISR3 (*(__I uint32_t*)0x4003853CU) /**< (USBHS) Host Pipe Status Register (n = 0) 3 */ 471 #define REG_USBHS_HSTPIPISR4 (*(__I uint32_t*)0x40038540U) /**< (USBHS) Host Pipe Status Register (n = 0) 4 */ 472 #define REG_USBHS_HSTPIPISR5 (*(__I uint32_t*)0x40038544U) /**< (USBHS) Host Pipe Status Register (n = 0) 5 */ 473 #define REG_USBHS_HSTPIPISR6 (*(__I uint32_t*)0x40038548U) /**< (USBHS) Host Pipe Status Register (n = 0) 6 */ 474 #define REG_USBHS_HSTPIPISR7 (*(__I uint32_t*)0x4003854CU) /**< (USBHS) Host Pipe Status Register (n = 0) 7 */ 475 #define REG_USBHS_HSTPIPISR8 (*(__I uint32_t*)0x40038550U) /**< (USBHS) Host Pipe Status Register (n = 0) 8 */ 476 #define REG_USBHS_HSTPIPISR9 (*(__I uint32_t*)0x40038554U) /**< (USBHS) Host Pipe Status Register (n = 0) 9 */ 477 #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */ 478 #define REG_USBHS_HSTPIPICR0 (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */ 479 #define REG_USBHS_HSTPIPICR1 (*(__O uint32_t*)0x40038564U) /**< (USBHS) Host Pipe Clear Register (n = 0) 1 */ 480 #define REG_USBHS_HSTPIPICR2 (*(__O uint32_t*)0x40038568U) /**< (USBHS) Host Pipe Clear Register (n = 0) 2 */ 481 #define REG_USBHS_HSTPIPICR3 (*(__O uint32_t*)0x4003856CU) /**< (USBHS) Host Pipe Clear Register (n = 0) 3 */ 482 #define REG_USBHS_HSTPIPICR4 (*(__O uint32_t*)0x40038570U) /**< (USBHS) Host Pipe Clear Register (n = 0) 4 */ 483 #define REG_USBHS_HSTPIPICR5 (*(__O uint32_t*)0x40038574U) /**< (USBHS) Host Pipe Clear Register (n = 0) 5 */ 484 #define REG_USBHS_HSTPIPICR6 (*(__O uint32_t*)0x40038578U) /**< (USBHS) Host Pipe Clear Register (n = 0) 6 */ 485 #define REG_USBHS_HSTPIPICR7 (*(__O uint32_t*)0x4003857CU) /**< (USBHS) Host Pipe Clear Register (n = 0) 7 */ 486 #define REG_USBHS_HSTPIPICR8 (*(__O uint32_t*)0x40038580U) /**< (USBHS) Host Pipe Clear Register (n = 0) 8 */ 487 #define REG_USBHS_HSTPIPICR9 (*(__O uint32_t*)0x40038584U) /**< (USBHS) Host Pipe Clear Register (n = 0) 9 */ 488 #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */ 489 #define REG_USBHS_HSTPIPIFR0 (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */ 490 #define REG_USBHS_HSTPIPIFR1 (*(__O uint32_t*)0x40038594U) /**< (USBHS) Host Pipe Set Register (n = 0) 1 */ 491 #define REG_USBHS_HSTPIPIFR2 (*(__O uint32_t*)0x40038598U) /**< (USBHS) Host Pipe Set Register (n = 0) 2 */ 492 #define REG_USBHS_HSTPIPIFR3 (*(__O uint32_t*)0x4003859CU) /**< (USBHS) Host Pipe Set Register (n = 0) 3 */ 493 #define REG_USBHS_HSTPIPIFR4 (*(__O uint32_t*)0x400385A0U) /**< (USBHS) Host Pipe Set Register (n = 0) 4 */ 494 #define REG_USBHS_HSTPIPIFR5 (*(__O uint32_t*)0x400385A4U) /**< (USBHS) Host Pipe Set Register (n = 0) 5 */ 495 #define REG_USBHS_HSTPIPIFR6 (*(__O uint32_t*)0x400385A8U) /**< (USBHS) Host Pipe Set Register (n = 0) 6 */ 496 #define REG_USBHS_HSTPIPIFR7 (*(__O uint32_t*)0x400385ACU) /**< (USBHS) Host Pipe Set Register (n = 0) 7 */ 497 #define REG_USBHS_HSTPIPIFR8 (*(__O uint32_t*)0x400385B0U) /**< (USBHS) Host Pipe Set Register (n = 0) 8 */ 498 #define REG_USBHS_HSTPIPIFR9 (*(__O uint32_t*)0x400385B4U) /**< (USBHS) Host Pipe Set Register (n = 0) 9 */ 499 #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */ 500 #define REG_USBHS_HSTPIPIMR0 (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */ 501 #define REG_USBHS_HSTPIPIMR1 (*(__I uint32_t*)0x400385C4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 1 */ 502 #define REG_USBHS_HSTPIPIMR2 (*(__I uint32_t*)0x400385C8U) /**< (USBHS) Host Pipe Mask Register (n = 0) 2 */ 503 #define REG_USBHS_HSTPIPIMR3 (*(__I uint32_t*)0x400385CCU) /**< (USBHS) Host Pipe Mask Register (n = 0) 3 */ 504 #define REG_USBHS_HSTPIPIMR4 (*(__I uint32_t*)0x400385D0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 4 */ 505 #define REG_USBHS_HSTPIPIMR5 (*(__I uint32_t*)0x400385D4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 5 */ 506 #define REG_USBHS_HSTPIPIMR6 (*(__I uint32_t*)0x400385D8U) /**< (USBHS) Host Pipe Mask Register (n = 0) 6 */ 507 #define REG_USBHS_HSTPIPIMR7 (*(__I uint32_t*)0x400385DCU) /**< (USBHS) Host Pipe Mask Register (n = 0) 7 */ 508 #define REG_USBHS_HSTPIPIMR8 (*(__I uint32_t*)0x400385E0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 8 */ 509 #define REG_USBHS_HSTPIPIMR9 (*(__I uint32_t*)0x400385E4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 9 */ 510 #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */ 511 #define REG_USBHS_HSTPIPIER0 (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */ 512 #define REG_USBHS_HSTPIPIER1 (*(__O uint32_t*)0x400385F4U) /**< (USBHS) Host Pipe Enable Register (n = 0) 1 */ 513 #define REG_USBHS_HSTPIPIER2 (*(__O uint32_t*)0x400385F8U) /**< (USBHS) Host Pipe Enable Register (n = 0) 2 */ 514 #define REG_USBHS_HSTPIPIER3 (*(__O uint32_t*)0x400385FCU) /**< (USBHS) Host Pipe Enable Register (n = 0) 3 */ 515 #define REG_USBHS_HSTPIPIER4 (*(__O uint32_t*)0x40038600U) /**< (USBHS) Host Pipe Enable Register (n = 0) 4 */ 516 #define REG_USBHS_HSTPIPIER5 (*(__O uint32_t*)0x40038604U) /**< (USBHS) Host Pipe Enable Register (n = 0) 5 */ 517 #define REG_USBHS_HSTPIPIER6 (*(__O uint32_t*)0x40038608U) /**< (USBHS) Host Pipe Enable Register (n = 0) 6 */ 518 #define REG_USBHS_HSTPIPIER7 (*(__O uint32_t*)0x4003860CU) /**< (USBHS) Host Pipe Enable Register (n = 0) 7 */ 519 #define REG_USBHS_HSTPIPIER8 (*(__O uint32_t*)0x40038610U) /**< (USBHS) Host Pipe Enable Register (n = 0) 8 */ 520 #define REG_USBHS_HSTPIPIER9 (*(__O uint32_t*)0x40038614U) /**< (USBHS) Host Pipe Enable Register (n = 0) 9 */ 521 #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */ 522 #define REG_USBHS_HSTPIPIDR0 (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */ 523 #define REG_USBHS_HSTPIPIDR1 (*(__O uint32_t*)0x40038624U) /**< (USBHS) Host Pipe Disable Register (n = 0) 1 */ 524 #define REG_USBHS_HSTPIPIDR2 (*(__O uint32_t*)0x40038628U) /**< (USBHS) Host Pipe Disable Register (n = 0) 2 */ 525 #define REG_USBHS_HSTPIPIDR3 (*(__O uint32_t*)0x4003862CU) /**< (USBHS) Host Pipe Disable Register (n = 0) 3 */ 526 #define REG_USBHS_HSTPIPIDR4 (*(__O uint32_t*)0x40038630U) /**< (USBHS) Host Pipe Disable Register (n = 0) 4 */ 527 #define REG_USBHS_HSTPIPIDR5 (*(__O uint32_t*)0x40038634U) /**< (USBHS) Host Pipe Disable Register (n = 0) 5 */ 528 #define REG_USBHS_HSTPIPIDR6 (*(__O uint32_t*)0x40038638U) /**< (USBHS) Host Pipe Disable Register (n = 0) 6 */ 529 #define REG_USBHS_HSTPIPIDR7 (*(__O uint32_t*)0x4003863CU) /**< (USBHS) Host Pipe Disable Register (n = 0) 7 */ 530 #define REG_USBHS_HSTPIPIDR8 (*(__O uint32_t*)0x40038640U) /**< (USBHS) Host Pipe Disable Register (n = 0) 8 */ 531 #define REG_USBHS_HSTPIPIDR9 (*(__O uint32_t*)0x40038644U) /**< (USBHS) Host Pipe Disable Register (n = 0) 9 */ 532 #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */ 533 #define REG_USBHS_HSTPIPINRQ0 (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */ 534 #define REG_USBHS_HSTPIPINRQ1 (*(__IO uint32_t*)0x40038654U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 1 */ 535 #define REG_USBHS_HSTPIPINRQ2 (*(__IO uint32_t*)0x40038658U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 2 */ 536 #define REG_USBHS_HSTPIPINRQ3 (*(__IO uint32_t*)0x4003865CU) /**< (USBHS) Host Pipe IN Request Register (n = 0) 3 */ 537 #define REG_USBHS_HSTPIPINRQ4 (*(__IO uint32_t*)0x40038660U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 4 */ 538 #define REG_USBHS_HSTPIPINRQ5 (*(__IO uint32_t*)0x40038664U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 5 */ 539 #define REG_USBHS_HSTPIPINRQ6 (*(__IO uint32_t*)0x40038668U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 6 */ 540 #define REG_USBHS_HSTPIPINRQ7 (*(__IO uint32_t*)0x4003866CU) /**< (USBHS) Host Pipe IN Request Register (n = 0) 7 */ 541 #define REG_USBHS_HSTPIPINRQ8 (*(__IO uint32_t*)0x40038670U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 8 */ 542 #define REG_USBHS_HSTPIPINRQ9 (*(__IO uint32_t*)0x40038674U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 9 */ 543 #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */ 544 #define REG_USBHS_HSTPIPERR0 (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */ 545 #define REG_USBHS_HSTPIPERR1 (*(__IO uint32_t*)0x40038684U) /**< (USBHS) Host Pipe Error Register (n = 0) 1 */ 546 #define REG_USBHS_HSTPIPERR2 (*(__IO uint32_t*)0x40038688U) /**< (USBHS) Host Pipe Error Register (n = 0) 2 */ 547 #define REG_USBHS_HSTPIPERR3 (*(__IO uint32_t*)0x4003868CU) /**< (USBHS) Host Pipe Error Register (n = 0) 3 */ 548 #define REG_USBHS_HSTPIPERR4 (*(__IO uint32_t*)0x40038690U) /**< (USBHS) Host Pipe Error Register (n = 0) 4 */ 549 #define REG_USBHS_HSTPIPERR5 (*(__IO uint32_t*)0x40038694U) /**< (USBHS) Host Pipe Error Register (n = 0) 5 */ 550 #define REG_USBHS_HSTPIPERR6 (*(__IO uint32_t*)0x40038698U) /**< (USBHS) Host Pipe Error Register (n = 0) 6 */ 551 #define REG_USBHS_HSTPIPERR7 (*(__IO uint32_t*)0x4003869CU) /**< (USBHS) Host Pipe Error Register (n = 0) 7 */ 552 #define REG_USBHS_HSTPIPERR8 (*(__IO uint32_t*)0x400386A0U) /**< (USBHS) Host Pipe Error Register (n = 0) 8 */ 553 #define REG_USBHS_HSTPIPERR9 (*(__IO uint32_t*)0x400386A4U) /**< (USBHS) Host Pipe Error Register (n = 0) 9 */ 554 #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< (USBHS) General Control Register */ 555 #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< (USBHS) General Status Register */ 556 #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< (USBHS) General Status Clear Register */ 557 #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< (USBHS) General Status Set Register */ 558 #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< (USBHS) General Test A1 Register */ 559 #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< (USBHS) General Test A2 Register */ 560 #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< (USBHS) General Version Register */ 561 #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< (USBHS) General Finite State Machine Register */ 562 563 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 564 565 /* ========== Instance Parameter definitions for USBHS peripheral ========== */ 566 #define USBHS_INSTANCE_ID 34 567 568 #endif /* _SAMV71_USBHS_INSTANCE_ */ 569
