1 /** 2 * \file 3 * 4 * \brief Instance description for UART1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_UART1_INSTANCE_H_ 32 #define _SAMV71_UART1_INSTANCE_H_ 33 34 /* ========== Register definition for UART1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_UART1_CR (0x400E0A00) /**< (UART1) Control Register */ 38 #define REG_UART1_MR (0x400E0A04) /**< (UART1) Mode Register */ 39 #define REG_UART1_IER (0x400E0A08) /**< (UART1) Interrupt Enable Register */ 40 #define REG_UART1_IDR (0x400E0A0C) /**< (UART1) Interrupt Disable Register */ 41 #define REG_UART1_IMR (0x400E0A10) /**< (UART1) Interrupt Mask Register */ 42 #define REG_UART1_SR (0x400E0A14) /**< (UART1) Status Register */ 43 #define REG_UART1_RHR (0x400E0A18) /**< (UART1) Receive Holding Register */ 44 #define REG_UART1_THR (0x400E0A1C) /**< (UART1) Transmit Holding Register */ 45 #define REG_UART1_BRGR (0x400E0A20) /**< (UART1) Baud Rate Generator Register */ 46 #define REG_UART1_CMPR (0x400E0A24) /**< (UART1) Comparison Register */ 47 #define REG_UART1_WPMR (0x400E0AE4) /**< (UART1) Write Protection Mode Register */ 48 #define REG_UART1_VERSION (0x400E0AFC) /**< (UART1) Version Register */ 49 50 #else 51 52 #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */ 53 #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< (UART1) Mode Register */ 54 #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Register */ 55 #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Register */ 56 #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< (UART1) Interrupt Mask Register */ 57 #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< (UART1) Status Register */ 58 #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< (UART1) Receive Holding Register */ 59 #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Register */ 60 #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< (UART1) Baud Rate Generator Register */ 61 #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< (UART1) Comparison Register */ 62 #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< (UART1) Write Protection Mode Register */ 63 #define REG_UART1_VERSION (*(__I uint32_t*)0x400E0AFCU) /**< (UART1) Version Register */ 64 65 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 /* ========== Instance Parameter definitions for UART1 peripheral ========== */ 68 #define UART1_DMAC_ID_RX 23 69 #define UART1_DMAC_ID_TX 22 70 #define UART1_INSTANCE_ID 8 71 72 #endif /* _SAMV71_UART1_INSTANCE_ */ 73
