1 /** 2 * \file 3 * 4 * \brief Instance description for TWIHS1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_TWIHS1_INSTANCE_H_ 32 #define _SAMV71_TWIHS1_INSTANCE_H_ 33 34 /* ========== Register definition for TWIHS1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TWIHS1_CR (0x4001C000) /**< (TWIHS1) Control Register */ 38 #define REG_TWIHS1_MMR (0x4001C004) /**< (TWIHS1) Master Mode Register */ 39 #define REG_TWIHS1_SMR (0x4001C008) /**< (TWIHS1) Slave Mode Register */ 40 #define REG_TWIHS1_IADR (0x4001C00C) /**< (TWIHS1) Internal Address Register */ 41 #define REG_TWIHS1_CWGR (0x4001C010) /**< (TWIHS1) Clock Waveform Generator Register */ 42 #define REG_TWIHS1_SR (0x4001C020) /**< (TWIHS1) Status Register */ 43 #define REG_TWIHS1_IER (0x4001C024) /**< (TWIHS1) Interrupt Enable Register */ 44 #define REG_TWIHS1_IDR (0x4001C028) /**< (TWIHS1) Interrupt Disable Register */ 45 #define REG_TWIHS1_IMR (0x4001C02C) /**< (TWIHS1) Interrupt Mask Register */ 46 #define REG_TWIHS1_RHR (0x4001C030) /**< (TWIHS1) Receive Holding Register */ 47 #define REG_TWIHS1_THR (0x4001C034) /**< (TWIHS1) Transmit Holding Register */ 48 #define REG_TWIHS1_SMBTR (0x4001C038) /**< (TWIHS1) SMBus Timing Register */ 49 #define REG_TWIHS1_FILTR (0x4001C044) /**< (TWIHS1) Filter Register */ 50 #define REG_TWIHS1_SWMR (0x4001C04C) /**< (TWIHS1) SleepWalking Matching Register */ 51 #define REG_TWIHS1_DR (0x4001C0D0) /**< (TWIHS1) Debug Register */ 52 #define REG_TWIHS1_WPMR (0x4001C0E4) /**< (TWIHS1) Write Protection Mode Register */ 53 #define REG_TWIHS1_WPSR (0x4001C0E8) /**< (TWIHS1) Write Protection Status Register */ 54 #define REG_TWIHS1_VER (0x4001C0FC) /**< (TWIHS1) Version Register */ 55 56 #else 57 58 #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< (TWIHS1) Control Register */ 59 #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< (TWIHS1) Master Mode Register */ 60 #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< (TWIHS1) Slave Mode Register */ 61 #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< (TWIHS1) Internal Address Register */ 62 #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< (TWIHS1) Clock Waveform Generator Register */ 63 #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< (TWIHS1) Status Register */ 64 #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< (TWIHS1) Interrupt Enable Register */ 65 #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< (TWIHS1) Interrupt Disable Register */ 66 #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< (TWIHS1) Interrupt Mask Register */ 67 #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< (TWIHS1) Receive Holding Register */ 68 #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< (TWIHS1) Transmit Holding Register */ 69 #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< (TWIHS1) SMBus Timing Register */ 70 #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< (TWIHS1) Filter Register */ 71 #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< (TWIHS1) SleepWalking Matching Register */ 72 #define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) /**< (TWIHS1) Debug Register */ 73 #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< (TWIHS1) Write Protection Mode Register */ 74 #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< (TWIHS1) Write Protection Status Register */ 75 #define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) /**< (TWIHS1) Version Register */ 76 77 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 /* ========== Instance Parameter definitions for TWIHS1 peripheral ========== */ 80 #define TWIHS1_DMAC_ID_RX 17 81 #define TWIHS1_DMAC_ID_TX 16 82 #define TWIHS1_INSTANCE_ID 20 83 84 #endif /* _SAMV71_TWIHS1_INSTANCE_ */ 85
