1 /** 2 * \file 3 * 4 * \brief Instance description for PWM0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_PWM0_INSTANCE_H_ 32 #define _SAMV71_PWM0_INSTANCE_H_ 33 34 /* ========== Register definition for PWM0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_PWM0_CMPV0 (0x40020130) /**< (PWM0) PWM Comparison 0 Value Register 0 */ 38 #define REG_PWM0_CMPVUPD0 (0x40020134) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */ 39 #define REG_PWM0_CMPM0 (0x40020138) /**< (PWM0) PWM Comparison 0 Mode Register 0 */ 40 #define REG_PWM0_CMPMUPD0 (0x4002013C) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */ 41 #define REG_PWM0_CMPV1 (0x40020140) /**< (PWM0) PWM Comparison 0 Value Register 1 */ 42 #define REG_PWM0_CMPVUPD1 (0x40020144) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */ 43 #define REG_PWM0_CMPM1 (0x40020148) /**< (PWM0) PWM Comparison 0 Mode Register 1 */ 44 #define REG_PWM0_CMPMUPD1 (0x4002014C) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */ 45 #define REG_PWM0_CMPV2 (0x40020150) /**< (PWM0) PWM Comparison 0 Value Register 2 */ 46 #define REG_PWM0_CMPVUPD2 (0x40020154) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */ 47 #define REG_PWM0_CMPM2 (0x40020158) /**< (PWM0) PWM Comparison 0 Mode Register 2 */ 48 #define REG_PWM0_CMPMUPD2 (0x4002015C) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */ 49 #define REG_PWM0_CMPV3 (0x40020160) /**< (PWM0) PWM Comparison 0 Value Register 3 */ 50 #define REG_PWM0_CMPVUPD3 (0x40020164) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */ 51 #define REG_PWM0_CMPM3 (0x40020168) /**< (PWM0) PWM Comparison 0 Mode Register 3 */ 52 #define REG_PWM0_CMPMUPD3 (0x4002016C) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */ 53 #define REG_PWM0_CMPV4 (0x40020170) /**< (PWM0) PWM Comparison 0 Value Register 4 */ 54 #define REG_PWM0_CMPVUPD4 (0x40020174) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */ 55 #define REG_PWM0_CMPM4 (0x40020178) /**< (PWM0) PWM Comparison 0 Mode Register 4 */ 56 #define REG_PWM0_CMPMUPD4 (0x4002017C) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */ 57 #define REG_PWM0_CMPV5 (0x40020180) /**< (PWM0) PWM Comparison 0 Value Register 5 */ 58 #define REG_PWM0_CMPVUPD5 (0x40020184) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */ 59 #define REG_PWM0_CMPM5 (0x40020188) /**< (PWM0) PWM Comparison 0 Mode Register 5 */ 60 #define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ 61 #define REG_PWM0_CMPV6 (0x40020190) /**< (PWM0) PWM Comparison 0 Value Register 6 */ 62 #define REG_PWM0_CMPVUPD6 (0x40020194) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */ 63 #define REG_PWM0_CMPM6 (0x40020198) /**< (PWM0) PWM Comparison 0 Mode Register 6 */ 64 #define REG_PWM0_CMPMUPD6 (0x4002019C) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */ 65 #define REG_PWM0_CMPV7 (0x400201A0) /**< (PWM0) PWM Comparison 0 Value Register 7 */ 66 #define REG_PWM0_CMPVUPD7 (0x400201A4) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */ 67 #define REG_PWM0_CMPM7 (0x400201A8) /**< (PWM0) PWM Comparison 0 Mode Register 7 */ 68 #define REG_PWM0_CMPMUPD7 (0x400201AC) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */ 69 #define REG_PWM0_CMR0 (0x40020200) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 0 */ 70 #define REG_PWM0_CDTY0 (0x40020204) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 0 */ 71 #define REG_PWM0_CDTYUPD0 (0x40020208) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */ 72 #define REG_PWM0_CPRD0 (0x4002020C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 0 */ 73 #define REG_PWM0_CPRDUPD0 (0x40020210) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 0 */ 74 #define REG_PWM0_CCNT0 (0x40020214) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 0 */ 75 #define REG_PWM0_DT0 (0x40020218) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 0 */ 76 #define REG_PWM0_DTUPD0 (0x4002021C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 0 */ 77 #define REG_PWM0_CMR1 (0x40020220) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 1 */ 78 #define REG_PWM0_CDTY1 (0x40020224) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 1 */ 79 #define REG_PWM0_CDTYUPD1 (0x40020228) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */ 80 #define REG_PWM0_CPRD1 (0x4002022C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 1 */ 81 #define REG_PWM0_CPRDUPD1 (0x40020230) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 1 */ 82 #define REG_PWM0_CCNT1 (0x40020234) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 1 */ 83 #define REG_PWM0_DT1 (0x40020238) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 1 */ 84 #define REG_PWM0_DTUPD1 (0x4002023C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 1 */ 85 #define REG_PWM0_CMR2 (0x40020240) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 2 */ 86 #define REG_PWM0_CDTY2 (0x40020244) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 2 */ 87 #define REG_PWM0_CDTYUPD2 (0x40020248) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */ 88 #define REG_PWM0_CPRD2 (0x4002024C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 2 */ 89 #define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 2 */ 90 #define REG_PWM0_CCNT2 (0x40020254) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 2 */ 91 #define REG_PWM0_DT2 (0x40020258) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 2 */ 92 #define REG_PWM0_DTUPD2 (0x4002025C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 2 */ 93 #define REG_PWM0_CMR3 (0x40020260) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 3 */ 94 #define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 3 */ 95 #define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */ 96 #define REG_PWM0_CPRD3 (0x4002026C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 3 */ 97 #define REG_PWM0_CPRDUPD3 (0x40020270) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 3 */ 98 #define REG_PWM0_CCNT3 (0x40020274) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 3 */ 99 #define REG_PWM0_DT3 (0x40020278) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 3 */ 100 #define REG_PWM0_DTUPD3 (0x4002027C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 3 */ 101 #define REG_PWM0_CLK (0x40020000) /**< (PWM0) PWM Clock Register */ 102 #define REG_PWM0_ENA (0x40020004) /**< (PWM0) PWM Enable Register */ 103 #define REG_PWM0_DIS (0x40020008) /**< (PWM0) PWM Disable Register */ 104 #define REG_PWM0_SR (0x4002000C) /**< (PWM0) PWM Status Register */ 105 #define REG_PWM0_IER1 (0x40020010) /**< (PWM0) PWM Interrupt Enable Register 1 */ 106 #define REG_PWM0_IDR1 (0x40020014) /**< (PWM0) PWM Interrupt Disable Register 1 */ 107 #define REG_PWM0_IMR1 (0x40020018) /**< (PWM0) PWM Interrupt Mask Register 1 */ 108 #define REG_PWM0_ISR1 (0x4002001C) /**< (PWM0) PWM Interrupt Status Register 1 */ 109 #define REG_PWM0_SCM (0x40020020) /**< (PWM0) PWM Sync Channels Mode Register */ 110 #define REG_PWM0_DMAR (0x40020024) /**< (PWM0) PWM DMA Register */ 111 #define REG_PWM0_SCUC (0x40020028) /**< (PWM0) PWM Sync Channels Update Control Register */ 112 #define REG_PWM0_SCUP (0x4002002C) /**< (PWM0) PWM Sync Channels Update Period Register */ 113 #define REG_PWM0_SCUPUPD (0x40020030) /**< (PWM0) PWM Sync Channels Update Period Update Register */ 114 #define REG_PWM0_IER2 (0x40020034) /**< (PWM0) PWM Interrupt Enable Register 2 */ 115 #define REG_PWM0_IDR2 (0x40020038) /**< (PWM0) PWM Interrupt Disable Register 2 */ 116 #define REG_PWM0_IMR2 (0x4002003C) /**< (PWM0) PWM Interrupt Mask Register 2 */ 117 #define REG_PWM0_ISR2 (0x40020040) /**< (PWM0) PWM Interrupt Status Register 2 */ 118 #define REG_PWM0_OOV (0x40020044) /**< (PWM0) PWM Output Override Value Register */ 119 #define REG_PWM0_OS (0x40020048) /**< (PWM0) PWM Output Selection Register */ 120 #define REG_PWM0_OSS (0x4002004C) /**< (PWM0) PWM Output Selection Set Register */ 121 #define REG_PWM0_OSC (0x40020050) /**< (PWM0) PWM Output Selection Clear Register */ 122 #define REG_PWM0_OSSUPD (0x40020054) /**< (PWM0) PWM Output Selection Set Update Register */ 123 #define REG_PWM0_OSCUPD (0x40020058) /**< (PWM0) PWM Output Selection Clear Update Register */ 124 #define REG_PWM0_FMR (0x4002005C) /**< (PWM0) PWM Fault Mode Register */ 125 #define REG_PWM0_FSR (0x40020060) /**< (PWM0) PWM Fault Status Register */ 126 #define REG_PWM0_FCR (0x40020064) /**< (PWM0) PWM Fault Clear Register */ 127 #define REG_PWM0_FPV1 (0x40020068) /**< (PWM0) PWM Fault Protection Value Register 1 */ 128 #define REG_PWM0_FPE (0x4002006C) /**< (PWM0) PWM Fault Protection Enable Register */ 129 #define REG_PWM0_ELMR (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ 130 #define REG_PWM0_ELMR0 (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ 131 #define REG_PWM0_ELMR1 (0x40020080) /**< (PWM0) PWM Event Line 0 Mode Register 1 */ 132 #define REG_PWM0_SSPR (0x400200A0) /**< (PWM0) PWM Spread Spectrum Register */ 133 #define REG_PWM0_SSPUP (0x400200A4) /**< (PWM0) PWM Spread Spectrum Update Register */ 134 #define REG_PWM0_SMMR (0x400200B0) /**< (PWM0) PWM Stepper Motor Mode Register */ 135 #define REG_PWM0_FPV2 (0x400200C0) /**< (PWM0) PWM Fault Protection Value 2 Register */ 136 #define REG_PWM0_WPCR (0x400200E4) /**< (PWM0) PWM Write Protection Control Register */ 137 #define REG_PWM0_WPSR (0x400200E8) /**< (PWM0) PWM Write Protection Status Register */ 138 #define REG_PWM0_VERSION (0x400200FC) /**< (PWM0) Version Register */ 139 #define REG_PWM0_CMUPD0 (0x40020400) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ 140 #define REG_PWM0_CMUPD1 (0x40020420) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ 141 #define REG_PWM0_ETRG1 (0x4002042C) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */ 142 #define REG_PWM0_LEBR1 (0x40020430) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ 143 #define REG_PWM0_CMUPD2 (0x40020440) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ 144 #define REG_PWM0_ETRG2 (0x4002044C) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */ 145 #define REG_PWM0_LEBR2 (0x40020450) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ 146 #define REG_PWM0_CMUPD3 (0x40020460) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ 147 148 #else 149 150 #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< (PWM0) PWM Comparison 0 Value Register 0 */ 151 #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */ 152 #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< (PWM0) PWM Comparison 0 Mode Register 0 */ 153 #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */ 154 #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< (PWM0) PWM Comparison 0 Value Register 1 */ 155 #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */ 156 #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< (PWM0) PWM Comparison 0 Mode Register 1 */ 157 #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */ 158 #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< (PWM0) PWM Comparison 0 Value Register 2 */ 159 #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */ 160 #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< (PWM0) PWM Comparison 0 Mode Register 2 */ 161 #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */ 162 #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< (PWM0) PWM Comparison 0 Value Register 3 */ 163 #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */ 164 #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< (PWM0) PWM Comparison 0 Mode Register 3 */ 165 #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */ 166 #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< (PWM0) PWM Comparison 0 Value Register 4 */ 167 #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */ 168 #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< (PWM0) PWM Comparison 0 Mode Register 4 */ 169 #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */ 170 #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< (PWM0) PWM Comparison 0 Value Register 5 */ 171 #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */ 172 #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< (PWM0) PWM Comparison 0 Mode Register 5 */ 173 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ 174 #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< (PWM0) PWM Comparison 0 Value Register 6 */ 175 #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */ 176 #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< (PWM0) PWM Comparison 0 Mode Register 6 */ 177 #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */ 178 #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< (PWM0) PWM Comparison 0 Value Register 7 */ 179 #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */ 180 #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< (PWM0) PWM Comparison 0 Mode Register 7 */ 181 #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */ 182 #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 0 */ 183 #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 0 */ 184 #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */ 185 #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 0 */ 186 #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 0 */ 187 #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 0 */ 188 #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 0 */ 189 #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 0 */ 190 #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 1 */ 191 #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 1 */ 192 #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */ 193 #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 1 */ 194 #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 1 */ 195 #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 1 */ 196 #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 1 */ 197 #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 1 */ 198 #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 2 */ 199 #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 2 */ 200 #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */ 201 #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 2 */ 202 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 2 */ 203 #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 2 */ 204 #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 2 */ 205 #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 2 */ 206 #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 3 */ 207 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 3 */ 208 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */ 209 #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 3 */ 210 #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 3 */ 211 #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 3 */ 212 #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 3 */ 213 #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 3 */ 214 #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< (PWM0) PWM Clock Register */ 215 #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< (PWM0) PWM Enable Register */ 216 #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< (PWM0) PWM Disable Register */ 217 #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< (PWM0) PWM Status Register */ 218 #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< (PWM0) PWM Interrupt Enable Register 1 */ 219 #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< (PWM0) PWM Interrupt Disable Register 1 */ 220 #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< (PWM0) PWM Interrupt Mask Register 1 */ 221 #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< (PWM0) PWM Interrupt Status Register 1 */ 222 #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< (PWM0) PWM Sync Channels Mode Register */ 223 #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< (PWM0) PWM DMA Register */ 224 #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< (PWM0) PWM Sync Channels Update Control Register */ 225 #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< (PWM0) PWM Sync Channels Update Period Register */ 226 #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< (PWM0) PWM Sync Channels Update Period Update Register */ 227 #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< (PWM0) PWM Interrupt Enable Register 2 */ 228 #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< (PWM0) PWM Interrupt Disable Register 2 */ 229 #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< (PWM0) PWM Interrupt Mask Register 2 */ 230 #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< (PWM0) PWM Interrupt Status Register 2 */ 231 #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< (PWM0) PWM Output Override Value Register */ 232 #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< (PWM0) PWM Output Selection Register */ 233 #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< (PWM0) PWM Output Selection Set Register */ 234 #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< (PWM0) PWM Output Selection Clear Register */ 235 #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< (PWM0) PWM Output Selection Set Update Register */ 236 #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< (PWM0) PWM Output Selection Clear Update Register */ 237 #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< (PWM0) PWM Fault Mode Register */ 238 #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< (PWM0) PWM Fault Status Register */ 239 #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< (PWM0) PWM Fault Clear Register */ 240 #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< (PWM0) PWM Fault Protection Value Register 1 */ 241 #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< (PWM0) PWM Fault Protection Enable Register */ 242 #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ 243 #define REG_PWM0_ELMR0 (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ 244 #define REG_PWM0_ELMR1 (*(__IO uint32_t*)0x40020080U) /**< (PWM0) PWM Event Line 0 Mode Register 1 */ 245 #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< (PWM0) PWM Spread Spectrum Register */ 246 #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< (PWM0) PWM Spread Spectrum Update Register */ 247 #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< (PWM0) PWM Stepper Motor Mode Register */ 248 #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< (PWM0) PWM Fault Protection Value 2 Register */ 249 #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< (PWM0) PWM Write Protection Control Register */ 250 #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< (PWM0) PWM Write Protection Status Register */ 251 #define REG_PWM0_VERSION (*(__I uint32_t*)0x400200FCU) /**< (PWM0) Version Register */ 252 #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ 253 #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ 254 #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */ 255 #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ 256 #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ 257 #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */ 258 #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ 259 #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ 260 261 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 262 263 /* ========== Instance Parameter definitions for PWM0 peripheral ========== */ 264 #define PWM0_DMAC_ID_TX 13 265 #define PWM0_INSTANCE_ID 31 266 267 #endif /* _SAMV71_PWM0_INSTANCE_ */ 268
