1 /** 2 * \file 3 * 4 * \brief Instance description for ICM 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_ICM_INSTANCE_H_ 32 #define _SAMV71_ICM_INSTANCE_H_ 33 34 /* ========== Register definition for ICM peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_ICM_CFG (0x40048000) /**< (ICM) Configuration Register */ 38 #define REG_ICM_CTRL (0x40048004) /**< (ICM) Control Register */ 39 #define REG_ICM_SR (0x40048008) /**< (ICM) Status Register */ 40 #define REG_ICM_IER (0x40048010) /**< (ICM) Interrupt Enable Register */ 41 #define REG_ICM_IDR (0x40048014) /**< (ICM) Interrupt Disable Register */ 42 #define REG_ICM_IMR (0x40048018) /**< (ICM) Interrupt Mask Register */ 43 #define REG_ICM_ISR (0x4004801C) /**< (ICM) Interrupt Status Register */ 44 #define REG_ICM_UASR (0x40048020) /**< (ICM) Undefined Access Status Register */ 45 #define REG_ICM_DSCR (0x40048030) /**< (ICM) Region Descriptor Area Start Address Register */ 46 #define REG_ICM_HASH (0x40048034) /**< (ICM) Region Hash Area Start Address Register */ 47 #define REG_ICM_UIHVAL (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */ 48 #define REG_ICM_UIHVAL0 (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */ 49 #define REG_ICM_UIHVAL1 (0x4004803C) /**< (ICM) User Initial Hash Value 0 Register 1 */ 50 #define REG_ICM_UIHVAL2 (0x40048040) /**< (ICM) User Initial Hash Value 0 Register 2 */ 51 #define REG_ICM_UIHVAL3 (0x40048044) /**< (ICM) User Initial Hash Value 0 Register 3 */ 52 #define REG_ICM_UIHVAL4 (0x40048048) /**< (ICM) User Initial Hash Value 0 Register 4 */ 53 #define REG_ICM_UIHVAL5 (0x4004804C) /**< (ICM) User Initial Hash Value 0 Register 5 */ 54 #define REG_ICM_UIHVAL6 (0x40048050) /**< (ICM) User Initial Hash Value 0 Register 6 */ 55 #define REG_ICM_UIHVAL7 (0x40048054) /**< (ICM) User Initial Hash Value 0 Register 7 */ 56 57 #else 58 59 #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< (ICM) Configuration Register */ 60 #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< (ICM) Control Register */ 61 #define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< (ICM) Status Register */ 62 #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< (ICM) Interrupt Enable Register */ 63 #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< (ICM) Interrupt Disable Register */ 64 #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< (ICM) Interrupt Mask Register */ 65 #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< (ICM) Interrupt Status Register */ 66 #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< (ICM) Undefined Access Status Register */ 67 #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< (ICM) Region Descriptor Area Start Address Register */ 68 #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< (ICM) Region Hash Area Start Address Register */ 69 #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */ 70 #define REG_ICM_UIHVAL0 (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */ 71 #define REG_ICM_UIHVAL1 (*(__O uint32_t*)0x4004803CU) /**< (ICM) User Initial Hash Value 0 Register 1 */ 72 #define REG_ICM_UIHVAL2 (*(__O uint32_t*)0x40048040U) /**< (ICM) User Initial Hash Value 0 Register 2 */ 73 #define REG_ICM_UIHVAL3 (*(__O uint32_t*)0x40048044U) /**< (ICM) User Initial Hash Value 0 Register 3 */ 74 #define REG_ICM_UIHVAL4 (*(__O uint32_t*)0x40048048U) /**< (ICM) User Initial Hash Value 0 Register 4 */ 75 #define REG_ICM_UIHVAL5 (*(__O uint32_t*)0x4004804CU) /**< (ICM) User Initial Hash Value 0 Register 5 */ 76 #define REG_ICM_UIHVAL6 (*(__O uint32_t*)0x40048050U) /**< (ICM) User Initial Hash Value 0 Register 6 */ 77 #define REG_ICM_UIHVAL7 (*(__O uint32_t*)0x40048054U) /**< (ICM) User Initial Hash Value 0 Register 7 */ 78 79 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* ========== Instance Parameter definitions for ICM peripheral ========== */ 82 #define ICM_INSTANCE_ID 32 83 84 #endif /* _SAMV71_ICM_INSTANCE_ */ 85
