1 /** 2 * \file 3 * 4 * \brief Instance description for DACC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_DACC_INSTANCE_H_ 32 #define _SAMV71_DACC_INSTANCE_H_ 33 34 /* ========== Register definition for DACC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_DACC_CR (0x40040000) /**< (DACC) Control Register */ 38 #define REG_DACC_MR (0x40040004) /**< (DACC) Mode Register */ 39 #define REG_DACC_TRIGR (0x40040008) /**< (DACC) Trigger Register */ 40 #define REG_DACC_CHER (0x40040010) /**< (DACC) Channel Enable Register */ 41 #define REG_DACC_CHDR (0x40040014) /**< (DACC) Channel Disable Register */ 42 #define REG_DACC_CHSR (0x40040018) /**< (DACC) Channel Status Register */ 43 #define REG_DACC_CDR (0x4004001C) /**< (DACC) Conversion Data Register 0 */ 44 #define REG_DACC_CDR0 (0x4004001C) /**< (DACC) Conversion Data Register 0 */ 45 #define REG_DACC_CDR1 (0x40040020) /**< (DACC) Conversion Data Register 1 */ 46 #define REG_DACC_IER (0x40040024) /**< (DACC) Interrupt Enable Register */ 47 #define REG_DACC_IDR (0x40040028) /**< (DACC) Interrupt Disable Register */ 48 #define REG_DACC_IMR (0x4004002C) /**< (DACC) Interrupt Mask Register */ 49 #define REG_DACC_ISR (0x40040030) /**< (DACC) Interrupt Status Register */ 50 #define REG_DACC_ACR (0x40040094) /**< (DACC) Analog Current Register */ 51 #define REG_DACC_WPMR (0x400400E4) /**< (DACC) Write Protection Mode Register */ 52 #define REG_DACC_WPSR (0x400400E8) /**< (DACC) Write Protection Status Register */ 53 #define REG_DACC_VERSION (0x400400FC) /**< (DACC) Version Register */ 54 55 #else 56 57 #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< (DACC) Control Register */ 58 #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< (DACC) Mode Register */ 59 #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< (DACC) Trigger Register */ 60 #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< (DACC) Channel Enable Register */ 61 #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< (DACC) Channel Disable Register */ 62 #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< (DACC) Channel Status Register */ 63 #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */ 64 #define REG_DACC_CDR0 (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */ 65 #define REG_DACC_CDR1 (*(__O uint32_t*)0x40040020U) /**< (DACC) Conversion Data Register 1 */ 66 #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< (DACC) Interrupt Enable Register */ 67 #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< (DACC) Interrupt Disable Register */ 68 #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< (DACC) Interrupt Mask Register */ 69 #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< (DACC) Interrupt Status Register */ 70 #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< (DACC) Analog Current Register */ 71 #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< (DACC) Write Protection Mode Register */ 72 #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< (DACC) Write Protection Status Register */ 73 #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) /**< (DACC) Version Register */ 74 75 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 /* ========== Instance Parameter definitions for DACC peripheral ========== */ 78 #define DACC_DMAC_ID_TX 30 79 #define DACC_INSTANCE_ID 30 80 81 #endif /* _SAMV71_DACC_INSTANCE_ */ 82
