1 /** 2 * \file 3 * 4 * \brief Instance description for AES 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_AES_INSTANCE_H_ 32 #define _SAMV71_AES_INSTANCE_H_ 33 34 /* ========== Register definition for AES peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_AES_CR (0x4006C000) /**< (AES) Control Register */ 38 #define REG_AES_MR (0x4006C004) /**< (AES) Mode Register */ 39 #define REG_AES_IER (0x4006C010) /**< (AES) Interrupt Enable Register */ 40 #define REG_AES_IDR (0x4006C014) /**< (AES) Interrupt Disable Register */ 41 #define REG_AES_IMR (0x4006C018) /**< (AES) Interrupt Mask Register */ 42 #define REG_AES_ISR (0x4006C01C) /**< (AES) Interrupt Status Register */ 43 #define REG_AES_KEYWR (0x4006C020) /**< (AES) Key Word Register 0 */ 44 #define REG_AES_KEYWR0 (0x4006C020) /**< (AES) Key Word Register 0 */ 45 #define REG_AES_KEYWR1 (0x4006C024) /**< (AES) Key Word Register 1 */ 46 #define REG_AES_KEYWR2 (0x4006C028) /**< (AES) Key Word Register 2 */ 47 #define REG_AES_KEYWR3 (0x4006C02C) /**< (AES) Key Word Register 3 */ 48 #define REG_AES_KEYWR4 (0x4006C030) /**< (AES) Key Word Register 4 */ 49 #define REG_AES_KEYWR5 (0x4006C034) /**< (AES) Key Word Register 5 */ 50 #define REG_AES_KEYWR6 (0x4006C038) /**< (AES) Key Word Register 6 */ 51 #define REG_AES_KEYWR7 (0x4006C03C) /**< (AES) Key Word Register 7 */ 52 #define REG_AES_IDATAR (0x4006C040) /**< (AES) Input Data Register 0 */ 53 #define REG_AES_IDATAR0 (0x4006C040) /**< (AES) Input Data Register 0 */ 54 #define REG_AES_IDATAR1 (0x4006C044) /**< (AES) Input Data Register 1 */ 55 #define REG_AES_IDATAR2 (0x4006C048) /**< (AES) Input Data Register 2 */ 56 #define REG_AES_IDATAR3 (0x4006C04C) /**< (AES) Input Data Register 3 */ 57 #define REG_AES_ODATAR (0x4006C050) /**< (AES) Output Data Register 0 */ 58 #define REG_AES_ODATAR0 (0x4006C050) /**< (AES) Output Data Register 0 */ 59 #define REG_AES_ODATAR1 (0x4006C054) /**< (AES) Output Data Register 1 */ 60 #define REG_AES_ODATAR2 (0x4006C058) /**< (AES) Output Data Register 2 */ 61 #define REG_AES_ODATAR3 (0x4006C05C) /**< (AES) Output Data Register 3 */ 62 #define REG_AES_IVR (0x4006C060) /**< (AES) Initialization Vector Register 0 */ 63 #define REG_AES_IVR0 (0x4006C060) /**< (AES) Initialization Vector Register 0 */ 64 #define REG_AES_IVR1 (0x4006C064) /**< (AES) Initialization Vector Register 1 */ 65 #define REG_AES_IVR2 (0x4006C068) /**< (AES) Initialization Vector Register 2 */ 66 #define REG_AES_IVR3 (0x4006C06C) /**< (AES) Initialization Vector Register 3 */ 67 #define REG_AES_AADLENR (0x4006C070) /**< (AES) Additional Authenticated Data Length Register */ 68 #define REG_AES_CLENR (0x4006C074) /**< (AES) Plaintext/Ciphertext Length Register */ 69 #define REG_AES_GHASHR (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */ 70 #define REG_AES_GHASHR0 (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */ 71 #define REG_AES_GHASHR1 (0x4006C07C) /**< (AES) GCM Intermediate Hash Word Register 1 */ 72 #define REG_AES_GHASHR2 (0x4006C080) /**< (AES) GCM Intermediate Hash Word Register 2 */ 73 #define REG_AES_GHASHR3 (0x4006C084) /**< (AES) GCM Intermediate Hash Word Register 3 */ 74 #define REG_AES_TAGR (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */ 75 #define REG_AES_TAGR0 (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */ 76 #define REG_AES_TAGR1 (0x4006C08C) /**< (AES) GCM Authentication Tag Word Register 1 */ 77 #define REG_AES_TAGR2 (0x4006C090) /**< (AES) GCM Authentication Tag Word Register 2 */ 78 #define REG_AES_TAGR3 (0x4006C094) /**< (AES) GCM Authentication Tag Word Register 3 */ 79 #define REG_AES_CTRR (0x4006C098) /**< (AES) GCM Encryption Counter Value Register */ 80 #define REG_AES_GCMHR (0x4006C09C) /**< (AES) GCM H Word Register 0 */ 81 #define REG_AES_GCMHR0 (0x4006C09C) /**< (AES) GCM H Word Register 0 */ 82 #define REG_AES_GCMHR1 (0x4006C0A0) /**< (AES) GCM H Word Register 1 */ 83 #define REG_AES_GCMHR2 (0x4006C0A4) /**< (AES) GCM H Word Register 2 */ 84 #define REG_AES_GCMHR3 (0x4006C0A8) /**< (AES) GCM H Word Register 3 */ 85 #define REG_AES_VERSION (0x4006C0FC) /**< (AES) Version Register */ 86 87 #else 88 89 #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< (AES) Control Register */ 90 #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< (AES) Mode Register */ 91 #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< (AES) Interrupt Enable Register */ 92 #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< (AES) Interrupt Disable Register */ 93 #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< (AES) Interrupt Mask Register */ 94 #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< (AES) Interrupt Status Register */ 95 #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */ 96 #define REG_AES_KEYWR0 (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */ 97 #define REG_AES_KEYWR1 (*(__O uint32_t*)0x4006C024U) /**< (AES) Key Word Register 1 */ 98 #define REG_AES_KEYWR2 (*(__O uint32_t*)0x4006C028U) /**< (AES) Key Word Register 2 */ 99 #define REG_AES_KEYWR3 (*(__O uint32_t*)0x4006C02CU) /**< (AES) Key Word Register 3 */ 100 #define REG_AES_KEYWR4 (*(__O uint32_t*)0x4006C030U) /**< (AES) Key Word Register 4 */ 101 #define REG_AES_KEYWR5 (*(__O uint32_t*)0x4006C034U) /**< (AES) Key Word Register 5 */ 102 #define REG_AES_KEYWR6 (*(__O uint32_t*)0x4006C038U) /**< (AES) Key Word Register 6 */ 103 #define REG_AES_KEYWR7 (*(__O uint32_t*)0x4006C03CU) /**< (AES) Key Word Register 7 */ 104 #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */ 105 #define REG_AES_IDATAR0 (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */ 106 #define REG_AES_IDATAR1 (*(__O uint32_t*)0x4006C044U) /**< (AES) Input Data Register 1 */ 107 #define REG_AES_IDATAR2 (*(__O uint32_t*)0x4006C048U) /**< (AES) Input Data Register 2 */ 108 #define REG_AES_IDATAR3 (*(__O uint32_t*)0x4006C04CU) /**< (AES) Input Data Register 3 */ 109 #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */ 110 #define REG_AES_ODATAR0 (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */ 111 #define REG_AES_ODATAR1 (*(__I uint32_t*)0x4006C054U) /**< (AES) Output Data Register 1 */ 112 #define REG_AES_ODATAR2 (*(__I uint32_t*)0x4006C058U) /**< (AES) Output Data Register 2 */ 113 #define REG_AES_ODATAR3 (*(__I uint32_t*)0x4006C05CU) /**< (AES) Output Data Register 3 */ 114 #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */ 115 #define REG_AES_IVR0 (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */ 116 #define REG_AES_IVR1 (*(__O uint32_t*)0x4006C064U) /**< (AES) Initialization Vector Register 1 */ 117 #define REG_AES_IVR2 (*(__O uint32_t*)0x4006C068U) /**< (AES) Initialization Vector Register 2 */ 118 #define REG_AES_IVR3 (*(__O uint32_t*)0x4006C06CU) /**< (AES) Initialization Vector Register 3 */ 119 #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< (AES) Additional Authenticated Data Length Register */ 120 #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< (AES) Plaintext/Ciphertext Length Register */ 121 #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */ 122 #define REG_AES_GHASHR0 (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */ 123 #define REG_AES_GHASHR1 (*(__IO uint32_t*)0x4006C07CU) /**< (AES) GCM Intermediate Hash Word Register 1 */ 124 #define REG_AES_GHASHR2 (*(__IO uint32_t*)0x4006C080U) /**< (AES) GCM Intermediate Hash Word Register 2 */ 125 #define REG_AES_GHASHR3 (*(__IO uint32_t*)0x4006C084U) /**< (AES) GCM Intermediate Hash Word Register 3 */ 126 #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */ 127 #define REG_AES_TAGR0 (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */ 128 #define REG_AES_TAGR1 (*(__I uint32_t*)0x4006C08CU) /**< (AES) GCM Authentication Tag Word Register 1 */ 129 #define REG_AES_TAGR2 (*(__I uint32_t*)0x4006C090U) /**< (AES) GCM Authentication Tag Word Register 2 */ 130 #define REG_AES_TAGR3 (*(__I uint32_t*)0x4006C094U) /**< (AES) GCM Authentication Tag Word Register 3 */ 131 #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< (AES) GCM Encryption Counter Value Register */ 132 #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */ 133 #define REG_AES_GCMHR0 (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */ 134 #define REG_AES_GCMHR1 (*(__IO uint32_t*)0x4006C0A0U) /**< (AES) GCM H Word Register 1 */ 135 #define REG_AES_GCMHR2 (*(__IO uint32_t*)0x4006C0A4U) /**< (AES) GCM H Word Register 2 */ 136 #define REG_AES_GCMHR3 (*(__IO uint32_t*)0x4006C0A8U) /**< (AES) GCM H Word Register 3 */ 137 #define REG_AES_VERSION (*(__I uint32_t*)0x4006C0FCU) /**< (AES) Version Register */ 138 139 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 /* ========== Instance Parameter definitions for AES peripheral ========== */ 142 #define AES_DMAC_ID_TX 37 143 #define AES_DMAC_ID_RX 38 144 #define AES_INSTANCE_ID 56 145 146 #endif /* _SAMV71_AES_INSTANCE_ */ 147
