1 /** 2 * \file 3 * 4 * \brief Instance description for USART0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_USART0_INSTANCE_H_ 32 #define _SAME70_USART0_INSTANCE_H_ 33 34 /* ========== Register definition for USART0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_USART0_US_CR (0x40024000) /**< (USART0) Control Register */ 38 #define REG_USART0_US_MR (0x40024004) /**< (USART0) Mode Register */ 39 #define REG_USART0_US_IER (0x40024008) /**< (USART0) Interrupt Enable Register */ 40 #define REG_USART0_US_IDR (0x4002400C) /**< (USART0) Interrupt Disable Register */ 41 #define REG_USART0_US_IMR (0x40024010) /**< (USART0) Interrupt Mask Register */ 42 #define REG_USART0_US_CSR (0x40024014) /**< (USART0) Channel Status Register */ 43 #define REG_USART0_US_RHR (0x40024018) /**< (USART0) Receive Holding Register */ 44 #define REG_USART0_US_THR (0x4002401C) /**< (USART0) Transmit Holding Register */ 45 #define REG_USART0_US_BRGR (0x40024020) /**< (USART0) Baud Rate Generator Register */ 46 #define REG_USART0_US_RTOR (0x40024024) /**< (USART0) Receiver Timeout Register */ 47 #define REG_USART0_US_TTGR (0x40024028) /**< (USART0) Transmitter Timeguard Register */ 48 #define REG_USART0_US_FIDI (0x40024040) /**< (USART0) FI DI Ratio Register */ 49 #define REG_USART0_US_NER (0x40024044) /**< (USART0) Number of Errors Register */ 50 #define REG_USART0_US_IF (0x4002404C) /**< (USART0) IrDA Filter Register */ 51 #define REG_USART0_US_MAN (0x40024050) /**< (USART0) Manchester Configuration Register */ 52 #define REG_USART0_US_LINMR (0x40024054) /**< (USART0) LIN Mode Register */ 53 #define REG_USART0_US_LINIR (0x40024058) /**< (USART0) LIN Identifier Register */ 54 #define REG_USART0_US_LINBRR (0x4002405C) /**< (USART0) LIN Baud Rate Register */ 55 #define REG_USART0_US_LONMR (0x40024060) /**< (USART0) LON Mode Register */ 56 #define REG_USART0_US_LONPR (0x40024064) /**< (USART0) LON Preamble Register */ 57 #define REG_USART0_US_LONDL (0x40024068) /**< (USART0) LON Data Length Register */ 58 #define REG_USART0_US_LONL2HDR (0x4002406C) /**< (USART0) LON L2HDR Register */ 59 #define REG_USART0_US_LONBL (0x40024070) /**< (USART0) LON Backlog Register */ 60 #define REG_USART0_US_LONB1TX (0x40024074) /**< (USART0) LON Beta1 Tx Register */ 61 #define REG_USART0_US_LONB1RX (0x40024078) /**< (USART0) LON Beta1 Rx Register */ 62 #define REG_USART0_US_LONPRIO (0x4002407C) /**< (USART0) LON Priority Register */ 63 #define REG_USART0_US_IDTTX (0x40024080) /**< (USART0) LON IDT Tx Register */ 64 #define REG_USART0_US_IDTRX (0x40024084) /**< (USART0) LON IDT Rx Register */ 65 #define REG_USART0_US_ICDIFF (0x40024088) /**< (USART0) IC DIFF Register */ 66 #define REG_USART0_US_WPMR (0x400240E4) /**< (USART0) Write Protection Mode Register */ 67 #define REG_USART0_US_WPSR (0x400240E8) /**< (USART0) Write Protection Status Register */ 68 69 #else 70 71 #define REG_USART0_US_CR (*(__O uint32_t*)0x40024000U) /**< (USART0) Control Register */ 72 #define REG_USART0_US_MR (*(__IO uint32_t*)0x40024004U) /**< (USART0) Mode Register */ 73 #define REG_USART0_US_IER (*(__O uint32_t*)0x40024008U) /**< (USART0) Interrupt Enable Register */ 74 #define REG_USART0_US_IDR (*(__O uint32_t*)0x4002400CU) /**< (USART0) Interrupt Disable Register */ 75 #define REG_USART0_US_IMR (*(__I uint32_t*)0x40024010U) /**< (USART0) Interrupt Mask Register */ 76 #define REG_USART0_US_CSR (*(__I uint32_t*)0x40024014U) /**< (USART0) Channel Status Register */ 77 #define REG_USART0_US_RHR (*(__I uint32_t*)0x40024018U) /**< (USART0) Receive Holding Register */ 78 #define REG_USART0_US_THR (*(__O uint32_t*)0x4002401CU) /**< (USART0) Transmit Holding Register */ 79 #define REG_USART0_US_BRGR (*(__IO uint32_t*)0x40024020U) /**< (USART0) Baud Rate Generator Register */ 80 #define REG_USART0_US_RTOR (*(__IO uint32_t*)0x40024024U) /**< (USART0) Receiver Timeout Register */ 81 #define REG_USART0_US_TTGR (*(__IO uint32_t*)0x40024028U) /**< (USART0) Transmitter Timeguard Register */ 82 #define REG_USART0_US_FIDI (*(__IO uint32_t*)0x40024040U) /**< (USART0) FI DI Ratio Register */ 83 #define REG_USART0_US_NER (*(__I uint32_t*)0x40024044U) /**< (USART0) Number of Errors Register */ 84 #define REG_USART0_US_IF (*(__IO uint32_t*)0x4002404CU) /**< (USART0) IrDA Filter Register */ 85 #define REG_USART0_US_MAN (*(__IO uint32_t*)0x40024050U) /**< (USART0) Manchester Configuration Register */ 86 #define REG_USART0_US_LINMR (*(__IO uint32_t*)0x40024054U) /**< (USART0) LIN Mode Register */ 87 #define REG_USART0_US_LINIR (*(__IO uint32_t*)0x40024058U) /**< (USART0) LIN Identifier Register */ 88 #define REG_USART0_US_LINBRR (*(__I uint32_t*)0x4002405CU) /**< (USART0) LIN Baud Rate Register */ 89 #define REG_USART0_US_LONMR (*(__IO uint32_t*)0x40024060U) /**< (USART0) LON Mode Register */ 90 #define REG_USART0_US_LONPR (*(__IO uint32_t*)0x40024064U) /**< (USART0) LON Preamble Register */ 91 #define REG_USART0_US_LONDL (*(__IO uint32_t*)0x40024068U) /**< (USART0) LON Data Length Register */ 92 #define REG_USART0_US_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< (USART0) LON L2HDR Register */ 93 #define REG_USART0_US_LONBL (*(__I uint32_t*)0x40024070U) /**< (USART0) LON Backlog Register */ 94 #define REG_USART0_US_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< (USART0) LON Beta1 Tx Register */ 95 #define REG_USART0_US_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< (USART0) LON Beta1 Rx Register */ 96 #define REG_USART0_US_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< (USART0) LON Priority Register */ 97 #define REG_USART0_US_IDTTX (*(__IO uint32_t*)0x40024080U) /**< (USART0) LON IDT Tx Register */ 98 #define REG_USART0_US_IDTRX (*(__IO uint32_t*)0x40024084U) /**< (USART0) LON IDT Rx Register */ 99 #define REG_USART0_US_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< (USART0) IC DIFF Register */ 100 #define REG_USART0_US_WPMR (*(__IO uint32_t*)0x400240E4U) /**< (USART0) Write Protection Mode Register */ 101 #define REG_USART0_US_WPSR (*(__I uint32_t*)0x400240E8U) /**< (USART0) Write Protection Status Register */ 102 103 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 /* ========== Instance Parameter definitions for USART0 peripheral ========== */ 106 #define USART0_DMAC_ID_RX 8 107 #define USART0_DMAC_ID_TX 7 108 #define USART0_INSTANCE_ID 13 109 #define USART0_CLOCK_ID 13 110 #define USART0_USCLKS_MCK 0 /* MCK */ 111 #define USART0_USCLKS_DIV 1 /* MCK/8 */ 112 #define USART0_USCLKS_PCK 2 /* PCK4 */ 113 #define USART0_USCLKS_SCK 3 /* SCK */ 114 115 #endif /* _SAME70_USART0_INSTANCE_ */ 116
