1 /** 2 * \file 3 * 4 * \brief Instance description for I2SC1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_I2SC1_INSTANCE_H_ 32 #define _SAME70_I2SC1_INSTANCE_H_ 33 34 /* ========== Register definition for I2SC1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_I2SC1_CR (0x40090000) /**< (I2SC1) Control Register */ 38 #define REG_I2SC1_MR (0x40090004) /**< (I2SC1) Mode Register */ 39 #define REG_I2SC1_SR (0x40090008) /**< (I2SC1) Status Register */ 40 #define REG_I2SC1_SCR (0x4009000C) /**< (I2SC1) Status Clear Register */ 41 #define REG_I2SC1_SSR (0x40090010) /**< (I2SC1) Status Set Register */ 42 #define REG_I2SC1_IER (0x40090014) /**< (I2SC1) Interrupt Enable Register */ 43 #define REG_I2SC1_IDR (0x40090018) /**< (I2SC1) Interrupt Disable Register */ 44 #define REG_I2SC1_IMR (0x4009001C) /**< (I2SC1) Interrupt Mask Register */ 45 #define REG_I2SC1_RHR (0x40090020) /**< (I2SC1) Receiver Holding Register */ 46 #define REG_I2SC1_THR (0x40090024) /**< (I2SC1) Transmitter Holding Register */ 47 48 #else 49 50 #define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< (I2SC1) Control Register */ 51 #define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< (I2SC1) Mode Register */ 52 #define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< (I2SC1) Status Register */ 53 #define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< (I2SC1) Status Clear Register */ 54 #define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< (I2SC1) Status Set Register */ 55 #define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< (I2SC1) Interrupt Enable Register */ 56 #define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< (I2SC1) Interrupt Disable Register */ 57 #define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< (I2SC1) Interrupt Mask Register */ 58 #define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< (I2SC1) Receiver Holding Register */ 59 #define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< (I2SC1) Transmitter Holding Register */ 60 61 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* ========== Instance Parameter definitions for I2SC1 peripheral ========== */ 64 #define I2SC1_INSTANCE_ID 70 65 #define I2SC1_CLOCK_ID 70 66 #define I2SC1_DMAC_ID_TX_LEFT 46 67 #define I2SC1_DMAC_ID_RX_LEFT 47 68 #define I2SC1_DMAC_ID_TX_RIGHT 50 69 #define I2SC1_DMAC_ID_RX_RIGHT 51 70 71 #endif /* _SAME70_I2SC1_INSTANCE_ */ 72
