1 /** 2 * \file 3 * 4 * \brief Instance description for GMAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_GMAC_INSTANCE_H_ 32 #define _SAME70_GMAC_INSTANCE_H_ 33 34 /* ========== Register definition for GMAC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_GMAC_SAB1 (0x40050088) /**< (GMAC) Specific Address 1 Bottom Register 0 */ 38 #define REG_GMAC_SAT1 (0x4005008C) /**< (GMAC) Specific Address 1 Top Register 0 */ 39 #define REG_GMAC_SAB2 (0x40050090) /**< (GMAC) Specific Address 1 Bottom Register 1 */ 40 #define REG_GMAC_SAT2 (0x40050094) /**< (GMAC) Specific Address 1 Top Register 1 */ 41 #define REG_GMAC_SAB3 (0x40050098) /**< (GMAC) Specific Address 1 Bottom Register 2 */ 42 #define REG_GMAC_SAT3 (0x4005009C) /**< (GMAC) Specific Address 1 Top Register 2 */ 43 #define REG_GMAC_SAB4 (0x400500A0) /**< (GMAC) Specific Address 1 Bottom Register 3 */ 44 #define REG_GMAC_SAT4 (0x400500A4) /**< (GMAC) Specific Address 1 Top Register 3 */ 45 #define REG_GMAC_ST2CW00 (0x40050700) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */ 46 #define REG_GMAC_ST2CW10 (0x40050704) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */ 47 #define REG_GMAC_ST2CW01 (0x40050708) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */ 48 #define REG_GMAC_ST2CW11 (0x4005070C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */ 49 #define REG_GMAC_ST2CW02 (0x40050710) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */ 50 #define REG_GMAC_ST2CW12 (0x40050714) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */ 51 #define REG_GMAC_ST2CW03 (0x40050718) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */ 52 #define REG_GMAC_ST2CW13 (0x4005071C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */ 53 #define REG_GMAC_ST2CW04 (0x40050720) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */ 54 #define REG_GMAC_ST2CW14 (0x40050724) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */ 55 #define REG_GMAC_ST2CW05 (0x40050728) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */ 56 #define REG_GMAC_ST2CW15 (0x4005072C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */ 57 #define REG_GMAC_ST2CW06 (0x40050730) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */ 58 #define REG_GMAC_ST2CW16 (0x40050734) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */ 59 #define REG_GMAC_ST2CW07 (0x40050738) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */ 60 #define REG_GMAC_ST2CW17 (0x4005073C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */ 61 #define REG_GMAC_ST2CW08 (0x40050740) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */ 62 #define REG_GMAC_ST2CW18 (0x40050744) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */ 63 #define REG_GMAC_ST2CW09 (0x40050748) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */ 64 #define REG_GMAC_ST2CW19 (0x4005074C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */ 65 #define REG_GMAC_ST2CW010 (0x40050750) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */ 66 #define REG_GMAC_ST2CW110 (0x40050754) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */ 67 #define REG_GMAC_ST2CW011 (0x40050758) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */ 68 #define REG_GMAC_ST2CW111 (0x4005075C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */ 69 #define REG_GMAC_ST2CW012 (0x40050760) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */ 70 #define REG_GMAC_ST2CW112 (0x40050764) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */ 71 #define REG_GMAC_ST2CW013 (0x40050768) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */ 72 #define REG_GMAC_ST2CW113 (0x4005076C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */ 73 #define REG_GMAC_ST2CW014 (0x40050770) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */ 74 #define REG_GMAC_ST2CW114 (0x40050774) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */ 75 #define REG_GMAC_ST2CW015 (0x40050778) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */ 76 #define REG_GMAC_ST2CW115 (0x4005077C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */ 77 #define REG_GMAC_ST2CW016 (0x40050780) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */ 78 #define REG_GMAC_ST2CW116 (0x40050784) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */ 79 #define REG_GMAC_ST2CW017 (0x40050788) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */ 80 #define REG_GMAC_ST2CW117 (0x4005078C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */ 81 #define REG_GMAC_ST2CW018 (0x40050790) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */ 82 #define REG_GMAC_ST2CW118 (0x40050794) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */ 83 #define REG_GMAC_ST2CW019 (0x40050798) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */ 84 #define REG_GMAC_ST2CW119 (0x4005079C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */ 85 #define REG_GMAC_ST2CW020 (0x400507A0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */ 86 #define REG_GMAC_ST2CW120 (0x400507A4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */ 87 #define REG_GMAC_ST2CW021 (0x400507A8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */ 88 #define REG_GMAC_ST2CW121 (0x400507AC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */ 89 #define REG_GMAC_ST2CW022 (0x400507B0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */ 90 #define REG_GMAC_ST2CW122 (0x400507B4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */ 91 #define REG_GMAC_ST2CW023 (0x400507B8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */ 92 #define REG_GMAC_ST2CW123 (0x400507BC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */ 93 #define REG_GMAC_NCR (0x40050000) /**< (GMAC) Network Control Register */ 94 #define REG_GMAC_NCFGR (0x40050004) /**< (GMAC) Network Configuration Register */ 95 #define REG_GMAC_NSR (0x40050008) /**< (GMAC) Network Status Register */ 96 #define REG_GMAC_UR (0x4005000C) /**< (GMAC) User Register */ 97 #define REG_GMAC_DCFGR (0x40050010) /**< (GMAC) DMA Configuration Register */ 98 #define REG_GMAC_TSR (0x40050014) /**< (GMAC) Transmit Status Register */ 99 #define REG_GMAC_RBQB (0x40050018) /**< (GMAC) Receive Buffer Queue Base Address Register */ 100 #define REG_GMAC_TBQB (0x4005001C) /**< (GMAC) Transmit Buffer Queue Base Address Register */ 101 #define REG_GMAC_RSR (0x40050020) /**< (GMAC) Receive Status Register */ 102 #define REG_GMAC_ISR (0x40050024) /**< (GMAC) Interrupt Status Register */ 103 #define REG_GMAC_IER (0x40050028) /**< (GMAC) Interrupt Enable Register */ 104 #define REG_GMAC_IDR (0x4005002C) /**< (GMAC) Interrupt Disable Register */ 105 #define REG_GMAC_IMR (0x40050030) /**< (GMAC) Interrupt Mask Register */ 106 #define REG_GMAC_MAN (0x40050034) /**< (GMAC) PHY Maintenance Register */ 107 #define REG_GMAC_RPQ (0x40050038) /**< (GMAC) Received Pause Quantum Register */ 108 #define REG_GMAC_TPQ (0x4005003C) /**< (GMAC) Transmit Pause Quantum Register */ 109 #define REG_GMAC_TPSF (0x40050040) /**< (GMAC) TX Partial Store and Forward Register */ 110 #define REG_GMAC_RPSF (0x40050044) /**< (GMAC) RX Partial Store and Forward Register */ 111 #define REG_GMAC_RJFML (0x40050048) /**< (GMAC) RX Jumbo Frame Max Length Register */ 112 #define REG_GMAC_HRB (0x40050080) /**< (GMAC) Hash Register Bottom */ 113 #define REG_GMAC_HRT (0x40050084) /**< (GMAC) Hash Register Top */ 114 #define REG_GMAC_TIDM1 (0x400500A8) /**< (GMAC) Type ID Match 1 Register */ 115 #define REG_GMAC_TIDM2 (0x400500AC) /**< (GMAC) Type ID Match 2 Register */ 116 #define REG_GMAC_TIDM3 (0x400500B0) /**< (GMAC) Type ID Match 3 Register */ 117 #define REG_GMAC_TIDM4 (0x400500B4) /**< (GMAC) Type ID Match 4 Register */ 118 #define REG_GMAC_WOL (0x400500B8) /**< (GMAC) Wake on LAN Register */ 119 #define REG_GMAC_IPGS (0x400500BC) /**< (GMAC) IPG Stretch Register */ 120 #define REG_GMAC_SVLAN (0x400500C0) /**< (GMAC) Stacked VLAN Register */ 121 #define REG_GMAC_TPFCP (0x400500C4) /**< (GMAC) Transmit PFC Pause Register */ 122 #define REG_GMAC_SAMB1 (0x400500C8) /**< (GMAC) Specific Address 1 Mask Bottom Register */ 123 #define REG_GMAC_SAMT1 (0x400500CC) /**< (GMAC) Specific Address 1 Mask Top Register */ 124 #define REG_GMAC_NSC (0x400500DC) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */ 125 #define REG_GMAC_SCL (0x400500E0) /**< (GMAC) 1588 Timer Second Comparison Low Register */ 126 #define REG_GMAC_SCH (0x400500E4) /**< (GMAC) 1588 Timer Second Comparison High Register */ 127 #define REG_GMAC_EFTSH (0x400500E8) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */ 128 #define REG_GMAC_EFRSH (0x400500EC) /**< (GMAC) PTP Event Frame Received Seconds High Register */ 129 #define REG_GMAC_PEFTSH (0x400500F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ 130 #define REG_GMAC_PEFRSH (0x400500F4) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */ 131 #define REG_GMAC_OTLO (0x40050100) /**< (GMAC) Octets Transmitted Low Register */ 132 #define REG_GMAC_OTHI (0x40050104) /**< (GMAC) Octets Transmitted High Register */ 133 #define REG_GMAC_FT (0x40050108) /**< (GMAC) Frames Transmitted Register */ 134 #define REG_GMAC_BCFT (0x4005010C) /**< (GMAC) Broadcast Frames Transmitted Register */ 135 #define REG_GMAC_MFT (0x40050110) /**< (GMAC) Multicast Frames Transmitted Register */ 136 #define REG_GMAC_PFT (0x40050114) /**< (GMAC) Pause Frames Transmitted Register */ 137 #define REG_GMAC_BFT64 (0x40050118) /**< (GMAC) 64 Byte Frames Transmitted Register */ 138 #define REG_GMAC_TBFT127 (0x4005011C) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */ 139 #define REG_GMAC_TBFT255 (0x40050120) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */ 140 #define REG_GMAC_TBFT511 (0x40050124) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */ 141 #define REG_GMAC_TBFT1023 (0x40050128) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */ 142 #define REG_GMAC_TBFT1518 (0x4005012C) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ 143 #define REG_GMAC_GTBFT1518 (0x40050130) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ 144 #define REG_GMAC_TUR (0x40050134) /**< (GMAC) Transmit Underruns Register */ 145 #define REG_GMAC_SCF (0x40050138) /**< (GMAC) Single Collision Frames Register */ 146 #define REG_GMAC_MCF (0x4005013C) /**< (GMAC) Multiple Collision Frames Register */ 147 #define REG_GMAC_EC (0x40050140) /**< (GMAC) Excessive Collisions Register */ 148 #define REG_GMAC_LC (0x40050144) /**< (GMAC) Late Collisions Register */ 149 #define REG_GMAC_DTF (0x40050148) /**< (GMAC) Deferred Transmission Frames Register */ 150 #define REG_GMAC_CSE (0x4005014C) /**< (GMAC) Carrier Sense Errors Register */ 151 #define REG_GMAC_ORLO (0x40050150) /**< (GMAC) Octets Received Low Received Register */ 152 #define REG_GMAC_ORHI (0x40050154) /**< (GMAC) Octets Received High Received Register */ 153 #define REG_GMAC_FR (0x40050158) /**< (GMAC) Frames Received Register */ 154 #define REG_GMAC_BCFR (0x4005015C) /**< (GMAC) Broadcast Frames Received Register */ 155 #define REG_GMAC_MFR (0x40050160) /**< (GMAC) Multicast Frames Received Register */ 156 #define REG_GMAC_PFR (0x40050164) /**< (GMAC) Pause Frames Received Register */ 157 #define REG_GMAC_BFR64 (0x40050168) /**< (GMAC) 64 Byte Frames Received Register */ 158 #define REG_GMAC_TBFR127 (0x4005016C) /**< (GMAC) 65 to 127 Byte Frames Received Register */ 159 #define REG_GMAC_TBFR255 (0x40050170) /**< (GMAC) 128 to 255 Byte Frames Received Register */ 160 #define REG_GMAC_TBFR511 (0x40050174) /**< (GMAC) 256 to 511 Byte Frames Received Register */ 161 #define REG_GMAC_TBFR1023 (0x40050178) /**< (GMAC) 512 to 1023 Byte Frames Received Register */ 162 #define REG_GMAC_TBFR1518 (0x4005017C) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */ 163 #define REG_GMAC_TMXBFR (0x40050180) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */ 164 #define REG_GMAC_UFR (0x40050184) /**< (GMAC) Undersize Frames Received Register */ 165 #define REG_GMAC_OFR (0x40050188) /**< (GMAC) Oversize Frames Received Register */ 166 #define REG_GMAC_JR (0x4005018C) /**< (GMAC) Jabbers Received Register */ 167 #define REG_GMAC_FCSE (0x40050190) /**< (GMAC) Frame Check Sequence Errors Register */ 168 #define REG_GMAC_LFFE (0x40050194) /**< (GMAC) Length Field Frame Errors Register */ 169 #define REG_GMAC_RSE (0x40050198) /**< (GMAC) Receive Symbol Errors Register */ 170 #define REG_GMAC_AE (0x4005019C) /**< (GMAC) Alignment Errors Register */ 171 #define REG_GMAC_RRE (0x400501A0) /**< (GMAC) Receive Resource Errors Register */ 172 #define REG_GMAC_ROE (0x400501A4) /**< (GMAC) Receive Overrun Register */ 173 #define REG_GMAC_IHCE (0x400501A8) /**< (GMAC) IP Header Checksum Errors Register */ 174 #define REG_GMAC_TCE (0x400501AC) /**< (GMAC) TCP Checksum Errors Register */ 175 #define REG_GMAC_UCE (0x400501B0) /**< (GMAC) UDP Checksum Errors Register */ 176 #define REG_GMAC_TISUBN (0x400501BC) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ 177 #define REG_GMAC_TSH (0x400501C0) /**< (GMAC) 1588 Timer Seconds High Register */ 178 #define REG_GMAC_TSL (0x400501D0) /**< (GMAC) 1588 Timer Seconds Low Register */ 179 #define REG_GMAC_TN (0x400501D4) /**< (GMAC) 1588 Timer Nanoseconds Register */ 180 #define REG_GMAC_TA (0x400501D8) /**< (GMAC) 1588 Timer Adjust Register */ 181 #define REG_GMAC_TI (0x400501DC) /**< (GMAC) 1588 Timer Increment Register */ 182 #define REG_GMAC_EFTSL (0x400501E0) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */ 183 #define REG_GMAC_EFTN (0x400501E4) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ 184 #define REG_GMAC_EFRSL (0x400501E8) /**< (GMAC) PTP Event Frame Received Seconds Low Register */ 185 #define REG_GMAC_EFRN (0x400501EC) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */ 186 #define REG_GMAC_PEFTSL (0x400501F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ 187 #define REG_GMAC_PEFTN (0x400501F4) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ 188 #define REG_GMAC_PEFRSL (0x400501F8) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */ 189 #define REG_GMAC_PEFRN (0x400501FC) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ 190 #define REG_GMAC_RXLPI (0x40050270) /**< (GMAC) Received LPI Transitions */ 191 #define REG_GMAC_RXLPITIME (0x40050274) /**< (GMAC) Received LPI Time */ 192 #define REG_GMAC_TXLPI (0x40050278) /**< (GMAC) Transmit LPI Transitions */ 193 #define REG_GMAC_TXLPITIME (0x4005027C) /**< (GMAC) Transmit LPI Time */ 194 #define REG_GMAC_ISRPQ (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */ 195 #define REG_GMAC_ISRPQ0 (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */ 196 #define REG_GMAC_ISRPQ1 (0x40050404) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */ 197 #define REG_GMAC_ISRPQ2 (0x40050408) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */ 198 #define REG_GMAC_ISRPQ3 (0x4005040C) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */ 199 #define REG_GMAC_ISRPQ4 (0x40050410) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */ 200 #define REG_GMAC_TBQBAPQ (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ 201 #define REG_GMAC_TBQBAPQ0 (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */ 202 #define REG_GMAC_TBQBAPQ1 (0x40050444) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */ 203 #define REG_GMAC_TBQBAPQ2 (0x40050448) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */ 204 #define REG_GMAC_TBQBAPQ3 (0x4005044C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */ 205 #define REG_GMAC_TBQBAPQ4 (0x40050450) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */ 206 #define REG_GMAC_RBQBAPQ (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ 207 #define REG_GMAC_RBQBAPQ0 (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */ 208 #define REG_GMAC_RBQBAPQ1 (0x40050484) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */ 209 #define REG_GMAC_RBQBAPQ2 (0x40050488) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */ 210 #define REG_GMAC_RBQBAPQ3 (0x4005048C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */ 211 #define REG_GMAC_RBQBAPQ4 (0x40050490) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */ 212 #define REG_GMAC_RBSRPQ (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */ 213 #define REG_GMAC_RBSRPQ0 (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */ 214 #define REG_GMAC_RBSRPQ1 (0x400504A4) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */ 215 #define REG_GMAC_RBSRPQ2 (0x400504A8) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */ 216 #define REG_GMAC_RBSRPQ3 (0x400504AC) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */ 217 #define REG_GMAC_RBSRPQ4 (0x400504B0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */ 218 #define REG_GMAC_CBSCR (0x400504BC) /**< (GMAC) Credit-Based Shaping Control Register */ 219 #define REG_GMAC_CBSISQA (0x400504C0) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ 220 #define REG_GMAC_CBSISQB (0x400504C4) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ 221 #define REG_GMAC_ST1RPQ (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue */ 222 #define REG_GMAC_ST1RPQ0 (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */ 223 #define REG_GMAC_ST1RPQ1 (0x40050504) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */ 224 #define REG_GMAC_ST1RPQ2 (0x40050508) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */ 225 #define REG_GMAC_ST1RPQ3 (0x4005050C) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */ 226 #define REG_GMAC_ST2RPQ (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue */ 227 #define REG_GMAC_ST2RPQ0 (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */ 228 #define REG_GMAC_ST2RPQ1 (0x40050544) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */ 229 #define REG_GMAC_ST2RPQ2 (0x40050548) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */ 230 #define REG_GMAC_ST2RPQ3 (0x4005054C) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */ 231 #define REG_GMAC_ST2RPQ4 (0x40050550) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */ 232 #define REG_GMAC_ST2RPQ5 (0x40050554) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */ 233 #define REG_GMAC_ST2RPQ6 (0x40050558) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */ 234 #define REG_GMAC_ST2RPQ7 (0x4005055C) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */ 235 #define REG_GMAC_IERPQ (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */ 236 #define REG_GMAC_IERPQ0 (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */ 237 #define REG_GMAC_IERPQ1 (0x40050604) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */ 238 #define REG_GMAC_IERPQ2 (0x40050608) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */ 239 #define REG_GMAC_IERPQ3 (0x4005060C) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */ 240 #define REG_GMAC_IERPQ4 (0x40050610) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */ 241 #define REG_GMAC_IDRPQ (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */ 242 #define REG_GMAC_IDRPQ0 (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */ 243 #define REG_GMAC_IDRPQ1 (0x40050624) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */ 244 #define REG_GMAC_IDRPQ2 (0x40050628) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */ 245 #define REG_GMAC_IDRPQ3 (0x4005062C) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */ 246 #define REG_GMAC_IDRPQ4 (0x40050630) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */ 247 #define REG_GMAC_IMRPQ (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */ 248 #define REG_GMAC_IMRPQ0 (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */ 249 #define REG_GMAC_IMRPQ1 (0x40050644) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */ 250 #define REG_GMAC_IMRPQ2 (0x40050648) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */ 251 #define REG_GMAC_IMRPQ3 (0x4005064C) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */ 252 #define REG_GMAC_IMRPQ4 (0x40050650) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */ 253 #define REG_GMAC_ST2ER (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register */ 254 #define REG_GMAC_ST2ER0 (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register 0 */ 255 #define REG_GMAC_ST2ER1 (0x400506E4) /**< (GMAC) Screening Type 2 Ethertype Register 1 */ 256 #define REG_GMAC_ST2ER2 (0x400506E8) /**< (GMAC) Screening Type 2 Ethertype Register 2 */ 257 #define REG_GMAC_ST2ER3 (0x400506EC) /**< (GMAC) Screening Type 2 Ethertype Register 3 */ 258 259 #else 260 261 #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< (GMAC) Specific Address 1 Bottom Register 0 */ 262 #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< (GMAC) Specific Address 1 Top Register 0 */ 263 #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< (GMAC) Specific Address 1 Bottom Register 1 */ 264 #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< (GMAC) Specific Address 1 Top Register 1 */ 265 #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< (GMAC) Specific Address 1 Bottom Register 2 */ 266 #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< (GMAC) Specific Address 1 Top Register 2 */ 267 #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< (GMAC) Specific Address 1 Bottom Register 3 */ 268 #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< (GMAC) Specific Address 1 Top Register 3 */ 269 #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */ 270 #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */ 271 #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */ 272 #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */ 273 #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */ 274 #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */ 275 #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */ 276 #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */ 277 #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */ 278 #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */ 279 #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */ 280 #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */ 281 #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */ 282 #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */ 283 #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */ 284 #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */ 285 #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */ 286 #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */ 287 #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */ 288 #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */ 289 #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */ 290 #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */ 291 #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */ 292 #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */ 293 #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */ 294 #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */ 295 #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */ 296 #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */ 297 #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */ 298 #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */ 299 #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */ 300 #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */ 301 #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */ 302 #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */ 303 #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */ 304 #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */ 305 #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */ 306 #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */ 307 #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */ 308 #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */ 309 #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */ 310 #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */ 311 #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */ 312 #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */ 313 #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */ 314 #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */ 315 #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */ 316 #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */ 317 #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< (GMAC) Network Control Register */ 318 #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< (GMAC) Network Configuration Register */ 319 #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< (GMAC) Network Status Register */ 320 #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< (GMAC) User Register */ 321 #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< (GMAC) DMA Configuration Register */ 322 #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< (GMAC) Transmit Status Register */ 323 #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< (GMAC) Receive Buffer Queue Base Address Register */ 324 #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< (GMAC) Transmit Buffer Queue Base Address Register */ 325 #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< (GMAC) Receive Status Register */ 326 #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< (GMAC) Interrupt Status Register */ 327 #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< (GMAC) Interrupt Enable Register */ 328 #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< (GMAC) Interrupt Disable Register */ 329 #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< (GMAC) Interrupt Mask Register */ 330 #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< (GMAC) PHY Maintenance Register */ 331 #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< (GMAC) Received Pause Quantum Register */ 332 #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< (GMAC) Transmit Pause Quantum Register */ 333 #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< (GMAC) TX Partial Store and Forward Register */ 334 #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< (GMAC) RX Partial Store and Forward Register */ 335 #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< (GMAC) RX Jumbo Frame Max Length Register */ 336 #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< (GMAC) Hash Register Bottom */ 337 #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< (GMAC) Hash Register Top */ 338 #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< (GMAC) Type ID Match 1 Register */ 339 #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< (GMAC) Type ID Match 2 Register */ 340 #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< (GMAC) Type ID Match 3 Register */ 341 #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< (GMAC) Type ID Match 4 Register */ 342 #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< (GMAC) Wake on LAN Register */ 343 #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< (GMAC) IPG Stretch Register */ 344 #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< (GMAC) Stacked VLAN Register */ 345 #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< (GMAC) Transmit PFC Pause Register */ 346 #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< (GMAC) Specific Address 1 Mask Bottom Register */ 347 #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< (GMAC) Specific Address 1 Mask Top Register */ 348 #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */ 349 #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< (GMAC) 1588 Timer Second Comparison Low Register */ 350 #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< (GMAC) 1588 Timer Second Comparison High Register */ 351 #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */ 352 #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< (GMAC) PTP Event Frame Received Seconds High Register */ 353 #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ 354 #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */ 355 #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< (GMAC) Octets Transmitted Low Register */ 356 #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< (GMAC) Octets Transmitted High Register */ 357 #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< (GMAC) Frames Transmitted Register */ 358 #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< (GMAC) Broadcast Frames Transmitted Register */ 359 #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< (GMAC) Multicast Frames Transmitted Register */ 360 #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< (GMAC) Pause Frames Transmitted Register */ 361 #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< (GMAC) 64 Byte Frames Transmitted Register */ 362 #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */ 363 #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */ 364 #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */ 365 #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */ 366 #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ 367 #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ 368 #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< (GMAC) Transmit Underruns Register */ 369 #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< (GMAC) Single Collision Frames Register */ 370 #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< (GMAC) Multiple Collision Frames Register */ 371 #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< (GMAC) Excessive Collisions Register */ 372 #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< (GMAC) Late Collisions Register */ 373 #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< (GMAC) Deferred Transmission Frames Register */ 374 #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< (GMAC) Carrier Sense Errors Register */ 375 #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< (GMAC) Octets Received Low Received Register */ 376 #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< (GMAC) Octets Received High Received Register */ 377 #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< (GMAC) Frames Received Register */ 378 #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< (GMAC) Broadcast Frames Received Register */ 379 #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< (GMAC) Multicast Frames Received Register */ 380 #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< (GMAC) Pause Frames Received Register */ 381 #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< (GMAC) 64 Byte Frames Received Register */ 382 #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< (GMAC) 65 to 127 Byte Frames Received Register */ 383 #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< (GMAC) 128 to 255 Byte Frames Received Register */ 384 #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< (GMAC) 256 to 511 Byte Frames Received Register */ 385 #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< (GMAC) 512 to 1023 Byte Frames Received Register */ 386 #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */ 387 #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */ 388 #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< (GMAC) Undersize Frames Received Register */ 389 #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< (GMAC) Oversize Frames Received Register */ 390 #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< (GMAC) Jabbers Received Register */ 391 #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< (GMAC) Frame Check Sequence Errors Register */ 392 #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< (GMAC) Length Field Frame Errors Register */ 393 #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< (GMAC) Receive Symbol Errors Register */ 394 #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< (GMAC) Alignment Errors Register */ 395 #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< (GMAC) Receive Resource Errors Register */ 396 #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< (GMAC) Receive Overrun Register */ 397 #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< (GMAC) IP Header Checksum Errors Register */ 398 #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< (GMAC) TCP Checksum Errors Register */ 399 #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< (GMAC) UDP Checksum Errors Register */ 400 #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ 401 #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< (GMAC) 1588 Timer Seconds High Register */ 402 #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< (GMAC) 1588 Timer Seconds Low Register */ 403 #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< (GMAC) 1588 Timer Nanoseconds Register */ 404 #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< (GMAC) 1588 Timer Adjust Register */ 405 #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< (GMAC) 1588 Timer Increment Register */ 406 #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */ 407 #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ 408 #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< (GMAC) PTP Event Frame Received Seconds Low Register */ 409 #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */ 410 #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ 411 #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ 412 #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */ 413 #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ 414 #define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< (GMAC) Received LPI Transitions */ 415 #define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< (GMAC) Received LPI Time */ 416 #define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< (GMAC) Transmit LPI Transitions */ 417 #define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< (GMAC) Transmit LPI Time */ 418 #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */ 419 #define REG_GMAC_ISRPQ0 (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */ 420 #define REG_GMAC_ISRPQ1 (*(__I uint32_t*)0x40050404U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */ 421 #define REG_GMAC_ISRPQ2 (*(__I uint32_t*)0x40050408U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */ 422 #define REG_GMAC_ISRPQ3 (*(__I uint32_t*)0x4005040CU) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */ 423 #define REG_GMAC_ISRPQ4 (*(__I uint32_t*)0x40050410U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */ 424 #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ 425 #define REG_GMAC_TBQBAPQ0 (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */ 426 #define REG_GMAC_TBQBAPQ1 (*(__IO uint32_t*)0x40050444U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */ 427 #define REG_GMAC_TBQBAPQ2 (*(__IO uint32_t*)0x40050448U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */ 428 #define REG_GMAC_TBQBAPQ3 (*(__IO uint32_t*)0x4005044CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */ 429 #define REG_GMAC_TBQBAPQ4 (*(__IO uint32_t*)0x40050450U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */ 430 #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ 431 #define REG_GMAC_RBQBAPQ0 (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */ 432 #define REG_GMAC_RBQBAPQ1 (*(__IO uint32_t*)0x40050484U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */ 433 #define REG_GMAC_RBQBAPQ2 (*(__IO uint32_t*)0x40050488U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */ 434 #define REG_GMAC_RBQBAPQ3 (*(__IO uint32_t*)0x4005048CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */ 435 #define REG_GMAC_RBQBAPQ4 (*(__IO uint32_t*)0x40050490U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */ 436 #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */ 437 #define REG_GMAC_RBSRPQ0 (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */ 438 #define REG_GMAC_RBSRPQ1 (*(__IO uint32_t*)0x400504A4U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */ 439 #define REG_GMAC_RBSRPQ2 (*(__IO uint32_t*)0x400504A8U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */ 440 #define REG_GMAC_RBSRPQ3 (*(__IO uint32_t*)0x400504ACU) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */ 441 #define REG_GMAC_RBSRPQ4 (*(__IO uint32_t*)0x400504B0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */ 442 #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< (GMAC) Credit-Based Shaping Control Register */ 443 #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ 444 #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ 445 #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue */ 446 #define REG_GMAC_ST1RPQ0 (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */ 447 #define REG_GMAC_ST1RPQ1 (*(__IO uint32_t*)0x40050504U) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */ 448 #define REG_GMAC_ST1RPQ2 (*(__IO uint32_t*)0x40050508U) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */ 449 #define REG_GMAC_ST1RPQ3 (*(__IO uint32_t*)0x4005050CU) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */ 450 #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue */ 451 #define REG_GMAC_ST2RPQ0 (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */ 452 #define REG_GMAC_ST2RPQ1 (*(__IO uint32_t*)0x40050544U) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */ 453 #define REG_GMAC_ST2RPQ2 (*(__IO uint32_t*)0x40050548U) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */ 454 #define REG_GMAC_ST2RPQ3 (*(__IO uint32_t*)0x4005054CU) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */ 455 #define REG_GMAC_ST2RPQ4 (*(__IO uint32_t*)0x40050550U) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */ 456 #define REG_GMAC_ST2RPQ5 (*(__IO uint32_t*)0x40050554U) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */ 457 #define REG_GMAC_ST2RPQ6 (*(__IO uint32_t*)0x40050558U) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */ 458 #define REG_GMAC_ST2RPQ7 (*(__IO uint32_t*)0x4005055CU) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */ 459 #define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */ 460 #define REG_GMAC_IERPQ0 (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */ 461 #define REG_GMAC_IERPQ1 (*(__O uint32_t*)0x40050604U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */ 462 #define REG_GMAC_IERPQ2 (*(__O uint32_t*)0x40050608U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */ 463 #define REG_GMAC_IERPQ3 (*(__O uint32_t*)0x4005060CU) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */ 464 #define REG_GMAC_IERPQ4 (*(__O uint32_t*)0x40050610U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */ 465 #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */ 466 #define REG_GMAC_IDRPQ0 (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */ 467 #define REG_GMAC_IDRPQ1 (*(__O uint32_t*)0x40050624U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */ 468 #define REG_GMAC_IDRPQ2 (*(__O uint32_t*)0x40050628U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */ 469 #define REG_GMAC_IDRPQ3 (*(__O uint32_t*)0x4005062CU) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */ 470 #define REG_GMAC_IDRPQ4 (*(__O uint32_t*)0x40050630U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */ 471 #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */ 472 #define REG_GMAC_IMRPQ0 (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */ 473 #define REG_GMAC_IMRPQ1 (*(__IO uint32_t*)0x40050644U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */ 474 #define REG_GMAC_IMRPQ2 (*(__IO uint32_t*)0x40050648U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */ 475 #define REG_GMAC_IMRPQ3 (*(__IO uint32_t*)0x4005064CU) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */ 476 #define REG_GMAC_IMRPQ4 (*(__IO uint32_t*)0x40050650U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */ 477 #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register */ 478 #define REG_GMAC_ST2ER0 (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register 0 */ 479 #define REG_GMAC_ST2ER1 (*(__IO uint32_t*)0x400506E4U) /**< (GMAC) Screening Type 2 Ethertype Register 1 */ 480 #define REG_GMAC_ST2ER2 (*(__IO uint32_t*)0x400506E8U) /**< (GMAC) Screening Type 2 Ethertype Register 2 */ 481 #define REG_GMAC_ST2ER3 (*(__IO uint32_t*)0x400506ECU) /**< (GMAC) Screening Type 2 Ethertype Register 3 */ 482 483 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 484 485 /* ========== Instance Parameter definitions for GMAC peripheral ========== */ 486 #define GMAC_INSTANCE_ID 39 487 #define GMAC_CLOCK_ID 39 488 489 #endif /* _SAME70_GMAC_INSTANCE_ */ 490
