1 /** 2 * \file 3 * 4 * \brief Instance description for UART0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_UART0_INSTANCE_H_ 32 #define _SAME70_UART0_INSTANCE_H_ 33 34 /* ========== Register definition for UART0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_UART0_CR (0x400E0800) /**< (UART0) Control Register */ 38 #define REG_UART0_MR (0x400E0804) /**< (UART0) Mode Register */ 39 #define REG_UART0_IER (0x400E0808) /**< (UART0) Interrupt Enable Register */ 40 #define REG_UART0_IDR (0x400E080C) /**< (UART0) Interrupt Disable Register */ 41 #define REG_UART0_IMR (0x400E0810) /**< (UART0) Interrupt Mask Register */ 42 #define REG_UART0_SR (0x400E0814) /**< (UART0) Status Register */ 43 #define REG_UART0_RHR (0x400E0818) /**< (UART0) Receive Holding Register */ 44 #define REG_UART0_THR (0x400E081C) /**< (UART0) Transmit Holding Register */ 45 #define REG_UART0_BRGR (0x400E0820) /**< (UART0) Baud Rate Generator Register */ 46 #define REG_UART0_CMPR (0x400E0824) /**< (UART0) Comparison Register */ 47 #define REG_UART0_WPMR (0x400E08E4) /**< (UART0) Write Protection Mode Register */ 48 49 #else 50 51 #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */ 52 #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< (UART0) Mode Register */ 53 #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Register */ 54 #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Register */ 55 #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< (UART0) Interrupt Mask Register */ 56 #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< (UART0) Status Register */ 57 #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< (UART0) Receive Holding Register */ 58 #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Register */ 59 #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< (UART0) Baud Rate Generator Register */ 60 #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< (UART0) Comparison Register */ 61 #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< (UART0) Write Protection Mode Register */ 62 63 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 /* ========== Instance Parameter definitions for UART0 peripheral ========== */ 66 #define UART0_DMAC_ID_RX 21 67 #define UART0_DMAC_ID_TX 20 68 #define UART0_INSTANCE_ID 7 69 70 #endif /* _SAME70_UART0_INSTANCE_ */ 71
