1 /** 2 * \file 3 * 4 * \brief Instance description for TWIHS2 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_TWIHS2_INSTANCE_H_ 32 #define _SAME70_TWIHS2_INSTANCE_H_ 33 34 /* ========== Register definition for TWIHS2 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TWIHS2_CR (0x40060000) /**< (TWIHS2) Control Register */ 38 #define REG_TWIHS2_MMR (0x40060004) /**< (TWIHS2) Master Mode Register */ 39 #define REG_TWIHS2_SMR (0x40060008) /**< (TWIHS2) Slave Mode Register */ 40 #define REG_TWIHS2_IADR (0x4006000C) /**< (TWIHS2) Internal Address Register */ 41 #define REG_TWIHS2_CWGR (0x40060010) /**< (TWIHS2) Clock Waveform Generator Register */ 42 #define REG_TWIHS2_SR (0x40060020) /**< (TWIHS2) Status Register */ 43 #define REG_TWIHS2_IER (0x40060024) /**< (TWIHS2) Interrupt Enable Register */ 44 #define REG_TWIHS2_IDR (0x40060028) /**< (TWIHS2) Interrupt Disable Register */ 45 #define REG_TWIHS2_IMR (0x4006002C) /**< (TWIHS2) Interrupt Mask Register */ 46 #define REG_TWIHS2_RHR (0x40060030) /**< (TWIHS2) Receive Holding Register */ 47 #define REG_TWIHS2_THR (0x40060034) /**< (TWIHS2) Transmit Holding Register */ 48 #define REG_TWIHS2_SMBTR (0x40060038) /**< (TWIHS2) SMBus Timing Register */ 49 #define REG_TWIHS2_FILTR (0x40060044) /**< (TWIHS2) Filter Register */ 50 #define REG_TWIHS2_SWMR (0x4006004C) /**< (TWIHS2) SleepWalking Matching Register */ 51 #define REG_TWIHS2_WPMR (0x400600E4) /**< (TWIHS2) Write Protection Mode Register */ 52 #define REG_TWIHS2_WPSR (0x400600E8) /**< (TWIHS2) Write Protection Status Register */ 53 54 #else 55 56 #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< (TWIHS2) Control Register */ 57 #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< (TWIHS2) Master Mode Register */ 58 #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< (TWIHS2) Slave Mode Register */ 59 #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< (TWIHS2) Internal Address Register */ 60 #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< (TWIHS2) Clock Waveform Generator Register */ 61 #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< (TWIHS2) Status Register */ 62 #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< (TWIHS2) Interrupt Enable Register */ 63 #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< (TWIHS2) Interrupt Disable Register */ 64 #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< (TWIHS2) Interrupt Mask Register */ 65 #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< (TWIHS2) Receive Holding Register */ 66 #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< (TWIHS2) Transmit Holding Register */ 67 #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< (TWIHS2) SMBus Timing Register */ 68 #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< (TWIHS2) Filter Register */ 69 #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< (TWIHS2) SleepWalking Matching Register */ 70 #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< (TWIHS2) Write Protection Mode Register */ 71 #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< (TWIHS2) Write Protection Status Register */ 72 73 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* ========== Instance Parameter definitions for TWIHS2 peripheral ========== */ 76 #define TWIHS2_DMAC_ID_RX 19 77 #define TWIHS2_DMAC_ID_TX 18 78 #define TWIHS2_INSTANCE_ID 41 79 80 #endif /* _SAME70_TWIHS2_INSTANCE_ */ 81
