1 /** 2 * \file 3 * 4 * \brief Instance description for TC2 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_TC2_INSTANCE_H_ 32 #define _SAME70_TC2_INSTANCE_H_ 33 34 /* ========== Register definition for TC2 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TC2_CCR0 (0x40014000) /**< (TC2) Channel Control Register (channel = 0) 0 */ 38 #define REG_TC2_CMR0 (0x40014004) /**< (TC2) Channel Mode Register (channel = 0) 0 */ 39 #define REG_TC2_SMMR0 (0x40014008) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */ 40 #define REG_TC2_RAB0 (0x4001400C) /**< (TC2) Register AB (channel = 0) 0 */ 41 #define REG_TC2_CV0 (0x40014010) /**< (TC2) Counter Value (channel = 0) 0 */ 42 #define REG_TC2_RA0 (0x40014014) /**< (TC2) Register A (channel = 0) 0 */ 43 #define REG_TC2_RB0 (0x40014018) /**< (TC2) Register B (channel = 0) 0 */ 44 #define REG_TC2_RC0 (0x4001401C) /**< (TC2) Register C (channel = 0) 0 */ 45 #define REG_TC2_SR0 (0x40014020) /**< (TC2) Status Register (channel = 0) 0 */ 46 #define REG_TC2_IER0 (0x40014024) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */ 47 #define REG_TC2_IDR0 (0x40014028) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */ 48 #define REG_TC2_IMR0 (0x4001402C) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */ 49 #define REG_TC2_EMR0 (0x40014030) /**< (TC2) Extended Mode Register (channel = 0) 0 */ 50 #define REG_TC2_CCR1 (0x40014040) /**< (TC2) Channel Control Register (channel = 0) 1 */ 51 #define REG_TC2_CMR1 (0x40014044) /**< (TC2) Channel Mode Register (channel = 0) 1 */ 52 #define REG_TC2_SMMR1 (0x40014048) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */ 53 #define REG_TC2_RAB1 (0x4001404C) /**< (TC2) Register AB (channel = 0) 1 */ 54 #define REG_TC2_CV1 (0x40014050) /**< (TC2) Counter Value (channel = 0) 1 */ 55 #define REG_TC2_RA1 (0x40014054) /**< (TC2) Register A (channel = 0) 1 */ 56 #define REG_TC2_RB1 (0x40014058) /**< (TC2) Register B (channel = 0) 1 */ 57 #define REG_TC2_RC1 (0x4001405C) /**< (TC2) Register C (channel = 0) 1 */ 58 #define REG_TC2_SR1 (0x40014060) /**< (TC2) Status Register (channel = 0) 1 */ 59 #define REG_TC2_IER1 (0x40014064) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */ 60 #define REG_TC2_IDR1 (0x40014068) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */ 61 #define REG_TC2_IMR1 (0x4001406C) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */ 62 #define REG_TC2_EMR1 (0x40014070) /**< (TC2) Extended Mode Register (channel = 0) 1 */ 63 #define REG_TC2_CCR2 (0x40014080) /**< (TC2) Channel Control Register (channel = 0) 2 */ 64 #define REG_TC2_CMR2 (0x40014084) /**< (TC2) Channel Mode Register (channel = 0) 2 */ 65 #define REG_TC2_SMMR2 (0x40014088) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */ 66 #define REG_TC2_RAB2 (0x4001408C) /**< (TC2) Register AB (channel = 0) 2 */ 67 #define REG_TC2_CV2 (0x40014090) /**< (TC2) Counter Value (channel = 0) 2 */ 68 #define REG_TC2_RA2 (0x40014094) /**< (TC2) Register A (channel = 0) 2 */ 69 #define REG_TC2_RB2 (0x40014098) /**< (TC2) Register B (channel = 0) 2 */ 70 #define REG_TC2_RC2 (0x4001409C) /**< (TC2) Register C (channel = 0) 2 */ 71 #define REG_TC2_SR2 (0x400140A0) /**< (TC2) Status Register (channel = 0) 2 */ 72 #define REG_TC2_IER2 (0x400140A4) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */ 73 #define REG_TC2_IDR2 (0x400140A8) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */ 74 #define REG_TC2_IMR2 (0x400140AC) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */ 75 #define REG_TC2_EMR2 (0x400140B0) /**< (TC2) Extended Mode Register (channel = 0) 2 */ 76 #define REG_TC2_BCR (0x400140C0) /**< (TC2) Block Control Register */ 77 #define REG_TC2_BMR (0x400140C4) /**< (TC2) Block Mode Register */ 78 #define REG_TC2_QIER (0x400140C8) /**< (TC2) QDEC Interrupt Enable Register */ 79 #define REG_TC2_QIDR (0x400140CC) /**< (TC2) QDEC Interrupt Disable Register */ 80 #define REG_TC2_QIMR (0x400140D0) /**< (TC2) QDEC Interrupt Mask Register */ 81 #define REG_TC2_QISR (0x400140D4) /**< (TC2) QDEC Interrupt Status Register */ 82 #define REG_TC2_FMR (0x400140D8) /**< (TC2) Fault Mode Register */ 83 #define REG_TC2_WPMR (0x400140E4) /**< (TC2) Write Protection Mode Register */ 84 85 #else 86 87 #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< (TC2) Channel Control Register (channel = 0) 0 */ 88 #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< (TC2) Channel Mode Register (channel = 0) 0 */ 89 #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */ 90 #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< (TC2) Register AB (channel = 0) 0 */ 91 #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< (TC2) Counter Value (channel = 0) 0 */ 92 #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< (TC2) Register A (channel = 0) 0 */ 93 #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< (TC2) Register B (channel = 0) 0 */ 94 #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< (TC2) Register C (channel = 0) 0 */ 95 #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< (TC2) Status Register (channel = 0) 0 */ 96 #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */ 97 #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */ 98 #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */ 99 #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< (TC2) Extended Mode Register (channel = 0) 0 */ 100 #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< (TC2) Channel Control Register (channel = 0) 1 */ 101 #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< (TC2) Channel Mode Register (channel = 0) 1 */ 102 #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */ 103 #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< (TC2) Register AB (channel = 0) 1 */ 104 #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< (TC2) Counter Value (channel = 0) 1 */ 105 #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< (TC2) Register A (channel = 0) 1 */ 106 #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< (TC2) Register B (channel = 0) 1 */ 107 #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< (TC2) Register C (channel = 0) 1 */ 108 #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< (TC2) Status Register (channel = 0) 1 */ 109 #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */ 110 #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */ 111 #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */ 112 #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< (TC2) Extended Mode Register (channel = 0) 1 */ 113 #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< (TC2) Channel Control Register (channel = 0) 2 */ 114 #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< (TC2) Channel Mode Register (channel = 0) 2 */ 115 #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */ 116 #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< (TC2) Register AB (channel = 0) 2 */ 117 #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< (TC2) Counter Value (channel = 0) 2 */ 118 #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< (TC2) Register A (channel = 0) 2 */ 119 #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< (TC2) Register B (channel = 0) 2 */ 120 #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< (TC2) Register C (channel = 0) 2 */ 121 #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< (TC2) Status Register (channel = 0) 2 */ 122 #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */ 123 #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */ 124 #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */ 125 #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< (TC2) Extended Mode Register (channel = 0) 2 */ 126 #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< (TC2) Block Control Register */ 127 #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< (TC2) Block Mode Register */ 128 #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< (TC2) QDEC Interrupt Enable Register */ 129 #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< (TC2) QDEC Interrupt Disable Register */ 130 #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< (TC2) QDEC Interrupt Mask Register */ 131 #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< (TC2) QDEC Interrupt Status Register */ 132 #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< (TC2) Fault Mode Register */ 133 #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< (TC2) Write Protection Mode Register */ 134 135 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* ========== Instance Parameter definitions for TC2 peripheral ========== */ 138 #define TC2_DMAC_ID_RX 42 139 #define TC2_INSTANCE_ID_CHANNEL0 47 140 #define TC2_INSTANCE_ID_CHANNEL1 48 141 #define TC2_INSTANCE_ID_CHANNEL2 49 142 143 #endif /* _SAME70_TC2_INSTANCE_ */ 144
