1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_TC_COMPONENT_H_ 32 #define _SAME70_TC_COMPONENT_H_ 33 #define _SAME70_TC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Timer Counter 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR TC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define TC_6082 /**< (TC) Module ID */ 46 #define REV_TC ZG /**< (TC) Module revision */ 47 48 /* -------- TC_CCR : (TC Offset: 0x00) (/W 32) Channel Control Register (channel = 0) -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t CLKEN:1; /**< bit: 0 Counter Clock Enable Command */ 54 uint32_t CLKDIS:1; /**< bit: 1 Counter Clock Disable Command */ 55 uint32_t SWTRG:1; /**< bit: 2 Software Trigger Command */ 56 uint32_t :29; /**< bit: 3..31 Reserved */ 57 } bit; /**< Structure used for bit access */ 58 uint32_t reg; /**< Type used for register access */ 59 } TC_CCR_Type; 60 #endif 61 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define TC_CCR_OFFSET (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */ 64 65 #define TC_CCR_CLKEN_Pos 0 /**< (TC_CCR) Counter Clock Enable Command Position */ 66 #define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */ 67 #define TC_CCR_CLKEN TC_CCR_CLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKEN_Msk instead */ 68 #define TC_CCR_CLKDIS_Pos 1 /**< (TC_CCR) Counter Clock Disable Command Position */ 69 #define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */ 70 #define TC_CCR_CLKDIS TC_CCR_CLKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKDIS_Msk instead */ 71 #define TC_CCR_SWTRG_Pos 2 /**< (TC_CCR) Software Trigger Command Position */ 72 #define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */ 73 #define TC_CCR_SWTRG TC_CCR_SWTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_SWTRG_Msk instead */ 74 #define TC_CCR_MASK _U_(0x07) /**< \deprecated (TC_CCR) Register MASK (Use TC_CCR_Msk instead) */ 75 #define TC_CCR_Msk _U_(0x07) /**< (TC_CCR) Register Mask */ 76 77 78 /* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */ 79 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 80 #if COMPONENT_TYPEDEF_STYLE == 'N' 81 typedef union { 82 struct { 83 uint32_t TCCLKS:3; /**< bit: 0..2 Clock Selection */ 84 uint32_t CLKI:1; /**< bit: 3 Clock Invert */ 85 uint32_t BURST:2; /**< bit: 4..5 Burst Signal Selection */ 86 uint32_t LDBSTOP:1; /**< bit: 6 Counter Clock Stopped with RB Loading */ 87 uint32_t LDBDIS:1; /**< bit: 7 Counter Clock Disable with RB Loading */ 88 uint32_t ETRGEDG:2; /**< bit: 8..9 External Trigger Edge Selection */ 89 uint32_t ABETRG:1; /**< bit: 10 TIOAx or TIOBx External Trigger Selection */ 90 uint32_t :3; /**< bit: 11..13 Reserved */ 91 uint32_t CPCTRG:1; /**< bit: 14 RC Compare Trigger Enable */ 92 uint32_t WAVE:1; /**< bit: 15 Waveform Mode */ 93 uint32_t LDRA:2; /**< bit: 16..17 RA Loading Edge Selection */ 94 uint32_t LDRB:2; /**< bit: 18..19 RB Loading Edge Selection */ 95 uint32_t SBSMPLR:3; /**< bit: 20..22 Loading Edge Subsampling Ratio */ 96 uint32_t :9; /**< bit: 23..31 Reserved */ 97 } bit; /**< Structure used for bit access */ 98 uint32_t reg; /**< Type used for register access */ 99 } TC_CMR_Type; 100 #endif 101 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 #define TC_CMR_OFFSET (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */ 104 105 #define TC_CMR_TCCLKS_Pos 0 /**< (TC_CMR) Clock Selection Position */ 106 #define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */ 107 #define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) 108 #define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ 109 #define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ 110 #define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ 111 #define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ 112 #define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ 113 #define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */ 114 #define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */ 115 #define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */ 116 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */ 117 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */ 118 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */ 119 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */ 120 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */ 121 #define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */ 122 #define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */ 123 #define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */ 124 #define TC_CMR_CLKI_Pos 3 /**< (TC_CMR) Clock Invert Position */ 125 #define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */ 126 #define TC_CMR_CLKI TC_CMR_CLKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CLKI_Msk instead */ 127 #define TC_CMR_BURST_Pos 4 /**< (TC_CMR) Burst Signal Selection Position */ 128 #define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */ 129 #define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) 130 #define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ 131 #define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */ 132 #define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */ 133 #define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */ 134 #define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 135 #define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ 136 #define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ 137 #define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ 138 #define TC_CMR_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ 139 #define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ 140 #define TC_CMR_LDBSTOP TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */ 141 #define TC_CMR_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ 142 #define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ 143 #define TC_CMR_LDBDIS TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */ 144 #define TC_CMR_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ 145 #define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ 146 #define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) 147 #define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ 148 #define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ 149 #define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ 150 #define TC_CMR_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */ 151 #define TC_CMR_ETRGEDG_NONE (TC_CMR_ETRGEDG_NONE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 152 #define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ 153 #define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ 154 #define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ 155 #define TC_CMR_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ 156 #define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ 157 #define TC_CMR_ABETRG TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */ 158 #define TC_CMR_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ 159 #define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ 160 #define TC_CMR_CPCTRG TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */ 161 #define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */ 162 #define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ 163 #define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */ 164 #define TC_CMR_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ 165 #define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ 166 #define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)) 167 #define TC_CMR_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */ 168 #define TC_CMR_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ 169 #define TC_CMR_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ 170 #define TC_CMR_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ 171 #define TC_CMR_LDRA_NONE (TC_CMR_LDRA_NONE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) None Position */ 172 #define TC_CMR_LDRA_RISING (TC_CMR_LDRA_RISING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 173 #define TC_CMR_LDRA_FALLING (TC_CMR_LDRA_FALLING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 174 #define TC_CMR_LDRA_EDGE (TC_CMR_LDRA_EDGE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 175 #define TC_CMR_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ 176 #define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ 177 #define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)) 178 #define TC_CMR_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */ 179 #define TC_CMR_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ 180 #define TC_CMR_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ 181 #define TC_CMR_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ 182 #define TC_CMR_LDRB_NONE (TC_CMR_LDRB_NONE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) None Position */ 183 #define TC_CMR_LDRB_RISING (TC_CMR_LDRB_RISING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 184 #define TC_CMR_LDRB_FALLING (TC_CMR_LDRB_FALLING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 185 #define TC_CMR_LDRB_EDGE (TC_CMR_LDRB_EDGE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 186 #define TC_CMR_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ 187 #define TC_CMR_SBSMPLR_Msk (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ 188 #define TC_CMR_SBSMPLR(value) (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)) 189 #define TC_CMR_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */ 190 #define TC_CMR_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */ 191 #define TC_CMR_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */ 192 #define TC_CMR_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */ 193 #define TC_CMR_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */ 194 #define TC_CMR_SBSMPLR_ONE (TC_CMR_SBSMPLR_ONE_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ 195 #define TC_CMR_SBSMPLR_HALF (TC_CMR_SBSMPLR_HALF_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ 196 #define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ 197 #define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ 198 #define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ 199 #define TC_CMR_MASK _U_(0x7FC7FF) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */ 200 #define TC_CMR_Msk _U_(0x7FC7FF) /**< (TC_CMR) Register Mask */ 201 202 /* CAPTURE mode */ 203 #define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ 204 #define TC_CMR_CAPTURE_LDBSTOP_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ 205 #define TC_CMR_CAPTURE_LDBSTOP TC_CMR_CAPTURE_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBSTOP_Msk instead */ 206 #define TC_CMR_CAPTURE_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ 207 #define TC_CMR_CAPTURE_LDBDIS_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ 208 #define TC_CMR_CAPTURE_LDBDIS TC_CMR_CAPTURE_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBDIS_Msk instead */ 209 #define TC_CMR_CAPTURE_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ 210 #define TC_CMR_CAPTURE_ETRGEDG_Msk (_U_(0x3) << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ 211 #define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) 212 #define TC_CMR_CAPTURE_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE The clock is not gated by an external signal. */ 213 #define TC_CMR_CAPTURE_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge */ 214 #define TC_CMR_CAPTURE_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge */ 215 #define TC_CMR_CAPTURE_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge */ 216 #define TC_CMR_CAPTURE_ETRGEDG_NONE (TC_CMR_CAPTURE_ETRGEDG_NONE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 217 #define TC_CMR_CAPTURE_ETRGEDG_RISING (TC_CMR_CAPTURE_ETRGEDG_RISING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ 218 #define TC_CMR_CAPTURE_ETRGEDG_FALLING (TC_CMR_CAPTURE_ETRGEDG_FALLING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ 219 #define TC_CMR_CAPTURE_ETRGEDG_EDGE (TC_CMR_CAPTURE_ETRGEDG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ 220 #define TC_CMR_CAPTURE_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ 221 #define TC_CMR_CAPTURE_ABETRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ 222 #define TC_CMR_CAPTURE_ABETRG TC_CMR_CAPTURE_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_ABETRG_Msk instead */ 223 #define TC_CMR_CAPTURE_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ 224 #define TC_CMR_CAPTURE_CPCTRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ 225 #define TC_CMR_CAPTURE_CPCTRG TC_CMR_CAPTURE_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_CPCTRG_Msk instead */ 226 #define TC_CMR_CAPTURE_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ 227 #define TC_CMR_CAPTURE_LDRA_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ 228 #define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) 229 #define TC_CMR_CAPTURE_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ 230 #define TC_CMR_CAPTURE_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 231 #define TC_CMR_CAPTURE_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 232 #define TC_CMR_CAPTURE_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 233 #define TC_CMR_CAPTURE_LDRA_NONE (TC_CMR_CAPTURE_LDRA_NONE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) None Position */ 234 #define TC_CMR_CAPTURE_LDRA_RISING (TC_CMR_CAPTURE_LDRA_RISING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 235 #define TC_CMR_CAPTURE_LDRA_FALLING (TC_CMR_CAPTURE_LDRA_FALLING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 236 #define TC_CMR_CAPTURE_LDRA_EDGE (TC_CMR_CAPTURE_LDRA_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 237 #define TC_CMR_CAPTURE_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ 238 #define TC_CMR_CAPTURE_LDRB_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ 239 #define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) 240 #define TC_CMR_CAPTURE_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ 241 #define TC_CMR_CAPTURE_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 242 #define TC_CMR_CAPTURE_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 243 #define TC_CMR_CAPTURE_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 244 #define TC_CMR_CAPTURE_LDRB_NONE (TC_CMR_CAPTURE_LDRB_NONE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) None Position */ 245 #define TC_CMR_CAPTURE_LDRB_RISING (TC_CMR_CAPTURE_LDRB_RISING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 246 #define TC_CMR_CAPTURE_LDRB_FALLING (TC_CMR_CAPTURE_LDRB_FALLING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 247 #define TC_CMR_CAPTURE_LDRB_EDGE (TC_CMR_CAPTURE_LDRB_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 248 #define TC_CMR_CAPTURE_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ 249 #define TC_CMR_CAPTURE_SBSMPLR_Msk (_U_(0x7) << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ 250 #define TC_CMR_CAPTURE_SBSMPLR(value) (TC_CMR_CAPTURE_SBSMPLR_Msk & ((value) << TC_CMR_CAPTURE_SBSMPLR_Pos)) 251 #define TC_CMR_CAPTURE_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE Load a Capture Register each selected edge */ 252 #define TC_CMR_CAPTURE_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) CAPTURE Load a Capture Register every 2 selected edges */ 253 #define TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) CAPTURE Load a Capture Register every 4 selected edges */ 254 #define TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) CAPTURE Load a Capture Register every 8 selected edges */ 255 #define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) CAPTURE Load a Capture Register every 16 selected edges */ 256 #define TC_CMR_CAPTURE_SBSMPLR_ONE (TC_CMR_CAPTURE_SBSMPLR_ONE_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ 257 #define TC_CMR_CAPTURE_SBSMPLR_HALF (TC_CMR_CAPTURE_SBSMPLR_HALF_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ 258 #define TC_CMR_CAPTURE_SBSMPLR_FOURTH (TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ 259 #define TC_CMR_CAPTURE_SBSMPLR_EIGHTH (TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ 260 #define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH (TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ 261 #define TC_CMR_CAPTURE_MASK _U_(0x7F47C0) /**< \deprecated (TC_CMR_CAPTURE) Register MASK (Use TC_CMR_CAPTURE_Msk instead) */ 262 #define TC_CMR_CAPTURE_Msk _U_(0x7F47C0) /**< (TC_CMR_CAPTURE) Register Mask */ 263 264 /* WAVEFORM mode */ 265 #define TC_CMR_WAVEFORM_CPCSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RC Compare Position */ 266 #define TC_CMR_WAVEFORM_CPCSTOP_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RC Compare Mask */ 267 #define TC_CMR_WAVEFORM_CPCSTOP TC_CMR_WAVEFORM_CPCSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCSTOP_Msk instead */ 268 #define TC_CMR_WAVEFORM_CPCDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RC Loading Position */ 269 #define TC_CMR_WAVEFORM_CPCDIS_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RC Loading Mask */ 270 #define TC_CMR_WAVEFORM_CPCDIS TC_CMR_WAVEFORM_CPCDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCDIS_Msk instead */ 271 #define TC_CMR_WAVEFORM_EEVTEDG_Pos 8 /**< (TC_CMR) External Event Edge Selection Position */ 272 #define TC_CMR_WAVEFORM_EEVTEDG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) External Event Edge Selection Mask */ 273 #define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) 274 #define TC_CMR_WAVEFORM_EEVTEDG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM None */ 275 #define TC_CMR_WAVEFORM_EEVTEDG_RISING_Val _U_(0x1) /**< (TC_CMR) WAVEFORM Rising edge */ 276 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) WAVEFORM Falling edge */ 277 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM Each edges */ 278 #define TC_CMR_WAVEFORM_EEVTEDG_NONE (TC_CMR_WAVEFORM_EEVTEDG_NONE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) None Position */ 279 #define TC_CMR_WAVEFORM_EEVTEDG_RISING (TC_CMR_WAVEFORM_EEVTEDG_RISING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Rising edge Position */ 280 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING (TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Falling edge Position */ 281 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Each edges Position */ 282 #define TC_CMR_WAVEFORM_EEVT_Pos 10 /**< (TC_CMR) External Event Selection Position */ 283 #define TC_CMR_WAVEFORM_EEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) External Event Selection Mask */ 284 #define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) 285 #define TC_CMR_WAVEFORM_EEVT_TIOB_Val _U_(0x0) /**< (TC_CMR) WAVEFORM TIOB */ 286 #define TC_CMR_WAVEFORM_EEVT_XC0_Val _U_(0x1) /**< (TC_CMR) WAVEFORM XC0 */ 287 #define TC_CMR_WAVEFORM_EEVT_XC1_Val _U_(0x2) /**< (TC_CMR) WAVEFORM XC1 */ 288 #define TC_CMR_WAVEFORM_EEVT_XC2_Val _U_(0x3) /**< (TC_CMR) WAVEFORM XC2 */ 289 #define TC_CMR_WAVEFORM_EEVT_TIOB (TC_CMR_WAVEFORM_EEVT_TIOB_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) TIOB Position */ 290 #define TC_CMR_WAVEFORM_EEVT_XC0 (TC_CMR_WAVEFORM_EEVT_XC0_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC0 Position */ 291 #define TC_CMR_WAVEFORM_EEVT_XC1 (TC_CMR_WAVEFORM_EEVT_XC1_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC1 Position */ 292 #define TC_CMR_WAVEFORM_EEVT_XC2 (TC_CMR_WAVEFORM_EEVT_XC2_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC2 Position */ 293 #define TC_CMR_WAVEFORM_ENETRG_Pos 12 /**< (TC_CMR) External Event Trigger Enable Position */ 294 #define TC_CMR_WAVEFORM_ENETRG_Msk (_U_(0x1) << TC_CMR_WAVEFORM_ENETRG_Pos) /**< (TC_CMR) External Event Trigger Enable Mask */ 295 #define TC_CMR_WAVEFORM_ENETRG TC_CMR_WAVEFORM_ENETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_ENETRG_Msk instead */ 296 #define TC_CMR_WAVEFORM_WAVSEL_Pos 13 /**< (TC_CMR) Waveform Selection Position */ 297 #define TC_CMR_WAVEFORM_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) Waveform Selection Mask */ 298 #define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) 299 #define TC_CMR_WAVEFORM_WAVSEL_UP_Val _U_(0x0) /**< (TC_CMR) WAVEFORM UP mode without automatic trigger on RC Compare */ 300 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val _U_(0x1) /**< (TC_CMR) WAVEFORM UPDOWN mode without automatic trigger on RC Compare */ 301 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val _U_(0x2) /**< (TC_CMR) WAVEFORM UP mode with automatic trigger on RC Compare */ 302 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val _U_(0x3) /**< (TC_CMR) WAVEFORM UPDOWN mode with automatic trigger on RC Compare */ 303 #define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ 304 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ 305 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ 306 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ 307 #define TC_CMR_WAVEFORM_ACPA_Pos 16 /**< (TC_CMR) RA Compare Effect on TIOAx Position */ 308 #define TC_CMR_WAVEFORM_ACPA_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) RA Compare Effect on TIOAx Mask */ 309 #define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) 310 #define TC_CMR_WAVEFORM_ACPA_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 311 #define TC_CMR_WAVEFORM_ACPA_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 312 #define TC_CMR_WAVEFORM_ACPA_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 313 #define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 314 #define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) NONE Position */ 315 #define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) SET Position */ 316 #define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) CLEAR Position */ 317 #define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) TOGGLE Position */ 318 #define TC_CMR_WAVEFORM_ACPC_Pos 18 /**< (TC_CMR) RC Compare Effect on TIOAx Position */ 319 #define TC_CMR_WAVEFORM_ACPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOAx Mask */ 320 #define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) 321 #define TC_CMR_WAVEFORM_ACPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 322 #define TC_CMR_WAVEFORM_ACPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 323 #define TC_CMR_WAVEFORM_ACPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 324 #define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 325 #define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) NONE Position */ 326 #define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) SET Position */ 327 #define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) CLEAR Position */ 328 #define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) TOGGLE Position */ 329 #define TC_CMR_WAVEFORM_AEEVT_Pos 20 /**< (TC_CMR) External Event Effect on TIOAx Position */ 330 #define TC_CMR_WAVEFORM_AEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOAx Mask */ 331 #define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) 332 #define TC_CMR_WAVEFORM_AEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 333 #define TC_CMR_WAVEFORM_AEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 334 #define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 335 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 336 #define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) NONE Position */ 337 #define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) SET Position */ 338 #define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 339 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 340 #define TC_CMR_WAVEFORM_ASWTRG_Pos 22 /**< (TC_CMR) Software Trigger Effect on TIOAx Position */ 341 #define TC_CMR_WAVEFORM_ASWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOAx Mask */ 342 #define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) 343 #define TC_CMR_WAVEFORM_ASWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 344 #define TC_CMR_WAVEFORM_ASWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 345 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 346 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 347 #define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) NONE Position */ 348 #define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) SET Position */ 349 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 350 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 351 #define TC_CMR_WAVEFORM_BCPB_Pos 24 /**< (TC_CMR) RB Compare Effect on TIOBx Position */ 352 #define TC_CMR_WAVEFORM_BCPB_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) RB Compare Effect on TIOBx Mask */ 353 #define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) 354 #define TC_CMR_WAVEFORM_BCPB_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 355 #define TC_CMR_WAVEFORM_BCPB_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 356 #define TC_CMR_WAVEFORM_BCPB_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 357 #define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 358 #define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) NONE Position */ 359 #define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) SET Position */ 360 #define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) CLEAR Position */ 361 #define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) TOGGLE Position */ 362 #define TC_CMR_WAVEFORM_BCPC_Pos 26 /**< (TC_CMR) RC Compare Effect on TIOBx Position */ 363 #define TC_CMR_WAVEFORM_BCPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOBx Mask */ 364 #define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) 365 #define TC_CMR_WAVEFORM_BCPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 366 #define TC_CMR_WAVEFORM_BCPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 367 #define TC_CMR_WAVEFORM_BCPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 368 #define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 369 #define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) NONE Position */ 370 #define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) SET Position */ 371 #define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) CLEAR Position */ 372 #define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) TOGGLE Position */ 373 #define TC_CMR_WAVEFORM_BEEVT_Pos 28 /**< (TC_CMR) External Event Effect on TIOBx Position */ 374 #define TC_CMR_WAVEFORM_BEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOBx Mask */ 375 #define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) 376 #define TC_CMR_WAVEFORM_BEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 377 #define TC_CMR_WAVEFORM_BEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 378 #define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 379 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 380 #define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) NONE Position */ 381 #define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) SET Position */ 382 #define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 383 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 384 #define TC_CMR_WAVEFORM_BSWTRG_Pos 30 /**< (TC_CMR) Software Trigger Effect on TIOBx Position */ 385 #define TC_CMR_WAVEFORM_BSWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOBx Mask */ 386 #define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) 387 #define TC_CMR_WAVEFORM_BSWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ 388 #define TC_CMR_WAVEFORM_BSWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ 389 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ 390 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ 391 #define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) NONE Position */ 392 #define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) SET Position */ 393 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 394 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 395 #define TC_CMR_WAVEFORM_MASK _U_(0xFFFF7FC0) /**< \deprecated (TC_CMR_WAVEFORM) Register MASK (Use TC_CMR_WAVEFORM_Msk instead) */ 396 #define TC_CMR_WAVEFORM_Msk _U_(0xFFFF7FC0) /**< (TC_CMR_WAVEFORM) Register Mask */ 397 398 /* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */ 399 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 400 #if COMPONENT_TYPEDEF_STYLE == 'N' 401 typedef union { 402 struct { 403 uint32_t GCEN:1; /**< bit: 0 Gray Count Enable */ 404 uint32_t DOWN:1; /**< bit: 1 Down Count */ 405 uint32_t :30; /**< bit: 2..31 Reserved */ 406 } bit; /**< Structure used for bit access */ 407 uint32_t reg; /**< Type used for register access */ 408 } TC_SMMR_Type; 409 #endif 410 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 411 412 #define TC_SMMR_OFFSET (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */ 413 414 #define TC_SMMR_GCEN_Pos 0 /**< (TC_SMMR) Gray Count Enable Position */ 415 #define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */ 416 #define TC_SMMR_GCEN TC_SMMR_GCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_GCEN_Msk instead */ 417 #define TC_SMMR_DOWN_Pos 1 /**< (TC_SMMR) Down Count Position */ 418 #define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */ 419 #define TC_SMMR_DOWN TC_SMMR_DOWN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_DOWN_Msk instead */ 420 #define TC_SMMR_MASK _U_(0x03) /**< \deprecated (TC_SMMR) Register MASK (Use TC_SMMR_Msk instead) */ 421 #define TC_SMMR_Msk _U_(0x03) /**< (TC_SMMR) Register Mask */ 422 423 424 /* -------- TC_RAB : (TC Offset: 0x0c) (R/ 32) Register AB (channel = 0) -------- */ 425 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 426 #if COMPONENT_TYPEDEF_STYLE == 'N' 427 typedef union { 428 struct { 429 uint32_t RAB:32; /**< bit: 0..31 Register A or Register B */ 430 } bit; /**< Structure used for bit access */ 431 uint32_t reg; /**< Type used for register access */ 432 } TC_RAB_Type; 433 #endif 434 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define TC_RAB_OFFSET (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */ 437 438 #define TC_RAB_RAB_Pos 0 /**< (TC_RAB) Register A or Register B Position */ 439 #define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */ 440 #define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos)) 441 #define TC_RAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RAB) Register MASK (Use TC_RAB_Msk instead) */ 442 #define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */ 443 444 445 /* -------- TC_CV : (TC Offset: 0x10) (R/ 32) Counter Value (channel = 0) -------- */ 446 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 447 #if COMPONENT_TYPEDEF_STYLE == 'N' 448 typedef union { 449 struct { 450 uint32_t CV:32; /**< bit: 0..31 Counter Value */ 451 } bit; /**< Structure used for bit access */ 452 uint32_t reg; /**< Type used for register access */ 453 } TC_CV_Type; 454 #endif 455 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 456 457 #define TC_CV_OFFSET (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */ 458 459 #define TC_CV_CV_Pos 0 /**< (TC_CV) Counter Value Position */ 460 #define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */ 461 #define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) 462 #define TC_CV_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_CV) Register MASK (Use TC_CV_Msk instead) */ 463 #define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */ 464 465 466 /* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */ 467 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 468 #if COMPONENT_TYPEDEF_STYLE == 'N' 469 typedef union { 470 struct { 471 uint32_t RA:32; /**< bit: 0..31 Register A */ 472 } bit; /**< Structure used for bit access */ 473 uint32_t reg; /**< Type used for register access */ 474 } TC_RA_Type; 475 #endif 476 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 477 478 #define TC_RA_OFFSET (0x14) /**< (TC_RA) Register A (channel = 0) Offset */ 479 480 #define TC_RA_RA_Pos 0 /**< (TC_RA) Register A Position */ 481 #define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */ 482 #define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) 483 #define TC_RA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RA) Register MASK (Use TC_RA_Msk instead) */ 484 #define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */ 485 486 487 /* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */ 488 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 489 #if COMPONENT_TYPEDEF_STYLE == 'N' 490 typedef union { 491 struct { 492 uint32_t RB:32; /**< bit: 0..31 Register B */ 493 } bit; /**< Structure used for bit access */ 494 uint32_t reg; /**< Type used for register access */ 495 } TC_RB_Type; 496 #endif 497 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 498 499 #define TC_RB_OFFSET (0x18) /**< (TC_RB) Register B (channel = 0) Offset */ 500 501 #define TC_RB_RB_Pos 0 /**< (TC_RB) Register B Position */ 502 #define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */ 503 #define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) 504 #define TC_RB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RB) Register MASK (Use TC_RB_Msk instead) */ 505 #define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */ 506 507 508 /* -------- TC_RC : (TC Offset: 0x1c) (R/W 32) Register C (channel = 0) -------- */ 509 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 510 #if COMPONENT_TYPEDEF_STYLE == 'N' 511 typedef union { 512 struct { 513 uint32_t RC:32; /**< bit: 0..31 Register C */ 514 } bit; /**< Structure used for bit access */ 515 uint32_t reg; /**< Type used for register access */ 516 } TC_RC_Type; 517 #endif 518 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 519 520 #define TC_RC_OFFSET (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */ 521 522 #define TC_RC_RC_Pos 0 /**< (TC_RC) Register C Position */ 523 #define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */ 524 #define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) 525 #define TC_RC_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RC) Register MASK (Use TC_RC_Msk instead) */ 526 #define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */ 527 528 529 /* -------- TC_SR : (TC Offset: 0x20) (R/ 32) Status Register (channel = 0) -------- */ 530 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 531 #if COMPONENT_TYPEDEF_STYLE == 'N' 532 typedef union { 533 struct { 534 uint32_t COVFS:1; /**< bit: 0 Counter Overflow Status (cleared on read) */ 535 uint32_t LOVRS:1; /**< bit: 1 Load Overrun Status (cleared on read) */ 536 uint32_t CPAS:1; /**< bit: 2 RA Compare Status (cleared on read) */ 537 uint32_t CPBS:1; /**< bit: 3 RB Compare Status (cleared on read) */ 538 uint32_t CPCS:1; /**< bit: 4 RC Compare Status (cleared on read) */ 539 uint32_t LDRAS:1; /**< bit: 5 RA Loading Status (cleared on read) */ 540 uint32_t LDRBS:1; /**< bit: 6 RB Loading Status (cleared on read) */ 541 uint32_t ETRGS:1; /**< bit: 7 External Trigger Status (cleared on read) */ 542 uint32_t :8; /**< bit: 8..15 Reserved */ 543 uint32_t CLKSTA:1; /**< bit: 16 Clock Enabling Status */ 544 uint32_t MTIOA:1; /**< bit: 17 TIOAx Mirror */ 545 uint32_t MTIOB:1; /**< bit: 18 TIOBx Mirror */ 546 uint32_t :13; /**< bit: 19..31 Reserved */ 547 } bit; /**< Structure used for bit access */ 548 uint32_t reg; /**< Type used for register access */ 549 } TC_SR_Type; 550 #endif 551 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 552 553 #define TC_SR_OFFSET (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */ 554 555 #define TC_SR_COVFS_Pos 0 /**< (TC_SR) Counter Overflow Status (cleared on read) Position */ 556 #define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */ 557 #define TC_SR_COVFS TC_SR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_COVFS_Msk instead */ 558 #define TC_SR_LOVRS_Pos 1 /**< (TC_SR) Load Overrun Status (cleared on read) Position */ 559 #define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */ 560 #define TC_SR_LOVRS TC_SR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LOVRS_Msk instead */ 561 #define TC_SR_CPAS_Pos 2 /**< (TC_SR) RA Compare Status (cleared on read) Position */ 562 #define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */ 563 #define TC_SR_CPAS TC_SR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPAS_Msk instead */ 564 #define TC_SR_CPBS_Pos 3 /**< (TC_SR) RB Compare Status (cleared on read) Position */ 565 #define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */ 566 #define TC_SR_CPBS TC_SR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPBS_Msk instead */ 567 #define TC_SR_CPCS_Pos 4 /**< (TC_SR) RC Compare Status (cleared on read) Position */ 568 #define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */ 569 #define TC_SR_CPCS TC_SR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPCS_Msk instead */ 570 #define TC_SR_LDRAS_Pos 5 /**< (TC_SR) RA Loading Status (cleared on read) Position */ 571 #define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */ 572 #define TC_SR_LDRAS TC_SR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRAS_Msk instead */ 573 #define TC_SR_LDRBS_Pos 6 /**< (TC_SR) RB Loading Status (cleared on read) Position */ 574 #define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */ 575 #define TC_SR_LDRBS TC_SR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRBS_Msk instead */ 576 #define TC_SR_ETRGS_Pos 7 /**< (TC_SR) External Trigger Status (cleared on read) Position */ 577 #define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */ 578 #define TC_SR_ETRGS TC_SR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_ETRGS_Msk instead */ 579 #define TC_SR_CLKSTA_Pos 16 /**< (TC_SR) Clock Enabling Status Position */ 580 #define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */ 581 #define TC_SR_CLKSTA TC_SR_CLKSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CLKSTA_Msk instead */ 582 #define TC_SR_MTIOA_Pos 17 /**< (TC_SR) TIOAx Mirror Position */ 583 #define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */ 584 #define TC_SR_MTIOA TC_SR_MTIOA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOA_Msk instead */ 585 #define TC_SR_MTIOB_Pos 18 /**< (TC_SR) TIOBx Mirror Position */ 586 #define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */ 587 #define TC_SR_MTIOB TC_SR_MTIOB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOB_Msk instead */ 588 #define TC_SR_MASK _U_(0x700FF) /**< \deprecated (TC_SR) Register MASK (Use TC_SR_Msk instead) */ 589 #define TC_SR_Msk _U_(0x700FF) /**< (TC_SR) Register Mask */ 590 591 592 /* -------- TC_IER : (TC Offset: 0x24) (/W 32) Interrupt Enable Register (channel = 0) -------- */ 593 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 594 #if COMPONENT_TYPEDEF_STYLE == 'N' 595 typedef union { 596 struct { 597 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 598 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 599 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 600 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 601 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 602 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 603 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 604 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 605 uint32_t :24; /**< bit: 8..31 Reserved */ 606 } bit; /**< Structure used for bit access */ 607 uint32_t reg; /**< Type used for register access */ 608 } TC_IER_Type; 609 #endif 610 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 611 612 #define TC_IER_OFFSET (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */ 613 614 #define TC_IER_COVFS_Pos 0 /**< (TC_IER) Counter Overflow Position */ 615 #define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */ 616 #define TC_IER_COVFS TC_IER_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_COVFS_Msk instead */ 617 #define TC_IER_LOVRS_Pos 1 /**< (TC_IER) Load Overrun Position */ 618 #define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */ 619 #define TC_IER_LOVRS TC_IER_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LOVRS_Msk instead */ 620 #define TC_IER_CPAS_Pos 2 /**< (TC_IER) RA Compare Position */ 621 #define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */ 622 #define TC_IER_CPAS TC_IER_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPAS_Msk instead */ 623 #define TC_IER_CPBS_Pos 3 /**< (TC_IER) RB Compare Position */ 624 #define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */ 625 #define TC_IER_CPBS TC_IER_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPBS_Msk instead */ 626 #define TC_IER_CPCS_Pos 4 /**< (TC_IER) RC Compare Position */ 627 #define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */ 628 #define TC_IER_CPCS TC_IER_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPCS_Msk instead */ 629 #define TC_IER_LDRAS_Pos 5 /**< (TC_IER) RA Loading Position */ 630 #define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */ 631 #define TC_IER_LDRAS TC_IER_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRAS_Msk instead */ 632 #define TC_IER_LDRBS_Pos 6 /**< (TC_IER) RB Loading Position */ 633 #define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */ 634 #define TC_IER_LDRBS TC_IER_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRBS_Msk instead */ 635 #define TC_IER_ETRGS_Pos 7 /**< (TC_IER) External Trigger Position */ 636 #define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */ 637 #define TC_IER_ETRGS TC_IER_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_ETRGS_Msk instead */ 638 #define TC_IER_MASK _U_(0xFF) /**< \deprecated (TC_IER) Register MASK (Use TC_IER_Msk instead) */ 639 #define TC_IER_Msk _U_(0xFF) /**< (TC_IER) Register Mask */ 640 641 642 /* -------- TC_IDR : (TC Offset: 0x28) (/W 32) Interrupt Disable Register (channel = 0) -------- */ 643 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 644 #if COMPONENT_TYPEDEF_STYLE == 'N' 645 typedef union { 646 struct { 647 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 648 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 649 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 650 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 651 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 652 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 653 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 654 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 655 uint32_t :24; /**< bit: 8..31 Reserved */ 656 } bit; /**< Structure used for bit access */ 657 uint32_t reg; /**< Type used for register access */ 658 } TC_IDR_Type; 659 #endif 660 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 661 662 #define TC_IDR_OFFSET (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */ 663 664 #define TC_IDR_COVFS_Pos 0 /**< (TC_IDR) Counter Overflow Position */ 665 #define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */ 666 #define TC_IDR_COVFS TC_IDR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_COVFS_Msk instead */ 667 #define TC_IDR_LOVRS_Pos 1 /**< (TC_IDR) Load Overrun Position */ 668 #define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */ 669 #define TC_IDR_LOVRS TC_IDR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LOVRS_Msk instead */ 670 #define TC_IDR_CPAS_Pos 2 /**< (TC_IDR) RA Compare Position */ 671 #define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */ 672 #define TC_IDR_CPAS TC_IDR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPAS_Msk instead */ 673 #define TC_IDR_CPBS_Pos 3 /**< (TC_IDR) RB Compare Position */ 674 #define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */ 675 #define TC_IDR_CPBS TC_IDR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPBS_Msk instead */ 676 #define TC_IDR_CPCS_Pos 4 /**< (TC_IDR) RC Compare Position */ 677 #define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */ 678 #define TC_IDR_CPCS TC_IDR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPCS_Msk instead */ 679 #define TC_IDR_LDRAS_Pos 5 /**< (TC_IDR) RA Loading Position */ 680 #define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */ 681 #define TC_IDR_LDRAS TC_IDR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRAS_Msk instead */ 682 #define TC_IDR_LDRBS_Pos 6 /**< (TC_IDR) RB Loading Position */ 683 #define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */ 684 #define TC_IDR_LDRBS TC_IDR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRBS_Msk instead */ 685 #define TC_IDR_ETRGS_Pos 7 /**< (TC_IDR) External Trigger Position */ 686 #define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */ 687 #define TC_IDR_ETRGS TC_IDR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_ETRGS_Msk instead */ 688 #define TC_IDR_MASK _U_(0xFF) /**< \deprecated (TC_IDR) Register MASK (Use TC_IDR_Msk instead) */ 689 #define TC_IDR_Msk _U_(0xFF) /**< (TC_IDR) Register Mask */ 690 691 692 /* -------- TC_IMR : (TC Offset: 0x2c) (R/ 32) Interrupt Mask Register (channel = 0) -------- */ 693 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 694 #if COMPONENT_TYPEDEF_STYLE == 'N' 695 typedef union { 696 struct { 697 uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ 698 uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ 699 uint32_t CPAS:1; /**< bit: 2 RA Compare */ 700 uint32_t CPBS:1; /**< bit: 3 RB Compare */ 701 uint32_t CPCS:1; /**< bit: 4 RC Compare */ 702 uint32_t LDRAS:1; /**< bit: 5 RA Loading */ 703 uint32_t LDRBS:1; /**< bit: 6 RB Loading */ 704 uint32_t ETRGS:1; /**< bit: 7 External Trigger */ 705 uint32_t :24; /**< bit: 8..31 Reserved */ 706 } bit; /**< Structure used for bit access */ 707 uint32_t reg; /**< Type used for register access */ 708 } TC_IMR_Type; 709 #endif 710 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 711 712 #define TC_IMR_OFFSET (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */ 713 714 #define TC_IMR_COVFS_Pos 0 /**< (TC_IMR) Counter Overflow Position */ 715 #define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */ 716 #define TC_IMR_COVFS TC_IMR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_COVFS_Msk instead */ 717 #define TC_IMR_LOVRS_Pos 1 /**< (TC_IMR) Load Overrun Position */ 718 #define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */ 719 #define TC_IMR_LOVRS TC_IMR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LOVRS_Msk instead */ 720 #define TC_IMR_CPAS_Pos 2 /**< (TC_IMR) RA Compare Position */ 721 #define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */ 722 #define TC_IMR_CPAS TC_IMR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPAS_Msk instead */ 723 #define TC_IMR_CPBS_Pos 3 /**< (TC_IMR) RB Compare Position */ 724 #define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */ 725 #define TC_IMR_CPBS TC_IMR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPBS_Msk instead */ 726 #define TC_IMR_CPCS_Pos 4 /**< (TC_IMR) RC Compare Position */ 727 #define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */ 728 #define TC_IMR_CPCS TC_IMR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPCS_Msk instead */ 729 #define TC_IMR_LDRAS_Pos 5 /**< (TC_IMR) RA Loading Position */ 730 #define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */ 731 #define TC_IMR_LDRAS TC_IMR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRAS_Msk instead */ 732 #define TC_IMR_LDRBS_Pos 6 /**< (TC_IMR) RB Loading Position */ 733 #define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */ 734 #define TC_IMR_LDRBS TC_IMR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRBS_Msk instead */ 735 #define TC_IMR_ETRGS_Pos 7 /**< (TC_IMR) External Trigger Position */ 736 #define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */ 737 #define TC_IMR_ETRGS TC_IMR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_ETRGS_Msk instead */ 738 #define TC_IMR_MASK _U_(0xFF) /**< \deprecated (TC_IMR) Register MASK (Use TC_IMR_Msk instead) */ 739 #define TC_IMR_Msk _U_(0xFF) /**< (TC_IMR) Register Mask */ 740 741 742 /* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */ 743 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 744 #if COMPONENT_TYPEDEF_STYLE == 'N' 745 typedef union { 746 struct { 747 uint32_t TRIGSRCA:2; /**< bit: 0..1 Trigger Source for Input A */ 748 uint32_t :2; /**< bit: 2..3 Reserved */ 749 uint32_t TRIGSRCB:2; /**< bit: 4..5 Trigger Source for Input B */ 750 uint32_t :2; /**< bit: 6..7 Reserved */ 751 uint32_t NODIVCLK:1; /**< bit: 8 No Divided Clock */ 752 uint32_t :23; /**< bit: 9..31 Reserved */ 753 } bit; /**< Structure used for bit access */ 754 uint32_t reg; /**< Type used for register access */ 755 } TC_EMR_Type; 756 #endif 757 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 758 759 #define TC_EMR_OFFSET (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */ 760 761 #define TC_EMR_TRIGSRCA_Pos 0 /**< (TC_EMR) Trigger Source for Input A Position */ 762 #define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */ 763 #define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)) 764 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ 765 #define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */ 766 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */ 767 #define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */ 768 #define TC_EMR_TRIGSRCB_Pos 4 /**< (TC_EMR) Trigger Source for Input B Position */ 769 #define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */ 770 #define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)) 771 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ 772 #define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */ 773 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */ 774 #define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */ 775 #define TC_EMR_NODIVCLK_Pos 8 /**< (TC_EMR) No Divided Clock Position */ 776 #define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */ 777 #define TC_EMR_NODIVCLK TC_EMR_NODIVCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_EMR_NODIVCLK_Msk instead */ 778 #define TC_EMR_MASK _U_(0x133) /**< \deprecated (TC_EMR) Register MASK (Use TC_EMR_Msk instead) */ 779 #define TC_EMR_Msk _U_(0x133) /**< (TC_EMR) Register Mask */ 780 781 782 /* -------- TC_BCR : (TC Offset: 0xc0) (/W 32) Block Control Register -------- */ 783 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 784 #if COMPONENT_TYPEDEF_STYLE == 'N' 785 typedef union { 786 struct { 787 uint32_t SYNC:1; /**< bit: 0 Synchro Command */ 788 uint32_t :31; /**< bit: 1..31 Reserved */ 789 } bit; /**< Structure used for bit access */ 790 uint32_t reg; /**< Type used for register access */ 791 } TC_BCR_Type; 792 #endif 793 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 794 795 #define TC_BCR_OFFSET (0xC0) /**< (TC_BCR) Block Control Register Offset */ 796 797 #define TC_BCR_SYNC_Pos 0 /**< (TC_BCR) Synchro Command Position */ 798 #define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */ 799 #define TC_BCR_SYNC TC_BCR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BCR_SYNC_Msk instead */ 800 #define TC_BCR_MASK _U_(0x01) /**< \deprecated (TC_BCR) Register MASK (Use TC_BCR_Msk instead) */ 801 #define TC_BCR_Msk _U_(0x01) /**< (TC_BCR) Register Mask */ 802 803 804 /* -------- TC_BMR : (TC Offset: 0xc4) (R/W 32) Block Mode Register -------- */ 805 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 806 #if COMPONENT_TYPEDEF_STYLE == 'N' 807 typedef union { 808 struct { 809 uint32_t TC0XC0S:2; /**< bit: 0..1 External Clock Signal 0 Selection */ 810 uint32_t TC1XC1S:2; /**< bit: 2..3 External Clock Signal 1 Selection */ 811 uint32_t TC2XC2S:2; /**< bit: 4..5 External Clock Signal 2 Selection */ 812 uint32_t :2; /**< bit: 6..7 Reserved */ 813 uint32_t QDEN:1; /**< bit: 8 Quadrature Decoder Enabled */ 814 uint32_t POSEN:1; /**< bit: 9 Position Enabled */ 815 uint32_t SPEEDEN:1; /**< bit: 10 Speed Enabled */ 816 uint32_t QDTRANS:1; /**< bit: 11 Quadrature Decoding Transparent */ 817 uint32_t EDGPHA:1; /**< bit: 12 Edge on PHA Count Mode */ 818 uint32_t INVA:1; /**< bit: 13 Inverted PHA */ 819 uint32_t INVB:1; /**< bit: 14 Inverted PHB */ 820 uint32_t INVIDX:1; /**< bit: 15 Inverted Index */ 821 uint32_t SWAP:1; /**< bit: 16 Swap PHA and PHB */ 822 uint32_t IDXPHB:1; /**< bit: 17 Index Pin is PHB Pin */ 823 uint32_t :2; /**< bit: 18..19 Reserved */ 824 uint32_t MAXFILT:6; /**< bit: 20..25 Maximum Filter */ 825 uint32_t :6; /**< bit: 26..31 Reserved */ 826 } bit; /**< Structure used for bit access */ 827 uint32_t reg; /**< Type used for register access */ 828 } TC_BMR_Type; 829 #endif 830 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 831 832 #define TC_BMR_OFFSET (0xC4) /**< (TC_BMR) Block Mode Register Offset */ 833 834 #define TC_BMR_TC0XC0S_Pos 0 /**< (TC_BMR) External Clock Signal 0 Selection Position */ 835 #define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */ 836 #define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) 837 #define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */ 838 #define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */ 839 #define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */ 840 #define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */ 841 #define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */ 842 #define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */ 843 #define TC_BMR_TC1XC1S_Pos 2 /**< (TC_BMR) External Clock Signal 1 Selection Position */ 844 #define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */ 845 #define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) 846 #define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */ 847 #define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */ 848 #define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */ 849 #define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */ 850 #define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */ 851 #define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */ 852 #define TC_BMR_TC2XC2S_Pos 4 /**< (TC_BMR) External Clock Signal 2 Selection Position */ 853 #define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */ 854 #define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) 855 #define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */ 856 #define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */ 857 #define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */ 858 #define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */ 859 #define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */ 860 #define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */ 861 #define TC_BMR_QDEN_Pos 8 /**< (TC_BMR) Quadrature Decoder Enabled Position */ 862 #define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */ 863 #define TC_BMR_QDEN TC_BMR_QDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDEN_Msk instead */ 864 #define TC_BMR_POSEN_Pos 9 /**< (TC_BMR) Position Enabled Position */ 865 #define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */ 866 #define TC_BMR_POSEN TC_BMR_POSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_POSEN_Msk instead */ 867 #define TC_BMR_SPEEDEN_Pos 10 /**< (TC_BMR) Speed Enabled Position */ 868 #define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */ 869 #define TC_BMR_SPEEDEN TC_BMR_SPEEDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SPEEDEN_Msk instead */ 870 #define TC_BMR_QDTRANS_Pos 11 /**< (TC_BMR) Quadrature Decoding Transparent Position */ 871 #define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */ 872 #define TC_BMR_QDTRANS TC_BMR_QDTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDTRANS_Msk instead */ 873 #define TC_BMR_EDGPHA_Pos 12 /**< (TC_BMR) Edge on PHA Count Mode Position */ 874 #define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */ 875 #define TC_BMR_EDGPHA TC_BMR_EDGPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_EDGPHA_Msk instead */ 876 #define TC_BMR_INVA_Pos 13 /**< (TC_BMR) Inverted PHA Position */ 877 #define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */ 878 #define TC_BMR_INVA TC_BMR_INVA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVA_Msk instead */ 879 #define TC_BMR_INVB_Pos 14 /**< (TC_BMR) Inverted PHB Position */ 880 #define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */ 881 #define TC_BMR_INVB TC_BMR_INVB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVB_Msk instead */ 882 #define TC_BMR_INVIDX_Pos 15 /**< (TC_BMR) Inverted Index Position */ 883 #define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */ 884 #define TC_BMR_INVIDX TC_BMR_INVIDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVIDX_Msk instead */ 885 #define TC_BMR_SWAP_Pos 16 /**< (TC_BMR) Swap PHA and PHB Position */ 886 #define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */ 887 #define TC_BMR_SWAP TC_BMR_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SWAP_Msk instead */ 888 #define TC_BMR_IDXPHB_Pos 17 /**< (TC_BMR) Index Pin is PHB Pin Position */ 889 #define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */ 890 #define TC_BMR_IDXPHB TC_BMR_IDXPHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_IDXPHB_Msk instead */ 891 #define TC_BMR_MAXFILT_Pos 20 /**< (TC_BMR) Maximum Filter Position */ 892 #define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */ 893 #define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)) 894 #define TC_BMR_MASK _U_(0x3F3FF3F) /**< \deprecated (TC_BMR) Register MASK (Use TC_BMR_Msk instead) */ 895 #define TC_BMR_Msk _U_(0x3F3FF3F) /**< (TC_BMR) Register Mask */ 896 897 898 /* -------- TC_QIER : (TC Offset: 0xc8) (/W 32) QDEC Interrupt Enable Register -------- */ 899 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 900 #if COMPONENT_TYPEDEF_STYLE == 'N' 901 typedef union { 902 struct { 903 uint32_t IDX:1; /**< bit: 0 Index */ 904 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 905 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 906 uint32_t :29; /**< bit: 3..31 Reserved */ 907 } bit; /**< Structure used for bit access */ 908 uint32_t reg; /**< Type used for register access */ 909 } TC_QIER_Type; 910 #endif 911 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 912 913 #define TC_QIER_OFFSET (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */ 914 915 #define TC_QIER_IDX_Pos 0 /**< (TC_QIER) Index Position */ 916 #define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */ 917 #define TC_QIER_IDX TC_QIER_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_IDX_Msk instead */ 918 #define TC_QIER_DIRCHG_Pos 1 /**< (TC_QIER) Direction Change Position */ 919 #define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */ 920 #define TC_QIER_DIRCHG TC_QIER_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_DIRCHG_Msk instead */ 921 #define TC_QIER_QERR_Pos 2 /**< (TC_QIER) Quadrature Error Position */ 922 #define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */ 923 #define TC_QIER_QERR TC_QIER_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_QERR_Msk instead */ 924 #define TC_QIER_MASK _U_(0x07) /**< \deprecated (TC_QIER) Register MASK (Use TC_QIER_Msk instead) */ 925 #define TC_QIER_Msk _U_(0x07) /**< (TC_QIER) Register Mask */ 926 927 928 /* -------- TC_QIDR : (TC Offset: 0xcc) (/W 32) QDEC Interrupt Disable Register -------- */ 929 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 930 #if COMPONENT_TYPEDEF_STYLE == 'N' 931 typedef union { 932 struct { 933 uint32_t IDX:1; /**< bit: 0 Index */ 934 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 935 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 936 uint32_t :29; /**< bit: 3..31 Reserved */ 937 } bit; /**< Structure used for bit access */ 938 uint32_t reg; /**< Type used for register access */ 939 } TC_QIDR_Type; 940 #endif 941 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 942 943 #define TC_QIDR_OFFSET (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */ 944 945 #define TC_QIDR_IDX_Pos 0 /**< (TC_QIDR) Index Position */ 946 #define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */ 947 #define TC_QIDR_IDX TC_QIDR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_IDX_Msk instead */ 948 #define TC_QIDR_DIRCHG_Pos 1 /**< (TC_QIDR) Direction Change Position */ 949 #define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */ 950 #define TC_QIDR_DIRCHG TC_QIDR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_DIRCHG_Msk instead */ 951 #define TC_QIDR_QERR_Pos 2 /**< (TC_QIDR) Quadrature Error Position */ 952 #define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */ 953 #define TC_QIDR_QERR TC_QIDR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_QERR_Msk instead */ 954 #define TC_QIDR_MASK _U_(0x07) /**< \deprecated (TC_QIDR) Register MASK (Use TC_QIDR_Msk instead) */ 955 #define TC_QIDR_Msk _U_(0x07) /**< (TC_QIDR) Register Mask */ 956 957 958 /* -------- TC_QIMR : (TC Offset: 0xd0) (R/ 32) QDEC Interrupt Mask Register -------- */ 959 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 960 #if COMPONENT_TYPEDEF_STYLE == 'N' 961 typedef union { 962 struct { 963 uint32_t IDX:1; /**< bit: 0 Index */ 964 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 965 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 966 uint32_t :29; /**< bit: 3..31 Reserved */ 967 } bit; /**< Structure used for bit access */ 968 uint32_t reg; /**< Type used for register access */ 969 } TC_QIMR_Type; 970 #endif 971 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 972 973 #define TC_QIMR_OFFSET (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */ 974 975 #define TC_QIMR_IDX_Pos 0 /**< (TC_QIMR) Index Position */ 976 #define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */ 977 #define TC_QIMR_IDX TC_QIMR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_IDX_Msk instead */ 978 #define TC_QIMR_DIRCHG_Pos 1 /**< (TC_QIMR) Direction Change Position */ 979 #define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */ 980 #define TC_QIMR_DIRCHG TC_QIMR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_DIRCHG_Msk instead */ 981 #define TC_QIMR_QERR_Pos 2 /**< (TC_QIMR) Quadrature Error Position */ 982 #define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */ 983 #define TC_QIMR_QERR TC_QIMR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_QERR_Msk instead */ 984 #define TC_QIMR_MASK _U_(0x07) /**< \deprecated (TC_QIMR) Register MASK (Use TC_QIMR_Msk instead) */ 985 #define TC_QIMR_Msk _U_(0x07) /**< (TC_QIMR) Register Mask */ 986 987 988 /* -------- TC_QISR : (TC Offset: 0xd4) (R/ 32) QDEC Interrupt Status Register -------- */ 989 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 990 #if COMPONENT_TYPEDEF_STYLE == 'N' 991 typedef union { 992 struct { 993 uint32_t IDX:1; /**< bit: 0 Index */ 994 uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ 995 uint32_t QERR:1; /**< bit: 2 Quadrature Error */ 996 uint32_t :5; /**< bit: 3..7 Reserved */ 997 uint32_t DIR:1; /**< bit: 8 Direction */ 998 uint32_t :23; /**< bit: 9..31 Reserved */ 999 } bit; /**< Structure used for bit access */ 1000 uint32_t reg; /**< Type used for register access */ 1001 } TC_QISR_Type; 1002 #endif 1003 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1004 1005 #define TC_QISR_OFFSET (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */ 1006 1007 #define TC_QISR_IDX_Pos 0 /**< (TC_QISR) Index Position */ 1008 #define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */ 1009 #define TC_QISR_IDX TC_QISR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_IDX_Msk instead */ 1010 #define TC_QISR_DIRCHG_Pos 1 /**< (TC_QISR) Direction Change Position */ 1011 #define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */ 1012 #define TC_QISR_DIRCHG TC_QISR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIRCHG_Msk instead */ 1013 #define TC_QISR_QERR_Pos 2 /**< (TC_QISR) Quadrature Error Position */ 1014 #define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */ 1015 #define TC_QISR_QERR TC_QISR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_QERR_Msk instead */ 1016 #define TC_QISR_DIR_Pos 8 /**< (TC_QISR) Direction Position */ 1017 #define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */ 1018 #define TC_QISR_DIR TC_QISR_DIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIR_Msk instead */ 1019 #define TC_QISR_MASK _U_(0x107) /**< \deprecated (TC_QISR) Register MASK (Use TC_QISR_Msk instead) */ 1020 #define TC_QISR_Msk _U_(0x107) /**< (TC_QISR) Register Mask */ 1021 1022 1023 /* -------- TC_FMR : (TC Offset: 0xd8) (R/W 32) Fault Mode Register -------- */ 1024 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1025 #if COMPONENT_TYPEDEF_STYLE == 'N' 1026 typedef union { 1027 struct { 1028 uint32_t ENCF0:1; /**< bit: 0 Enable Compare Fault Channel 0 */ 1029 uint32_t ENCF1:1; /**< bit: 1 Enable Compare Fault Channel 1 */ 1030 uint32_t :30; /**< bit: 2..31 Reserved */ 1031 } bit; /**< Structure used for bit access */ 1032 struct { 1033 uint32_t ENCF:2; /**< bit: 0..1 Enable Compare Fault Channel x */ 1034 uint32_t :30; /**< bit: 2..31 Reserved */ 1035 } vec; /**< Structure used for vec access */ 1036 uint32_t reg; /**< Type used for register access */ 1037 } TC_FMR_Type; 1038 #endif 1039 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1040 1041 #define TC_FMR_OFFSET (0xD8) /**< (TC_FMR) Fault Mode Register Offset */ 1042 1043 #define TC_FMR_ENCF0_Pos 0 /**< (TC_FMR) Enable Compare Fault Channel 0 Position */ 1044 #define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */ 1045 #define TC_FMR_ENCF0 TC_FMR_ENCF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF0_Msk instead */ 1046 #define TC_FMR_ENCF1_Pos 1 /**< (TC_FMR) Enable Compare Fault Channel 1 Position */ 1047 #define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */ 1048 #define TC_FMR_ENCF1 TC_FMR_ENCF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF1_Msk instead */ 1049 #define TC_FMR_MASK _U_(0x03) /**< \deprecated (TC_FMR) Register MASK (Use TC_FMR_Msk instead) */ 1050 #define TC_FMR_Msk _U_(0x03) /**< (TC_FMR) Register Mask */ 1051 1052 #define TC_FMR_ENCF_Pos 0 /**< (TC_FMR Position) Enable Compare Fault Channel x */ 1053 #define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */ 1054 #define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos)) 1055 1056 /* -------- TC_WPMR : (TC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 1057 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1058 #if COMPONENT_TYPEDEF_STYLE == 'N' 1059 typedef union { 1060 struct { 1061 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 1062 uint32_t :7; /**< bit: 1..7 Reserved */ 1063 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 1064 } bit; /**< Structure used for bit access */ 1065 uint32_t reg; /**< Type used for register access */ 1066 } TC_WPMR_Type; 1067 #endif 1068 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1069 1070 #define TC_WPMR_OFFSET (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */ 1071 1072 #define TC_WPMR_WPEN_Pos 0 /**< (TC_WPMR) Write Protection Enable Position */ 1073 #define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */ 1074 #define TC_WPMR_WPEN TC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_WPMR_WPEN_Msk instead */ 1075 #define TC_WPMR_WPKEY_Pos 8 /**< (TC_WPMR) Write Protection Key Position */ 1076 #define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */ 1077 #define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) 1078 #define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 1079 #define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 1080 #define TC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TC_WPMR) Register MASK (Use TC_WPMR_Msk instead) */ 1081 #define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */ 1082 1083 1084 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1085 #if COMPONENT_TYPEDEF_STYLE == 'R' 1086 /** \brief TC_CHANNEL hardware registers */ 1087 typedef struct { 1088 __O uint32_t TC_CCR; /**< (TC_CHANNEL Offset: 0x00) Channel Control Register (channel = 0) */ 1089 __IO uint32_t TC_CMR; /**< (TC_CHANNEL Offset: 0x04) Channel Mode Register (channel = 0) */ 1090 __IO uint32_t TC_SMMR; /**< (TC_CHANNEL Offset: 0x08) Stepper Motor Mode Register (channel = 0) */ 1091 __I uint32_t TC_RAB; /**< (TC_CHANNEL Offset: 0x0C) Register AB (channel = 0) */ 1092 __I uint32_t TC_CV; /**< (TC_CHANNEL Offset: 0x10) Counter Value (channel = 0) */ 1093 __IO uint32_t TC_RA; /**< (TC_CHANNEL Offset: 0x14) Register A (channel = 0) */ 1094 __IO uint32_t TC_RB; /**< (TC_CHANNEL Offset: 0x18) Register B (channel = 0) */ 1095 __IO uint32_t TC_RC; /**< (TC_CHANNEL Offset: 0x1C) Register C (channel = 0) */ 1096 __I uint32_t TC_SR; /**< (TC_CHANNEL Offset: 0x20) Status Register (channel = 0) */ 1097 __O uint32_t TC_IER; /**< (TC_CHANNEL Offset: 0x24) Interrupt Enable Register (channel = 0) */ 1098 __O uint32_t TC_IDR; /**< (TC_CHANNEL Offset: 0x28) Interrupt Disable Register (channel = 0) */ 1099 __I uint32_t TC_IMR; /**< (TC_CHANNEL Offset: 0x2C) Interrupt Mask Register (channel = 0) */ 1100 __IO uint32_t TC_EMR; /**< (TC_CHANNEL Offset: 0x30) Extended Mode Register (channel = 0) */ 1101 __I uint8_t Reserved1[12]; 1102 } TcChannel; 1103 1104 #define TCCHANNEL_NUMBER 3 1105 /** \brief TC hardware registers */ 1106 typedef struct { 1107 TcChannel TcChannel[TCCHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ 1108 __O uint32_t TC_BCR; /**< (TC Offset: 0xC0) Block Control Register */ 1109 __IO uint32_t TC_BMR; /**< (TC Offset: 0xC4) Block Mode Register */ 1110 __O uint32_t TC_QIER; /**< (TC Offset: 0xC8) QDEC Interrupt Enable Register */ 1111 __O uint32_t TC_QIDR; /**< (TC Offset: 0xCC) QDEC Interrupt Disable Register */ 1112 __I uint32_t TC_QIMR; /**< (TC Offset: 0xD0) QDEC Interrupt Mask Register */ 1113 __I uint32_t TC_QISR; /**< (TC Offset: 0xD4) QDEC Interrupt Status Register */ 1114 __IO uint32_t TC_FMR; /**< (TC Offset: 0xD8) Fault Mode Register */ 1115 __I uint8_t Reserved1[8]; 1116 __IO uint32_t TC_WPMR; /**< (TC Offset: 0xE4) Write Protection Mode Register */ 1117 } Tc; 1118 1119 #elif COMPONENT_TYPEDEF_STYLE == 'N' 1120 /** \brief TC_CHANNEL hardware registers */ 1121 typedef struct { 1122 __O TC_CCR_Type TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */ 1123 __IO TC_CMR_Type TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */ 1124 __IO TC_SMMR_Type TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */ 1125 __I TC_RAB_Type TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */ 1126 __I TC_CV_Type TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */ 1127 __IO TC_RA_Type TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */ 1128 __IO TC_RB_Type TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */ 1129 __IO TC_RC_Type TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */ 1130 __I TC_SR_Type TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */ 1131 __O TC_IER_Type TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */ 1132 __O TC_IDR_Type TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */ 1133 __I TC_IMR_Type TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */ 1134 __IO TC_EMR_Type TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */ 1135 __I uint8_t Reserved1[12]; 1136 } TcChannel; 1137 1138 /** \brief TC hardware registers */ 1139 typedef struct { 1140 TcChannel TC_CHANNEL[3]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ 1141 __O TC_BCR_Type TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */ 1142 __IO TC_BMR_Type TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */ 1143 __O TC_QIER_Type TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */ 1144 __O TC_QIDR_Type TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */ 1145 __I TC_QIMR_Type TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */ 1146 __I TC_QISR_Type TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */ 1147 __IO TC_FMR_Type TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */ 1148 __I uint8_t Reserved1[8]; 1149 __IO TC_WPMR_Type TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 1150 } Tc; 1151 1152 #else /* COMPONENT_TYPEDEF_STYLE */ 1153 #error Unknown component typedef style 1154 #endif /* COMPONENT_TYPEDEF_STYLE */ 1155 1156 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1157 /** @} end of Timer Counter */ 1158 1159 #endif /* _SAME70_TC_COMPONENT_H_ */ 1160
