1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_USART0_INSTANCE_ 31 #define _SAM4S_USART0_INSTANCE_ 32 33 /* ========== Register definition for USART0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ 36 #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ 37 #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ 38 #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ 39 #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ 40 #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ 41 #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ 42 #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ 43 #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ 44 #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ 45 #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ 46 #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ 47 #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */ 48 #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ 49 #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ 50 #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ 51 #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ 52 #define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */ 53 #define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */ 54 #define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ 55 #define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ 56 #define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ 57 #define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ 58 #define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ 59 #define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ 60 #define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */ 61 #define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */ 62 #else 63 #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ 64 #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ 65 #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ 66 #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ 67 #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ 68 #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ 69 #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ 70 #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ 71 #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ 72 #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ 73 #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ 74 #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ 75 #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */ 76 #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ 77 #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ 78 #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ 79 #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ 80 #define REG_USART0_RPR (*(__IO uint32_t*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */ 81 #define REG_USART0_RCR (*(__IO uint32_t*)0x40024104U) /**< \brief (USART0) Receive Counter Register */ 82 #define REG_USART0_TPR (*(__IO uint32_t*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ 83 #define REG_USART0_TCR (*(__IO uint32_t*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ 84 #define REG_USART0_RNPR (*(__IO uint32_t*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ 85 #define REG_USART0_RNCR (*(__IO uint32_t*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ 86 #define REG_USART0_TNPR (*(__IO uint32_t*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ 87 #define REG_USART0_TNCR (*(__IO uint32_t*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ 88 #define REG_USART0_PTCR (*(__O uint32_t*)0x40024120U) /**< \brief (USART0) Transfer Control Register */ 89 #define REG_USART0_PTSR (*(__I uint32_t*)0x40024124U) /**< \brief (USART0) Transfer Status Register */ 90 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 #endif /* _SAM4S_USART0_INSTANCE_ */ 93
