1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_SSC_INSTANCE_ 31 #define _SAM4S_SSC_INSTANCE_ 32 33 /* ========== Register definition for SSC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ 36 #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ 37 #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ 38 #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ 39 #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ 40 #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ 41 #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ 42 #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ 43 #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ 44 #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ 45 #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ 46 #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ 47 #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ 48 #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ 49 #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ 50 #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ 51 #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ 52 #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ 53 #define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */ 54 #define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */ 55 #define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ 56 #define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ 57 #define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ 58 #define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ 59 #define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ 60 #define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ 61 #define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */ 62 #define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */ 63 #else 64 #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ 65 #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ 66 #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ 67 #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ 68 #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ 69 #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ 70 #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ 71 #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ 72 #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ 73 #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ 74 #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ 75 #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ 76 #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ 77 #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ 78 #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ 79 #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ 80 #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ 81 #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ 82 #define REG_SSC_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */ 83 #define REG_SSC_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (SSC) Receive Counter Register */ 84 #define REG_SSC_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ 85 #define REG_SSC_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ 86 #define REG_SSC_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ 87 #define REG_SSC_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ 88 #define REG_SSC_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ 89 #define REG_SSC_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ 90 #define REG_SSC_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (SSC) Transfer Control Register */ 91 #define REG_SSC_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (SSC) Transfer Status Register */ 92 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #endif /* _SAM4S_SSC_INSTANCE_ */ 95
