1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_SPI_INSTANCE_ 31 #define _SAM4S_SPI_INSTANCE_ 32 33 /* ========== Register definition for SPI peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */ 36 #define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */ 37 #define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */ 38 #define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */ 39 #define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */ 40 #define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ 41 #define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ 42 #define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ 43 #define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */ 44 #define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Mode Register */ 45 #define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ 46 #define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */ 47 #define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */ 48 #define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ 49 #define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ 50 #define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ 51 #define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ 52 #define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ 53 #define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ 54 #define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */ 55 #define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */ 56 #else 57 #define REG_SPI_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI) Control Register */ 58 #define REG_SPI_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI) Mode Register */ 59 #define REG_SPI_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI) Receive Data Register */ 60 #define REG_SPI_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */ 61 #define REG_SPI_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI) Status Register */ 62 #define REG_SPI_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ 63 #define REG_SPI_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ 64 #define REG_SPI_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ 65 #define REG_SPI_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI) Chip Select Register */ 66 #define REG_SPI_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI) Write Protection Mode Register */ 67 #define REG_SPI_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ 68 #define REG_SPI_RPR (*(__IO uint32_t*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */ 69 #define REG_SPI_RCR (*(__IO uint32_t*)0x40008104U) /**< \brief (SPI) Receive Counter Register */ 70 #define REG_SPI_TPR (*(__IO uint32_t*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ 71 #define REG_SPI_TCR (*(__IO uint32_t*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ 72 #define REG_SPI_RNPR (*(__IO uint32_t*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ 73 #define REG_SPI_RNCR (*(__IO uint32_t*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ 74 #define REG_SPI_TNPR (*(__IO uint32_t*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ 75 #define REG_SPI_TNCR (*(__IO uint32_t*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ 76 #define REG_SPI_PTCR (*(__O uint32_t*)0x40008120U) /**< \brief (SPI) Transfer Control Register */ 77 #define REG_SPI_PTSR (*(__I uint32_t*)0x40008124U) /**< \brief (SPI) Transfer Status Register */ 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 #endif /* _SAM4S_SPI_INSTANCE_ */ 81
