1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_TC_COMPONENT_ 31 #define _SAM4S_TC_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Timer Counter */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM4S_TC Timer Counter */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief TcChannel hardware registers */ 41 typedef struct { 42 __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ 43 __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ 44 __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ 45 __I uint32_t Reserved1[1]; 46 __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ 47 __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ 48 __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ 49 __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ 50 __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ 51 __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ 52 __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ 53 __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ 54 __I uint32_t Reserved2[4]; 55 } TcChannel; 56 /** \brief Tc hardware registers */ 57 #define TCCHANNEL_NUMBER 3 58 typedef struct { 59 TcChannel TcChannel[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ 60 __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ 61 __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ 62 __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ 63 __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ 64 __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ 65 __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ 66 __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ 67 __I uint32_t Reserved1[2]; 68 __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ 69 } Tc; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ 72 #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ 73 #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ 74 #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ 75 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ 76 #define TC_CMR_TCCLKS_Pos 0 77 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ 78 #define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) 79 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/2 clock signal (from PMC) */ 80 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ 81 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ 82 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ 83 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ 84 #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ 85 #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ 86 #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ 87 #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ 88 #define TC_CMR_BURST_Pos 4 89 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ 90 #define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) 91 #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ 92 #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ 93 #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ 94 #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ 95 #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ 96 #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ 97 #define TC_CMR_ETRGEDG_Pos 8 98 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ 99 #define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) 100 #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ 101 #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ 102 #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ 103 #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ 104 #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ 105 #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ 106 #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ 107 #define TC_CMR_LDRA_Pos 16 108 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ 109 #define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) 110 #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ 111 #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ 112 #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ 113 #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ 114 #define TC_CMR_LDRB_Pos 18 115 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ 116 #define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) 117 #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ 118 #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ 119 #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ 120 #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ 121 #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ 122 #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ 123 #define TC_CMR_EEVTEDG_Pos 8 124 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ 125 #define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) 126 #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ 127 #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ 128 #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ 129 #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ 130 #define TC_CMR_EEVT_Pos 10 131 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ 132 #define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) 133 #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ 134 #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ 135 #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ 136 #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ 137 #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ 138 #define TC_CMR_WAVSEL_Pos 13 139 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ 140 #define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) 141 #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ 142 #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ 143 #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ 144 #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ 145 #define TC_CMR_ACPA_Pos 16 146 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ 147 #define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) 148 #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ 149 #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ 150 #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ 151 #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ 152 #define TC_CMR_ACPC_Pos 18 153 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ 154 #define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) 155 #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ 156 #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ 157 #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ 158 #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ 159 #define TC_CMR_AEEVT_Pos 20 160 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ 161 #define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) 162 #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ 163 #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ 164 #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ 165 #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ 166 #define TC_CMR_ASWTRG_Pos 22 167 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ 168 #define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) 169 #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ 170 #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ 171 #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ 172 #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ 173 #define TC_CMR_BCPB_Pos 24 174 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ 175 #define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) 176 #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ 177 #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ 178 #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ 179 #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ 180 #define TC_CMR_BCPC_Pos 26 181 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ 182 #define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) 183 #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ 184 #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ 185 #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ 186 #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ 187 #define TC_CMR_BEEVT_Pos 28 188 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ 189 #define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) 190 #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ 191 #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ 192 #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ 193 #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ 194 #define TC_CMR_BSWTRG_Pos 30 195 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ 196 #define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) 197 #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ 198 #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ 199 #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ 200 #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ 201 202 /* CAPTURE mode */ 203 #define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ 204 #define TC_CMR_CAPTURE_LDBSTOP_Msk (0x1u << TC_CMR_CAPTURE_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ 205 #define TC_CMR_CAPTURE_LDBSTOP TC_CMR_CAPTURE_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBSTOP_Msk instead */ 206 #define TC_CMR_CAPTURE_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ 207 #define TC_CMR_CAPTURE_LDBDIS_Msk (0x1u << TC_CMR_CAPTURE_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ 208 #define TC_CMR_CAPTURE_LDBDIS TC_CMR_CAPTURE_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBDIS_Msk instead */ 209 #define TC_CMR_CAPTURE_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ 210 #define TC_CMR_CAPTURE_ETRGEDG_Msk (0x3u << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ 211 #define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) 212 #define TC_CMR_CAPTURE_ETRGEDG_NONE_Val 0x0u /**< (TC_CMR) CAPTURE The clock is not gated by an external signal. */ 213 #define TC_CMR_CAPTURE_ETRGEDG_RISING_Val 0x1u /**< (TC_CMR) CAPTURE Rising edge */ 214 #define TC_CMR_CAPTURE_ETRGEDG_FALLING_Val 0x2u /**< (TC_CMR) CAPTURE Falling edge */ 215 #define TC_CMR_CAPTURE_ETRGEDG_EDGE_Val 0x3u /**< (TC_CMR) CAPTURE Each edge */ 216 #define TC_CMR_CAPTURE_ETRGEDG_NONE (TC_CMR_CAPTURE_ETRGEDG_NONE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ 217 #define TC_CMR_CAPTURE_ETRGEDG_RISING (TC_CMR_CAPTURE_ETRGEDG_RISING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ 218 #define TC_CMR_CAPTURE_ETRGEDG_FALLING (TC_CMR_CAPTURE_ETRGEDG_FALLING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ 219 #define TC_CMR_CAPTURE_ETRGEDG_EDGE (TC_CMR_CAPTURE_ETRGEDG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ 220 #define TC_CMR_CAPTURE_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ 221 #define TC_CMR_CAPTURE_ABETRG_Msk (0x1u << TC_CMR_CAPTURE_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ 222 #define TC_CMR_CAPTURE_ABETRG TC_CMR_CAPTURE_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_ABETRG_Msk instead */ 223 #define TC_CMR_CAPTURE_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ 224 #define TC_CMR_CAPTURE_CPCTRG_Msk (0x1u << TC_CMR_CAPTURE_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ 225 #define TC_CMR_CAPTURE_CPCTRG TC_CMR_CAPTURE_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_CPCTRG_Msk instead */ 226 #define TC_CMR_CAPTURE_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ 227 #define TC_CMR_CAPTURE_LDRA_Msk (0x3u << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ 228 #define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) 229 #define TC_CMR_CAPTURE_LDRA_NONE_Val 0x0u /**< (TC_CMR) CAPTURE None */ 230 #define TC_CMR_CAPTURE_LDRA_RISING_Val 0x1u /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 231 #define TC_CMR_CAPTURE_LDRA_FALLING_Val 0x2u /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 232 #define TC_CMR_CAPTURE_LDRA_EDGE_Val 0x3u /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 233 #define TC_CMR_CAPTURE_LDRA_NONE (TC_CMR_CAPTURE_LDRA_NONE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) None Position */ 234 #define TC_CMR_CAPTURE_LDRA_RISING (TC_CMR_CAPTURE_LDRA_RISING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 235 #define TC_CMR_CAPTURE_LDRA_FALLING (TC_CMR_CAPTURE_LDRA_FALLING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 236 #define TC_CMR_CAPTURE_LDRA_EDGE (TC_CMR_CAPTURE_LDRA_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 237 #define TC_CMR_CAPTURE_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ 238 #define TC_CMR_CAPTURE_LDRB_Msk (0x3u << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ 239 #define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) 240 #define TC_CMR_CAPTURE_LDRB_NONE_Val 0x0u /**< (TC_CMR) CAPTURE None */ 241 #define TC_CMR_CAPTURE_LDRB_RISING_Val 0x1u /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ 242 #define TC_CMR_CAPTURE_LDRB_FALLING_Val 0x2u /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ 243 #define TC_CMR_CAPTURE_LDRB_EDGE_Val 0x3u /**< (TC_CMR) CAPTURE Each edge of TIOAx */ 244 #define TC_CMR_CAPTURE_LDRB_NONE (TC_CMR_CAPTURE_LDRB_NONE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) None Position */ 245 #define TC_CMR_CAPTURE_LDRB_RISING (TC_CMR_CAPTURE_LDRB_RISING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ 246 #define TC_CMR_CAPTURE_LDRB_FALLING (TC_CMR_CAPTURE_LDRB_FALLING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ 247 #define TC_CMR_CAPTURE_LDRB_EDGE (TC_CMR_CAPTURE_LDRB_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ 248 #define TC_CMR_CAPTURE_MASK 0x7F47C0u /**< \deprecated (TC_CMR_CAPTURE) Register MASK (Use TC_CMR_CAPTURE_Msk instead) */ 249 #define TC_CMR_CAPTURE_Msk 0x7F47C0u /**< (TC_CMR_CAPTURE) Register Mask */ 250 251 /* WAVEFORM mode */ 252 #define TC_CMR_WAVEFORM_CPCSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RC Compare Position */ 253 #define TC_CMR_WAVEFORM_CPCSTOP_Msk (0x1u << TC_CMR_WAVEFORM_CPCSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RC Compare Mask */ 254 #define TC_CMR_WAVEFORM_CPCSTOP TC_CMR_WAVEFORM_CPCSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCSTOP_Msk instead */ 255 #define TC_CMR_WAVEFORM_CPCDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RC Loading Position */ 256 #define TC_CMR_WAVEFORM_CPCDIS_Msk (0x1u << TC_CMR_WAVEFORM_CPCDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RC Loading Mask */ 257 #define TC_CMR_WAVEFORM_CPCDIS TC_CMR_WAVEFORM_CPCDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCDIS_Msk instead */ 258 #define TC_CMR_WAVEFORM_EEVTEDG_Pos 8 /**< (TC_CMR) External Event Edge Selection Position */ 259 #define TC_CMR_WAVEFORM_EEVTEDG_Msk (0x3u << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) External Event Edge Selection Mask */ 260 #define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) 261 #define TC_CMR_WAVEFORM_EEVTEDG_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM None */ 262 #define TC_CMR_WAVEFORM_EEVTEDG_RISING_Val 0x1u /**< (TC_CMR) WAVEFORM Rising edge */ 263 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val 0x2u /**< (TC_CMR) WAVEFORM Falling edge */ 264 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val 0x3u /**< (TC_CMR) WAVEFORM Each edges */ 265 #define TC_CMR_WAVEFORM_EEVTEDG_NONE (TC_CMR_WAVEFORM_EEVTEDG_NONE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) None Position */ 266 #define TC_CMR_WAVEFORM_EEVTEDG_RISING (TC_CMR_WAVEFORM_EEVTEDG_RISING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Rising edge Position */ 267 #define TC_CMR_WAVEFORM_EEVTEDG_FALLING (TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Falling edge Position */ 268 #define TC_CMR_WAVEFORM_EEVTEDG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Each edges Position */ 269 #define TC_CMR_WAVEFORM_EEVT_Pos 10 /**< (TC_CMR) External Event Selection Position */ 270 #define TC_CMR_WAVEFORM_EEVT_Msk (0x3u << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) External Event Selection Mask */ 271 #define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) 272 #define TC_CMR_WAVEFORM_EEVT_TIOB_Val 0x0u /**< (TC_CMR) WAVEFORM TIOB */ 273 #define TC_CMR_WAVEFORM_EEVT_XC0_Val 0x1u /**< (TC_CMR) WAVEFORM XC0 */ 274 #define TC_CMR_WAVEFORM_EEVT_XC1_Val 0x2u /**< (TC_CMR) WAVEFORM XC1 */ 275 #define TC_CMR_WAVEFORM_EEVT_XC2_Val 0x3u /**< (TC_CMR) WAVEFORM XC2 */ 276 #define TC_CMR_WAVEFORM_EEVT_TIOB (TC_CMR_WAVEFORM_EEVT_TIOB_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) TIOB Position */ 277 #define TC_CMR_WAVEFORM_EEVT_XC0 (TC_CMR_WAVEFORM_EEVT_XC0_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC0 Position */ 278 #define TC_CMR_WAVEFORM_EEVT_XC1 (TC_CMR_WAVEFORM_EEVT_XC1_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC1 Position */ 279 #define TC_CMR_WAVEFORM_EEVT_XC2 (TC_CMR_WAVEFORM_EEVT_XC2_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC2 Position */ 280 #define TC_CMR_WAVEFORM_ENETRG_Pos 12 /**< (TC_CMR) External Event Trigger Enable Position */ 281 #define TC_CMR_WAVEFORM_ENETRG_Msk (0x1u << TC_CMR_WAVEFORM_ENETRG_Pos) /**< (TC_CMR) External Event Trigger Enable Mask */ 282 #define TC_CMR_WAVEFORM_ENETRG TC_CMR_WAVEFORM_ENETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_ENETRG_Msk instead */ 283 #define TC_CMR_WAVEFORM_WAVSEL_Pos 13 /**< (TC_CMR) Waveform Selection Position */ 284 #define TC_CMR_WAVEFORM_WAVSEL_Msk (0x3u << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) Waveform Selection Mask */ 285 #define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) 286 #define TC_CMR_WAVEFORM_WAVSEL_UP_Val 0x0u /**< (TC_CMR) WAVEFORM UP mode without automatic trigger on RC Compare */ 287 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val 0x1u /**< (TC_CMR) WAVEFORM UPDOWN mode without automatic trigger on RC Compare */ 288 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val 0x2u /**< (TC_CMR) WAVEFORM UP mode with automatic trigger on RC Compare */ 289 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val 0x3u /**< (TC_CMR) WAVEFORM UPDOWN mode with automatic trigger on RC Compare */ 290 #define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ 291 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ 292 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ 293 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ 294 #define TC_CMR_WAVEFORM_ACPA_Pos 16 /**< (TC_CMR) RA Compare Effect on TIOAx Position */ 295 #define TC_CMR_WAVEFORM_ACPA_Msk (0x3u << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) RA Compare Effect on TIOAx Mask */ 296 #define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) 297 #define TC_CMR_WAVEFORM_ACPA_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 298 #define TC_CMR_WAVEFORM_ACPA_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 299 #define TC_CMR_WAVEFORM_ACPA_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 300 #define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 301 #define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) NONE Position */ 302 #define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) SET Position */ 303 #define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) CLEAR Position */ 304 #define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) TOGGLE Position */ 305 #define TC_CMR_WAVEFORM_ACPC_Pos 18 /**< (TC_CMR) RC Compare Effect on TIOAx Position */ 306 #define TC_CMR_WAVEFORM_ACPC_Msk (0x3u << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOAx Mask */ 307 #define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) 308 #define TC_CMR_WAVEFORM_ACPC_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 309 #define TC_CMR_WAVEFORM_ACPC_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 310 #define TC_CMR_WAVEFORM_ACPC_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 311 #define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 312 #define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) NONE Position */ 313 #define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) SET Position */ 314 #define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) CLEAR Position */ 315 #define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) TOGGLE Position */ 316 #define TC_CMR_WAVEFORM_AEEVT_Pos 20 /**< (TC_CMR) External Event Effect on TIOAx Position */ 317 #define TC_CMR_WAVEFORM_AEEVT_Msk (0x3u << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOAx Mask */ 318 #define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) 319 #define TC_CMR_WAVEFORM_AEEVT_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 320 #define TC_CMR_WAVEFORM_AEEVT_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 321 #define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 322 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 323 #define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) NONE Position */ 324 #define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) SET Position */ 325 #define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 326 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 327 #define TC_CMR_WAVEFORM_ASWTRG_Pos 22 /**< (TC_CMR) Software Trigger Effect on TIOAx Position */ 328 #define TC_CMR_WAVEFORM_ASWTRG_Msk (0x3u << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOAx Mask */ 329 #define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) 330 #define TC_CMR_WAVEFORM_ASWTRG_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 331 #define TC_CMR_WAVEFORM_ASWTRG_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 332 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 333 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 334 #define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) NONE Position */ 335 #define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) SET Position */ 336 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 337 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 338 #define TC_CMR_WAVEFORM_BCPB_Pos 24 /**< (TC_CMR) RB Compare Effect on TIOBx Position */ 339 #define TC_CMR_WAVEFORM_BCPB_Msk (0x3u << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) RB Compare Effect on TIOBx Mask */ 340 #define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) 341 #define TC_CMR_WAVEFORM_BCPB_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 342 #define TC_CMR_WAVEFORM_BCPB_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 343 #define TC_CMR_WAVEFORM_BCPB_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 344 #define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 345 #define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) NONE Position */ 346 #define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) SET Position */ 347 #define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) CLEAR Position */ 348 #define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) TOGGLE Position */ 349 #define TC_CMR_WAVEFORM_BCPC_Pos 26 /**< (TC_CMR) RC Compare Effect on TIOBx Position */ 350 #define TC_CMR_WAVEFORM_BCPC_Msk (0x3u << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOBx Mask */ 351 #define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) 352 #define TC_CMR_WAVEFORM_BCPC_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 353 #define TC_CMR_WAVEFORM_BCPC_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 354 #define TC_CMR_WAVEFORM_BCPC_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 355 #define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 356 #define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) NONE Position */ 357 #define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) SET Position */ 358 #define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) CLEAR Position */ 359 #define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) TOGGLE Position */ 360 #define TC_CMR_WAVEFORM_BEEVT_Pos 28 /**< (TC_CMR) External Event Effect on TIOBx Position */ 361 #define TC_CMR_WAVEFORM_BEEVT_Msk (0x3u << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOBx Mask */ 362 #define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) 363 #define TC_CMR_WAVEFORM_BEEVT_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 364 #define TC_CMR_WAVEFORM_BEEVT_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 365 #define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 366 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 367 #define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) NONE Position */ 368 #define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) SET Position */ 369 #define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) CLEAR Position */ 370 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ 371 #define TC_CMR_WAVEFORM_BSWTRG_Pos 30 /**< (TC_CMR) Software Trigger Effect on TIOBx Position */ 372 #define TC_CMR_WAVEFORM_BSWTRG_Msk (0x3u << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOBx Mask */ 373 #define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) 374 #define TC_CMR_WAVEFORM_BSWTRG_NONE_Val 0x0u /**< (TC_CMR) WAVEFORM NONE */ 375 #define TC_CMR_WAVEFORM_BSWTRG_SET_Val 0x1u /**< (TC_CMR) WAVEFORM SET */ 376 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val 0x2u /**< (TC_CMR) WAVEFORM CLEAR */ 377 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val 0x3u /**< (TC_CMR) WAVEFORM TOGGLE */ 378 #define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) NONE Position */ 379 #define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) SET Position */ 380 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) CLEAR Position */ 381 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ 382 #define TC_CMR_WAVEFORM_MASK 0xFFFF7FC0u /**< \deprecated (TC_CMR_WAVEFORM) Register MASK (Use TC_CMR_WAVEFORM_Msk instead) */ 383 #define TC_CMR_WAVEFORM_Msk 0xFFFF7FC0u /**< (TC_CMR_WAVEFORM) Register Mask */ 384 385 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ 386 #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ 387 #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ 388 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ 389 #define TC_CV_CV_Pos 0 390 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ 391 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ 392 #define TC_RA_RA_Pos 0 393 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ 394 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) 395 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ 396 #define TC_RB_RB_Pos 0 397 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ 398 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) 399 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ 400 #define TC_RC_RC_Pos 0 401 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ 402 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) 403 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ 404 #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ 405 #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ 406 #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ 407 #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ 408 #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ 409 #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ 410 #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ 411 #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ 412 #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ 413 #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ 414 #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ 415 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ 416 #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ 417 #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ 418 #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ 419 #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ 420 #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ 421 #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ 422 #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ 423 #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ 424 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ 425 #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ 426 #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ 427 #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ 428 #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ 429 #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ 430 #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ 431 #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ 432 #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ 433 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ 434 #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ 435 #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ 436 #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ 437 #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ 438 #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ 439 #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ 440 #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ 441 #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ 442 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ 443 #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ 444 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ 445 #define TC_BMR_TC0XC0S_Pos 0 446 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ 447 #define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) 448 #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ 449 #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ 450 #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ 451 #define TC_BMR_TC1XC1S_Pos 2 452 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ 453 #define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) 454 #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ 455 #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ 456 #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ 457 #define TC_BMR_TC2XC2S_Pos 4 458 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ 459 #define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) 460 #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ 461 #define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ 462 #define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ 463 #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ 464 #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ 465 #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ 466 #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ 467 #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ 468 #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ 469 #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ 470 #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ 471 #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ 472 #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ 473 #define TC_BMR_MAXFILT_Pos 20 474 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ 475 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) 476 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ 477 #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ 478 #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ 479 #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ 480 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ 481 #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ 482 #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ 483 #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ 484 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ 485 #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ 486 #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ 487 #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ 488 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ 489 #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ 490 #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ 491 #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ 492 #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ 493 /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ 494 #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ 495 #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ 496 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ 497 #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ 498 #define TC_WPMR_WPKEY_Pos 8 499 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ 500 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) 501 #define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 502 503 /*@}*/ 504 505 506 #endif /* _SAM4S_TC_COMPONENT_ */ 507
