1 /** 2 * \file 3 * 4 * \brief Component description for USBC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_USBC_COMPONENT_ 30 #define _SAM4L_USBC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR USBC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_USBC USB 2.0 Interface */ 36 /*@{*/ 37 38 #define USBC_I7553 39 #define REV_USBC 0x310 40 41 /* -------- USBC_UDCON : (USBC Offset: 0x000) (R/W 32) Device General Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t UADD:7; /*!< bit: 0.. 6 USB Address */ 46 uint32_t ADDEN:1; /*!< bit: 7 Address Enable */ 47 uint32_t DETACH:1; /*!< bit: 8 Detach */ 48 uint32_t RMWKUP:1; /*!< bit: 9 Remote Wake-Up */ 49 uint32_t SPDCONF:2; /*!< bit: 10..11 Speed configuration */ 50 uint32_t LS:1; /*!< bit: 12 Low Speed Mode Force */ 51 uint32_t TSTJ:1; /*!< bit: 13 Test mode J */ 52 uint32_t TSTK:1; /*!< bit: 14 Test mode K */ 53 uint32_t TSTPCKT:1; /*!< bit: 15 Test Packet mode */ 54 uint32_t OPMODE2:1; /*!< bit: 16 Specific Operational mode */ 55 uint32_t GNAK:1; /*!< bit: 17 Global NAK */ 56 uint32_t :14; /*!< bit: 18..31 Reserved */ 57 } bit; /*!< Structure used for bit access */ 58 uint32_t reg; /*!< Type used for register access */ 59 } USBC_UDCON_Type; 60 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 62 #define USBC_UDCON_OFFSET 0x000 /**< \brief (USBC_UDCON offset) Device General Control Register */ 63 #define USBC_UDCON_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UDCON reset_value) Device General Control Register */ 64 65 #define USBC_UDCON_UADD_Pos 0 /**< \brief (USBC_UDCON) USB Address */ 66 #define USBC_UDCON_UADD_Msk (_U_(0x7F) << USBC_UDCON_UADD_Pos) 67 #define USBC_UDCON_UADD(value) (USBC_UDCON_UADD_Msk & ((value) << USBC_UDCON_UADD_Pos)) 68 #define USBC_UDCON_ADDEN_Pos 7 /**< \brief (USBC_UDCON) Address Enable */ 69 #define USBC_UDCON_ADDEN (_U_(0x1) << USBC_UDCON_ADDEN_Pos) 70 #define USBC_UDCON_DETACH_Pos 8 /**< \brief (USBC_UDCON) Detach */ 71 #define USBC_UDCON_DETACH (_U_(0x1) << USBC_UDCON_DETACH_Pos) 72 #define USBC_UDCON_RMWKUP_Pos 9 /**< \brief (USBC_UDCON) Remote Wake-Up */ 73 #define USBC_UDCON_RMWKUP (_U_(0x1) << USBC_UDCON_RMWKUP_Pos) 74 #define USBC_UDCON_SPDCONF_Pos 10 /**< \brief (USBC_UDCON) Speed configuration */ 75 #define USBC_UDCON_SPDCONF_Msk (_U_(0x3) << USBC_UDCON_SPDCONF_Pos) 76 #define USBC_UDCON_SPDCONF(value) (USBC_UDCON_SPDCONF_Msk & ((value) << USBC_UDCON_SPDCONF_Pos)) 77 #define USBC_UDCON_LS_Pos 12 /**< \brief (USBC_UDCON) Low Speed Mode Force */ 78 #define USBC_UDCON_LS (_U_(0x1) << USBC_UDCON_LS_Pos) 79 #define USBC_UDCON_TSTJ_Pos 13 /**< \brief (USBC_UDCON) Test mode J */ 80 #define USBC_UDCON_TSTJ (_U_(0x1) << USBC_UDCON_TSTJ_Pos) 81 #define USBC_UDCON_TSTK_Pos 14 /**< \brief (USBC_UDCON) Test mode K */ 82 #define USBC_UDCON_TSTK (_U_(0x1) << USBC_UDCON_TSTK_Pos) 83 #define USBC_UDCON_TSTPCKT_Pos 15 /**< \brief (USBC_UDCON) Test Packet mode */ 84 #define USBC_UDCON_TSTPCKT (_U_(0x1) << USBC_UDCON_TSTPCKT_Pos) 85 #define USBC_UDCON_OPMODE2_Pos 16 /**< \brief (USBC_UDCON) Specific Operational mode */ 86 #define USBC_UDCON_OPMODE2 (_U_(0x1) << USBC_UDCON_OPMODE2_Pos) 87 #define USBC_UDCON_GNAK_Pos 17 /**< \brief (USBC_UDCON) Global NAK */ 88 #define USBC_UDCON_GNAK (_U_(0x1) << USBC_UDCON_GNAK_Pos) 89 #define USBC_UDCON_MASK _U_(0x0003FFFF) /**< \brief (USBC_UDCON) MASK Register */ 90 91 /* -------- USBC_UDINT : (USBC Offset: 0x004) (R/ 32) Device Global Interupt Register -------- */ 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 93 typedef union { 94 struct { 95 uint32_t SUSP:1; /*!< bit: 0 Suspend Interrupt */ 96 uint32_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt */ 97 uint32_t SOF:1; /*!< bit: 2 Start of Frame Interrupt */ 98 uint32_t EORST:1; /*!< bit: 3 End of Reset Interrupt */ 99 uint32_t WAKEUP:1; /*!< bit: 4 Wake-Up Interrupt */ 100 uint32_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt */ 101 uint32_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt */ 102 uint32_t :5; /*!< bit: 7..11 Reserved */ 103 uint32_t EP0INT:1; /*!< bit: 12 Endpoint 0 Interrupt */ 104 uint32_t EP1INT:1; /*!< bit: 13 Endpoint 1 Interrupt */ 105 uint32_t EP2INT:1; /*!< bit: 14 Endpoint 2 Interrupt */ 106 uint32_t EP3INT:1; /*!< bit: 15 Endpoint 3 Interrupt */ 107 uint32_t EP4INT:1; /*!< bit: 16 Endpoint 4 Interrupt */ 108 uint32_t EP5INT:1; /*!< bit: 17 Endpoint 5 Interrupt */ 109 uint32_t EP6INT:1; /*!< bit: 18 Endpoint 6 Interrupt */ 110 uint32_t EP7INT:1; /*!< bit: 19 Endpoint 7 Interrupt */ 111 uint32_t :12; /*!< bit: 20..31 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint32_t reg; /*!< Type used for register access */ 114 } USBC_UDINT_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define USBC_UDINT_OFFSET 0x004 /**< \brief (USBC_UDINT offset) Device Global Interupt Register */ 118 #define USBC_UDINT_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINT reset_value) Device Global Interupt Register */ 119 120 #define USBC_UDINT_SUSP_Pos 0 /**< \brief (USBC_UDINT) Suspend Interrupt */ 121 #define USBC_UDINT_SUSP (_U_(0x1) << USBC_UDINT_SUSP_Pos) 122 #define USBC_UDINT_MSOF_Pos 1 /**< \brief (USBC_UDINT) Micro Start of Frame Interrupt */ 123 #define USBC_UDINT_MSOF (_U_(0x1) << USBC_UDINT_MSOF_Pos) 124 #define USBC_UDINT_SOF_Pos 2 /**< \brief (USBC_UDINT) Start of Frame Interrupt */ 125 #define USBC_UDINT_SOF (_U_(0x1) << USBC_UDINT_SOF_Pos) 126 #define USBC_UDINT_EORST_Pos 3 /**< \brief (USBC_UDINT) End of Reset Interrupt */ 127 #define USBC_UDINT_EORST (_U_(0x1) << USBC_UDINT_EORST_Pos) 128 #define USBC_UDINT_WAKEUP_Pos 4 /**< \brief (USBC_UDINT) Wake-Up Interrupt */ 129 #define USBC_UDINT_WAKEUP (_U_(0x1) << USBC_UDINT_WAKEUP_Pos) 130 #define USBC_UDINT_EORSM_Pos 5 /**< \brief (USBC_UDINT) End Of Resume Interrupt */ 131 #define USBC_UDINT_EORSM (_U_(0x1) << USBC_UDINT_EORSM_Pos) 132 #define USBC_UDINT_UPRSM_Pos 6 /**< \brief (USBC_UDINT) Upstream Resume Interrupt */ 133 #define USBC_UDINT_UPRSM (_U_(0x1) << USBC_UDINT_UPRSM_Pos) 134 #define USBC_UDINT_EP0INT_Pos 12 /**< \brief (USBC_UDINT) Endpoint 0 Interrupt */ 135 #define USBC_UDINT_EP0INT (_U_(0x1) << USBC_UDINT_EP0INT_Pos) 136 #define USBC_UDINT_EP1INT_Pos 13 /**< \brief (USBC_UDINT) Endpoint 1 Interrupt */ 137 #define USBC_UDINT_EP1INT (_U_(0x1) << USBC_UDINT_EP1INT_Pos) 138 #define USBC_UDINT_EP2INT_Pos 14 /**< \brief (USBC_UDINT) Endpoint 2 Interrupt */ 139 #define USBC_UDINT_EP2INT (_U_(0x1) << USBC_UDINT_EP2INT_Pos) 140 #define USBC_UDINT_EP3INT_Pos 15 /**< \brief (USBC_UDINT) Endpoint 3 Interrupt */ 141 #define USBC_UDINT_EP3INT (_U_(0x1) << USBC_UDINT_EP3INT_Pos) 142 #define USBC_UDINT_EP4INT_Pos 16 /**< \brief (USBC_UDINT) Endpoint 4 Interrupt */ 143 #define USBC_UDINT_EP4INT (_U_(0x1) << USBC_UDINT_EP4INT_Pos) 144 #define USBC_UDINT_EP5INT_Pos 17 /**< \brief (USBC_UDINT) Endpoint 5 Interrupt */ 145 #define USBC_UDINT_EP5INT (_U_(0x1) << USBC_UDINT_EP5INT_Pos) 146 #define USBC_UDINT_EP6INT_Pos 18 /**< \brief (USBC_UDINT) Endpoint 6 Interrupt */ 147 #define USBC_UDINT_EP6INT (_U_(0x1) << USBC_UDINT_EP6INT_Pos) 148 #define USBC_UDINT_EP7INT_Pos 19 /**< \brief (USBC_UDINT) Endpoint 7 Interrupt */ 149 #define USBC_UDINT_EP7INT (_U_(0x1) << USBC_UDINT_EP7INT_Pos) 150 #define USBC_UDINT_MASK _U_(0x000FF07F) /**< \brief (USBC_UDINT) MASK Register */ 151 152 /* -------- USBC_UDINTCLR : (USBC Offset: 0x008) ( /W 32) Device Global Interrupt Clear Register -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint32_t SUSPC:1; /*!< bit: 0 SUSP Interrupt Clear */ 157 uint32_t MSOFC:1; /*!< bit: 1 MSOF Interrupt Clear */ 158 uint32_t SOFC:1; /*!< bit: 2 SOF Interrupt Clear */ 159 uint32_t EORSTC:1; /*!< bit: 3 EORST Interrupt Clear */ 160 uint32_t WAKEUPC:1; /*!< bit: 4 WAKEUP Interrupt Clear */ 161 uint32_t EORSMC:1; /*!< bit: 5 EORSM Interrupt Clear */ 162 uint32_t UPRSMC:1; /*!< bit: 6 UPRSM Interrupt Clear */ 163 uint32_t :25; /*!< bit: 7..31 Reserved */ 164 } bit; /*!< Structure used for bit access */ 165 uint32_t reg; /*!< Type used for register access */ 166 } USBC_UDINTCLR_Type; 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 168 169 #define USBC_UDINTCLR_OFFSET 0x008 /**< \brief (USBC_UDINTCLR offset) Device Global Interrupt Clear Register */ 170 #define USBC_UDINTCLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINTCLR reset_value) Device Global Interrupt Clear Register */ 171 172 #define USBC_UDINTCLR_SUSPC_Pos 0 /**< \brief (USBC_UDINTCLR) SUSP Interrupt Clear */ 173 #define USBC_UDINTCLR_SUSPC (_U_(0x1) << USBC_UDINTCLR_SUSPC_Pos) 174 #define USBC_UDINTCLR_MSOFC_Pos 1 /**< \brief (USBC_UDINTCLR) MSOF Interrupt Clear */ 175 #define USBC_UDINTCLR_MSOFC (_U_(0x1) << USBC_UDINTCLR_MSOFC_Pos) 176 #define USBC_UDINTCLR_SOFC_Pos 2 /**< \brief (USBC_UDINTCLR) SOF Interrupt Clear */ 177 #define USBC_UDINTCLR_SOFC (_U_(0x1) << USBC_UDINTCLR_SOFC_Pos) 178 #define USBC_UDINTCLR_EORSTC_Pos 3 /**< \brief (USBC_UDINTCLR) EORST Interrupt Clear */ 179 #define USBC_UDINTCLR_EORSTC (_U_(0x1) << USBC_UDINTCLR_EORSTC_Pos) 180 #define USBC_UDINTCLR_WAKEUPC_Pos 4 /**< \brief (USBC_UDINTCLR) WAKEUP Interrupt Clear */ 181 #define USBC_UDINTCLR_WAKEUPC (_U_(0x1) << USBC_UDINTCLR_WAKEUPC_Pos) 182 #define USBC_UDINTCLR_EORSMC_Pos 5 /**< \brief (USBC_UDINTCLR) EORSM Interrupt Clear */ 183 #define USBC_UDINTCLR_EORSMC (_U_(0x1) << USBC_UDINTCLR_EORSMC_Pos) 184 #define USBC_UDINTCLR_UPRSMC_Pos 6 /**< \brief (USBC_UDINTCLR) UPRSM Interrupt Clear */ 185 #define USBC_UDINTCLR_UPRSMC (_U_(0x1) << USBC_UDINTCLR_UPRSMC_Pos) 186 #define USBC_UDINTCLR_MASK _U_(0x0000007F) /**< \brief (USBC_UDINTCLR) MASK Register */ 187 188 /* -------- USBC_UDINTSET : (USBC Offset: 0x00C) ( /W 32) Device Global Interrupt Set Regsiter -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint32_t SUSPS:1; /*!< bit: 0 SUSP Interrupt Set */ 193 uint32_t MSOFS:1; /*!< bit: 1 MSOF Interrupt Set */ 194 uint32_t SOFS:1; /*!< bit: 2 SOF Interrupt Set */ 195 uint32_t EORSTS:1; /*!< bit: 3 EORST Interrupt Set */ 196 uint32_t WAKEUPS:1; /*!< bit: 4 WAKEUP Interrupt Set */ 197 uint32_t EORSMS:1; /*!< bit: 5 EORSM Interrupt Set */ 198 uint32_t UPRSMS:1; /*!< bit: 6 UPRSM Interrupt Set */ 199 uint32_t :25; /*!< bit: 7..31 Reserved */ 200 } bit; /*!< Structure used for bit access */ 201 uint32_t reg; /*!< Type used for register access */ 202 } USBC_UDINTSET_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define USBC_UDINTSET_OFFSET 0x00C /**< \brief (USBC_UDINTSET offset) Device Global Interrupt Set Regsiter */ 206 #define USBC_UDINTSET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINTSET reset_value) Device Global Interrupt Set Regsiter */ 207 208 #define USBC_UDINTSET_SUSPS_Pos 0 /**< \brief (USBC_UDINTSET) SUSP Interrupt Set */ 209 #define USBC_UDINTSET_SUSPS (_U_(0x1) << USBC_UDINTSET_SUSPS_Pos) 210 #define USBC_UDINTSET_MSOFS_Pos 1 /**< \brief (USBC_UDINTSET) MSOF Interrupt Set */ 211 #define USBC_UDINTSET_MSOFS (_U_(0x1) << USBC_UDINTSET_MSOFS_Pos) 212 #define USBC_UDINTSET_SOFS_Pos 2 /**< \brief (USBC_UDINTSET) SOF Interrupt Set */ 213 #define USBC_UDINTSET_SOFS (_U_(0x1) << USBC_UDINTSET_SOFS_Pos) 214 #define USBC_UDINTSET_EORSTS_Pos 3 /**< \brief (USBC_UDINTSET) EORST Interrupt Set */ 215 #define USBC_UDINTSET_EORSTS (_U_(0x1) << USBC_UDINTSET_EORSTS_Pos) 216 #define USBC_UDINTSET_WAKEUPS_Pos 4 /**< \brief (USBC_UDINTSET) WAKEUP Interrupt Set */ 217 #define USBC_UDINTSET_WAKEUPS (_U_(0x1) << USBC_UDINTSET_WAKEUPS_Pos) 218 #define USBC_UDINTSET_EORSMS_Pos 5 /**< \brief (USBC_UDINTSET) EORSM Interrupt Set */ 219 #define USBC_UDINTSET_EORSMS (_U_(0x1) << USBC_UDINTSET_EORSMS_Pos) 220 #define USBC_UDINTSET_UPRSMS_Pos 6 /**< \brief (USBC_UDINTSET) UPRSM Interrupt Set */ 221 #define USBC_UDINTSET_UPRSMS (_U_(0x1) << USBC_UDINTSET_UPRSMS_Pos) 222 #define USBC_UDINTSET_MASK _U_(0x0000007F) /**< \brief (USBC_UDINTSET) MASK Register */ 223 224 /* -------- USBC_UDINTE : (USBC Offset: 0x010) (R/ 32) Device Global Interrupt Enable Register -------- */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef union { 227 struct { 228 uint32_t SUSPE:1; /*!< bit: 0 SUSP Interrupt Enable */ 229 uint32_t MSOFE:1; /*!< bit: 1 MSOF Interrupt Enable */ 230 uint32_t SOFE:1; /*!< bit: 2 SOF Interrupt Enable */ 231 uint32_t EORSTE:1; /*!< bit: 3 EORST Interrupt Enable */ 232 uint32_t WAKEUPE:1; /*!< bit: 4 WAKEUP Interrupt Enable */ 233 uint32_t EORSME:1; /*!< bit: 5 EORSM Interrupt Enable */ 234 uint32_t UPRSME:1; /*!< bit: 6 UPRSM Interrupt Enable */ 235 uint32_t :5; /*!< bit: 7..11 Reserved */ 236 uint32_t EP0INTE:1; /*!< bit: 12 EP0INT Interrupt Enable */ 237 uint32_t EP1INTE:1; /*!< bit: 13 EP1INT Interrupt Enable */ 238 uint32_t EP2INTE:1; /*!< bit: 14 EP2INT Interrupt Enable */ 239 uint32_t EP3INTE:1; /*!< bit: 15 EP3INT Interrupt Enable */ 240 uint32_t EP4INTE:1; /*!< bit: 16 EP4INT Interrupt Enable */ 241 uint32_t EP5INTE:1; /*!< bit: 17 EP5INT Interrupt Enable */ 242 uint32_t EP6INTE:1; /*!< bit: 18 EP6INT Interrupt Enable */ 243 uint32_t EP7INTE:1; /*!< bit: 19 EP7INT Interrupt Enable */ 244 uint32_t :12; /*!< bit: 20..31 Reserved */ 245 } bit; /*!< Structure used for bit access */ 246 uint32_t reg; /*!< Type used for register access */ 247 } USBC_UDINTE_Type; 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 #define USBC_UDINTE_OFFSET 0x010 /**< \brief (USBC_UDINTE offset) Device Global Interrupt Enable Register */ 251 #define USBC_UDINTE_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINTE reset_value) Device Global Interrupt Enable Register */ 252 253 #define USBC_UDINTE_SUSPE_Pos 0 /**< \brief (USBC_UDINTE) SUSP Interrupt Enable */ 254 #define USBC_UDINTE_SUSPE (_U_(0x1) << USBC_UDINTE_SUSPE_Pos) 255 #define USBC_UDINTE_MSOFE_Pos 1 /**< \brief (USBC_UDINTE) MSOF Interrupt Enable */ 256 #define USBC_UDINTE_MSOFE (_U_(0x1) << USBC_UDINTE_MSOFE_Pos) 257 #define USBC_UDINTE_SOFE_Pos 2 /**< \brief (USBC_UDINTE) SOF Interrupt Enable */ 258 #define USBC_UDINTE_SOFE (_U_(0x1) << USBC_UDINTE_SOFE_Pos) 259 #define USBC_UDINTE_EORSTE_Pos 3 /**< \brief (USBC_UDINTE) EORST Interrupt Enable */ 260 #define USBC_UDINTE_EORSTE (_U_(0x1) << USBC_UDINTE_EORSTE_Pos) 261 #define USBC_UDINTE_WAKEUPE_Pos 4 /**< \brief (USBC_UDINTE) WAKEUP Interrupt Enable */ 262 #define USBC_UDINTE_WAKEUPE (_U_(0x1) << USBC_UDINTE_WAKEUPE_Pos) 263 #define USBC_UDINTE_EORSME_Pos 5 /**< \brief (USBC_UDINTE) EORSM Interrupt Enable */ 264 #define USBC_UDINTE_EORSME (_U_(0x1) << USBC_UDINTE_EORSME_Pos) 265 #define USBC_UDINTE_UPRSME_Pos 6 /**< \brief (USBC_UDINTE) UPRSM Interrupt Enable */ 266 #define USBC_UDINTE_UPRSME (_U_(0x1) << USBC_UDINTE_UPRSME_Pos) 267 #define USBC_UDINTE_EP0INTE_Pos 12 /**< \brief (USBC_UDINTE) EP0INT Interrupt Enable */ 268 #define USBC_UDINTE_EP0INTE (_U_(0x1) << USBC_UDINTE_EP0INTE_Pos) 269 #define USBC_UDINTE_EP1INTE_Pos 13 /**< \brief (USBC_UDINTE) EP1INT Interrupt Enable */ 270 #define USBC_UDINTE_EP1INTE (_U_(0x1) << USBC_UDINTE_EP1INTE_Pos) 271 #define USBC_UDINTE_EP2INTE_Pos 14 /**< \brief (USBC_UDINTE) EP2INT Interrupt Enable */ 272 #define USBC_UDINTE_EP2INTE (_U_(0x1) << USBC_UDINTE_EP2INTE_Pos) 273 #define USBC_UDINTE_EP3INTE_Pos 15 /**< \brief (USBC_UDINTE) EP3INT Interrupt Enable */ 274 #define USBC_UDINTE_EP3INTE (_U_(0x1) << USBC_UDINTE_EP3INTE_Pos) 275 #define USBC_UDINTE_EP4INTE_Pos 16 /**< \brief (USBC_UDINTE) EP4INT Interrupt Enable */ 276 #define USBC_UDINTE_EP4INTE (_U_(0x1) << USBC_UDINTE_EP4INTE_Pos) 277 #define USBC_UDINTE_EP5INTE_Pos 17 /**< \brief (USBC_UDINTE) EP5INT Interrupt Enable */ 278 #define USBC_UDINTE_EP5INTE (_U_(0x1) << USBC_UDINTE_EP5INTE_Pos) 279 #define USBC_UDINTE_EP6INTE_Pos 18 /**< \brief (USBC_UDINTE) EP6INT Interrupt Enable */ 280 #define USBC_UDINTE_EP6INTE (_U_(0x1) << USBC_UDINTE_EP6INTE_Pos) 281 #define USBC_UDINTE_EP7INTE_Pos 19 /**< \brief (USBC_UDINTE) EP7INT Interrupt Enable */ 282 #define USBC_UDINTE_EP7INTE (_U_(0x1) << USBC_UDINTE_EP7INTE_Pos) 283 #define USBC_UDINTE_MASK _U_(0x000FF07F) /**< \brief (USBC_UDINTE) MASK Register */ 284 285 /* -------- USBC_UDINTECLR : (USBC Offset: 0x014) ( /W 32) Device Global Interrupt Enable Clear Register -------- */ 286 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 287 typedef union { 288 struct { 289 uint32_t SUSPEC:1; /*!< bit: 0 SUSP Interrupt Enable Clear */ 290 uint32_t MSOFEC:1; /*!< bit: 1 MSOF Interrupt Enable Clear */ 291 uint32_t SOFEC:1; /*!< bit: 2 SOF Interrupt Enable Clear */ 292 uint32_t EORSTEC:1; /*!< bit: 3 EORST Interrupt Enable Clear */ 293 uint32_t WAKEUPEC:1; /*!< bit: 4 WAKEUP Interrupt Enable Clear */ 294 uint32_t EORSMEC:1; /*!< bit: 5 EORSM Interrupt Enable Clear */ 295 uint32_t UPRSMEC:1; /*!< bit: 6 UPRSM Interrupt Enable Clear */ 296 uint32_t :5; /*!< bit: 7..11 Reserved */ 297 uint32_t EP0INTEC:1; /*!< bit: 12 EP0INT Interrupt Enable Clear */ 298 uint32_t EP1INTEC:1; /*!< bit: 13 EP1INT Interrupt Enable Clear */ 299 uint32_t EP2INTEC:1; /*!< bit: 14 EP2INT Interrupt Enable Clear */ 300 uint32_t EP3INTEC:1; /*!< bit: 15 EP3INT Interrupt Enable Clear */ 301 uint32_t EP4INTEC:1; /*!< bit: 16 EP4INT Interrupt Enable Clear */ 302 uint32_t EP5INTEC:1; /*!< bit: 17 EP5INT Interrupt Enable Clear */ 303 uint32_t EP6INTEC:1; /*!< bit: 18 EP6INT Interrupt Enable Clear */ 304 uint32_t EP7INTEC:1; /*!< bit: 19 EP7INT Interrupt Enable Clear */ 305 uint32_t :12; /*!< bit: 20..31 Reserved */ 306 } bit; /*!< Structure used for bit access */ 307 uint32_t reg; /*!< Type used for register access */ 308 } USBC_UDINTECLR_Type; 309 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 310 311 #define USBC_UDINTECLR_OFFSET 0x014 /**< \brief (USBC_UDINTECLR offset) Device Global Interrupt Enable Clear Register */ 312 #define USBC_UDINTECLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINTECLR reset_value) Device Global Interrupt Enable Clear Register */ 313 314 #define USBC_UDINTECLR_SUSPEC_Pos 0 /**< \brief (USBC_UDINTECLR) SUSP Interrupt Enable Clear */ 315 #define USBC_UDINTECLR_SUSPEC (_U_(0x1) << USBC_UDINTECLR_SUSPEC_Pos) 316 #define USBC_UDINTECLR_MSOFEC_Pos 1 /**< \brief (USBC_UDINTECLR) MSOF Interrupt Enable Clear */ 317 #define USBC_UDINTECLR_MSOFEC (_U_(0x1) << USBC_UDINTECLR_MSOFEC_Pos) 318 #define USBC_UDINTECLR_SOFEC_Pos 2 /**< \brief (USBC_UDINTECLR) SOF Interrupt Enable Clear */ 319 #define USBC_UDINTECLR_SOFEC (_U_(0x1) << USBC_UDINTECLR_SOFEC_Pos) 320 #define USBC_UDINTECLR_EORSTEC_Pos 3 /**< \brief (USBC_UDINTECLR) EORST Interrupt Enable Clear */ 321 #define USBC_UDINTECLR_EORSTEC (_U_(0x1) << USBC_UDINTECLR_EORSTEC_Pos) 322 #define USBC_UDINTECLR_WAKEUPEC_Pos 4 /**< \brief (USBC_UDINTECLR) WAKEUP Interrupt Enable Clear */ 323 #define USBC_UDINTECLR_WAKEUPEC (_U_(0x1) << USBC_UDINTECLR_WAKEUPEC_Pos) 324 #define USBC_UDINTECLR_EORSMEC_Pos 5 /**< \brief (USBC_UDINTECLR) EORSM Interrupt Enable Clear */ 325 #define USBC_UDINTECLR_EORSMEC (_U_(0x1) << USBC_UDINTECLR_EORSMEC_Pos) 326 #define USBC_UDINTECLR_UPRSMEC_Pos 6 /**< \brief (USBC_UDINTECLR) UPRSM Interrupt Enable Clear */ 327 #define USBC_UDINTECLR_UPRSMEC (_U_(0x1) << USBC_UDINTECLR_UPRSMEC_Pos) 328 #define USBC_UDINTECLR_EP0INTEC_Pos 12 /**< \brief (USBC_UDINTECLR) EP0INT Interrupt Enable Clear */ 329 #define USBC_UDINTECLR_EP0INTEC (_U_(0x1) << USBC_UDINTECLR_EP0INTEC_Pos) 330 #define USBC_UDINTECLR_EP1INTEC_Pos 13 /**< \brief (USBC_UDINTECLR) EP1INT Interrupt Enable Clear */ 331 #define USBC_UDINTECLR_EP1INTEC (_U_(0x1) << USBC_UDINTECLR_EP1INTEC_Pos) 332 #define USBC_UDINTECLR_EP2INTEC_Pos 14 /**< \brief (USBC_UDINTECLR) EP2INT Interrupt Enable Clear */ 333 #define USBC_UDINTECLR_EP2INTEC (_U_(0x1) << USBC_UDINTECLR_EP2INTEC_Pos) 334 #define USBC_UDINTECLR_EP3INTEC_Pos 15 /**< \brief (USBC_UDINTECLR) EP3INT Interrupt Enable Clear */ 335 #define USBC_UDINTECLR_EP3INTEC (_U_(0x1) << USBC_UDINTECLR_EP3INTEC_Pos) 336 #define USBC_UDINTECLR_EP4INTEC_Pos 16 /**< \brief (USBC_UDINTECLR) EP4INT Interrupt Enable Clear */ 337 #define USBC_UDINTECLR_EP4INTEC (_U_(0x1) << USBC_UDINTECLR_EP4INTEC_Pos) 338 #define USBC_UDINTECLR_EP5INTEC_Pos 17 /**< \brief (USBC_UDINTECLR) EP5INT Interrupt Enable Clear */ 339 #define USBC_UDINTECLR_EP5INTEC (_U_(0x1) << USBC_UDINTECLR_EP5INTEC_Pos) 340 #define USBC_UDINTECLR_EP6INTEC_Pos 18 /**< \brief (USBC_UDINTECLR) EP6INT Interrupt Enable Clear */ 341 #define USBC_UDINTECLR_EP6INTEC (_U_(0x1) << USBC_UDINTECLR_EP6INTEC_Pos) 342 #define USBC_UDINTECLR_EP7INTEC_Pos 19 /**< \brief (USBC_UDINTECLR) EP7INT Interrupt Enable Clear */ 343 #define USBC_UDINTECLR_EP7INTEC (_U_(0x1) << USBC_UDINTECLR_EP7INTEC_Pos) 344 #define USBC_UDINTECLR_MASK _U_(0x000FF07F) /**< \brief (USBC_UDINTECLR) MASK Register */ 345 346 /* -------- USBC_UDINTESET : (USBC Offset: 0x018) ( /W 32) Device Global Interrupt Enable Set Register -------- */ 347 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 348 typedef union { 349 struct { 350 uint32_t SUSPES:1; /*!< bit: 0 SUSP Interrupt Enable Set */ 351 uint32_t MSOFES:1; /*!< bit: 1 MSOF Interrupt Enable Set */ 352 uint32_t SOFES:1; /*!< bit: 2 SOF Interrupt Enable Set */ 353 uint32_t EORSTES:1; /*!< bit: 3 EORST Interrupt Enable Set */ 354 uint32_t WAKEUPES:1; /*!< bit: 4 WAKEUP Interrupt Enable Set */ 355 uint32_t EORSMES:1; /*!< bit: 5 EORSM Interrupt Enable Set */ 356 uint32_t UPRSMES:1; /*!< bit: 6 UPRSM Interrupt Enable Set */ 357 uint32_t :5; /*!< bit: 7..11 Reserved */ 358 uint32_t EP0INTES:1; /*!< bit: 12 EP0INT Interrupt Enable Set */ 359 uint32_t EP1INTES:1; /*!< bit: 13 EP1INT Interrupt Enable Set */ 360 uint32_t EP2INTES:1; /*!< bit: 14 EP2INT Interrupt Enable Set */ 361 uint32_t EP3INTES:1; /*!< bit: 15 EP3INT Interrupt Enable Set */ 362 uint32_t EP4INTES:1; /*!< bit: 16 EP4INT Interrupt Enable Set */ 363 uint32_t EP5INTES:1; /*!< bit: 17 EP5INT Interrupt Enable Set */ 364 uint32_t EP6INTES:1; /*!< bit: 18 EP6INT Interrupt Enable Set */ 365 uint32_t EP7INTES:1; /*!< bit: 19 EP7INT Interrupt Enable Set */ 366 uint32_t :12; /*!< bit: 20..31 Reserved */ 367 } bit; /*!< Structure used for bit access */ 368 uint32_t reg; /*!< Type used for register access */ 369 } USBC_UDINTESET_Type; 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 #define USBC_UDINTESET_OFFSET 0x018 /**< \brief (USBC_UDINTESET offset) Device Global Interrupt Enable Set Register */ 373 #define USBC_UDINTESET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDINTESET reset_value) Device Global Interrupt Enable Set Register */ 374 375 #define USBC_UDINTESET_SUSPES_Pos 0 /**< \brief (USBC_UDINTESET) SUSP Interrupt Enable Set */ 376 #define USBC_UDINTESET_SUSPES (_U_(0x1) << USBC_UDINTESET_SUSPES_Pos) 377 #define USBC_UDINTESET_MSOFES_Pos 1 /**< \brief (USBC_UDINTESET) MSOF Interrupt Enable Set */ 378 #define USBC_UDINTESET_MSOFES (_U_(0x1) << USBC_UDINTESET_MSOFES_Pos) 379 #define USBC_UDINTESET_SOFES_Pos 2 /**< \brief (USBC_UDINTESET) SOF Interrupt Enable Set */ 380 #define USBC_UDINTESET_SOFES (_U_(0x1) << USBC_UDINTESET_SOFES_Pos) 381 #define USBC_UDINTESET_EORSTES_Pos 3 /**< \brief (USBC_UDINTESET) EORST Interrupt Enable Set */ 382 #define USBC_UDINTESET_EORSTES (_U_(0x1) << USBC_UDINTESET_EORSTES_Pos) 383 #define USBC_UDINTESET_WAKEUPES_Pos 4 /**< \brief (USBC_UDINTESET) WAKEUP Interrupt Enable Set */ 384 #define USBC_UDINTESET_WAKEUPES (_U_(0x1) << USBC_UDINTESET_WAKEUPES_Pos) 385 #define USBC_UDINTESET_EORSMES_Pos 5 /**< \brief (USBC_UDINTESET) EORSM Interrupt Enable Set */ 386 #define USBC_UDINTESET_EORSMES (_U_(0x1) << USBC_UDINTESET_EORSMES_Pos) 387 #define USBC_UDINTESET_UPRSMES_Pos 6 /**< \brief (USBC_UDINTESET) UPRSM Interrupt Enable Set */ 388 #define USBC_UDINTESET_UPRSMES (_U_(0x1) << USBC_UDINTESET_UPRSMES_Pos) 389 #define USBC_UDINTESET_EP0INTES_Pos 12 /**< \brief (USBC_UDINTESET) EP0INT Interrupt Enable Set */ 390 #define USBC_UDINTESET_EP0INTES (_U_(0x1) << USBC_UDINTESET_EP0INTES_Pos) 391 #define USBC_UDINTESET_EP1INTES_Pos 13 /**< \brief (USBC_UDINTESET) EP1INT Interrupt Enable Set */ 392 #define USBC_UDINTESET_EP1INTES (_U_(0x1) << USBC_UDINTESET_EP1INTES_Pos) 393 #define USBC_UDINTESET_EP2INTES_Pos 14 /**< \brief (USBC_UDINTESET) EP2INT Interrupt Enable Set */ 394 #define USBC_UDINTESET_EP2INTES (_U_(0x1) << USBC_UDINTESET_EP2INTES_Pos) 395 #define USBC_UDINTESET_EP3INTES_Pos 15 /**< \brief (USBC_UDINTESET) EP3INT Interrupt Enable Set */ 396 #define USBC_UDINTESET_EP3INTES (_U_(0x1) << USBC_UDINTESET_EP3INTES_Pos) 397 #define USBC_UDINTESET_EP4INTES_Pos 16 /**< \brief (USBC_UDINTESET) EP4INT Interrupt Enable Set */ 398 #define USBC_UDINTESET_EP4INTES (_U_(0x1) << USBC_UDINTESET_EP4INTES_Pos) 399 #define USBC_UDINTESET_EP5INTES_Pos 17 /**< \brief (USBC_UDINTESET) EP5INT Interrupt Enable Set */ 400 #define USBC_UDINTESET_EP5INTES (_U_(0x1) << USBC_UDINTESET_EP5INTES_Pos) 401 #define USBC_UDINTESET_EP6INTES_Pos 18 /**< \brief (USBC_UDINTESET) EP6INT Interrupt Enable Set */ 402 #define USBC_UDINTESET_EP6INTES (_U_(0x1) << USBC_UDINTESET_EP6INTES_Pos) 403 #define USBC_UDINTESET_EP7INTES_Pos 19 /**< \brief (USBC_UDINTESET) EP7INT Interrupt Enable Set */ 404 #define USBC_UDINTESET_EP7INTES (_U_(0x1) << USBC_UDINTESET_EP7INTES_Pos) 405 #define USBC_UDINTESET_MASK _U_(0x000FF07F) /**< \brief (USBC_UDINTESET) MASK Register */ 406 407 /* -------- USBC_UERST : (USBC Offset: 0x01C) (R/W 32) Endpoint Enable/Reset Register -------- */ 408 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 409 typedef union { 410 struct { 411 uint32_t EPEN0:1; /*!< bit: 0 Endpoint0 Enable */ 412 uint32_t EPEN1:1; /*!< bit: 1 Endpoint1 Enable */ 413 uint32_t EPEN2:1; /*!< bit: 2 Endpoint2 Enable */ 414 uint32_t EPEN3:1; /*!< bit: 3 Endpoint3 Enable */ 415 uint32_t EPEN4:1; /*!< bit: 4 Endpoint4 Enable */ 416 uint32_t EPEN5:1; /*!< bit: 5 Endpoint5 Enable */ 417 uint32_t EPEN6:1; /*!< bit: 6 Endpoint6 Enable */ 418 uint32_t EPEN7:1; /*!< bit: 7 Endpoint7 Enable */ 419 uint32_t :24; /*!< bit: 8..31 Reserved */ 420 } bit; /*!< Structure used for bit access */ 421 uint32_t reg; /*!< Type used for register access */ 422 } USBC_UERST_Type; 423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 424 425 #define USBC_UERST_OFFSET 0x01C /**< \brief (USBC_UERST offset) Endpoint Enable/Reset Register */ 426 #define USBC_UERST_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UERST reset_value) Endpoint Enable/Reset Register */ 427 428 #define USBC_UERST_EPEN0_Pos 0 /**< \brief (USBC_UERST) Endpoint0 Enable */ 429 #define USBC_UERST_EPEN0 (_U_(0x1) << USBC_UERST_EPEN0_Pos) 430 #define USBC_UERST_EPEN1_Pos 1 /**< \brief (USBC_UERST) Endpoint1 Enable */ 431 #define USBC_UERST_EPEN1 (_U_(0x1) << USBC_UERST_EPEN1_Pos) 432 #define USBC_UERST_EPEN2_Pos 2 /**< \brief (USBC_UERST) Endpoint2 Enable */ 433 #define USBC_UERST_EPEN2 (_U_(0x1) << USBC_UERST_EPEN2_Pos) 434 #define USBC_UERST_EPEN3_Pos 3 /**< \brief (USBC_UERST) Endpoint3 Enable */ 435 #define USBC_UERST_EPEN3 (_U_(0x1) << USBC_UERST_EPEN3_Pos) 436 #define USBC_UERST_EPEN4_Pos 4 /**< \brief (USBC_UERST) Endpoint4 Enable */ 437 #define USBC_UERST_EPEN4 (_U_(0x1) << USBC_UERST_EPEN4_Pos) 438 #define USBC_UERST_EPEN5_Pos 5 /**< \brief (USBC_UERST) Endpoint5 Enable */ 439 #define USBC_UERST_EPEN5 (_U_(0x1) << USBC_UERST_EPEN5_Pos) 440 #define USBC_UERST_EPEN6_Pos 6 /**< \brief (USBC_UERST) Endpoint6 Enable */ 441 #define USBC_UERST_EPEN6 (_U_(0x1) << USBC_UERST_EPEN6_Pos) 442 #define USBC_UERST_EPEN7_Pos 7 /**< \brief (USBC_UERST) Endpoint7 Enable */ 443 #define USBC_UERST_EPEN7 (_U_(0x1) << USBC_UERST_EPEN7_Pos) 444 #define USBC_UERST_MASK _U_(0x000000FF) /**< \brief (USBC_UERST) MASK Register */ 445 446 /* -------- USBC_UDFNUM : (USBC Offset: 0x020) (R/ 32) Device Frame Number Register -------- */ 447 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 448 typedef union { 449 struct { 450 uint32_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 451 uint32_t FNUM:11; /*!< bit: 3..13 Frame Number */ 452 uint32_t :1; /*!< bit: 14 Reserved */ 453 uint32_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ 454 uint32_t :16; /*!< bit: 16..31 Reserved */ 455 } bit; /*!< Structure used for bit access */ 456 uint32_t reg; /*!< Type used for register access */ 457 } USBC_UDFNUM_Type; 458 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 459 460 #define USBC_UDFNUM_OFFSET 0x020 /**< \brief (USBC_UDFNUM offset) Device Frame Number Register */ 461 #define USBC_UDFNUM_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDFNUM reset_value) Device Frame Number Register */ 462 463 #define USBC_UDFNUM_MFNUM_Pos 0 /**< \brief (USBC_UDFNUM) Micro Frame Number */ 464 #define USBC_UDFNUM_MFNUM_Msk (_U_(0x7) << USBC_UDFNUM_MFNUM_Pos) 465 #define USBC_UDFNUM_MFNUM(value) (USBC_UDFNUM_MFNUM_Msk & ((value) << USBC_UDFNUM_MFNUM_Pos)) 466 #define USBC_UDFNUM_FNUM_Pos 3 /**< \brief (USBC_UDFNUM) Frame Number */ 467 #define USBC_UDFNUM_FNUM_Msk (_U_(0x7FF) << USBC_UDFNUM_FNUM_Pos) 468 #define USBC_UDFNUM_FNUM(value) (USBC_UDFNUM_FNUM_Msk & ((value) << USBC_UDFNUM_FNUM_Pos)) 469 #define USBC_UDFNUM_FNCERR_Pos 15 /**< \brief (USBC_UDFNUM) Frame Number CRC Error */ 470 #define USBC_UDFNUM_FNCERR (_U_(0x1) << USBC_UDFNUM_FNCERR_Pos) 471 #define USBC_UDFNUM_MASK _U_(0x0000BFFF) /**< \brief (USBC_UDFNUM) MASK Register */ 472 473 /* -------- USBC_UECFG0 : (USBC Offset: 0x100) (R/W 32) Endpoint Configuration Register -------- */ 474 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 475 typedef union { 476 struct { 477 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 478 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 479 uint32_t :1; /*!< bit: 3 Reserved */ 480 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 481 uint32_t :1; /*!< bit: 7 Reserved */ 482 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 483 uint32_t :2; /*!< bit: 9..10 Reserved */ 484 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 485 uint32_t :3; /*!< bit: 13..15 Reserved */ 486 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 487 uint32_t :12; /*!< bit: 20..31 Reserved */ 488 } bit; /*!< Structure used for bit access */ 489 uint32_t reg; /*!< Type used for register access */ 490 } USBC_UECFG0_Type; 491 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 492 493 #define USBC_UECFG0_OFFSET 0x100 /**< \brief (USBC_UECFG0 offset) Endpoint Configuration Register */ 494 #define USBC_UECFG0_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG0 reset_value) Endpoint Configuration Register */ 495 496 #define USBC_UECFG0_EPBK_Pos 2 /**< \brief (USBC_UECFG0) Endpoint Bank */ 497 #define USBC_UECFG0_EPBK (_U_(0x1) << USBC_UECFG0_EPBK_Pos) 498 #define USBC_UECFG0_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG0) */ 499 #define USBC_UECFG0_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG0) */ 500 #define USBC_UECFG0_EPBK_SINGLE (USBC_UECFG0_EPBK_SINGLE_Val << USBC_UECFG0_EPBK_Pos) 501 #define USBC_UECFG0_EPBK_DOUBLE (USBC_UECFG0_EPBK_DOUBLE_Val << USBC_UECFG0_EPBK_Pos) 502 #define USBC_UECFG0_EPSIZE_Pos 4 /**< \brief (USBC_UECFG0) Endpoint Size */ 503 #define USBC_UECFG0_EPSIZE_Msk (_U_(0x7) << USBC_UECFG0_EPSIZE_Pos) 504 #define USBC_UECFG0_EPSIZE(value) (USBC_UECFG0_EPSIZE_Msk & ((value) << USBC_UECFG0_EPSIZE_Pos)) 505 #define USBC_UECFG0_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG0) */ 506 #define USBC_UECFG0_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG0) */ 507 #define USBC_UECFG0_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG0) */ 508 #define USBC_UECFG0_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG0) */ 509 #define USBC_UECFG0_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG0) */ 510 #define USBC_UECFG0_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG0) */ 511 #define USBC_UECFG0_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG0) */ 512 #define USBC_UECFG0_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG0) */ 513 #define USBC_UECFG0_EPSIZE_8 (USBC_UECFG0_EPSIZE_8_Val << USBC_UECFG0_EPSIZE_Pos) 514 #define USBC_UECFG0_EPSIZE_16 (USBC_UECFG0_EPSIZE_16_Val << USBC_UECFG0_EPSIZE_Pos) 515 #define USBC_UECFG0_EPSIZE_32 (USBC_UECFG0_EPSIZE_32_Val << USBC_UECFG0_EPSIZE_Pos) 516 #define USBC_UECFG0_EPSIZE_64 (USBC_UECFG0_EPSIZE_64_Val << USBC_UECFG0_EPSIZE_Pos) 517 #define USBC_UECFG0_EPSIZE_128 (USBC_UECFG0_EPSIZE_128_Val << USBC_UECFG0_EPSIZE_Pos) 518 #define USBC_UECFG0_EPSIZE_256 (USBC_UECFG0_EPSIZE_256_Val << USBC_UECFG0_EPSIZE_Pos) 519 #define USBC_UECFG0_EPSIZE_512 (USBC_UECFG0_EPSIZE_512_Val << USBC_UECFG0_EPSIZE_Pos) 520 #define USBC_UECFG0_EPSIZE_1024 (USBC_UECFG0_EPSIZE_1024_Val << USBC_UECFG0_EPSIZE_Pos) 521 #define USBC_UECFG0_EPDIR_Pos 8 /**< \brief (USBC_UECFG0) Endpoint Direction */ 522 #define USBC_UECFG0_EPDIR (_U_(0x1) << USBC_UECFG0_EPDIR_Pos) 523 #define USBC_UECFG0_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG0) */ 524 #define USBC_UECFG0_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG0) */ 525 #define USBC_UECFG0_EPDIR_OUT (USBC_UECFG0_EPDIR_OUT_Val << USBC_UECFG0_EPDIR_Pos) 526 #define USBC_UECFG0_EPDIR_IN (USBC_UECFG0_EPDIR_IN_Val << USBC_UECFG0_EPDIR_Pos) 527 #define USBC_UECFG0_EPTYPE_Pos 11 /**< \brief (USBC_UECFG0) Endpoint Type */ 528 #define USBC_UECFG0_EPTYPE_Msk (_U_(0x3) << USBC_UECFG0_EPTYPE_Pos) 529 #define USBC_UECFG0_EPTYPE(value) (USBC_UECFG0_EPTYPE_Msk & ((value) << USBC_UECFG0_EPTYPE_Pos)) 530 #define USBC_UECFG0_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG0) */ 531 #define USBC_UECFG0_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG0) */ 532 #define USBC_UECFG0_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG0) */ 533 #define USBC_UECFG0_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG0) */ 534 #define USBC_UECFG0_EPTYPE_CONTROL (USBC_UECFG0_EPTYPE_CONTROL_Val << USBC_UECFG0_EPTYPE_Pos) 535 #define USBC_UECFG0_EPTYPE_ISOCHRONOUS (USBC_UECFG0_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG0_EPTYPE_Pos) 536 #define USBC_UECFG0_EPTYPE_BULK (USBC_UECFG0_EPTYPE_BULK_Val << USBC_UECFG0_EPTYPE_Pos) 537 #define USBC_UECFG0_EPTYPE_INTERRUPT (USBC_UECFG0_EPTYPE_INTERRUPT_Val << USBC_UECFG0_EPTYPE_Pos) 538 #define USBC_UECFG0_REPNB_Pos 16 /**< \brief (USBC_UECFG0) Redirected Endpoint Number */ 539 #define USBC_UECFG0_REPNB_Msk (_U_(0xF) << USBC_UECFG0_REPNB_Pos) 540 #define USBC_UECFG0_REPNB(value) (USBC_UECFG0_REPNB_Msk & ((value) << USBC_UECFG0_REPNB_Pos)) 541 #define USBC_UECFG0_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG0) MASK Register */ 542 543 /* -------- USBC_UECFG1 : (USBC Offset: 0x104) (R/W 32) Endpoint Configuration Register -------- */ 544 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 545 typedef union { 546 struct { 547 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 548 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 549 uint32_t :1; /*!< bit: 3 Reserved */ 550 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 551 uint32_t :1; /*!< bit: 7 Reserved */ 552 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 553 uint32_t :2; /*!< bit: 9..10 Reserved */ 554 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 555 uint32_t :3; /*!< bit: 13..15 Reserved */ 556 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 557 uint32_t :12; /*!< bit: 20..31 Reserved */ 558 } bit; /*!< Structure used for bit access */ 559 uint32_t reg; /*!< Type used for register access */ 560 } USBC_UECFG1_Type; 561 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 562 563 #define USBC_UECFG1_OFFSET 0x104 /**< \brief (USBC_UECFG1 offset) Endpoint Configuration Register */ 564 #define USBC_UECFG1_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG1 reset_value) Endpoint Configuration Register */ 565 566 #define USBC_UECFG1_EPBK_Pos 2 /**< \brief (USBC_UECFG1) Endpoint Bank */ 567 #define USBC_UECFG1_EPBK (_U_(0x1) << USBC_UECFG1_EPBK_Pos) 568 #define USBC_UECFG1_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG1) */ 569 #define USBC_UECFG1_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG1) */ 570 #define USBC_UECFG1_EPBK_SINGLE (USBC_UECFG1_EPBK_SINGLE_Val << USBC_UECFG1_EPBK_Pos) 571 #define USBC_UECFG1_EPBK_DOUBLE (USBC_UECFG1_EPBK_DOUBLE_Val << USBC_UECFG1_EPBK_Pos) 572 #define USBC_UECFG1_EPSIZE_Pos 4 /**< \brief (USBC_UECFG1) Endpoint Size */ 573 #define USBC_UECFG1_EPSIZE_Msk (_U_(0x7) << USBC_UECFG1_EPSIZE_Pos) 574 #define USBC_UECFG1_EPSIZE(value) (USBC_UECFG1_EPSIZE_Msk & ((value) << USBC_UECFG1_EPSIZE_Pos)) 575 #define USBC_UECFG1_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG1) */ 576 #define USBC_UECFG1_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG1) */ 577 #define USBC_UECFG1_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG1) */ 578 #define USBC_UECFG1_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG1) */ 579 #define USBC_UECFG1_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG1) */ 580 #define USBC_UECFG1_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG1) */ 581 #define USBC_UECFG1_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG1) */ 582 #define USBC_UECFG1_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG1) */ 583 #define USBC_UECFG1_EPSIZE_8 (USBC_UECFG1_EPSIZE_8_Val << USBC_UECFG1_EPSIZE_Pos) 584 #define USBC_UECFG1_EPSIZE_16 (USBC_UECFG1_EPSIZE_16_Val << USBC_UECFG1_EPSIZE_Pos) 585 #define USBC_UECFG1_EPSIZE_32 (USBC_UECFG1_EPSIZE_32_Val << USBC_UECFG1_EPSIZE_Pos) 586 #define USBC_UECFG1_EPSIZE_64 (USBC_UECFG1_EPSIZE_64_Val << USBC_UECFG1_EPSIZE_Pos) 587 #define USBC_UECFG1_EPSIZE_128 (USBC_UECFG1_EPSIZE_128_Val << USBC_UECFG1_EPSIZE_Pos) 588 #define USBC_UECFG1_EPSIZE_256 (USBC_UECFG1_EPSIZE_256_Val << USBC_UECFG1_EPSIZE_Pos) 589 #define USBC_UECFG1_EPSIZE_512 (USBC_UECFG1_EPSIZE_512_Val << USBC_UECFG1_EPSIZE_Pos) 590 #define USBC_UECFG1_EPSIZE_1024 (USBC_UECFG1_EPSIZE_1024_Val << USBC_UECFG1_EPSIZE_Pos) 591 #define USBC_UECFG1_EPDIR_Pos 8 /**< \brief (USBC_UECFG1) Endpoint Direction */ 592 #define USBC_UECFG1_EPDIR (_U_(0x1) << USBC_UECFG1_EPDIR_Pos) 593 #define USBC_UECFG1_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG1) */ 594 #define USBC_UECFG1_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG1) */ 595 #define USBC_UECFG1_EPDIR_OUT (USBC_UECFG1_EPDIR_OUT_Val << USBC_UECFG1_EPDIR_Pos) 596 #define USBC_UECFG1_EPDIR_IN (USBC_UECFG1_EPDIR_IN_Val << USBC_UECFG1_EPDIR_Pos) 597 #define USBC_UECFG1_EPTYPE_Pos 11 /**< \brief (USBC_UECFG1) Endpoint Type */ 598 #define USBC_UECFG1_EPTYPE_Msk (_U_(0x3) << USBC_UECFG1_EPTYPE_Pos) 599 #define USBC_UECFG1_EPTYPE(value) (USBC_UECFG1_EPTYPE_Msk & ((value) << USBC_UECFG1_EPTYPE_Pos)) 600 #define USBC_UECFG1_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG1) */ 601 #define USBC_UECFG1_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG1) */ 602 #define USBC_UECFG1_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG1) */ 603 #define USBC_UECFG1_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG1) */ 604 #define USBC_UECFG1_EPTYPE_CONTROL (USBC_UECFG1_EPTYPE_CONTROL_Val << USBC_UECFG1_EPTYPE_Pos) 605 #define USBC_UECFG1_EPTYPE_ISOCHRONOUS (USBC_UECFG1_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG1_EPTYPE_Pos) 606 #define USBC_UECFG1_EPTYPE_BULK (USBC_UECFG1_EPTYPE_BULK_Val << USBC_UECFG1_EPTYPE_Pos) 607 #define USBC_UECFG1_EPTYPE_INTERRUPT (USBC_UECFG1_EPTYPE_INTERRUPT_Val << USBC_UECFG1_EPTYPE_Pos) 608 #define USBC_UECFG1_REPNB_Pos 16 /**< \brief (USBC_UECFG1) Redirected Endpoint Number */ 609 #define USBC_UECFG1_REPNB_Msk (_U_(0xF) << USBC_UECFG1_REPNB_Pos) 610 #define USBC_UECFG1_REPNB(value) (USBC_UECFG1_REPNB_Msk & ((value) << USBC_UECFG1_REPNB_Pos)) 611 #define USBC_UECFG1_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG1) MASK Register */ 612 613 /* -------- USBC_UECFG2 : (USBC Offset: 0x108) (R/W 32) Endpoint Configuration Register -------- */ 614 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 615 typedef union { 616 struct { 617 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 618 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 619 uint32_t :1; /*!< bit: 3 Reserved */ 620 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 621 uint32_t :1; /*!< bit: 7 Reserved */ 622 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 623 uint32_t :2; /*!< bit: 9..10 Reserved */ 624 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 625 uint32_t :3; /*!< bit: 13..15 Reserved */ 626 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 627 uint32_t :12; /*!< bit: 20..31 Reserved */ 628 } bit; /*!< Structure used for bit access */ 629 uint32_t reg; /*!< Type used for register access */ 630 } USBC_UECFG2_Type; 631 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 632 633 #define USBC_UECFG2_OFFSET 0x108 /**< \brief (USBC_UECFG2 offset) Endpoint Configuration Register */ 634 #define USBC_UECFG2_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG2 reset_value) Endpoint Configuration Register */ 635 636 #define USBC_UECFG2_EPBK_Pos 2 /**< \brief (USBC_UECFG2) Endpoint Bank */ 637 #define USBC_UECFG2_EPBK (_U_(0x1) << USBC_UECFG2_EPBK_Pos) 638 #define USBC_UECFG2_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG2) */ 639 #define USBC_UECFG2_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG2) */ 640 #define USBC_UECFG2_EPBK_SINGLE (USBC_UECFG2_EPBK_SINGLE_Val << USBC_UECFG2_EPBK_Pos) 641 #define USBC_UECFG2_EPBK_DOUBLE (USBC_UECFG2_EPBK_DOUBLE_Val << USBC_UECFG2_EPBK_Pos) 642 #define USBC_UECFG2_EPSIZE_Pos 4 /**< \brief (USBC_UECFG2) Endpoint Size */ 643 #define USBC_UECFG2_EPSIZE_Msk (_U_(0x7) << USBC_UECFG2_EPSIZE_Pos) 644 #define USBC_UECFG2_EPSIZE(value) (USBC_UECFG2_EPSIZE_Msk & ((value) << USBC_UECFG2_EPSIZE_Pos)) 645 #define USBC_UECFG2_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG2) */ 646 #define USBC_UECFG2_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG2) */ 647 #define USBC_UECFG2_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG2) */ 648 #define USBC_UECFG2_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG2) */ 649 #define USBC_UECFG2_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG2) */ 650 #define USBC_UECFG2_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG2) */ 651 #define USBC_UECFG2_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG2) */ 652 #define USBC_UECFG2_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG2) */ 653 #define USBC_UECFG2_EPSIZE_8 (USBC_UECFG2_EPSIZE_8_Val << USBC_UECFG2_EPSIZE_Pos) 654 #define USBC_UECFG2_EPSIZE_16 (USBC_UECFG2_EPSIZE_16_Val << USBC_UECFG2_EPSIZE_Pos) 655 #define USBC_UECFG2_EPSIZE_32 (USBC_UECFG2_EPSIZE_32_Val << USBC_UECFG2_EPSIZE_Pos) 656 #define USBC_UECFG2_EPSIZE_64 (USBC_UECFG2_EPSIZE_64_Val << USBC_UECFG2_EPSIZE_Pos) 657 #define USBC_UECFG2_EPSIZE_128 (USBC_UECFG2_EPSIZE_128_Val << USBC_UECFG2_EPSIZE_Pos) 658 #define USBC_UECFG2_EPSIZE_256 (USBC_UECFG2_EPSIZE_256_Val << USBC_UECFG2_EPSIZE_Pos) 659 #define USBC_UECFG2_EPSIZE_512 (USBC_UECFG2_EPSIZE_512_Val << USBC_UECFG2_EPSIZE_Pos) 660 #define USBC_UECFG2_EPSIZE_1024 (USBC_UECFG2_EPSIZE_1024_Val << USBC_UECFG2_EPSIZE_Pos) 661 #define USBC_UECFG2_EPDIR_Pos 8 /**< \brief (USBC_UECFG2) Endpoint Direction */ 662 #define USBC_UECFG2_EPDIR (_U_(0x1) << USBC_UECFG2_EPDIR_Pos) 663 #define USBC_UECFG2_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG2) */ 664 #define USBC_UECFG2_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG2) */ 665 #define USBC_UECFG2_EPDIR_OUT (USBC_UECFG2_EPDIR_OUT_Val << USBC_UECFG2_EPDIR_Pos) 666 #define USBC_UECFG2_EPDIR_IN (USBC_UECFG2_EPDIR_IN_Val << USBC_UECFG2_EPDIR_Pos) 667 #define USBC_UECFG2_EPTYPE_Pos 11 /**< \brief (USBC_UECFG2) Endpoint Type */ 668 #define USBC_UECFG2_EPTYPE_Msk (_U_(0x3) << USBC_UECFG2_EPTYPE_Pos) 669 #define USBC_UECFG2_EPTYPE(value) (USBC_UECFG2_EPTYPE_Msk & ((value) << USBC_UECFG2_EPTYPE_Pos)) 670 #define USBC_UECFG2_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG2) */ 671 #define USBC_UECFG2_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG2) */ 672 #define USBC_UECFG2_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG2) */ 673 #define USBC_UECFG2_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG2) */ 674 #define USBC_UECFG2_EPTYPE_CONTROL (USBC_UECFG2_EPTYPE_CONTROL_Val << USBC_UECFG2_EPTYPE_Pos) 675 #define USBC_UECFG2_EPTYPE_ISOCHRONOUS (USBC_UECFG2_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG2_EPTYPE_Pos) 676 #define USBC_UECFG2_EPTYPE_BULK (USBC_UECFG2_EPTYPE_BULK_Val << USBC_UECFG2_EPTYPE_Pos) 677 #define USBC_UECFG2_EPTYPE_INTERRUPT (USBC_UECFG2_EPTYPE_INTERRUPT_Val << USBC_UECFG2_EPTYPE_Pos) 678 #define USBC_UECFG2_REPNB_Pos 16 /**< \brief (USBC_UECFG2) Redirected Endpoint Number */ 679 #define USBC_UECFG2_REPNB_Msk (_U_(0xF) << USBC_UECFG2_REPNB_Pos) 680 #define USBC_UECFG2_REPNB(value) (USBC_UECFG2_REPNB_Msk & ((value) << USBC_UECFG2_REPNB_Pos)) 681 #define USBC_UECFG2_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG2) MASK Register */ 682 683 /* -------- USBC_UECFG3 : (USBC Offset: 0x10C) (R/W 32) Endpoint Configuration Register -------- */ 684 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 685 typedef union { 686 struct { 687 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 688 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 689 uint32_t :1; /*!< bit: 3 Reserved */ 690 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 691 uint32_t :1; /*!< bit: 7 Reserved */ 692 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 693 uint32_t :2; /*!< bit: 9..10 Reserved */ 694 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 695 uint32_t :3; /*!< bit: 13..15 Reserved */ 696 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 697 uint32_t :12; /*!< bit: 20..31 Reserved */ 698 } bit; /*!< Structure used for bit access */ 699 uint32_t reg; /*!< Type used for register access */ 700 } USBC_UECFG3_Type; 701 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 702 703 #define USBC_UECFG3_OFFSET 0x10C /**< \brief (USBC_UECFG3 offset) Endpoint Configuration Register */ 704 #define USBC_UECFG3_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG3 reset_value) Endpoint Configuration Register */ 705 706 #define USBC_UECFG3_EPBK_Pos 2 /**< \brief (USBC_UECFG3) Endpoint Bank */ 707 #define USBC_UECFG3_EPBK (_U_(0x1) << USBC_UECFG3_EPBK_Pos) 708 #define USBC_UECFG3_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG3) */ 709 #define USBC_UECFG3_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG3) */ 710 #define USBC_UECFG3_EPBK_SINGLE (USBC_UECFG3_EPBK_SINGLE_Val << USBC_UECFG3_EPBK_Pos) 711 #define USBC_UECFG3_EPBK_DOUBLE (USBC_UECFG3_EPBK_DOUBLE_Val << USBC_UECFG3_EPBK_Pos) 712 #define USBC_UECFG3_EPSIZE_Pos 4 /**< \brief (USBC_UECFG3) Endpoint Size */ 713 #define USBC_UECFG3_EPSIZE_Msk (_U_(0x7) << USBC_UECFG3_EPSIZE_Pos) 714 #define USBC_UECFG3_EPSIZE(value) (USBC_UECFG3_EPSIZE_Msk & ((value) << USBC_UECFG3_EPSIZE_Pos)) 715 #define USBC_UECFG3_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG3) */ 716 #define USBC_UECFG3_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG3) */ 717 #define USBC_UECFG3_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG3) */ 718 #define USBC_UECFG3_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG3) */ 719 #define USBC_UECFG3_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG3) */ 720 #define USBC_UECFG3_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG3) */ 721 #define USBC_UECFG3_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG3) */ 722 #define USBC_UECFG3_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG3) */ 723 #define USBC_UECFG3_EPSIZE_8 (USBC_UECFG3_EPSIZE_8_Val << USBC_UECFG3_EPSIZE_Pos) 724 #define USBC_UECFG3_EPSIZE_16 (USBC_UECFG3_EPSIZE_16_Val << USBC_UECFG3_EPSIZE_Pos) 725 #define USBC_UECFG3_EPSIZE_32 (USBC_UECFG3_EPSIZE_32_Val << USBC_UECFG3_EPSIZE_Pos) 726 #define USBC_UECFG3_EPSIZE_64 (USBC_UECFG3_EPSIZE_64_Val << USBC_UECFG3_EPSIZE_Pos) 727 #define USBC_UECFG3_EPSIZE_128 (USBC_UECFG3_EPSIZE_128_Val << USBC_UECFG3_EPSIZE_Pos) 728 #define USBC_UECFG3_EPSIZE_256 (USBC_UECFG3_EPSIZE_256_Val << USBC_UECFG3_EPSIZE_Pos) 729 #define USBC_UECFG3_EPSIZE_512 (USBC_UECFG3_EPSIZE_512_Val << USBC_UECFG3_EPSIZE_Pos) 730 #define USBC_UECFG3_EPSIZE_1024 (USBC_UECFG3_EPSIZE_1024_Val << USBC_UECFG3_EPSIZE_Pos) 731 #define USBC_UECFG3_EPDIR_Pos 8 /**< \brief (USBC_UECFG3) Endpoint Direction */ 732 #define USBC_UECFG3_EPDIR (_U_(0x1) << USBC_UECFG3_EPDIR_Pos) 733 #define USBC_UECFG3_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG3) */ 734 #define USBC_UECFG3_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG3) */ 735 #define USBC_UECFG3_EPDIR_OUT (USBC_UECFG3_EPDIR_OUT_Val << USBC_UECFG3_EPDIR_Pos) 736 #define USBC_UECFG3_EPDIR_IN (USBC_UECFG3_EPDIR_IN_Val << USBC_UECFG3_EPDIR_Pos) 737 #define USBC_UECFG3_EPTYPE_Pos 11 /**< \brief (USBC_UECFG3) Endpoint Type */ 738 #define USBC_UECFG3_EPTYPE_Msk (_U_(0x3) << USBC_UECFG3_EPTYPE_Pos) 739 #define USBC_UECFG3_EPTYPE(value) (USBC_UECFG3_EPTYPE_Msk & ((value) << USBC_UECFG3_EPTYPE_Pos)) 740 #define USBC_UECFG3_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG3) */ 741 #define USBC_UECFG3_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG3) */ 742 #define USBC_UECFG3_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG3) */ 743 #define USBC_UECFG3_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG3) */ 744 #define USBC_UECFG3_EPTYPE_CONTROL (USBC_UECFG3_EPTYPE_CONTROL_Val << USBC_UECFG3_EPTYPE_Pos) 745 #define USBC_UECFG3_EPTYPE_ISOCHRONOUS (USBC_UECFG3_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG3_EPTYPE_Pos) 746 #define USBC_UECFG3_EPTYPE_BULK (USBC_UECFG3_EPTYPE_BULK_Val << USBC_UECFG3_EPTYPE_Pos) 747 #define USBC_UECFG3_EPTYPE_INTERRUPT (USBC_UECFG3_EPTYPE_INTERRUPT_Val << USBC_UECFG3_EPTYPE_Pos) 748 #define USBC_UECFG3_REPNB_Pos 16 /**< \brief (USBC_UECFG3) Redirected Endpoint Number */ 749 #define USBC_UECFG3_REPNB_Msk (_U_(0xF) << USBC_UECFG3_REPNB_Pos) 750 #define USBC_UECFG3_REPNB(value) (USBC_UECFG3_REPNB_Msk & ((value) << USBC_UECFG3_REPNB_Pos)) 751 #define USBC_UECFG3_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG3) MASK Register */ 752 753 /* -------- USBC_UECFG4 : (USBC Offset: 0x110) (R/W 32) Endpoint Configuration Register -------- */ 754 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 755 typedef union { 756 struct { 757 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 758 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 759 uint32_t :1; /*!< bit: 3 Reserved */ 760 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 761 uint32_t :1; /*!< bit: 7 Reserved */ 762 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 763 uint32_t :2; /*!< bit: 9..10 Reserved */ 764 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 765 uint32_t :3; /*!< bit: 13..15 Reserved */ 766 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 767 uint32_t :12; /*!< bit: 20..31 Reserved */ 768 } bit; /*!< Structure used for bit access */ 769 uint32_t reg; /*!< Type used for register access */ 770 } USBC_UECFG4_Type; 771 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 772 773 #define USBC_UECFG4_OFFSET 0x110 /**< \brief (USBC_UECFG4 offset) Endpoint Configuration Register */ 774 #define USBC_UECFG4_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG4 reset_value) Endpoint Configuration Register */ 775 776 #define USBC_UECFG4_EPBK_Pos 2 /**< \brief (USBC_UECFG4) Endpoint Bank */ 777 #define USBC_UECFG4_EPBK (_U_(0x1) << USBC_UECFG4_EPBK_Pos) 778 #define USBC_UECFG4_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG4) */ 779 #define USBC_UECFG4_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG4) */ 780 #define USBC_UECFG4_EPBK_SINGLE (USBC_UECFG4_EPBK_SINGLE_Val << USBC_UECFG4_EPBK_Pos) 781 #define USBC_UECFG4_EPBK_DOUBLE (USBC_UECFG4_EPBK_DOUBLE_Val << USBC_UECFG4_EPBK_Pos) 782 #define USBC_UECFG4_EPSIZE_Pos 4 /**< \brief (USBC_UECFG4) Endpoint Size */ 783 #define USBC_UECFG4_EPSIZE_Msk (_U_(0x7) << USBC_UECFG4_EPSIZE_Pos) 784 #define USBC_UECFG4_EPSIZE(value) (USBC_UECFG4_EPSIZE_Msk & ((value) << USBC_UECFG4_EPSIZE_Pos)) 785 #define USBC_UECFG4_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG4) */ 786 #define USBC_UECFG4_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG4) */ 787 #define USBC_UECFG4_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG4) */ 788 #define USBC_UECFG4_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG4) */ 789 #define USBC_UECFG4_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG4) */ 790 #define USBC_UECFG4_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG4) */ 791 #define USBC_UECFG4_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG4) */ 792 #define USBC_UECFG4_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG4) */ 793 #define USBC_UECFG4_EPSIZE_8 (USBC_UECFG4_EPSIZE_8_Val << USBC_UECFG4_EPSIZE_Pos) 794 #define USBC_UECFG4_EPSIZE_16 (USBC_UECFG4_EPSIZE_16_Val << USBC_UECFG4_EPSIZE_Pos) 795 #define USBC_UECFG4_EPSIZE_32 (USBC_UECFG4_EPSIZE_32_Val << USBC_UECFG4_EPSIZE_Pos) 796 #define USBC_UECFG4_EPSIZE_64 (USBC_UECFG4_EPSIZE_64_Val << USBC_UECFG4_EPSIZE_Pos) 797 #define USBC_UECFG4_EPSIZE_128 (USBC_UECFG4_EPSIZE_128_Val << USBC_UECFG4_EPSIZE_Pos) 798 #define USBC_UECFG4_EPSIZE_256 (USBC_UECFG4_EPSIZE_256_Val << USBC_UECFG4_EPSIZE_Pos) 799 #define USBC_UECFG4_EPSIZE_512 (USBC_UECFG4_EPSIZE_512_Val << USBC_UECFG4_EPSIZE_Pos) 800 #define USBC_UECFG4_EPSIZE_1024 (USBC_UECFG4_EPSIZE_1024_Val << USBC_UECFG4_EPSIZE_Pos) 801 #define USBC_UECFG4_EPDIR_Pos 8 /**< \brief (USBC_UECFG4) Endpoint Direction */ 802 #define USBC_UECFG4_EPDIR (_U_(0x1) << USBC_UECFG4_EPDIR_Pos) 803 #define USBC_UECFG4_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG4) */ 804 #define USBC_UECFG4_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG4) */ 805 #define USBC_UECFG4_EPDIR_OUT (USBC_UECFG4_EPDIR_OUT_Val << USBC_UECFG4_EPDIR_Pos) 806 #define USBC_UECFG4_EPDIR_IN (USBC_UECFG4_EPDIR_IN_Val << USBC_UECFG4_EPDIR_Pos) 807 #define USBC_UECFG4_EPTYPE_Pos 11 /**< \brief (USBC_UECFG4) Endpoint Type */ 808 #define USBC_UECFG4_EPTYPE_Msk (_U_(0x3) << USBC_UECFG4_EPTYPE_Pos) 809 #define USBC_UECFG4_EPTYPE(value) (USBC_UECFG4_EPTYPE_Msk & ((value) << USBC_UECFG4_EPTYPE_Pos)) 810 #define USBC_UECFG4_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG4) */ 811 #define USBC_UECFG4_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG4) */ 812 #define USBC_UECFG4_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG4) */ 813 #define USBC_UECFG4_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG4) */ 814 #define USBC_UECFG4_EPTYPE_CONTROL (USBC_UECFG4_EPTYPE_CONTROL_Val << USBC_UECFG4_EPTYPE_Pos) 815 #define USBC_UECFG4_EPTYPE_ISOCHRONOUS (USBC_UECFG4_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG4_EPTYPE_Pos) 816 #define USBC_UECFG4_EPTYPE_BULK (USBC_UECFG4_EPTYPE_BULK_Val << USBC_UECFG4_EPTYPE_Pos) 817 #define USBC_UECFG4_EPTYPE_INTERRUPT (USBC_UECFG4_EPTYPE_INTERRUPT_Val << USBC_UECFG4_EPTYPE_Pos) 818 #define USBC_UECFG4_REPNB_Pos 16 /**< \brief (USBC_UECFG4) Redirected Endpoint Number */ 819 #define USBC_UECFG4_REPNB_Msk (_U_(0xF) << USBC_UECFG4_REPNB_Pos) 820 #define USBC_UECFG4_REPNB(value) (USBC_UECFG4_REPNB_Msk & ((value) << USBC_UECFG4_REPNB_Pos)) 821 #define USBC_UECFG4_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG4) MASK Register */ 822 823 /* -------- USBC_UECFG5 : (USBC Offset: 0x114) (R/W 32) Endpoint Configuration Register -------- */ 824 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 825 typedef union { 826 struct { 827 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 828 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 829 uint32_t :1; /*!< bit: 3 Reserved */ 830 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 831 uint32_t :1; /*!< bit: 7 Reserved */ 832 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 833 uint32_t :2; /*!< bit: 9..10 Reserved */ 834 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 835 uint32_t :3; /*!< bit: 13..15 Reserved */ 836 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 837 uint32_t :12; /*!< bit: 20..31 Reserved */ 838 } bit; /*!< Structure used for bit access */ 839 uint32_t reg; /*!< Type used for register access */ 840 } USBC_UECFG5_Type; 841 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 842 843 #define USBC_UECFG5_OFFSET 0x114 /**< \brief (USBC_UECFG5 offset) Endpoint Configuration Register */ 844 #define USBC_UECFG5_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG5 reset_value) Endpoint Configuration Register */ 845 846 #define USBC_UECFG5_EPBK_Pos 2 /**< \brief (USBC_UECFG5) Endpoint Bank */ 847 #define USBC_UECFG5_EPBK (_U_(0x1) << USBC_UECFG5_EPBK_Pos) 848 #define USBC_UECFG5_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG5) */ 849 #define USBC_UECFG5_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG5) */ 850 #define USBC_UECFG5_EPBK_SINGLE (USBC_UECFG5_EPBK_SINGLE_Val << USBC_UECFG5_EPBK_Pos) 851 #define USBC_UECFG5_EPBK_DOUBLE (USBC_UECFG5_EPBK_DOUBLE_Val << USBC_UECFG5_EPBK_Pos) 852 #define USBC_UECFG5_EPSIZE_Pos 4 /**< \brief (USBC_UECFG5) Endpoint Size */ 853 #define USBC_UECFG5_EPSIZE_Msk (_U_(0x7) << USBC_UECFG5_EPSIZE_Pos) 854 #define USBC_UECFG5_EPSIZE(value) (USBC_UECFG5_EPSIZE_Msk & ((value) << USBC_UECFG5_EPSIZE_Pos)) 855 #define USBC_UECFG5_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG5) */ 856 #define USBC_UECFG5_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG5) */ 857 #define USBC_UECFG5_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG5) */ 858 #define USBC_UECFG5_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG5) */ 859 #define USBC_UECFG5_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG5) */ 860 #define USBC_UECFG5_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG5) */ 861 #define USBC_UECFG5_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG5) */ 862 #define USBC_UECFG5_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG5) */ 863 #define USBC_UECFG5_EPSIZE_8 (USBC_UECFG5_EPSIZE_8_Val << USBC_UECFG5_EPSIZE_Pos) 864 #define USBC_UECFG5_EPSIZE_16 (USBC_UECFG5_EPSIZE_16_Val << USBC_UECFG5_EPSIZE_Pos) 865 #define USBC_UECFG5_EPSIZE_32 (USBC_UECFG5_EPSIZE_32_Val << USBC_UECFG5_EPSIZE_Pos) 866 #define USBC_UECFG5_EPSIZE_64 (USBC_UECFG5_EPSIZE_64_Val << USBC_UECFG5_EPSIZE_Pos) 867 #define USBC_UECFG5_EPSIZE_128 (USBC_UECFG5_EPSIZE_128_Val << USBC_UECFG5_EPSIZE_Pos) 868 #define USBC_UECFG5_EPSIZE_256 (USBC_UECFG5_EPSIZE_256_Val << USBC_UECFG5_EPSIZE_Pos) 869 #define USBC_UECFG5_EPSIZE_512 (USBC_UECFG5_EPSIZE_512_Val << USBC_UECFG5_EPSIZE_Pos) 870 #define USBC_UECFG5_EPSIZE_1024 (USBC_UECFG5_EPSIZE_1024_Val << USBC_UECFG5_EPSIZE_Pos) 871 #define USBC_UECFG5_EPDIR_Pos 8 /**< \brief (USBC_UECFG5) Endpoint Direction */ 872 #define USBC_UECFG5_EPDIR (_U_(0x1) << USBC_UECFG5_EPDIR_Pos) 873 #define USBC_UECFG5_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG5) */ 874 #define USBC_UECFG5_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG5) */ 875 #define USBC_UECFG5_EPDIR_OUT (USBC_UECFG5_EPDIR_OUT_Val << USBC_UECFG5_EPDIR_Pos) 876 #define USBC_UECFG5_EPDIR_IN (USBC_UECFG5_EPDIR_IN_Val << USBC_UECFG5_EPDIR_Pos) 877 #define USBC_UECFG5_EPTYPE_Pos 11 /**< \brief (USBC_UECFG5) Endpoint Type */ 878 #define USBC_UECFG5_EPTYPE_Msk (_U_(0x3) << USBC_UECFG5_EPTYPE_Pos) 879 #define USBC_UECFG5_EPTYPE(value) (USBC_UECFG5_EPTYPE_Msk & ((value) << USBC_UECFG5_EPTYPE_Pos)) 880 #define USBC_UECFG5_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG5) */ 881 #define USBC_UECFG5_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG5) */ 882 #define USBC_UECFG5_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG5) */ 883 #define USBC_UECFG5_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG5) */ 884 #define USBC_UECFG5_EPTYPE_CONTROL (USBC_UECFG5_EPTYPE_CONTROL_Val << USBC_UECFG5_EPTYPE_Pos) 885 #define USBC_UECFG5_EPTYPE_ISOCHRONOUS (USBC_UECFG5_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG5_EPTYPE_Pos) 886 #define USBC_UECFG5_EPTYPE_BULK (USBC_UECFG5_EPTYPE_BULK_Val << USBC_UECFG5_EPTYPE_Pos) 887 #define USBC_UECFG5_EPTYPE_INTERRUPT (USBC_UECFG5_EPTYPE_INTERRUPT_Val << USBC_UECFG5_EPTYPE_Pos) 888 #define USBC_UECFG5_REPNB_Pos 16 /**< \brief (USBC_UECFG5) Redirected Endpoint Number */ 889 #define USBC_UECFG5_REPNB_Msk (_U_(0xF) << USBC_UECFG5_REPNB_Pos) 890 #define USBC_UECFG5_REPNB(value) (USBC_UECFG5_REPNB_Msk & ((value) << USBC_UECFG5_REPNB_Pos)) 891 #define USBC_UECFG5_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG5) MASK Register */ 892 893 /* -------- USBC_UECFG6 : (USBC Offset: 0x118) (R/W 32) Endpoint Configuration Register -------- */ 894 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 895 typedef union { 896 struct { 897 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 898 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 899 uint32_t :1; /*!< bit: 3 Reserved */ 900 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 901 uint32_t :1; /*!< bit: 7 Reserved */ 902 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 903 uint32_t :2; /*!< bit: 9..10 Reserved */ 904 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 905 uint32_t :3; /*!< bit: 13..15 Reserved */ 906 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 907 uint32_t :12; /*!< bit: 20..31 Reserved */ 908 } bit; /*!< Structure used for bit access */ 909 uint32_t reg; /*!< Type used for register access */ 910 } USBC_UECFG6_Type; 911 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 912 913 #define USBC_UECFG6_OFFSET 0x118 /**< \brief (USBC_UECFG6 offset) Endpoint Configuration Register */ 914 #define USBC_UECFG6_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG6 reset_value) Endpoint Configuration Register */ 915 916 #define USBC_UECFG6_EPBK_Pos 2 /**< \brief (USBC_UECFG6) Endpoint Bank */ 917 #define USBC_UECFG6_EPBK (_U_(0x1) << USBC_UECFG6_EPBK_Pos) 918 #define USBC_UECFG6_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG6) */ 919 #define USBC_UECFG6_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG6) */ 920 #define USBC_UECFG6_EPBK_SINGLE (USBC_UECFG6_EPBK_SINGLE_Val << USBC_UECFG6_EPBK_Pos) 921 #define USBC_UECFG6_EPBK_DOUBLE (USBC_UECFG6_EPBK_DOUBLE_Val << USBC_UECFG6_EPBK_Pos) 922 #define USBC_UECFG6_EPSIZE_Pos 4 /**< \brief (USBC_UECFG6) Endpoint Size */ 923 #define USBC_UECFG6_EPSIZE_Msk (_U_(0x7) << USBC_UECFG6_EPSIZE_Pos) 924 #define USBC_UECFG6_EPSIZE(value) (USBC_UECFG6_EPSIZE_Msk & ((value) << USBC_UECFG6_EPSIZE_Pos)) 925 #define USBC_UECFG6_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG6) */ 926 #define USBC_UECFG6_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG6) */ 927 #define USBC_UECFG6_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG6) */ 928 #define USBC_UECFG6_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG6) */ 929 #define USBC_UECFG6_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG6) */ 930 #define USBC_UECFG6_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG6) */ 931 #define USBC_UECFG6_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG6) */ 932 #define USBC_UECFG6_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG6) */ 933 #define USBC_UECFG6_EPSIZE_8 (USBC_UECFG6_EPSIZE_8_Val << USBC_UECFG6_EPSIZE_Pos) 934 #define USBC_UECFG6_EPSIZE_16 (USBC_UECFG6_EPSIZE_16_Val << USBC_UECFG6_EPSIZE_Pos) 935 #define USBC_UECFG6_EPSIZE_32 (USBC_UECFG6_EPSIZE_32_Val << USBC_UECFG6_EPSIZE_Pos) 936 #define USBC_UECFG6_EPSIZE_64 (USBC_UECFG6_EPSIZE_64_Val << USBC_UECFG6_EPSIZE_Pos) 937 #define USBC_UECFG6_EPSIZE_128 (USBC_UECFG6_EPSIZE_128_Val << USBC_UECFG6_EPSIZE_Pos) 938 #define USBC_UECFG6_EPSIZE_256 (USBC_UECFG6_EPSIZE_256_Val << USBC_UECFG6_EPSIZE_Pos) 939 #define USBC_UECFG6_EPSIZE_512 (USBC_UECFG6_EPSIZE_512_Val << USBC_UECFG6_EPSIZE_Pos) 940 #define USBC_UECFG6_EPSIZE_1024 (USBC_UECFG6_EPSIZE_1024_Val << USBC_UECFG6_EPSIZE_Pos) 941 #define USBC_UECFG6_EPDIR_Pos 8 /**< \brief (USBC_UECFG6) Endpoint Direction */ 942 #define USBC_UECFG6_EPDIR (_U_(0x1) << USBC_UECFG6_EPDIR_Pos) 943 #define USBC_UECFG6_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG6) */ 944 #define USBC_UECFG6_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG6) */ 945 #define USBC_UECFG6_EPDIR_OUT (USBC_UECFG6_EPDIR_OUT_Val << USBC_UECFG6_EPDIR_Pos) 946 #define USBC_UECFG6_EPDIR_IN (USBC_UECFG6_EPDIR_IN_Val << USBC_UECFG6_EPDIR_Pos) 947 #define USBC_UECFG6_EPTYPE_Pos 11 /**< \brief (USBC_UECFG6) Endpoint Type */ 948 #define USBC_UECFG6_EPTYPE_Msk (_U_(0x3) << USBC_UECFG6_EPTYPE_Pos) 949 #define USBC_UECFG6_EPTYPE(value) (USBC_UECFG6_EPTYPE_Msk & ((value) << USBC_UECFG6_EPTYPE_Pos)) 950 #define USBC_UECFG6_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG6) */ 951 #define USBC_UECFG6_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG6) */ 952 #define USBC_UECFG6_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG6) */ 953 #define USBC_UECFG6_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG6) */ 954 #define USBC_UECFG6_EPTYPE_CONTROL (USBC_UECFG6_EPTYPE_CONTROL_Val << USBC_UECFG6_EPTYPE_Pos) 955 #define USBC_UECFG6_EPTYPE_ISOCHRONOUS (USBC_UECFG6_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG6_EPTYPE_Pos) 956 #define USBC_UECFG6_EPTYPE_BULK (USBC_UECFG6_EPTYPE_BULK_Val << USBC_UECFG6_EPTYPE_Pos) 957 #define USBC_UECFG6_EPTYPE_INTERRUPT (USBC_UECFG6_EPTYPE_INTERRUPT_Val << USBC_UECFG6_EPTYPE_Pos) 958 #define USBC_UECFG6_REPNB_Pos 16 /**< \brief (USBC_UECFG6) Redirected Endpoint Number */ 959 #define USBC_UECFG6_REPNB_Msk (_U_(0xF) << USBC_UECFG6_REPNB_Pos) 960 #define USBC_UECFG6_REPNB(value) (USBC_UECFG6_REPNB_Msk & ((value) << USBC_UECFG6_REPNB_Pos)) 961 #define USBC_UECFG6_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG6) MASK Register */ 962 963 /* -------- USBC_UECFG7 : (USBC Offset: 0x11C) (R/W 32) Endpoint Configuration Register -------- */ 964 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 965 typedef union { 966 struct { 967 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 968 uint32_t EPBK:1; /*!< bit: 2 Endpoint Bank */ 969 uint32_t :1; /*!< bit: 3 Reserved */ 970 uint32_t EPSIZE:3; /*!< bit: 4.. 6 Endpoint Size */ 971 uint32_t :1; /*!< bit: 7 Reserved */ 972 uint32_t EPDIR:1; /*!< bit: 8 Endpoint Direction */ 973 uint32_t :2; /*!< bit: 9..10 Reserved */ 974 uint32_t EPTYPE:2; /*!< bit: 11..12 Endpoint Type */ 975 uint32_t :3; /*!< bit: 13..15 Reserved */ 976 uint32_t REPNB:4; /*!< bit: 16..19 Redirected Endpoint Number */ 977 uint32_t :12; /*!< bit: 20..31 Reserved */ 978 } bit; /*!< Structure used for bit access */ 979 uint32_t reg; /*!< Type used for register access */ 980 } USBC_UECFG7_Type; 981 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 982 983 #define USBC_UECFG7_OFFSET 0x11C /**< \brief (USBC_UECFG7 offset) Endpoint Configuration Register */ 984 #define USBC_UECFG7_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECFG7 reset_value) Endpoint Configuration Register */ 985 986 #define USBC_UECFG7_EPBK_Pos 2 /**< \brief (USBC_UECFG7) Endpoint Bank */ 987 #define USBC_UECFG7_EPBK (_U_(0x1) << USBC_UECFG7_EPBK_Pos) 988 #define USBC_UECFG7_EPBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UECFG7) */ 989 #define USBC_UECFG7_EPBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UECFG7) */ 990 #define USBC_UECFG7_EPBK_SINGLE (USBC_UECFG7_EPBK_SINGLE_Val << USBC_UECFG7_EPBK_Pos) 991 #define USBC_UECFG7_EPBK_DOUBLE (USBC_UECFG7_EPBK_DOUBLE_Val << USBC_UECFG7_EPBK_Pos) 992 #define USBC_UECFG7_EPSIZE_Pos 4 /**< \brief (USBC_UECFG7) Endpoint Size */ 993 #define USBC_UECFG7_EPSIZE_Msk (_U_(0x7) << USBC_UECFG7_EPSIZE_Pos) 994 #define USBC_UECFG7_EPSIZE(value) (USBC_UECFG7_EPSIZE_Msk & ((value) << USBC_UECFG7_EPSIZE_Pos)) 995 #define USBC_UECFG7_EPSIZE_8_Val _U_(0x0) /**< \brief (USBC_UECFG7) */ 996 #define USBC_UECFG7_EPSIZE_16_Val _U_(0x1) /**< \brief (USBC_UECFG7) */ 997 #define USBC_UECFG7_EPSIZE_32_Val _U_(0x2) /**< \brief (USBC_UECFG7) */ 998 #define USBC_UECFG7_EPSIZE_64_Val _U_(0x3) /**< \brief (USBC_UECFG7) */ 999 #define USBC_UECFG7_EPSIZE_128_Val _U_(0x4) /**< \brief (USBC_UECFG7) */ 1000 #define USBC_UECFG7_EPSIZE_256_Val _U_(0x5) /**< \brief (USBC_UECFG7) */ 1001 #define USBC_UECFG7_EPSIZE_512_Val _U_(0x6) /**< \brief (USBC_UECFG7) */ 1002 #define USBC_UECFG7_EPSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UECFG7) */ 1003 #define USBC_UECFG7_EPSIZE_8 (USBC_UECFG7_EPSIZE_8_Val << USBC_UECFG7_EPSIZE_Pos) 1004 #define USBC_UECFG7_EPSIZE_16 (USBC_UECFG7_EPSIZE_16_Val << USBC_UECFG7_EPSIZE_Pos) 1005 #define USBC_UECFG7_EPSIZE_32 (USBC_UECFG7_EPSIZE_32_Val << USBC_UECFG7_EPSIZE_Pos) 1006 #define USBC_UECFG7_EPSIZE_64 (USBC_UECFG7_EPSIZE_64_Val << USBC_UECFG7_EPSIZE_Pos) 1007 #define USBC_UECFG7_EPSIZE_128 (USBC_UECFG7_EPSIZE_128_Val << USBC_UECFG7_EPSIZE_Pos) 1008 #define USBC_UECFG7_EPSIZE_256 (USBC_UECFG7_EPSIZE_256_Val << USBC_UECFG7_EPSIZE_Pos) 1009 #define USBC_UECFG7_EPSIZE_512 (USBC_UECFG7_EPSIZE_512_Val << USBC_UECFG7_EPSIZE_Pos) 1010 #define USBC_UECFG7_EPSIZE_1024 (USBC_UECFG7_EPSIZE_1024_Val << USBC_UECFG7_EPSIZE_Pos) 1011 #define USBC_UECFG7_EPDIR_Pos 8 /**< \brief (USBC_UECFG7) Endpoint Direction */ 1012 #define USBC_UECFG7_EPDIR (_U_(0x1) << USBC_UECFG7_EPDIR_Pos) 1013 #define USBC_UECFG7_EPDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UECFG7) */ 1014 #define USBC_UECFG7_EPDIR_IN_Val _U_(0x1) /**< \brief (USBC_UECFG7) */ 1015 #define USBC_UECFG7_EPDIR_OUT (USBC_UECFG7_EPDIR_OUT_Val << USBC_UECFG7_EPDIR_Pos) 1016 #define USBC_UECFG7_EPDIR_IN (USBC_UECFG7_EPDIR_IN_Val << USBC_UECFG7_EPDIR_Pos) 1017 #define USBC_UECFG7_EPTYPE_Pos 11 /**< \brief (USBC_UECFG7) Endpoint Type */ 1018 #define USBC_UECFG7_EPTYPE_Msk (_U_(0x3) << USBC_UECFG7_EPTYPE_Pos) 1019 #define USBC_UECFG7_EPTYPE(value) (USBC_UECFG7_EPTYPE_Msk & ((value) << USBC_UECFG7_EPTYPE_Pos)) 1020 #define USBC_UECFG7_EPTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UECFG7) */ 1021 #define USBC_UECFG7_EPTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UECFG7) */ 1022 #define USBC_UECFG7_EPTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UECFG7) */ 1023 #define USBC_UECFG7_EPTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UECFG7) */ 1024 #define USBC_UECFG7_EPTYPE_CONTROL (USBC_UECFG7_EPTYPE_CONTROL_Val << USBC_UECFG7_EPTYPE_Pos) 1025 #define USBC_UECFG7_EPTYPE_ISOCHRONOUS (USBC_UECFG7_EPTYPE_ISOCHRONOUS_Val << USBC_UECFG7_EPTYPE_Pos) 1026 #define USBC_UECFG7_EPTYPE_BULK (USBC_UECFG7_EPTYPE_BULK_Val << USBC_UECFG7_EPTYPE_Pos) 1027 #define USBC_UECFG7_EPTYPE_INTERRUPT (USBC_UECFG7_EPTYPE_INTERRUPT_Val << USBC_UECFG7_EPTYPE_Pos) 1028 #define USBC_UECFG7_REPNB_Pos 16 /**< \brief (USBC_UECFG7) Redirected Endpoint Number */ 1029 #define USBC_UECFG7_REPNB_Msk (_U_(0xF) << USBC_UECFG7_REPNB_Pos) 1030 #define USBC_UECFG7_REPNB(value) (USBC_UECFG7_REPNB_Msk & ((value) << USBC_UECFG7_REPNB_Pos)) 1031 #define USBC_UECFG7_MASK _U_(0x000F1974) /**< \brief (USBC_UECFG7) MASK Register */ 1032 1033 /* -------- USBC_UESTA0 : (USBC Offset: 0x130) (R/ 32) Endpoint Status Register -------- */ 1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1035 typedef union { 1036 struct { 1037 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1038 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1039 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1040 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1041 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1042 uint32_t :1; /*!< bit: 5 Reserved */ 1043 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1044 uint32_t :1; /*!< bit: 7 Reserved */ 1045 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1046 uint32_t :1; /*!< bit: 10 Reserved */ 1047 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1048 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1049 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1050 uint32_t :1; /*!< bit: 16 Reserved */ 1051 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1052 uint32_t :14; /*!< bit: 18..31 Reserved */ 1053 } bit; /*!< Structure used for bit access */ 1054 uint32_t reg; /*!< Type used for register access */ 1055 } USBC_UESTA0_Type; 1056 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1057 1058 #define USBC_UESTA0_OFFSET 0x130 /**< \brief (USBC_UESTA0 offset) Endpoint Status Register */ 1059 #define USBC_UESTA0_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA0 reset_value) Endpoint Status Register */ 1060 1061 #define USBC_UESTA0_TXINI_Pos 0 /**< \brief (USBC_UESTA0) Transmitted IN Data Interrupt */ 1062 #define USBC_UESTA0_TXINI (_U_(0x1) << USBC_UESTA0_TXINI_Pos) 1063 #define USBC_UESTA0_RXOUTI_Pos 1 /**< \brief (USBC_UESTA0) Received OUT Data Interrupt */ 1064 #define USBC_UESTA0_RXOUTI (_U_(0x1) << USBC_UESTA0_RXOUTI_Pos) 1065 #define USBC_UESTA0_RXSTPI_Pos 2 /**< \brief (USBC_UESTA0) Received SETUP Interrupt */ 1066 #define USBC_UESTA0_RXSTPI (_U_(0x1) << USBC_UESTA0_RXSTPI_Pos) 1067 #define USBC_UESTA0_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA0) NAKed OUT Interrupt */ 1068 #define USBC_UESTA0_NAKOUTI (_U_(0x1) << USBC_UESTA0_NAKOUTI_Pos) 1069 #define USBC_UESTA0_NAKINI_Pos 4 /**< \brief (USBC_UESTA0) NAKed IN Interrupt */ 1070 #define USBC_UESTA0_NAKINI (_U_(0x1) << USBC_UESTA0_NAKINI_Pos) 1071 #define USBC_UESTA0_STALLEDI_Pos 6 /**< \brief (USBC_UESTA0) STALLed Interrupt */ 1072 #define USBC_UESTA0_STALLEDI (_U_(0x1) << USBC_UESTA0_STALLEDI_Pos) 1073 #define USBC_UESTA0_DTSEQ_Pos 8 /**< \brief (USBC_UESTA0) Data Toggle Sequence */ 1074 #define USBC_UESTA0_DTSEQ_Msk (_U_(0x3) << USBC_UESTA0_DTSEQ_Pos) 1075 #define USBC_UESTA0_DTSEQ(value) (USBC_UESTA0_DTSEQ_Msk & ((value) << USBC_UESTA0_DTSEQ_Pos)) 1076 #define USBC_UESTA0_RAMACERI_Pos 11 /**< \brief (USBC_UESTA0) Ram Access Error Interrupt */ 1077 #define USBC_UESTA0_RAMACERI (_U_(0x1) << USBC_UESTA0_RAMACERI_Pos) 1078 #define USBC_UESTA0_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA0) Number Of Busy Banks */ 1079 #define USBC_UESTA0_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA0_NBUSYBK_Pos) 1080 #define USBC_UESTA0_NBUSYBK(value) (USBC_UESTA0_NBUSYBK_Msk & ((value) << USBC_UESTA0_NBUSYBK_Pos)) 1081 #define USBC_UESTA0_CURRBK_Pos 14 /**< \brief (USBC_UESTA0) Current Bank */ 1082 #define USBC_UESTA0_CURRBK_Msk (_U_(0x3) << USBC_UESTA0_CURRBK_Pos) 1083 #define USBC_UESTA0_CURRBK(value) (USBC_UESTA0_CURRBK_Msk & ((value) << USBC_UESTA0_CURRBK_Pos)) 1084 #define USBC_UESTA0_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA0) Control Direction */ 1085 #define USBC_UESTA0_CTRLDIR (_U_(0x1) << USBC_UESTA0_CTRLDIR_Pos) 1086 #define USBC_UESTA0_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA0) */ 1087 #define USBC_UESTA0_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA0) */ 1088 #define USBC_UESTA0_CTRLDIR_OUT (USBC_UESTA0_CTRLDIR_OUT_Val << USBC_UESTA0_CTRLDIR_Pos) 1089 #define USBC_UESTA0_CTRLDIR_IN (USBC_UESTA0_CTRLDIR_IN_Val << USBC_UESTA0_CTRLDIR_Pos) 1090 #define USBC_UESTA0_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA0) MASK Register */ 1091 1092 /* -------- USBC_UESTA1 : (USBC Offset: 0x134) (R/ 32) Endpoint Status Register -------- */ 1093 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1094 typedef union { 1095 struct { 1096 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1097 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1098 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1099 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1100 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1101 uint32_t :1; /*!< bit: 5 Reserved */ 1102 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1103 uint32_t :1; /*!< bit: 7 Reserved */ 1104 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1105 uint32_t :1; /*!< bit: 10 Reserved */ 1106 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1107 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1108 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1109 uint32_t :1; /*!< bit: 16 Reserved */ 1110 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1111 uint32_t :14; /*!< bit: 18..31 Reserved */ 1112 } bit; /*!< Structure used for bit access */ 1113 uint32_t reg; /*!< Type used for register access */ 1114 } USBC_UESTA1_Type; 1115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1116 1117 #define USBC_UESTA1_OFFSET 0x134 /**< \brief (USBC_UESTA1 offset) Endpoint Status Register */ 1118 #define USBC_UESTA1_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA1 reset_value) Endpoint Status Register */ 1119 1120 #define USBC_UESTA1_TXINI_Pos 0 /**< \brief (USBC_UESTA1) Transmitted IN Data Interrupt */ 1121 #define USBC_UESTA1_TXINI (_U_(0x1) << USBC_UESTA1_TXINI_Pos) 1122 #define USBC_UESTA1_RXOUTI_Pos 1 /**< \brief (USBC_UESTA1) Received OUT Data Interrupt */ 1123 #define USBC_UESTA1_RXOUTI (_U_(0x1) << USBC_UESTA1_RXOUTI_Pos) 1124 #define USBC_UESTA1_RXSTPI_Pos 2 /**< \brief (USBC_UESTA1) Received SETUP Interrupt */ 1125 #define USBC_UESTA1_RXSTPI (_U_(0x1) << USBC_UESTA1_RXSTPI_Pos) 1126 #define USBC_UESTA1_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA1) NAKed OUT Interrupt */ 1127 #define USBC_UESTA1_NAKOUTI (_U_(0x1) << USBC_UESTA1_NAKOUTI_Pos) 1128 #define USBC_UESTA1_NAKINI_Pos 4 /**< \brief (USBC_UESTA1) NAKed IN Interrupt */ 1129 #define USBC_UESTA1_NAKINI (_U_(0x1) << USBC_UESTA1_NAKINI_Pos) 1130 #define USBC_UESTA1_STALLEDI_Pos 6 /**< \brief (USBC_UESTA1) STALLed Interrupt */ 1131 #define USBC_UESTA1_STALLEDI (_U_(0x1) << USBC_UESTA1_STALLEDI_Pos) 1132 #define USBC_UESTA1_DTSEQ_Pos 8 /**< \brief (USBC_UESTA1) Data Toggle Sequence */ 1133 #define USBC_UESTA1_DTSEQ_Msk (_U_(0x3) << USBC_UESTA1_DTSEQ_Pos) 1134 #define USBC_UESTA1_DTSEQ(value) (USBC_UESTA1_DTSEQ_Msk & ((value) << USBC_UESTA1_DTSEQ_Pos)) 1135 #define USBC_UESTA1_RAMACERI_Pos 11 /**< \brief (USBC_UESTA1) Ram Access Error Interrupt */ 1136 #define USBC_UESTA1_RAMACERI (_U_(0x1) << USBC_UESTA1_RAMACERI_Pos) 1137 #define USBC_UESTA1_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA1) Number Of Busy Banks */ 1138 #define USBC_UESTA1_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA1_NBUSYBK_Pos) 1139 #define USBC_UESTA1_NBUSYBK(value) (USBC_UESTA1_NBUSYBK_Msk & ((value) << USBC_UESTA1_NBUSYBK_Pos)) 1140 #define USBC_UESTA1_CURRBK_Pos 14 /**< \brief (USBC_UESTA1) Current Bank */ 1141 #define USBC_UESTA1_CURRBK_Msk (_U_(0x3) << USBC_UESTA1_CURRBK_Pos) 1142 #define USBC_UESTA1_CURRBK(value) (USBC_UESTA1_CURRBK_Msk & ((value) << USBC_UESTA1_CURRBK_Pos)) 1143 #define USBC_UESTA1_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA1) Control Direction */ 1144 #define USBC_UESTA1_CTRLDIR (_U_(0x1) << USBC_UESTA1_CTRLDIR_Pos) 1145 #define USBC_UESTA1_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA1) */ 1146 #define USBC_UESTA1_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA1) */ 1147 #define USBC_UESTA1_CTRLDIR_OUT (USBC_UESTA1_CTRLDIR_OUT_Val << USBC_UESTA1_CTRLDIR_Pos) 1148 #define USBC_UESTA1_CTRLDIR_IN (USBC_UESTA1_CTRLDIR_IN_Val << USBC_UESTA1_CTRLDIR_Pos) 1149 #define USBC_UESTA1_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA1) MASK Register */ 1150 1151 /* -------- USBC_UESTA2 : (USBC Offset: 0x138) (R/ 32) Endpoint Status Register -------- */ 1152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1153 typedef union { 1154 struct { 1155 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1156 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1157 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1158 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1159 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1160 uint32_t :1; /*!< bit: 5 Reserved */ 1161 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1162 uint32_t :1; /*!< bit: 7 Reserved */ 1163 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1164 uint32_t :1; /*!< bit: 10 Reserved */ 1165 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1166 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1167 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1168 uint32_t :1; /*!< bit: 16 Reserved */ 1169 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1170 uint32_t :14; /*!< bit: 18..31 Reserved */ 1171 } bit; /*!< Structure used for bit access */ 1172 uint32_t reg; /*!< Type used for register access */ 1173 } USBC_UESTA2_Type; 1174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1175 1176 #define USBC_UESTA2_OFFSET 0x138 /**< \brief (USBC_UESTA2 offset) Endpoint Status Register */ 1177 #define USBC_UESTA2_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA2 reset_value) Endpoint Status Register */ 1178 1179 #define USBC_UESTA2_TXINI_Pos 0 /**< \brief (USBC_UESTA2) Transmitted IN Data Interrupt */ 1180 #define USBC_UESTA2_TXINI (_U_(0x1) << USBC_UESTA2_TXINI_Pos) 1181 #define USBC_UESTA2_RXOUTI_Pos 1 /**< \brief (USBC_UESTA2) Received OUT Data Interrupt */ 1182 #define USBC_UESTA2_RXOUTI (_U_(0x1) << USBC_UESTA2_RXOUTI_Pos) 1183 #define USBC_UESTA2_RXSTPI_Pos 2 /**< \brief (USBC_UESTA2) Received SETUP Interrupt */ 1184 #define USBC_UESTA2_RXSTPI (_U_(0x1) << USBC_UESTA2_RXSTPI_Pos) 1185 #define USBC_UESTA2_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA2) NAKed OUT Interrupt */ 1186 #define USBC_UESTA2_NAKOUTI (_U_(0x1) << USBC_UESTA2_NAKOUTI_Pos) 1187 #define USBC_UESTA2_NAKINI_Pos 4 /**< \brief (USBC_UESTA2) NAKed IN Interrupt */ 1188 #define USBC_UESTA2_NAKINI (_U_(0x1) << USBC_UESTA2_NAKINI_Pos) 1189 #define USBC_UESTA2_STALLEDI_Pos 6 /**< \brief (USBC_UESTA2) STALLed Interrupt */ 1190 #define USBC_UESTA2_STALLEDI (_U_(0x1) << USBC_UESTA2_STALLEDI_Pos) 1191 #define USBC_UESTA2_DTSEQ_Pos 8 /**< \brief (USBC_UESTA2) Data Toggle Sequence */ 1192 #define USBC_UESTA2_DTSEQ_Msk (_U_(0x3) << USBC_UESTA2_DTSEQ_Pos) 1193 #define USBC_UESTA2_DTSEQ(value) (USBC_UESTA2_DTSEQ_Msk & ((value) << USBC_UESTA2_DTSEQ_Pos)) 1194 #define USBC_UESTA2_RAMACERI_Pos 11 /**< \brief (USBC_UESTA2) Ram Access Error Interrupt */ 1195 #define USBC_UESTA2_RAMACERI (_U_(0x1) << USBC_UESTA2_RAMACERI_Pos) 1196 #define USBC_UESTA2_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA2) Number Of Busy Banks */ 1197 #define USBC_UESTA2_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA2_NBUSYBK_Pos) 1198 #define USBC_UESTA2_NBUSYBK(value) (USBC_UESTA2_NBUSYBK_Msk & ((value) << USBC_UESTA2_NBUSYBK_Pos)) 1199 #define USBC_UESTA2_CURRBK_Pos 14 /**< \brief (USBC_UESTA2) Current Bank */ 1200 #define USBC_UESTA2_CURRBK_Msk (_U_(0x3) << USBC_UESTA2_CURRBK_Pos) 1201 #define USBC_UESTA2_CURRBK(value) (USBC_UESTA2_CURRBK_Msk & ((value) << USBC_UESTA2_CURRBK_Pos)) 1202 #define USBC_UESTA2_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA2) Control Direction */ 1203 #define USBC_UESTA2_CTRLDIR (_U_(0x1) << USBC_UESTA2_CTRLDIR_Pos) 1204 #define USBC_UESTA2_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA2) */ 1205 #define USBC_UESTA2_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA2) */ 1206 #define USBC_UESTA2_CTRLDIR_OUT (USBC_UESTA2_CTRLDIR_OUT_Val << USBC_UESTA2_CTRLDIR_Pos) 1207 #define USBC_UESTA2_CTRLDIR_IN (USBC_UESTA2_CTRLDIR_IN_Val << USBC_UESTA2_CTRLDIR_Pos) 1208 #define USBC_UESTA2_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA2) MASK Register */ 1209 1210 /* -------- USBC_UESTA3 : (USBC Offset: 0x13C) (R/ 32) Endpoint Status Register -------- */ 1211 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1212 typedef union { 1213 struct { 1214 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1215 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1216 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1217 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1218 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1219 uint32_t :1; /*!< bit: 5 Reserved */ 1220 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1221 uint32_t :1; /*!< bit: 7 Reserved */ 1222 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1223 uint32_t :1; /*!< bit: 10 Reserved */ 1224 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1225 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1226 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1227 uint32_t :1; /*!< bit: 16 Reserved */ 1228 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1229 uint32_t :14; /*!< bit: 18..31 Reserved */ 1230 } bit; /*!< Structure used for bit access */ 1231 uint32_t reg; /*!< Type used for register access */ 1232 } USBC_UESTA3_Type; 1233 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1234 1235 #define USBC_UESTA3_OFFSET 0x13C /**< \brief (USBC_UESTA3 offset) Endpoint Status Register */ 1236 #define USBC_UESTA3_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA3 reset_value) Endpoint Status Register */ 1237 1238 #define USBC_UESTA3_TXINI_Pos 0 /**< \brief (USBC_UESTA3) Transmitted IN Data Interrupt */ 1239 #define USBC_UESTA3_TXINI (_U_(0x1) << USBC_UESTA3_TXINI_Pos) 1240 #define USBC_UESTA3_RXOUTI_Pos 1 /**< \brief (USBC_UESTA3) Received OUT Data Interrupt */ 1241 #define USBC_UESTA3_RXOUTI (_U_(0x1) << USBC_UESTA3_RXOUTI_Pos) 1242 #define USBC_UESTA3_RXSTPI_Pos 2 /**< \brief (USBC_UESTA3) Received SETUP Interrupt */ 1243 #define USBC_UESTA3_RXSTPI (_U_(0x1) << USBC_UESTA3_RXSTPI_Pos) 1244 #define USBC_UESTA3_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA3) NAKed OUT Interrupt */ 1245 #define USBC_UESTA3_NAKOUTI (_U_(0x1) << USBC_UESTA3_NAKOUTI_Pos) 1246 #define USBC_UESTA3_NAKINI_Pos 4 /**< \brief (USBC_UESTA3) NAKed IN Interrupt */ 1247 #define USBC_UESTA3_NAKINI (_U_(0x1) << USBC_UESTA3_NAKINI_Pos) 1248 #define USBC_UESTA3_STALLEDI_Pos 6 /**< \brief (USBC_UESTA3) STALLed Interrupt */ 1249 #define USBC_UESTA3_STALLEDI (_U_(0x1) << USBC_UESTA3_STALLEDI_Pos) 1250 #define USBC_UESTA3_DTSEQ_Pos 8 /**< \brief (USBC_UESTA3) Data Toggle Sequence */ 1251 #define USBC_UESTA3_DTSEQ_Msk (_U_(0x3) << USBC_UESTA3_DTSEQ_Pos) 1252 #define USBC_UESTA3_DTSEQ(value) (USBC_UESTA3_DTSEQ_Msk & ((value) << USBC_UESTA3_DTSEQ_Pos)) 1253 #define USBC_UESTA3_RAMACERI_Pos 11 /**< \brief (USBC_UESTA3) Ram Access Error Interrupt */ 1254 #define USBC_UESTA3_RAMACERI (_U_(0x1) << USBC_UESTA3_RAMACERI_Pos) 1255 #define USBC_UESTA3_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA3) Number Of Busy Banks */ 1256 #define USBC_UESTA3_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA3_NBUSYBK_Pos) 1257 #define USBC_UESTA3_NBUSYBK(value) (USBC_UESTA3_NBUSYBK_Msk & ((value) << USBC_UESTA3_NBUSYBK_Pos)) 1258 #define USBC_UESTA3_CURRBK_Pos 14 /**< \brief (USBC_UESTA3) Current Bank */ 1259 #define USBC_UESTA3_CURRBK_Msk (_U_(0x3) << USBC_UESTA3_CURRBK_Pos) 1260 #define USBC_UESTA3_CURRBK(value) (USBC_UESTA3_CURRBK_Msk & ((value) << USBC_UESTA3_CURRBK_Pos)) 1261 #define USBC_UESTA3_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA3) Control Direction */ 1262 #define USBC_UESTA3_CTRLDIR (_U_(0x1) << USBC_UESTA3_CTRLDIR_Pos) 1263 #define USBC_UESTA3_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA3) */ 1264 #define USBC_UESTA3_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA3) */ 1265 #define USBC_UESTA3_CTRLDIR_OUT (USBC_UESTA3_CTRLDIR_OUT_Val << USBC_UESTA3_CTRLDIR_Pos) 1266 #define USBC_UESTA3_CTRLDIR_IN (USBC_UESTA3_CTRLDIR_IN_Val << USBC_UESTA3_CTRLDIR_Pos) 1267 #define USBC_UESTA3_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA3) MASK Register */ 1268 1269 /* -------- USBC_UESTA4 : (USBC Offset: 0x140) (R/ 32) Endpoint Status Register -------- */ 1270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1271 typedef union { 1272 struct { 1273 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1274 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1275 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1276 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1277 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1278 uint32_t :1; /*!< bit: 5 Reserved */ 1279 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1280 uint32_t :1; /*!< bit: 7 Reserved */ 1281 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1282 uint32_t :1; /*!< bit: 10 Reserved */ 1283 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1284 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1285 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1286 uint32_t :1; /*!< bit: 16 Reserved */ 1287 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1288 uint32_t :14; /*!< bit: 18..31 Reserved */ 1289 } bit; /*!< Structure used for bit access */ 1290 uint32_t reg; /*!< Type used for register access */ 1291 } USBC_UESTA4_Type; 1292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1293 1294 #define USBC_UESTA4_OFFSET 0x140 /**< \brief (USBC_UESTA4 offset) Endpoint Status Register */ 1295 #define USBC_UESTA4_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA4 reset_value) Endpoint Status Register */ 1296 1297 #define USBC_UESTA4_TXINI_Pos 0 /**< \brief (USBC_UESTA4) Transmitted IN Data Interrupt */ 1298 #define USBC_UESTA4_TXINI (_U_(0x1) << USBC_UESTA4_TXINI_Pos) 1299 #define USBC_UESTA4_RXOUTI_Pos 1 /**< \brief (USBC_UESTA4) Received OUT Data Interrupt */ 1300 #define USBC_UESTA4_RXOUTI (_U_(0x1) << USBC_UESTA4_RXOUTI_Pos) 1301 #define USBC_UESTA4_RXSTPI_Pos 2 /**< \brief (USBC_UESTA4) Received SETUP Interrupt */ 1302 #define USBC_UESTA4_RXSTPI (_U_(0x1) << USBC_UESTA4_RXSTPI_Pos) 1303 #define USBC_UESTA4_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA4) NAKed OUT Interrupt */ 1304 #define USBC_UESTA4_NAKOUTI (_U_(0x1) << USBC_UESTA4_NAKOUTI_Pos) 1305 #define USBC_UESTA4_NAKINI_Pos 4 /**< \brief (USBC_UESTA4) NAKed IN Interrupt */ 1306 #define USBC_UESTA4_NAKINI (_U_(0x1) << USBC_UESTA4_NAKINI_Pos) 1307 #define USBC_UESTA4_STALLEDI_Pos 6 /**< \brief (USBC_UESTA4) STALLed Interrupt */ 1308 #define USBC_UESTA4_STALLEDI (_U_(0x1) << USBC_UESTA4_STALLEDI_Pos) 1309 #define USBC_UESTA4_DTSEQ_Pos 8 /**< \brief (USBC_UESTA4) Data Toggle Sequence */ 1310 #define USBC_UESTA4_DTSEQ_Msk (_U_(0x3) << USBC_UESTA4_DTSEQ_Pos) 1311 #define USBC_UESTA4_DTSEQ(value) (USBC_UESTA4_DTSEQ_Msk & ((value) << USBC_UESTA4_DTSEQ_Pos)) 1312 #define USBC_UESTA4_RAMACERI_Pos 11 /**< \brief (USBC_UESTA4) Ram Access Error Interrupt */ 1313 #define USBC_UESTA4_RAMACERI (_U_(0x1) << USBC_UESTA4_RAMACERI_Pos) 1314 #define USBC_UESTA4_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA4) Number Of Busy Banks */ 1315 #define USBC_UESTA4_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA4_NBUSYBK_Pos) 1316 #define USBC_UESTA4_NBUSYBK(value) (USBC_UESTA4_NBUSYBK_Msk & ((value) << USBC_UESTA4_NBUSYBK_Pos)) 1317 #define USBC_UESTA4_CURRBK_Pos 14 /**< \brief (USBC_UESTA4) Current Bank */ 1318 #define USBC_UESTA4_CURRBK_Msk (_U_(0x3) << USBC_UESTA4_CURRBK_Pos) 1319 #define USBC_UESTA4_CURRBK(value) (USBC_UESTA4_CURRBK_Msk & ((value) << USBC_UESTA4_CURRBK_Pos)) 1320 #define USBC_UESTA4_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA4) Control Direction */ 1321 #define USBC_UESTA4_CTRLDIR (_U_(0x1) << USBC_UESTA4_CTRLDIR_Pos) 1322 #define USBC_UESTA4_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA4) */ 1323 #define USBC_UESTA4_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA4) */ 1324 #define USBC_UESTA4_CTRLDIR_OUT (USBC_UESTA4_CTRLDIR_OUT_Val << USBC_UESTA4_CTRLDIR_Pos) 1325 #define USBC_UESTA4_CTRLDIR_IN (USBC_UESTA4_CTRLDIR_IN_Val << USBC_UESTA4_CTRLDIR_Pos) 1326 #define USBC_UESTA4_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA4) MASK Register */ 1327 1328 /* -------- USBC_UESTA5 : (USBC Offset: 0x144) (R/ 32) Endpoint Status Register -------- */ 1329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1330 typedef union { 1331 struct { 1332 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1333 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1334 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1335 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1336 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1337 uint32_t :1; /*!< bit: 5 Reserved */ 1338 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1339 uint32_t :1; /*!< bit: 7 Reserved */ 1340 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1341 uint32_t :1; /*!< bit: 10 Reserved */ 1342 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1343 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1344 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1345 uint32_t :1; /*!< bit: 16 Reserved */ 1346 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1347 uint32_t :14; /*!< bit: 18..31 Reserved */ 1348 } bit; /*!< Structure used for bit access */ 1349 uint32_t reg; /*!< Type used for register access */ 1350 } USBC_UESTA5_Type; 1351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1352 1353 #define USBC_UESTA5_OFFSET 0x144 /**< \brief (USBC_UESTA5 offset) Endpoint Status Register */ 1354 #define USBC_UESTA5_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA5 reset_value) Endpoint Status Register */ 1355 1356 #define USBC_UESTA5_TXINI_Pos 0 /**< \brief (USBC_UESTA5) Transmitted IN Data Interrupt */ 1357 #define USBC_UESTA5_TXINI (_U_(0x1) << USBC_UESTA5_TXINI_Pos) 1358 #define USBC_UESTA5_RXOUTI_Pos 1 /**< \brief (USBC_UESTA5) Received OUT Data Interrupt */ 1359 #define USBC_UESTA5_RXOUTI (_U_(0x1) << USBC_UESTA5_RXOUTI_Pos) 1360 #define USBC_UESTA5_RXSTPI_Pos 2 /**< \brief (USBC_UESTA5) Received SETUP Interrupt */ 1361 #define USBC_UESTA5_RXSTPI (_U_(0x1) << USBC_UESTA5_RXSTPI_Pos) 1362 #define USBC_UESTA5_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA5) NAKed OUT Interrupt */ 1363 #define USBC_UESTA5_NAKOUTI (_U_(0x1) << USBC_UESTA5_NAKOUTI_Pos) 1364 #define USBC_UESTA5_NAKINI_Pos 4 /**< \brief (USBC_UESTA5) NAKed IN Interrupt */ 1365 #define USBC_UESTA5_NAKINI (_U_(0x1) << USBC_UESTA5_NAKINI_Pos) 1366 #define USBC_UESTA5_STALLEDI_Pos 6 /**< \brief (USBC_UESTA5) STALLed Interrupt */ 1367 #define USBC_UESTA5_STALLEDI (_U_(0x1) << USBC_UESTA5_STALLEDI_Pos) 1368 #define USBC_UESTA5_DTSEQ_Pos 8 /**< \brief (USBC_UESTA5) Data Toggle Sequence */ 1369 #define USBC_UESTA5_DTSEQ_Msk (_U_(0x3) << USBC_UESTA5_DTSEQ_Pos) 1370 #define USBC_UESTA5_DTSEQ(value) (USBC_UESTA5_DTSEQ_Msk & ((value) << USBC_UESTA5_DTSEQ_Pos)) 1371 #define USBC_UESTA5_RAMACERI_Pos 11 /**< \brief (USBC_UESTA5) Ram Access Error Interrupt */ 1372 #define USBC_UESTA5_RAMACERI (_U_(0x1) << USBC_UESTA5_RAMACERI_Pos) 1373 #define USBC_UESTA5_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA5) Number Of Busy Banks */ 1374 #define USBC_UESTA5_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA5_NBUSYBK_Pos) 1375 #define USBC_UESTA5_NBUSYBK(value) (USBC_UESTA5_NBUSYBK_Msk & ((value) << USBC_UESTA5_NBUSYBK_Pos)) 1376 #define USBC_UESTA5_CURRBK_Pos 14 /**< \brief (USBC_UESTA5) Current Bank */ 1377 #define USBC_UESTA5_CURRBK_Msk (_U_(0x3) << USBC_UESTA5_CURRBK_Pos) 1378 #define USBC_UESTA5_CURRBK(value) (USBC_UESTA5_CURRBK_Msk & ((value) << USBC_UESTA5_CURRBK_Pos)) 1379 #define USBC_UESTA5_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA5) Control Direction */ 1380 #define USBC_UESTA5_CTRLDIR (_U_(0x1) << USBC_UESTA5_CTRLDIR_Pos) 1381 #define USBC_UESTA5_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA5) */ 1382 #define USBC_UESTA5_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA5) */ 1383 #define USBC_UESTA5_CTRLDIR_OUT (USBC_UESTA5_CTRLDIR_OUT_Val << USBC_UESTA5_CTRLDIR_Pos) 1384 #define USBC_UESTA5_CTRLDIR_IN (USBC_UESTA5_CTRLDIR_IN_Val << USBC_UESTA5_CTRLDIR_Pos) 1385 #define USBC_UESTA5_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA5) MASK Register */ 1386 1387 /* -------- USBC_UESTA6 : (USBC Offset: 0x148) (R/ 32) Endpoint Status Register -------- */ 1388 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1389 typedef union { 1390 struct { 1391 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1392 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1393 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1394 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1395 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1396 uint32_t :1; /*!< bit: 5 Reserved */ 1397 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1398 uint32_t :1; /*!< bit: 7 Reserved */ 1399 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1400 uint32_t :1; /*!< bit: 10 Reserved */ 1401 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1402 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1403 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1404 uint32_t :1; /*!< bit: 16 Reserved */ 1405 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1406 uint32_t :14; /*!< bit: 18..31 Reserved */ 1407 } bit; /*!< Structure used for bit access */ 1408 uint32_t reg; /*!< Type used for register access */ 1409 } USBC_UESTA6_Type; 1410 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1411 1412 #define USBC_UESTA6_OFFSET 0x148 /**< \brief (USBC_UESTA6 offset) Endpoint Status Register */ 1413 #define USBC_UESTA6_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA6 reset_value) Endpoint Status Register */ 1414 1415 #define USBC_UESTA6_TXINI_Pos 0 /**< \brief (USBC_UESTA6) Transmitted IN Data Interrupt */ 1416 #define USBC_UESTA6_TXINI (_U_(0x1) << USBC_UESTA6_TXINI_Pos) 1417 #define USBC_UESTA6_RXOUTI_Pos 1 /**< \brief (USBC_UESTA6) Received OUT Data Interrupt */ 1418 #define USBC_UESTA6_RXOUTI (_U_(0x1) << USBC_UESTA6_RXOUTI_Pos) 1419 #define USBC_UESTA6_RXSTPI_Pos 2 /**< \brief (USBC_UESTA6) Received SETUP Interrupt */ 1420 #define USBC_UESTA6_RXSTPI (_U_(0x1) << USBC_UESTA6_RXSTPI_Pos) 1421 #define USBC_UESTA6_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA6) NAKed OUT Interrupt */ 1422 #define USBC_UESTA6_NAKOUTI (_U_(0x1) << USBC_UESTA6_NAKOUTI_Pos) 1423 #define USBC_UESTA6_NAKINI_Pos 4 /**< \brief (USBC_UESTA6) NAKed IN Interrupt */ 1424 #define USBC_UESTA6_NAKINI (_U_(0x1) << USBC_UESTA6_NAKINI_Pos) 1425 #define USBC_UESTA6_STALLEDI_Pos 6 /**< \brief (USBC_UESTA6) STALLed Interrupt */ 1426 #define USBC_UESTA6_STALLEDI (_U_(0x1) << USBC_UESTA6_STALLEDI_Pos) 1427 #define USBC_UESTA6_DTSEQ_Pos 8 /**< \brief (USBC_UESTA6) Data Toggle Sequence */ 1428 #define USBC_UESTA6_DTSEQ_Msk (_U_(0x3) << USBC_UESTA6_DTSEQ_Pos) 1429 #define USBC_UESTA6_DTSEQ(value) (USBC_UESTA6_DTSEQ_Msk & ((value) << USBC_UESTA6_DTSEQ_Pos)) 1430 #define USBC_UESTA6_RAMACERI_Pos 11 /**< \brief (USBC_UESTA6) Ram Access Error Interrupt */ 1431 #define USBC_UESTA6_RAMACERI (_U_(0x1) << USBC_UESTA6_RAMACERI_Pos) 1432 #define USBC_UESTA6_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA6) Number Of Busy Banks */ 1433 #define USBC_UESTA6_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA6_NBUSYBK_Pos) 1434 #define USBC_UESTA6_NBUSYBK(value) (USBC_UESTA6_NBUSYBK_Msk & ((value) << USBC_UESTA6_NBUSYBK_Pos)) 1435 #define USBC_UESTA6_CURRBK_Pos 14 /**< \brief (USBC_UESTA6) Current Bank */ 1436 #define USBC_UESTA6_CURRBK_Msk (_U_(0x3) << USBC_UESTA6_CURRBK_Pos) 1437 #define USBC_UESTA6_CURRBK(value) (USBC_UESTA6_CURRBK_Msk & ((value) << USBC_UESTA6_CURRBK_Pos)) 1438 #define USBC_UESTA6_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA6) Control Direction */ 1439 #define USBC_UESTA6_CTRLDIR (_U_(0x1) << USBC_UESTA6_CTRLDIR_Pos) 1440 #define USBC_UESTA6_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA6) */ 1441 #define USBC_UESTA6_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA6) */ 1442 #define USBC_UESTA6_CTRLDIR_OUT (USBC_UESTA6_CTRLDIR_OUT_Val << USBC_UESTA6_CTRLDIR_Pos) 1443 #define USBC_UESTA6_CTRLDIR_IN (USBC_UESTA6_CTRLDIR_IN_Val << USBC_UESTA6_CTRLDIR_Pos) 1444 #define USBC_UESTA6_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA6) MASK Register */ 1445 1446 /* -------- USBC_UESTA7 : (USBC Offset: 0x14C) (R/ 32) Endpoint Status Register -------- */ 1447 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1448 typedef union { 1449 struct { 1450 uint32_t TXINI:1; /*!< bit: 0 Transmitted IN Data Interrupt */ 1451 uint32_t RXOUTI:1; /*!< bit: 1 Received OUT Data Interrupt */ 1452 uint32_t RXSTPI:1; /*!< bit: 2 Received SETUP Interrupt */ 1453 uint32_t NAKOUTI:1; /*!< bit: 3 NAKed OUT Interrupt */ 1454 uint32_t NAKINI:1; /*!< bit: 4 NAKed IN Interrupt */ 1455 uint32_t :1; /*!< bit: 5 Reserved */ 1456 uint32_t STALLEDI:1; /*!< bit: 6 STALLed Interrupt */ 1457 uint32_t :1; /*!< bit: 7 Reserved */ 1458 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 1459 uint32_t :1; /*!< bit: 10 Reserved */ 1460 uint32_t RAMACERI:1; /*!< bit: 11 Ram Access Error Interrupt */ 1461 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number Of Busy Banks */ 1462 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 1463 uint32_t :1; /*!< bit: 16 Reserved */ 1464 uint32_t CTRLDIR:1; /*!< bit: 17 Control Direction */ 1465 uint32_t :14; /*!< bit: 18..31 Reserved */ 1466 } bit; /*!< Structure used for bit access */ 1467 uint32_t reg; /*!< Type used for register access */ 1468 } USBC_UESTA7_Type; 1469 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1470 1471 #define USBC_UESTA7_OFFSET 0x14C /**< \brief (USBC_UESTA7 offset) Endpoint Status Register */ 1472 #define USBC_UESTA7_RESETVALUE _U_(0x00000100); /**< \brief (USBC_UESTA7 reset_value) Endpoint Status Register */ 1473 1474 #define USBC_UESTA7_TXINI_Pos 0 /**< \brief (USBC_UESTA7) Transmitted IN Data Interrupt */ 1475 #define USBC_UESTA7_TXINI (_U_(0x1) << USBC_UESTA7_TXINI_Pos) 1476 #define USBC_UESTA7_RXOUTI_Pos 1 /**< \brief (USBC_UESTA7) Received OUT Data Interrupt */ 1477 #define USBC_UESTA7_RXOUTI (_U_(0x1) << USBC_UESTA7_RXOUTI_Pos) 1478 #define USBC_UESTA7_RXSTPI_Pos 2 /**< \brief (USBC_UESTA7) Received SETUP Interrupt */ 1479 #define USBC_UESTA7_RXSTPI (_U_(0x1) << USBC_UESTA7_RXSTPI_Pos) 1480 #define USBC_UESTA7_NAKOUTI_Pos 3 /**< \brief (USBC_UESTA7) NAKed OUT Interrupt */ 1481 #define USBC_UESTA7_NAKOUTI (_U_(0x1) << USBC_UESTA7_NAKOUTI_Pos) 1482 #define USBC_UESTA7_NAKINI_Pos 4 /**< \brief (USBC_UESTA7) NAKed IN Interrupt */ 1483 #define USBC_UESTA7_NAKINI (_U_(0x1) << USBC_UESTA7_NAKINI_Pos) 1484 #define USBC_UESTA7_STALLEDI_Pos 6 /**< \brief (USBC_UESTA7) STALLed Interrupt */ 1485 #define USBC_UESTA7_STALLEDI (_U_(0x1) << USBC_UESTA7_STALLEDI_Pos) 1486 #define USBC_UESTA7_DTSEQ_Pos 8 /**< \brief (USBC_UESTA7) Data Toggle Sequence */ 1487 #define USBC_UESTA7_DTSEQ_Msk (_U_(0x3) << USBC_UESTA7_DTSEQ_Pos) 1488 #define USBC_UESTA7_DTSEQ(value) (USBC_UESTA7_DTSEQ_Msk & ((value) << USBC_UESTA7_DTSEQ_Pos)) 1489 #define USBC_UESTA7_RAMACERI_Pos 11 /**< \brief (USBC_UESTA7) Ram Access Error Interrupt */ 1490 #define USBC_UESTA7_RAMACERI (_U_(0x1) << USBC_UESTA7_RAMACERI_Pos) 1491 #define USBC_UESTA7_NBUSYBK_Pos 12 /**< \brief (USBC_UESTA7) Number Of Busy Banks */ 1492 #define USBC_UESTA7_NBUSYBK_Msk (_U_(0x3) << USBC_UESTA7_NBUSYBK_Pos) 1493 #define USBC_UESTA7_NBUSYBK(value) (USBC_UESTA7_NBUSYBK_Msk & ((value) << USBC_UESTA7_NBUSYBK_Pos)) 1494 #define USBC_UESTA7_CURRBK_Pos 14 /**< \brief (USBC_UESTA7) Current Bank */ 1495 #define USBC_UESTA7_CURRBK_Msk (_U_(0x3) << USBC_UESTA7_CURRBK_Pos) 1496 #define USBC_UESTA7_CURRBK(value) (USBC_UESTA7_CURRBK_Msk & ((value) << USBC_UESTA7_CURRBK_Pos)) 1497 #define USBC_UESTA7_CTRLDIR_Pos 17 /**< \brief (USBC_UESTA7) Control Direction */ 1498 #define USBC_UESTA7_CTRLDIR (_U_(0x1) << USBC_UESTA7_CTRLDIR_Pos) 1499 #define USBC_UESTA7_CTRLDIR_OUT_Val _U_(0x0) /**< \brief (USBC_UESTA7) */ 1500 #define USBC_UESTA7_CTRLDIR_IN_Val _U_(0x1) /**< \brief (USBC_UESTA7) */ 1501 #define USBC_UESTA7_CTRLDIR_OUT (USBC_UESTA7_CTRLDIR_OUT_Val << USBC_UESTA7_CTRLDIR_Pos) 1502 #define USBC_UESTA7_CTRLDIR_IN (USBC_UESTA7_CTRLDIR_IN_Val << USBC_UESTA7_CTRLDIR_Pos) 1503 #define USBC_UESTA7_MASK _U_(0x0002FB5F) /**< \brief (USBC_UESTA7) MASK Register */ 1504 1505 /* -------- USBC_UESTA0CLR : (USBC Offset: 0x160) ( /W 32) Endpoint Status Clear Register -------- */ 1506 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1507 typedef union { 1508 struct { 1509 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1510 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1511 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1512 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1513 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1514 uint32_t :1; /*!< bit: 5 Reserved */ 1515 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1516 uint32_t :4; /*!< bit: 7..10 Reserved */ 1517 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1518 uint32_t :20; /*!< bit: 12..31 Reserved */ 1519 } bit; /*!< Structure used for bit access */ 1520 uint32_t reg; /*!< Type used for register access */ 1521 } USBC_UESTA0CLR_Type; 1522 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1523 1524 #define USBC_UESTA0CLR_OFFSET 0x160 /**< \brief (USBC_UESTA0CLR offset) Endpoint Status Clear Register */ 1525 #define USBC_UESTA0CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA0CLR reset_value) Endpoint Status Clear Register */ 1526 1527 #define USBC_UESTA0CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA0CLR) TXINI Clear */ 1528 #define USBC_UESTA0CLR_TXINIC (_U_(0x1) << USBC_UESTA0CLR_TXINIC_Pos) 1529 #define USBC_UESTA0CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA0CLR) RXOUTI Clear */ 1530 #define USBC_UESTA0CLR_RXOUTIC (_U_(0x1) << USBC_UESTA0CLR_RXOUTIC_Pos) 1531 #define USBC_UESTA0CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA0CLR) RXSTPI Clear */ 1532 #define USBC_UESTA0CLR_RXSTPIC (_U_(0x1) << USBC_UESTA0CLR_RXSTPIC_Pos) 1533 #define USBC_UESTA0CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA0CLR) NAKOUTI Clear */ 1534 #define USBC_UESTA0CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA0CLR_NAKOUTIC_Pos) 1535 #define USBC_UESTA0CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA0CLR) NAKINI Clear */ 1536 #define USBC_UESTA0CLR_NAKINIC (_U_(0x1) << USBC_UESTA0CLR_NAKINIC_Pos) 1537 #define USBC_UESTA0CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA0CLR) STALLEDI Clear */ 1538 #define USBC_UESTA0CLR_STALLEDIC (_U_(0x1) << USBC_UESTA0CLR_STALLEDIC_Pos) 1539 #define USBC_UESTA0CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA0CLR) RAMACERI Clear */ 1540 #define USBC_UESTA0CLR_RAMACERIC (_U_(0x1) << USBC_UESTA0CLR_RAMACERIC_Pos) 1541 #define USBC_UESTA0CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA0CLR) MASK Register */ 1542 1543 /* -------- USBC_UESTA1CLR : (USBC Offset: 0x164) ( /W 32) Endpoint Status Clear Register -------- */ 1544 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1545 typedef union { 1546 struct { 1547 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1548 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1549 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1550 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1551 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1552 uint32_t :1; /*!< bit: 5 Reserved */ 1553 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1554 uint32_t :4; /*!< bit: 7..10 Reserved */ 1555 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1556 uint32_t :20; /*!< bit: 12..31 Reserved */ 1557 } bit; /*!< Structure used for bit access */ 1558 uint32_t reg; /*!< Type used for register access */ 1559 } USBC_UESTA1CLR_Type; 1560 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1561 1562 #define USBC_UESTA1CLR_OFFSET 0x164 /**< \brief (USBC_UESTA1CLR offset) Endpoint Status Clear Register */ 1563 #define USBC_UESTA1CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA1CLR reset_value) Endpoint Status Clear Register */ 1564 1565 #define USBC_UESTA1CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA1CLR) TXINI Clear */ 1566 #define USBC_UESTA1CLR_TXINIC (_U_(0x1) << USBC_UESTA1CLR_TXINIC_Pos) 1567 #define USBC_UESTA1CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA1CLR) RXOUTI Clear */ 1568 #define USBC_UESTA1CLR_RXOUTIC (_U_(0x1) << USBC_UESTA1CLR_RXOUTIC_Pos) 1569 #define USBC_UESTA1CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA1CLR) RXSTPI Clear */ 1570 #define USBC_UESTA1CLR_RXSTPIC (_U_(0x1) << USBC_UESTA1CLR_RXSTPIC_Pos) 1571 #define USBC_UESTA1CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA1CLR) NAKOUTI Clear */ 1572 #define USBC_UESTA1CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA1CLR_NAKOUTIC_Pos) 1573 #define USBC_UESTA1CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA1CLR) NAKINI Clear */ 1574 #define USBC_UESTA1CLR_NAKINIC (_U_(0x1) << USBC_UESTA1CLR_NAKINIC_Pos) 1575 #define USBC_UESTA1CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA1CLR) STALLEDI Clear */ 1576 #define USBC_UESTA1CLR_STALLEDIC (_U_(0x1) << USBC_UESTA1CLR_STALLEDIC_Pos) 1577 #define USBC_UESTA1CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA1CLR) RAMACERI Clear */ 1578 #define USBC_UESTA1CLR_RAMACERIC (_U_(0x1) << USBC_UESTA1CLR_RAMACERIC_Pos) 1579 #define USBC_UESTA1CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA1CLR) MASK Register */ 1580 1581 /* -------- USBC_UESTA2CLR : (USBC Offset: 0x168) ( /W 32) Endpoint Status Clear Register -------- */ 1582 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1583 typedef union { 1584 struct { 1585 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1586 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1587 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1588 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1589 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1590 uint32_t :1; /*!< bit: 5 Reserved */ 1591 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1592 uint32_t :4; /*!< bit: 7..10 Reserved */ 1593 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1594 uint32_t :20; /*!< bit: 12..31 Reserved */ 1595 } bit; /*!< Structure used for bit access */ 1596 uint32_t reg; /*!< Type used for register access */ 1597 } USBC_UESTA2CLR_Type; 1598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1599 1600 #define USBC_UESTA2CLR_OFFSET 0x168 /**< \brief (USBC_UESTA2CLR offset) Endpoint Status Clear Register */ 1601 #define USBC_UESTA2CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA2CLR reset_value) Endpoint Status Clear Register */ 1602 1603 #define USBC_UESTA2CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA2CLR) TXINI Clear */ 1604 #define USBC_UESTA2CLR_TXINIC (_U_(0x1) << USBC_UESTA2CLR_TXINIC_Pos) 1605 #define USBC_UESTA2CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA2CLR) RXOUTI Clear */ 1606 #define USBC_UESTA2CLR_RXOUTIC (_U_(0x1) << USBC_UESTA2CLR_RXOUTIC_Pos) 1607 #define USBC_UESTA2CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA2CLR) RXSTPI Clear */ 1608 #define USBC_UESTA2CLR_RXSTPIC (_U_(0x1) << USBC_UESTA2CLR_RXSTPIC_Pos) 1609 #define USBC_UESTA2CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA2CLR) NAKOUTI Clear */ 1610 #define USBC_UESTA2CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA2CLR_NAKOUTIC_Pos) 1611 #define USBC_UESTA2CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA2CLR) NAKINI Clear */ 1612 #define USBC_UESTA2CLR_NAKINIC (_U_(0x1) << USBC_UESTA2CLR_NAKINIC_Pos) 1613 #define USBC_UESTA2CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA2CLR) STALLEDI Clear */ 1614 #define USBC_UESTA2CLR_STALLEDIC (_U_(0x1) << USBC_UESTA2CLR_STALLEDIC_Pos) 1615 #define USBC_UESTA2CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA2CLR) RAMACERI Clear */ 1616 #define USBC_UESTA2CLR_RAMACERIC (_U_(0x1) << USBC_UESTA2CLR_RAMACERIC_Pos) 1617 #define USBC_UESTA2CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA2CLR) MASK Register */ 1618 1619 /* -------- USBC_UESTA3CLR : (USBC Offset: 0x16C) ( /W 32) Endpoint Status Clear Register -------- */ 1620 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1621 typedef union { 1622 struct { 1623 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1624 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1625 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1626 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1627 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1628 uint32_t :1; /*!< bit: 5 Reserved */ 1629 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1630 uint32_t :4; /*!< bit: 7..10 Reserved */ 1631 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1632 uint32_t :20; /*!< bit: 12..31 Reserved */ 1633 } bit; /*!< Structure used for bit access */ 1634 uint32_t reg; /*!< Type used for register access */ 1635 } USBC_UESTA3CLR_Type; 1636 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1637 1638 #define USBC_UESTA3CLR_OFFSET 0x16C /**< \brief (USBC_UESTA3CLR offset) Endpoint Status Clear Register */ 1639 #define USBC_UESTA3CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA3CLR reset_value) Endpoint Status Clear Register */ 1640 1641 #define USBC_UESTA3CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA3CLR) TXINI Clear */ 1642 #define USBC_UESTA3CLR_TXINIC (_U_(0x1) << USBC_UESTA3CLR_TXINIC_Pos) 1643 #define USBC_UESTA3CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA3CLR) RXOUTI Clear */ 1644 #define USBC_UESTA3CLR_RXOUTIC (_U_(0x1) << USBC_UESTA3CLR_RXOUTIC_Pos) 1645 #define USBC_UESTA3CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA3CLR) RXSTPI Clear */ 1646 #define USBC_UESTA3CLR_RXSTPIC (_U_(0x1) << USBC_UESTA3CLR_RXSTPIC_Pos) 1647 #define USBC_UESTA3CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA3CLR) NAKOUTI Clear */ 1648 #define USBC_UESTA3CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA3CLR_NAKOUTIC_Pos) 1649 #define USBC_UESTA3CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA3CLR) NAKINI Clear */ 1650 #define USBC_UESTA3CLR_NAKINIC (_U_(0x1) << USBC_UESTA3CLR_NAKINIC_Pos) 1651 #define USBC_UESTA3CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA3CLR) STALLEDI Clear */ 1652 #define USBC_UESTA3CLR_STALLEDIC (_U_(0x1) << USBC_UESTA3CLR_STALLEDIC_Pos) 1653 #define USBC_UESTA3CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA3CLR) RAMACERI Clear */ 1654 #define USBC_UESTA3CLR_RAMACERIC (_U_(0x1) << USBC_UESTA3CLR_RAMACERIC_Pos) 1655 #define USBC_UESTA3CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA3CLR) MASK Register */ 1656 1657 /* -------- USBC_UESTA4CLR : (USBC Offset: 0x170) ( /W 32) Endpoint Status Clear Register -------- */ 1658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1659 typedef union { 1660 struct { 1661 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1662 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1663 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1664 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1665 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1666 uint32_t :1; /*!< bit: 5 Reserved */ 1667 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1668 uint32_t :4; /*!< bit: 7..10 Reserved */ 1669 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1670 uint32_t :20; /*!< bit: 12..31 Reserved */ 1671 } bit; /*!< Structure used for bit access */ 1672 uint32_t reg; /*!< Type used for register access */ 1673 } USBC_UESTA4CLR_Type; 1674 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1675 1676 #define USBC_UESTA4CLR_OFFSET 0x170 /**< \brief (USBC_UESTA4CLR offset) Endpoint Status Clear Register */ 1677 #define USBC_UESTA4CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA4CLR reset_value) Endpoint Status Clear Register */ 1678 1679 #define USBC_UESTA4CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA4CLR) TXINI Clear */ 1680 #define USBC_UESTA4CLR_TXINIC (_U_(0x1) << USBC_UESTA4CLR_TXINIC_Pos) 1681 #define USBC_UESTA4CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA4CLR) RXOUTI Clear */ 1682 #define USBC_UESTA4CLR_RXOUTIC (_U_(0x1) << USBC_UESTA4CLR_RXOUTIC_Pos) 1683 #define USBC_UESTA4CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA4CLR) RXSTPI Clear */ 1684 #define USBC_UESTA4CLR_RXSTPIC (_U_(0x1) << USBC_UESTA4CLR_RXSTPIC_Pos) 1685 #define USBC_UESTA4CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA4CLR) NAKOUTI Clear */ 1686 #define USBC_UESTA4CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA4CLR_NAKOUTIC_Pos) 1687 #define USBC_UESTA4CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA4CLR) NAKINI Clear */ 1688 #define USBC_UESTA4CLR_NAKINIC (_U_(0x1) << USBC_UESTA4CLR_NAKINIC_Pos) 1689 #define USBC_UESTA4CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA4CLR) STALLEDI Clear */ 1690 #define USBC_UESTA4CLR_STALLEDIC (_U_(0x1) << USBC_UESTA4CLR_STALLEDIC_Pos) 1691 #define USBC_UESTA4CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA4CLR) RAMACERI Clear */ 1692 #define USBC_UESTA4CLR_RAMACERIC (_U_(0x1) << USBC_UESTA4CLR_RAMACERIC_Pos) 1693 #define USBC_UESTA4CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA4CLR) MASK Register */ 1694 1695 /* -------- USBC_UESTA5CLR : (USBC Offset: 0x174) ( /W 32) Endpoint Status Clear Register -------- */ 1696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1697 typedef union { 1698 struct { 1699 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1700 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1701 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1702 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1703 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1704 uint32_t :1; /*!< bit: 5 Reserved */ 1705 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1706 uint32_t :4; /*!< bit: 7..10 Reserved */ 1707 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1708 uint32_t :20; /*!< bit: 12..31 Reserved */ 1709 } bit; /*!< Structure used for bit access */ 1710 uint32_t reg; /*!< Type used for register access */ 1711 } USBC_UESTA5CLR_Type; 1712 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1713 1714 #define USBC_UESTA5CLR_OFFSET 0x174 /**< \brief (USBC_UESTA5CLR offset) Endpoint Status Clear Register */ 1715 #define USBC_UESTA5CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA5CLR reset_value) Endpoint Status Clear Register */ 1716 1717 #define USBC_UESTA5CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA5CLR) TXINI Clear */ 1718 #define USBC_UESTA5CLR_TXINIC (_U_(0x1) << USBC_UESTA5CLR_TXINIC_Pos) 1719 #define USBC_UESTA5CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA5CLR) RXOUTI Clear */ 1720 #define USBC_UESTA5CLR_RXOUTIC (_U_(0x1) << USBC_UESTA5CLR_RXOUTIC_Pos) 1721 #define USBC_UESTA5CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA5CLR) RXSTPI Clear */ 1722 #define USBC_UESTA5CLR_RXSTPIC (_U_(0x1) << USBC_UESTA5CLR_RXSTPIC_Pos) 1723 #define USBC_UESTA5CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA5CLR) NAKOUTI Clear */ 1724 #define USBC_UESTA5CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA5CLR_NAKOUTIC_Pos) 1725 #define USBC_UESTA5CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA5CLR) NAKINI Clear */ 1726 #define USBC_UESTA5CLR_NAKINIC (_U_(0x1) << USBC_UESTA5CLR_NAKINIC_Pos) 1727 #define USBC_UESTA5CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA5CLR) STALLEDI Clear */ 1728 #define USBC_UESTA5CLR_STALLEDIC (_U_(0x1) << USBC_UESTA5CLR_STALLEDIC_Pos) 1729 #define USBC_UESTA5CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA5CLR) RAMACERI Clear */ 1730 #define USBC_UESTA5CLR_RAMACERIC (_U_(0x1) << USBC_UESTA5CLR_RAMACERIC_Pos) 1731 #define USBC_UESTA5CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA5CLR) MASK Register */ 1732 1733 /* -------- USBC_UESTA6CLR : (USBC Offset: 0x178) ( /W 32) Endpoint Status Clear Register -------- */ 1734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1735 typedef union { 1736 struct { 1737 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1738 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1739 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1740 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1741 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1742 uint32_t :1; /*!< bit: 5 Reserved */ 1743 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1744 uint32_t :4; /*!< bit: 7..10 Reserved */ 1745 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1746 uint32_t :20; /*!< bit: 12..31 Reserved */ 1747 } bit; /*!< Structure used for bit access */ 1748 uint32_t reg; /*!< Type used for register access */ 1749 } USBC_UESTA6CLR_Type; 1750 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1751 1752 #define USBC_UESTA6CLR_OFFSET 0x178 /**< \brief (USBC_UESTA6CLR offset) Endpoint Status Clear Register */ 1753 #define USBC_UESTA6CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA6CLR reset_value) Endpoint Status Clear Register */ 1754 1755 #define USBC_UESTA6CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA6CLR) TXINI Clear */ 1756 #define USBC_UESTA6CLR_TXINIC (_U_(0x1) << USBC_UESTA6CLR_TXINIC_Pos) 1757 #define USBC_UESTA6CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA6CLR) RXOUTI Clear */ 1758 #define USBC_UESTA6CLR_RXOUTIC (_U_(0x1) << USBC_UESTA6CLR_RXOUTIC_Pos) 1759 #define USBC_UESTA6CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA6CLR) RXSTPI Clear */ 1760 #define USBC_UESTA6CLR_RXSTPIC (_U_(0x1) << USBC_UESTA6CLR_RXSTPIC_Pos) 1761 #define USBC_UESTA6CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA6CLR) NAKOUTI Clear */ 1762 #define USBC_UESTA6CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA6CLR_NAKOUTIC_Pos) 1763 #define USBC_UESTA6CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA6CLR) NAKINI Clear */ 1764 #define USBC_UESTA6CLR_NAKINIC (_U_(0x1) << USBC_UESTA6CLR_NAKINIC_Pos) 1765 #define USBC_UESTA6CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA6CLR) STALLEDI Clear */ 1766 #define USBC_UESTA6CLR_STALLEDIC (_U_(0x1) << USBC_UESTA6CLR_STALLEDIC_Pos) 1767 #define USBC_UESTA6CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA6CLR) RAMACERI Clear */ 1768 #define USBC_UESTA6CLR_RAMACERIC (_U_(0x1) << USBC_UESTA6CLR_RAMACERIC_Pos) 1769 #define USBC_UESTA6CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA6CLR) MASK Register */ 1770 1771 /* -------- USBC_UESTA7CLR : (USBC Offset: 0x17C) ( /W 32) Endpoint Status Clear Register -------- */ 1772 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1773 typedef union { 1774 struct { 1775 uint32_t TXINIC:1; /*!< bit: 0 TXINI Clear */ 1776 uint32_t RXOUTIC:1; /*!< bit: 1 RXOUTI Clear */ 1777 uint32_t RXSTPIC:1; /*!< bit: 2 RXSTPI Clear */ 1778 uint32_t NAKOUTIC:1; /*!< bit: 3 NAKOUTI Clear */ 1779 uint32_t NAKINIC:1; /*!< bit: 4 NAKINI Clear */ 1780 uint32_t :1; /*!< bit: 5 Reserved */ 1781 uint32_t STALLEDIC:1; /*!< bit: 6 STALLEDI Clear */ 1782 uint32_t :4; /*!< bit: 7..10 Reserved */ 1783 uint32_t RAMACERIC:1; /*!< bit: 11 RAMACERI Clear */ 1784 uint32_t :20; /*!< bit: 12..31 Reserved */ 1785 } bit; /*!< Structure used for bit access */ 1786 uint32_t reg; /*!< Type used for register access */ 1787 } USBC_UESTA7CLR_Type; 1788 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1789 1790 #define USBC_UESTA7CLR_OFFSET 0x17C /**< \brief (USBC_UESTA7CLR offset) Endpoint Status Clear Register */ 1791 #define USBC_UESTA7CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA7CLR reset_value) Endpoint Status Clear Register */ 1792 1793 #define USBC_UESTA7CLR_TXINIC_Pos 0 /**< \brief (USBC_UESTA7CLR) TXINI Clear */ 1794 #define USBC_UESTA7CLR_TXINIC (_U_(0x1) << USBC_UESTA7CLR_TXINIC_Pos) 1795 #define USBC_UESTA7CLR_RXOUTIC_Pos 1 /**< \brief (USBC_UESTA7CLR) RXOUTI Clear */ 1796 #define USBC_UESTA7CLR_RXOUTIC (_U_(0x1) << USBC_UESTA7CLR_RXOUTIC_Pos) 1797 #define USBC_UESTA7CLR_RXSTPIC_Pos 2 /**< \brief (USBC_UESTA7CLR) RXSTPI Clear */ 1798 #define USBC_UESTA7CLR_RXSTPIC (_U_(0x1) << USBC_UESTA7CLR_RXSTPIC_Pos) 1799 #define USBC_UESTA7CLR_NAKOUTIC_Pos 3 /**< \brief (USBC_UESTA7CLR) NAKOUTI Clear */ 1800 #define USBC_UESTA7CLR_NAKOUTIC (_U_(0x1) << USBC_UESTA7CLR_NAKOUTIC_Pos) 1801 #define USBC_UESTA7CLR_NAKINIC_Pos 4 /**< \brief (USBC_UESTA7CLR) NAKINI Clear */ 1802 #define USBC_UESTA7CLR_NAKINIC (_U_(0x1) << USBC_UESTA7CLR_NAKINIC_Pos) 1803 #define USBC_UESTA7CLR_STALLEDIC_Pos 6 /**< \brief (USBC_UESTA7CLR) STALLEDI Clear */ 1804 #define USBC_UESTA7CLR_STALLEDIC (_U_(0x1) << USBC_UESTA7CLR_STALLEDIC_Pos) 1805 #define USBC_UESTA7CLR_RAMACERIC_Pos 11 /**< \brief (USBC_UESTA7CLR) RAMACERI Clear */ 1806 #define USBC_UESTA7CLR_RAMACERIC (_U_(0x1) << USBC_UESTA7CLR_RAMACERIC_Pos) 1807 #define USBC_UESTA7CLR_MASK _U_(0x0000085F) /**< \brief (USBC_UESTA7CLR) MASK Register */ 1808 1809 /* -------- USBC_UESTA0SET : (USBC Offset: 0x190) ( /W 32) Endpoint Status Set Register -------- */ 1810 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1811 typedef union { 1812 struct { 1813 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 1814 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 1815 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 1816 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 1817 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 1818 uint32_t :1; /*!< bit: 5 Reserved */ 1819 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 1820 uint32_t :4; /*!< bit: 7..10 Reserved */ 1821 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 1822 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 1823 uint32_t :19; /*!< bit: 13..31 Reserved */ 1824 } bit; /*!< Structure used for bit access */ 1825 uint32_t reg; /*!< Type used for register access */ 1826 } USBC_UESTA0SET_Type; 1827 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1828 1829 #define USBC_UESTA0SET_OFFSET 0x190 /**< \brief (USBC_UESTA0SET offset) Endpoint Status Set Register */ 1830 #define USBC_UESTA0SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA0SET reset_value) Endpoint Status Set Register */ 1831 1832 #define USBC_UESTA0SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA0SET) TXINI Set */ 1833 #define USBC_UESTA0SET_TXINIS (_U_(0x1) << USBC_UESTA0SET_TXINIS_Pos) 1834 #define USBC_UESTA0SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA0SET) RXOUTI Set */ 1835 #define USBC_UESTA0SET_RXOUTIS (_U_(0x1) << USBC_UESTA0SET_RXOUTIS_Pos) 1836 #define USBC_UESTA0SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA0SET) RXSTPI Set */ 1837 #define USBC_UESTA0SET_RXSTPIS (_U_(0x1) << USBC_UESTA0SET_RXSTPIS_Pos) 1838 #define USBC_UESTA0SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA0SET) NAKOUTI Set */ 1839 #define USBC_UESTA0SET_NAKOUTIS (_U_(0x1) << USBC_UESTA0SET_NAKOUTIS_Pos) 1840 #define USBC_UESTA0SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA0SET) NAKINI Set */ 1841 #define USBC_UESTA0SET_NAKINIS (_U_(0x1) << USBC_UESTA0SET_NAKINIS_Pos) 1842 #define USBC_UESTA0SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA0SET) STALLEDI Set */ 1843 #define USBC_UESTA0SET_STALLEDIS (_U_(0x1) << USBC_UESTA0SET_STALLEDIS_Pos) 1844 #define USBC_UESTA0SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA0SET) RAMACERI Set */ 1845 #define USBC_UESTA0SET_RAMACERIS (_U_(0x1) << USBC_UESTA0SET_RAMACERIS_Pos) 1846 #define USBC_UESTA0SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA0SET) NBUSYBK Set */ 1847 #define USBC_UESTA0SET_NBUSYBKS (_U_(0x1) << USBC_UESTA0SET_NBUSYBKS_Pos) 1848 #define USBC_UESTA0SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA0SET) MASK Register */ 1849 1850 /* -------- USBC_UESTA1SET : (USBC Offset: 0x194) ( /W 32) Endpoint Status Set Register -------- */ 1851 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1852 typedef union { 1853 struct { 1854 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 1855 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 1856 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 1857 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 1858 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 1859 uint32_t :1; /*!< bit: 5 Reserved */ 1860 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 1861 uint32_t :4; /*!< bit: 7..10 Reserved */ 1862 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 1863 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 1864 uint32_t :19; /*!< bit: 13..31 Reserved */ 1865 } bit; /*!< Structure used for bit access */ 1866 uint32_t reg; /*!< Type used for register access */ 1867 } USBC_UESTA1SET_Type; 1868 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1869 1870 #define USBC_UESTA1SET_OFFSET 0x194 /**< \brief (USBC_UESTA1SET offset) Endpoint Status Set Register */ 1871 #define USBC_UESTA1SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA1SET reset_value) Endpoint Status Set Register */ 1872 1873 #define USBC_UESTA1SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA1SET) TXINI Set */ 1874 #define USBC_UESTA1SET_TXINIS (_U_(0x1) << USBC_UESTA1SET_TXINIS_Pos) 1875 #define USBC_UESTA1SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA1SET) RXOUTI Set */ 1876 #define USBC_UESTA1SET_RXOUTIS (_U_(0x1) << USBC_UESTA1SET_RXOUTIS_Pos) 1877 #define USBC_UESTA1SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA1SET) RXSTPI Set */ 1878 #define USBC_UESTA1SET_RXSTPIS (_U_(0x1) << USBC_UESTA1SET_RXSTPIS_Pos) 1879 #define USBC_UESTA1SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA1SET) NAKOUTI Set */ 1880 #define USBC_UESTA1SET_NAKOUTIS (_U_(0x1) << USBC_UESTA1SET_NAKOUTIS_Pos) 1881 #define USBC_UESTA1SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA1SET) NAKINI Set */ 1882 #define USBC_UESTA1SET_NAKINIS (_U_(0x1) << USBC_UESTA1SET_NAKINIS_Pos) 1883 #define USBC_UESTA1SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA1SET) STALLEDI Set */ 1884 #define USBC_UESTA1SET_STALLEDIS (_U_(0x1) << USBC_UESTA1SET_STALLEDIS_Pos) 1885 #define USBC_UESTA1SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA1SET) RAMACERI Set */ 1886 #define USBC_UESTA1SET_RAMACERIS (_U_(0x1) << USBC_UESTA1SET_RAMACERIS_Pos) 1887 #define USBC_UESTA1SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA1SET) NBUSYBK Set */ 1888 #define USBC_UESTA1SET_NBUSYBKS (_U_(0x1) << USBC_UESTA1SET_NBUSYBKS_Pos) 1889 #define USBC_UESTA1SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA1SET) MASK Register */ 1890 1891 /* -------- USBC_UESTA2SET : (USBC Offset: 0x198) ( /W 32) Endpoint Status Set Register -------- */ 1892 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1893 typedef union { 1894 struct { 1895 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 1896 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 1897 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 1898 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 1899 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 1900 uint32_t :1; /*!< bit: 5 Reserved */ 1901 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 1902 uint32_t :4; /*!< bit: 7..10 Reserved */ 1903 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 1904 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 1905 uint32_t :19; /*!< bit: 13..31 Reserved */ 1906 } bit; /*!< Structure used for bit access */ 1907 uint32_t reg; /*!< Type used for register access */ 1908 } USBC_UESTA2SET_Type; 1909 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1910 1911 #define USBC_UESTA2SET_OFFSET 0x198 /**< \brief (USBC_UESTA2SET offset) Endpoint Status Set Register */ 1912 #define USBC_UESTA2SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA2SET reset_value) Endpoint Status Set Register */ 1913 1914 #define USBC_UESTA2SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA2SET) TXINI Set */ 1915 #define USBC_UESTA2SET_TXINIS (_U_(0x1) << USBC_UESTA2SET_TXINIS_Pos) 1916 #define USBC_UESTA2SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA2SET) RXOUTI Set */ 1917 #define USBC_UESTA2SET_RXOUTIS (_U_(0x1) << USBC_UESTA2SET_RXOUTIS_Pos) 1918 #define USBC_UESTA2SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA2SET) RXSTPI Set */ 1919 #define USBC_UESTA2SET_RXSTPIS (_U_(0x1) << USBC_UESTA2SET_RXSTPIS_Pos) 1920 #define USBC_UESTA2SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA2SET) NAKOUTI Set */ 1921 #define USBC_UESTA2SET_NAKOUTIS (_U_(0x1) << USBC_UESTA2SET_NAKOUTIS_Pos) 1922 #define USBC_UESTA2SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA2SET) NAKINI Set */ 1923 #define USBC_UESTA2SET_NAKINIS (_U_(0x1) << USBC_UESTA2SET_NAKINIS_Pos) 1924 #define USBC_UESTA2SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA2SET) STALLEDI Set */ 1925 #define USBC_UESTA2SET_STALLEDIS (_U_(0x1) << USBC_UESTA2SET_STALLEDIS_Pos) 1926 #define USBC_UESTA2SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA2SET) RAMACERI Set */ 1927 #define USBC_UESTA2SET_RAMACERIS (_U_(0x1) << USBC_UESTA2SET_RAMACERIS_Pos) 1928 #define USBC_UESTA2SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA2SET) NBUSYBK Set */ 1929 #define USBC_UESTA2SET_NBUSYBKS (_U_(0x1) << USBC_UESTA2SET_NBUSYBKS_Pos) 1930 #define USBC_UESTA2SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA2SET) MASK Register */ 1931 1932 /* -------- USBC_UESTA3SET : (USBC Offset: 0x19C) ( /W 32) Endpoint Status Set Register -------- */ 1933 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1934 typedef union { 1935 struct { 1936 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 1937 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 1938 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 1939 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 1940 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 1941 uint32_t :1; /*!< bit: 5 Reserved */ 1942 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 1943 uint32_t :4; /*!< bit: 7..10 Reserved */ 1944 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 1945 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 1946 uint32_t :19; /*!< bit: 13..31 Reserved */ 1947 } bit; /*!< Structure used for bit access */ 1948 uint32_t reg; /*!< Type used for register access */ 1949 } USBC_UESTA3SET_Type; 1950 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1951 1952 #define USBC_UESTA3SET_OFFSET 0x19C /**< \brief (USBC_UESTA3SET offset) Endpoint Status Set Register */ 1953 #define USBC_UESTA3SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA3SET reset_value) Endpoint Status Set Register */ 1954 1955 #define USBC_UESTA3SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA3SET) TXINI Set */ 1956 #define USBC_UESTA3SET_TXINIS (_U_(0x1) << USBC_UESTA3SET_TXINIS_Pos) 1957 #define USBC_UESTA3SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA3SET) RXOUTI Set */ 1958 #define USBC_UESTA3SET_RXOUTIS (_U_(0x1) << USBC_UESTA3SET_RXOUTIS_Pos) 1959 #define USBC_UESTA3SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA3SET) RXSTPI Set */ 1960 #define USBC_UESTA3SET_RXSTPIS (_U_(0x1) << USBC_UESTA3SET_RXSTPIS_Pos) 1961 #define USBC_UESTA3SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA3SET) NAKOUTI Set */ 1962 #define USBC_UESTA3SET_NAKOUTIS (_U_(0x1) << USBC_UESTA3SET_NAKOUTIS_Pos) 1963 #define USBC_UESTA3SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA3SET) NAKINI Set */ 1964 #define USBC_UESTA3SET_NAKINIS (_U_(0x1) << USBC_UESTA3SET_NAKINIS_Pos) 1965 #define USBC_UESTA3SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA3SET) STALLEDI Set */ 1966 #define USBC_UESTA3SET_STALLEDIS (_U_(0x1) << USBC_UESTA3SET_STALLEDIS_Pos) 1967 #define USBC_UESTA3SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA3SET) RAMACERI Set */ 1968 #define USBC_UESTA3SET_RAMACERIS (_U_(0x1) << USBC_UESTA3SET_RAMACERIS_Pos) 1969 #define USBC_UESTA3SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA3SET) NBUSYBK Set */ 1970 #define USBC_UESTA3SET_NBUSYBKS (_U_(0x1) << USBC_UESTA3SET_NBUSYBKS_Pos) 1971 #define USBC_UESTA3SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA3SET) MASK Register */ 1972 1973 /* -------- USBC_UESTA4SET : (USBC Offset: 0x1A0) ( /W 32) Endpoint Status Set Register -------- */ 1974 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1975 typedef union { 1976 struct { 1977 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 1978 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 1979 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 1980 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 1981 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 1982 uint32_t :1; /*!< bit: 5 Reserved */ 1983 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 1984 uint32_t :4; /*!< bit: 7..10 Reserved */ 1985 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 1986 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 1987 uint32_t :19; /*!< bit: 13..31 Reserved */ 1988 } bit; /*!< Structure used for bit access */ 1989 uint32_t reg; /*!< Type used for register access */ 1990 } USBC_UESTA4SET_Type; 1991 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1992 1993 #define USBC_UESTA4SET_OFFSET 0x1A0 /**< \brief (USBC_UESTA4SET offset) Endpoint Status Set Register */ 1994 #define USBC_UESTA4SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA4SET reset_value) Endpoint Status Set Register */ 1995 1996 #define USBC_UESTA4SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA4SET) TXINI Set */ 1997 #define USBC_UESTA4SET_TXINIS (_U_(0x1) << USBC_UESTA4SET_TXINIS_Pos) 1998 #define USBC_UESTA4SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA4SET) RXOUTI Set */ 1999 #define USBC_UESTA4SET_RXOUTIS (_U_(0x1) << USBC_UESTA4SET_RXOUTIS_Pos) 2000 #define USBC_UESTA4SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA4SET) RXSTPI Set */ 2001 #define USBC_UESTA4SET_RXSTPIS (_U_(0x1) << USBC_UESTA4SET_RXSTPIS_Pos) 2002 #define USBC_UESTA4SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA4SET) NAKOUTI Set */ 2003 #define USBC_UESTA4SET_NAKOUTIS (_U_(0x1) << USBC_UESTA4SET_NAKOUTIS_Pos) 2004 #define USBC_UESTA4SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA4SET) NAKINI Set */ 2005 #define USBC_UESTA4SET_NAKINIS (_U_(0x1) << USBC_UESTA4SET_NAKINIS_Pos) 2006 #define USBC_UESTA4SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA4SET) STALLEDI Set */ 2007 #define USBC_UESTA4SET_STALLEDIS (_U_(0x1) << USBC_UESTA4SET_STALLEDIS_Pos) 2008 #define USBC_UESTA4SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA4SET) RAMACERI Set */ 2009 #define USBC_UESTA4SET_RAMACERIS (_U_(0x1) << USBC_UESTA4SET_RAMACERIS_Pos) 2010 #define USBC_UESTA4SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA4SET) NBUSYBK Set */ 2011 #define USBC_UESTA4SET_NBUSYBKS (_U_(0x1) << USBC_UESTA4SET_NBUSYBKS_Pos) 2012 #define USBC_UESTA4SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA4SET) MASK Register */ 2013 2014 /* -------- USBC_UESTA5SET : (USBC Offset: 0x1A4) ( /W 32) Endpoint Status Set Register -------- */ 2015 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2016 typedef union { 2017 struct { 2018 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 2019 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 2020 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 2021 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 2022 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 2023 uint32_t :1; /*!< bit: 5 Reserved */ 2024 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 2025 uint32_t :4; /*!< bit: 7..10 Reserved */ 2026 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 2027 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 2028 uint32_t :19; /*!< bit: 13..31 Reserved */ 2029 } bit; /*!< Structure used for bit access */ 2030 uint32_t reg; /*!< Type used for register access */ 2031 } USBC_UESTA5SET_Type; 2032 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2033 2034 #define USBC_UESTA5SET_OFFSET 0x1A4 /**< \brief (USBC_UESTA5SET offset) Endpoint Status Set Register */ 2035 #define USBC_UESTA5SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA5SET reset_value) Endpoint Status Set Register */ 2036 2037 #define USBC_UESTA5SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA5SET) TXINI Set */ 2038 #define USBC_UESTA5SET_TXINIS (_U_(0x1) << USBC_UESTA5SET_TXINIS_Pos) 2039 #define USBC_UESTA5SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA5SET) RXOUTI Set */ 2040 #define USBC_UESTA5SET_RXOUTIS (_U_(0x1) << USBC_UESTA5SET_RXOUTIS_Pos) 2041 #define USBC_UESTA5SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA5SET) RXSTPI Set */ 2042 #define USBC_UESTA5SET_RXSTPIS (_U_(0x1) << USBC_UESTA5SET_RXSTPIS_Pos) 2043 #define USBC_UESTA5SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA5SET) NAKOUTI Set */ 2044 #define USBC_UESTA5SET_NAKOUTIS (_U_(0x1) << USBC_UESTA5SET_NAKOUTIS_Pos) 2045 #define USBC_UESTA5SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA5SET) NAKINI Set */ 2046 #define USBC_UESTA5SET_NAKINIS (_U_(0x1) << USBC_UESTA5SET_NAKINIS_Pos) 2047 #define USBC_UESTA5SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA5SET) STALLEDI Set */ 2048 #define USBC_UESTA5SET_STALLEDIS (_U_(0x1) << USBC_UESTA5SET_STALLEDIS_Pos) 2049 #define USBC_UESTA5SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA5SET) RAMACERI Set */ 2050 #define USBC_UESTA5SET_RAMACERIS (_U_(0x1) << USBC_UESTA5SET_RAMACERIS_Pos) 2051 #define USBC_UESTA5SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA5SET) NBUSYBK Set */ 2052 #define USBC_UESTA5SET_NBUSYBKS (_U_(0x1) << USBC_UESTA5SET_NBUSYBKS_Pos) 2053 #define USBC_UESTA5SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA5SET) MASK Register */ 2054 2055 /* -------- USBC_UESTA6SET : (USBC Offset: 0x1A8) ( /W 32) Endpoint Status Set Register -------- */ 2056 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2057 typedef union { 2058 struct { 2059 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 2060 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 2061 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 2062 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 2063 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 2064 uint32_t :1; /*!< bit: 5 Reserved */ 2065 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 2066 uint32_t :4; /*!< bit: 7..10 Reserved */ 2067 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 2068 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 2069 uint32_t :19; /*!< bit: 13..31 Reserved */ 2070 } bit; /*!< Structure used for bit access */ 2071 uint32_t reg; /*!< Type used for register access */ 2072 } USBC_UESTA6SET_Type; 2073 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2074 2075 #define USBC_UESTA6SET_OFFSET 0x1A8 /**< \brief (USBC_UESTA6SET offset) Endpoint Status Set Register */ 2076 #define USBC_UESTA6SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA6SET reset_value) Endpoint Status Set Register */ 2077 2078 #define USBC_UESTA6SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA6SET) TXINI Set */ 2079 #define USBC_UESTA6SET_TXINIS (_U_(0x1) << USBC_UESTA6SET_TXINIS_Pos) 2080 #define USBC_UESTA6SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA6SET) RXOUTI Set */ 2081 #define USBC_UESTA6SET_RXOUTIS (_U_(0x1) << USBC_UESTA6SET_RXOUTIS_Pos) 2082 #define USBC_UESTA6SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA6SET) RXSTPI Set */ 2083 #define USBC_UESTA6SET_RXSTPIS (_U_(0x1) << USBC_UESTA6SET_RXSTPIS_Pos) 2084 #define USBC_UESTA6SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA6SET) NAKOUTI Set */ 2085 #define USBC_UESTA6SET_NAKOUTIS (_U_(0x1) << USBC_UESTA6SET_NAKOUTIS_Pos) 2086 #define USBC_UESTA6SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA6SET) NAKINI Set */ 2087 #define USBC_UESTA6SET_NAKINIS (_U_(0x1) << USBC_UESTA6SET_NAKINIS_Pos) 2088 #define USBC_UESTA6SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA6SET) STALLEDI Set */ 2089 #define USBC_UESTA6SET_STALLEDIS (_U_(0x1) << USBC_UESTA6SET_STALLEDIS_Pos) 2090 #define USBC_UESTA6SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA6SET) RAMACERI Set */ 2091 #define USBC_UESTA6SET_RAMACERIS (_U_(0x1) << USBC_UESTA6SET_RAMACERIS_Pos) 2092 #define USBC_UESTA6SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA6SET) NBUSYBK Set */ 2093 #define USBC_UESTA6SET_NBUSYBKS (_U_(0x1) << USBC_UESTA6SET_NBUSYBKS_Pos) 2094 #define USBC_UESTA6SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA6SET) MASK Register */ 2095 2096 /* -------- USBC_UESTA7SET : (USBC Offset: 0x1AC) ( /W 32) Endpoint Status Set Register -------- */ 2097 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2098 typedef union { 2099 struct { 2100 uint32_t TXINIS:1; /*!< bit: 0 TXINI Set */ 2101 uint32_t RXOUTIS:1; /*!< bit: 1 RXOUTI Set */ 2102 uint32_t RXSTPIS:1; /*!< bit: 2 RXSTPI Set */ 2103 uint32_t NAKOUTIS:1; /*!< bit: 3 NAKOUTI Set */ 2104 uint32_t NAKINIS:1; /*!< bit: 4 NAKINI Set */ 2105 uint32_t :1; /*!< bit: 5 Reserved */ 2106 uint32_t STALLEDIS:1; /*!< bit: 6 STALLEDI Set */ 2107 uint32_t :4; /*!< bit: 7..10 Reserved */ 2108 uint32_t RAMACERIS:1; /*!< bit: 11 RAMACERI Set */ 2109 uint32_t NBUSYBKS:1; /*!< bit: 12 NBUSYBK Set */ 2110 uint32_t :19; /*!< bit: 13..31 Reserved */ 2111 } bit; /*!< Structure used for bit access */ 2112 uint32_t reg; /*!< Type used for register access */ 2113 } USBC_UESTA7SET_Type; 2114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2115 2116 #define USBC_UESTA7SET_OFFSET 0x1AC /**< \brief (USBC_UESTA7SET offset) Endpoint Status Set Register */ 2117 #define USBC_UESTA7SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UESTA7SET reset_value) Endpoint Status Set Register */ 2118 2119 #define USBC_UESTA7SET_TXINIS_Pos 0 /**< \brief (USBC_UESTA7SET) TXINI Set */ 2120 #define USBC_UESTA7SET_TXINIS (_U_(0x1) << USBC_UESTA7SET_TXINIS_Pos) 2121 #define USBC_UESTA7SET_RXOUTIS_Pos 1 /**< \brief (USBC_UESTA7SET) RXOUTI Set */ 2122 #define USBC_UESTA7SET_RXOUTIS (_U_(0x1) << USBC_UESTA7SET_RXOUTIS_Pos) 2123 #define USBC_UESTA7SET_RXSTPIS_Pos 2 /**< \brief (USBC_UESTA7SET) RXSTPI Set */ 2124 #define USBC_UESTA7SET_RXSTPIS (_U_(0x1) << USBC_UESTA7SET_RXSTPIS_Pos) 2125 #define USBC_UESTA7SET_NAKOUTIS_Pos 3 /**< \brief (USBC_UESTA7SET) NAKOUTI Set */ 2126 #define USBC_UESTA7SET_NAKOUTIS (_U_(0x1) << USBC_UESTA7SET_NAKOUTIS_Pos) 2127 #define USBC_UESTA7SET_NAKINIS_Pos 4 /**< \brief (USBC_UESTA7SET) NAKINI Set */ 2128 #define USBC_UESTA7SET_NAKINIS (_U_(0x1) << USBC_UESTA7SET_NAKINIS_Pos) 2129 #define USBC_UESTA7SET_STALLEDIS_Pos 6 /**< \brief (USBC_UESTA7SET) STALLEDI Set */ 2130 #define USBC_UESTA7SET_STALLEDIS (_U_(0x1) << USBC_UESTA7SET_STALLEDIS_Pos) 2131 #define USBC_UESTA7SET_RAMACERIS_Pos 11 /**< \brief (USBC_UESTA7SET) RAMACERI Set */ 2132 #define USBC_UESTA7SET_RAMACERIS (_U_(0x1) << USBC_UESTA7SET_RAMACERIS_Pos) 2133 #define USBC_UESTA7SET_NBUSYBKS_Pos 12 /**< \brief (USBC_UESTA7SET) NBUSYBK Set */ 2134 #define USBC_UESTA7SET_NBUSYBKS (_U_(0x1) << USBC_UESTA7SET_NBUSYBKS_Pos) 2135 #define USBC_UESTA7SET_MASK _U_(0x0000185F) /**< \brief (USBC_UESTA7SET) MASK Register */ 2136 2137 /* -------- USBC_UECON0 : (USBC Offset: 0x1C0) (R/ 32) Endpoint Control Register -------- */ 2138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2139 typedef union { 2140 struct { 2141 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2142 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2143 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2144 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2145 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2146 uint32_t :1; /*!< bit: 5 Reserved */ 2147 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2148 uint32_t :1; /*!< bit: 7 Reserved */ 2149 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2150 uint32_t :2; /*!< bit: 9..10 Reserved */ 2151 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2152 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2153 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2154 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2155 uint32_t :2; /*!< bit: 15..16 Reserved */ 2156 uint32_t NYETDIS:1; /*!< bit: 17 NYET token disable */ 2157 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2158 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2159 uint32_t :4; /*!< bit: 20..23 Reserved */ 2160 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2161 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2162 uint32_t :6; /*!< bit: 26..31 Reserved */ 2163 } bit; /*!< Structure used for bit access */ 2164 uint32_t reg; /*!< Type used for register access */ 2165 } USBC_UECON0_Type; 2166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2167 2168 #define USBC_UECON0_OFFSET 0x1C0 /**< \brief (USBC_UECON0 offset) Endpoint Control Register */ 2169 #define USBC_UECON0_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON0 reset_value) Endpoint Control Register */ 2170 2171 #define USBC_UECON0_TXINE_Pos 0 /**< \brief (USBC_UECON0) TXIN Interrupt Enable */ 2172 #define USBC_UECON0_TXINE (_U_(0x1) << USBC_UECON0_TXINE_Pos) 2173 #define USBC_UECON0_RXOUTE_Pos 1 /**< \brief (USBC_UECON0) RXOUT Interrupt Enable */ 2174 #define USBC_UECON0_RXOUTE (_U_(0x1) << USBC_UECON0_RXOUTE_Pos) 2175 #define USBC_UECON0_RXSTPE_Pos 2 /**< \brief (USBC_UECON0) RXSTP Interrupt Enable */ 2176 #define USBC_UECON0_RXSTPE (_U_(0x1) << USBC_UECON0_RXSTPE_Pos) 2177 #define USBC_UECON0_NAKOUTE_Pos 3 /**< \brief (USBC_UECON0) NAKOUT Interrupt Enable */ 2178 #define USBC_UECON0_NAKOUTE (_U_(0x1) << USBC_UECON0_NAKOUTE_Pos) 2179 #define USBC_UECON0_NAKINE_Pos 4 /**< \brief (USBC_UECON0) NAKIN Interrupt Enable */ 2180 #define USBC_UECON0_NAKINE (_U_(0x1) << USBC_UECON0_NAKINE_Pos) 2181 #define USBC_UECON0_STALLEDE_Pos 6 /**< \brief (USBC_UECON0) STALLED Interrupt Enable */ 2182 #define USBC_UECON0_STALLEDE (_U_(0x1) << USBC_UECON0_STALLEDE_Pos) 2183 #define USBC_UECON0_NREPLY_Pos 8 /**< \brief (USBC_UECON0) No Reply */ 2184 #define USBC_UECON0_NREPLY (_U_(0x1) << USBC_UECON0_NREPLY_Pos) 2185 #define USBC_UECON0_RAMACERE_Pos 11 /**< \brief (USBC_UECON0) RAMACER Interrupt Enable */ 2186 #define USBC_UECON0_RAMACERE (_U_(0x1) << USBC_UECON0_RAMACERE_Pos) 2187 #define USBC_UECON0_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON0) Number of Busy Banks Interrupt Enable */ 2188 #define USBC_UECON0_NBUSYBKE (_U_(0x1) << USBC_UECON0_NBUSYBKE_Pos) 2189 #define USBC_UECON0_KILLBK_Pos 13 /**< \brief (USBC_UECON0) Kill IN Bank */ 2190 #define USBC_UECON0_KILLBK (_U_(0x1) << USBC_UECON0_KILLBK_Pos) 2191 #define USBC_UECON0_FIFOCON_Pos 14 /**< \brief (USBC_UECON0) FIFO Control */ 2192 #define USBC_UECON0_FIFOCON (_U_(0x1) << USBC_UECON0_FIFOCON_Pos) 2193 #define USBC_UECON0_NYETDIS_Pos 17 /**< \brief (USBC_UECON0) NYET token disable */ 2194 #define USBC_UECON0_NYETDIS (_U_(0x1) << USBC_UECON0_NYETDIS_Pos) 2195 #define USBC_UECON0_RSTDT_Pos 18 /**< \brief (USBC_UECON0) Reset Data Toggle */ 2196 #define USBC_UECON0_RSTDT (_U_(0x1) << USBC_UECON0_RSTDT_Pos) 2197 #define USBC_UECON0_STALLRQ_Pos 19 /**< \brief (USBC_UECON0) STALL Request */ 2198 #define USBC_UECON0_STALLRQ (_U_(0x1) << USBC_UECON0_STALLRQ_Pos) 2199 #define USBC_UECON0_BUSY0_Pos 24 /**< \brief (USBC_UECON0) Busy Bank1 Enable */ 2200 #define USBC_UECON0_BUSY0 (_U_(0x1) << USBC_UECON0_BUSY0_Pos) 2201 #define USBC_UECON0_BUSY1_Pos 25 /**< \brief (USBC_UECON0) Busy Bank0 Enable */ 2202 #define USBC_UECON0_BUSY1 (_U_(0x1) << USBC_UECON0_BUSY1_Pos) 2203 #define USBC_UECON0_MASK _U_(0x030E795F) /**< \brief (USBC_UECON0) MASK Register */ 2204 2205 /* -------- USBC_UECON1 : (USBC Offset: 0x1C4) (R/ 32) Endpoint Control Register -------- */ 2206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2207 typedef union { 2208 struct { 2209 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2210 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2211 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2212 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2213 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2214 uint32_t :1; /*!< bit: 5 Reserved */ 2215 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2216 uint32_t :1; /*!< bit: 7 Reserved */ 2217 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2218 uint32_t :2; /*!< bit: 9..10 Reserved */ 2219 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2220 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2221 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2222 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2223 uint32_t :2; /*!< bit: 15..16 Reserved */ 2224 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2225 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2226 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2227 uint32_t :4; /*!< bit: 20..23 Reserved */ 2228 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2229 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2230 uint32_t :6; /*!< bit: 26..31 Reserved */ 2231 } bit; /*!< Structure used for bit access */ 2232 uint32_t reg; /*!< Type used for register access */ 2233 } USBC_UECON1_Type; 2234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2235 2236 #define USBC_UECON1_OFFSET 0x1C4 /**< \brief (USBC_UECON1 offset) Endpoint Control Register */ 2237 #define USBC_UECON1_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON1 reset_value) Endpoint Control Register */ 2238 2239 #define USBC_UECON1_TXINE_Pos 0 /**< \brief (USBC_UECON1) TXIN Interrupt Enable */ 2240 #define USBC_UECON1_TXINE (_U_(0x1) << USBC_UECON1_TXINE_Pos) 2241 #define USBC_UECON1_RXOUTE_Pos 1 /**< \brief (USBC_UECON1) RXOUT Interrupt Enable */ 2242 #define USBC_UECON1_RXOUTE (_U_(0x1) << USBC_UECON1_RXOUTE_Pos) 2243 #define USBC_UECON1_RXSTPE_Pos 2 /**< \brief (USBC_UECON1) RXSTP Interrupt Enable */ 2244 #define USBC_UECON1_RXSTPE (_U_(0x1) << USBC_UECON1_RXSTPE_Pos) 2245 #define USBC_UECON1_NAKOUTE_Pos 3 /**< \brief (USBC_UECON1) NAKOUT Interrupt Enable */ 2246 #define USBC_UECON1_NAKOUTE (_U_(0x1) << USBC_UECON1_NAKOUTE_Pos) 2247 #define USBC_UECON1_NAKINE_Pos 4 /**< \brief (USBC_UECON1) NAKIN Interrupt Enable */ 2248 #define USBC_UECON1_NAKINE (_U_(0x1) << USBC_UECON1_NAKINE_Pos) 2249 #define USBC_UECON1_STALLEDE_Pos 6 /**< \brief (USBC_UECON1) STALLED Interrupt Enable */ 2250 #define USBC_UECON1_STALLEDE (_U_(0x1) << USBC_UECON1_STALLEDE_Pos) 2251 #define USBC_UECON1_NREPLY_Pos 8 /**< \brief (USBC_UECON1) No Reply */ 2252 #define USBC_UECON1_NREPLY (_U_(0x1) << USBC_UECON1_NREPLY_Pos) 2253 #define USBC_UECON1_RAMACERE_Pos 11 /**< \brief (USBC_UECON1) RAMACER Interrupt Enable */ 2254 #define USBC_UECON1_RAMACERE (_U_(0x1) << USBC_UECON1_RAMACERE_Pos) 2255 #define USBC_UECON1_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON1) Number of Busy Banks Interrupt Enable */ 2256 #define USBC_UECON1_NBUSYBKE (_U_(0x1) << USBC_UECON1_NBUSYBKE_Pos) 2257 #define USBC_UECON1_KILLBK_Pos 13 /**< \brief (USBC_UECON1) Kill IN Bank */ 2258 #define USBC_UECON1_KILLBK (_U_(0x1) << USBC_UECON1_KILLBK_Pos) 2259 #define USBC_UECON1_FIFOCON_Pos 14 /**< \brief (USBC_UECON1) FIFO Control */ 2260 #define USBC_UECON1_FIFOCON (_U_(0x1) << USBC_UECON1_FIFOCON_Pos) 2261 #define USBC_UECON1_NYETDIS_Pos 17 /**< \brief (USBC_UECON1) NYET Token Enable */ 2262 #define USBC_UECON1_NYETDIS (_U_(0x1) << USBC_UECON1_NYETDIS_Pos) 2263 #define USBC_UECON1_RSTDT_Pos 18 /**< \brief (USBC_UECON1) Reset Data Toggle */ 2264 #define USBC_UECON1_RSTDT (_U_(0x1) << USBC_UECON1_RSTDT_Pos) 2265 #define USBC_UECON1_STALLRQ_Pos 19 /**< \brief (USBC_UECON1) STALL Request */ 2266 #define USBC_UECON1_STALLRQ (_U_(0x1) << USBC_UECON1_STALLRQ_Pos) 2267 #define USBC_UECON1_BUSY0_Pos 24 /**< \brief (USBC_UECON1) Busy Bank1 Enable */ 2268 #define USBC_UECON1_BUSY0 (_U_(0x1) << USBC_UECON1_BUSY0_Pos) 2269 #define USBC_UECON1_BUSY1_Pos 25 /**< \brief (USBC_UECON1) Busy Bank0 Enable */ 2270 #define USBC_UECON1_BUSY1 (_U_(0x1) << USBC_UECON1_BUSY1_Pos) 2271 #define USBC_UECON1_MASK _U_(0x030E795F) /**< \brief (USBC_UECON1) MASK Register */ 2272 2273 /* -------- USBC_UECON2 : (USBC Offset: 0x1C8) (R/ 32) Endpoint Control Register -------- */ 2274 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2275 typedef union { 2276 struct { 2277 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2278 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2279 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2280 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2281 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2282 uint32_t :1; /*!< bit: 5 Reserved */ 2283 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2284 uint32_t :1; /*!< bit: 7 Reserved */ 2285 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2286 uint32_t :2; /*!< bit: 9..10 Reserved */ 2287 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2288 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2289 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2290 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2291 uint32_t :2; /*!< bit: 15..16 Reserved */ 2292 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2293 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2294 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2295 uint32_t :4; /*!< bit: 20..23 Reserved */ 2296 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2297 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2298 uint32_t :6; /*!< bit: 26..31 Reserved */ 2299 } bit; /*!< Structure used for bit access */ 2300 uint32_t reg; /*!< Type used for register access */ 2301 } USBC_UECON2_Type; 2302 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2303 2304 #define USBC_UECON2_OFFSET 0x1C8 /**< \brief (USBC_UECON2 offset) Endpoint Control Register */ 2305 #define USBC_UECON2_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON2 reset_value) Endpoint Control Register */ 2306 2307 #define USBC_UECON2_TXINE_Pos 0 /**< \brief (USBC_UECON2) TXIN Interrupt Enable */ 2308 #define USBC_UECON2_TXINE (_U_(0x1) << USBC_UECON2_TXINE_Pos) 2309 #define USBC_UECON2_RXOUTE_Pos 1 /**< \brief (USBC_UECON2) RXOUT Interrupt Enable */ 2310 #define USBC_UECON2_RXOUTE (_U_(0x1) << USBC_UECON2_RXOUTE_Pos) 2311 #define USBC_UECON2_RXSTPE_Pos 2 /**< \brief (USBC_UECON2) RXSTP Interrupt Enable */ 2312 #define USBC_UECON2_RXSTPE (_U_(0x1) << USBC_UECON2_RXSTPE_Pos) 2313 #define USBC_UECON2_NAKOUTE_Pos 3 /**< \brief (USBC_UECON2) NAKOUT Interrupt Enable */ 2314 #define USBC_UECON2_NAKOUTE (_U_(0x1) << USBC_UECON2_NAKOUTE_Pos) 2315 #define USBC_UECON2_NAKINE_Pos 4 /**< \brief (USBC_UECON2) NAKIN Interrupt Enable */ 2316 #define USBC_UECON2_NAKINE (_U_(0x1) << USBC_UECON2_NAKINE_Pos) 2317 #define USBC_UECON2_STALLEDE_Pos 6 /**< \brief (USBC_UECON2) STALLED Interrupt Enable */ 2318 #define USBC_UECON2_STALLEDE (_U_(0x1) << USBC_UECON2_STALLEDE_Pos) 2319 #define USBC_UECON2_NREPLY_Pos 8 /**< \brief (USBC_UECON2) No Reply */ 2320 #define USBC_UECON2_NREPLY (_U_(0x1) << USBC_UECON2_NREPLY_Pos) 2321 #define USBC_UECON2_RAMACERE_Pos 11 /**< \brief (USBC_UECON2) RAMACER Interrupt Enable */ 2322 #define USBC_UECON2_RAMACERE (_U_(0x1) << USBC_UECON2_RAMACERE_Pos) 2323 #define USBC_UECON2_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON2) Number of Busy Banks Interrupt Enable */ 2324 #define USBC_UECON2_NBUSYBKE (_U_(0x1) << USBC_UECON2_NBUSYBKE_Pos) 2325 #define USBC_UECON2_KILLBK_Pos 13 /**< \brief (USBC_UECON2) Kill IN Bank */ 2326 #define USBC_UECON2_KILLBK (_U_(0x1) << USBC_UECON2_KILLBK_Pos) 2327 #define USBC_UECON2_FIFOCON_Pos 14 /**< \brief (USBC_UECON2) FIFO Control */ 2328 #define USBC_UECON2_FIFOCON (_U_(0x1) << USBC_UECON2_FIFOCON_Pos) 2329 #define USBC_UECON2_NYETDIS_Pos 17 /**< \brief (USBC_UECON2) NYET Token Enable */ 2330 #define USBC_UECON2_NYETDIS (_U_(0x1) << USBC_UECON2_NYETDIS_Pos) 2331 #define USBC_UECON2_RSTDT_Pos 18 /**< \brief (USBC_UECON2) Reset Data Toggle */ 2332 #define USBC_UECON2_RSTDT (_U_(0x1) << USBC_UECON2_RSTDT_Pos) 2333 #define USBC_UECON2_STALLRQ_Pos 19 /**< \brief (USBC_UECON2) STALL Request */ 2334 #define USBC_UECON2_STALLRQ (_U_(0x1) << USBC_UECON2_STALLRQ_Pos) 2335 #define USBC_UECON2_BUSY0_Pos 24 /**< \brief (USBC_UECON2) Busy Bank1 Enable */ 2336 #define USBC_UECON2_BUSY0 (_U_(0x1) << USBC_UECON2_BUSY0_Pos) 2337 #define USBC_UECON2_BUSY1_Pos 25 /**< \brief (USBC_UECON2) Busy Bank0 Enable */ 2338 #define USBC_UECON2_BUSY1 (_U_(0x1) << USBC_UECON2_BUSY1_Pos) 2339 #define USBC_UECON2_MASK _U_(0x030E795F) /**< \brief (USBC_UECON2) MASK Register */ 2340 2341 /* -------- USBC_UECON3 : (USBC Offset: 0x1CC) (R/ 32) Endpoint Control Register -------- */ 2342 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2343 typedef union { 2344 struct { 2345 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2346 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2347 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2348 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2349 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2350 uint32_t :1; /*!< bit: 5 Reserved */ 2351 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2352 uint32_t :1; /*!< bit: 7 Reserved */ 2353 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2354 uint32_t :2; /*!< bit: 9..10 Reserved */ 2355 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2356 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2357 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2358 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2359 uint32_t :2; /*!< bit: 15..16 Reserved */ 2360 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2361 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2362 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2363 uint32_t :4; /*!< bit: 20..23 Reserved */ 2364 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2365 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2366 uint32_t :6; /*!< bit: 26..31 Reserved */ 2367 } bit; /*!< Structure used for bit access */ 2368 uint32_t reg; /*!< Type used for register access */ 2369 } USBC_UECON3_Type; 2370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2371 2372 #define USBC_UECON3_OFFSET 0x1CC /**< \brief (USBC_UECON3 offset) Endpoint Control Register */ 2373 #define USBC_UECON3_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON3 reset_value) Endpoint Control Register */ 2374 2375 #define USBC_UECON3_TXINE_Pos 0 /**< \brief (USBC_UECON3) TXIN Interrupt Enable */ 2376 #define USBC_UECON3_TXINE (_U_(0x1) << USBC_UECON3_TXINE_Pos) 2377 #define USBC_UECON3_RXOUTE_Pos 1 /**< \brief (USBC_UECON3) RXOUT Interrupt Enable */ 2378 #define USBC_UECON3_RXOUTE (_U_(0x1) << USBC_UECON3_RXOUTE_Pos) 2379 #define USBC_UECON3_RXSTPE_Pos 2 /**< \brief (USBC_UECON3) RXSTP Interrupt Enable */ 2380 #define USBC_UECON3_RXSTPE (_U_(0x1) << USBC_UECON3_RXSTPE_Pos) 2381 #define USBC_UECON3_NAKOUTE_Pos 3 /**< \brief (USBC_UECON3) NAKOUT Interrupt Enable */ 2382 #define USBC_UECON3_NAKOUTE (_U_(0x1) << USBC_UECON3_NAKOUTE_Pos) 2383 #define USBC_UECON3_NAKINE_Pos 4 /**< \brief (USBC_UECON3) NAKIN Interrupt Enable */ 2384 #define USBC_UECON3_NAKINE (_U_(0x1) << USBC_UECON3_NAKINE_Pos) 2385 #define USBC_UECON3_STALLEDE_Pos 6 /**< \brief (USBC_UECON3) STALLED Interrupt Enable */ 2386 #define USBC_UECON3_STALLEDE (_U_(0x1) << USBC_UECON3_STALLEDE_Pos) 2387 #define USBC_UECON3_NREPLY_Pos 8 /**< \brief (USBC_UECON3) No Reply */ 2388 #define USBC_UECON3_NREPLY (_U_(0x1) << USBC_UECON3_NREPLY_Pos) 2389 #define USBC_UECON3_RAMACERE_Pos 11 /**< \brief (USBC_UECON3) RAMACER Interrupt Enable */ 2390 #define USBC_UECON3_RAMACERE (_U_(0x1) << USBC_UECON3_RAMACERE_Pos) 2391 #define USBC_UECON3_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON3) Number of Busy Banks Interrupt Enable */ 2392 #define USBC_UECON3_NBUSYBKE (_U_(0x1) << USBC_UECON3_NBUSYBKE_Pos) 2393 #define USBC_UECON3_KILLBK_Pos 13 /**< \brief (USBC_UECON3) Kill IN Bank */ 2394 #define USBC_UECON3_KILLBK (_U_(0x1) << USBC_UECON3_KILLBK_Pos) 2395 #define USBC_UECON3_FIFOCON_Pos 14 /**< \brief (USBC_UECON3) FIFO Control */ 2396 #define USBC_UECON3_FIFOCON (_U_(0x1) << USBC_UECON3_FIFOCON_Pos) 2397 #define USBC_UECON3_NYETDIS_Pos 17 /**< \brief (USBC_UECON3) NYET Token Enable */ 2398 #define USBC_UECON3_NYETDIS (_U_(0x1) << USBC_UECON3_NYETDIS_Pos) 2399 #define USBC_UECON3_RSTDT_Pos 18 /**< \brief (USBC_UECON3) Reset Data Toggle */ 2400 #define USBC_UECON3_RSTDT (_U_(0x1) << USBC_UECON3_RSTDT_Pos) 2401 #define USBC_UECON3_STALLRQ_Pos 19 /**< \brief (USBC_UECON3) STALL Request */ 2402 #define USBC_UECON3_STALLRQ (_U_(0x1) << USBC_UECON3_STALLRQ_Pos) 2403 #define USBC_UECON3_BUSY0_Pos 24 /**< \brief (USBC_UECON3) Busy Bank1 Enable */ 2404 #define USBC_UECON3_BUSY0 (_U_(0x1) << USBC_UECON3_BUSY0_Pos) 2405 #define USBC_UECON3_BUSY1_Pos 25 /**< \brief (USBC_UECON3) Busy Bank0 Enable */ 2406 #define USBC_UECON3_BUSY1 (_U_(0x1) << USBC_UECON3_BUSY1_Pos) 2407 #define USBC_UECON3_MASK _U_(0x030E795F) /**< \brief (USBC_UECON3) MASK Register */ 2408 2409 /* -------- USBC_UECON4 : (USBC Offset: 0x1D0) (R/ 32) Endpoint Control Register -------- */ 2410 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2411 typedef union { 2412 struct { 2413 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2414 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2415 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2416 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2417 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2418 uint32_t :1; /*!< bit: 5 Reserved */ 2419 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2420 uint32_t :1; /*!< bit: 7 Reserved */ 2421 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2422 uint32_t :2; /*!< bit: 9..10 Reserved */ 2423 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2424 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2425 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2426 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2427 uint32_t :2; /*!< bit: 15..16 Reserved */ 2428 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2429 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2430 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2431 uint32_t :4; /*!< bit: 20..23 Reserved */ 2432 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2433 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2434 uint32_t :6; /*!< bit: 26..31 Reserved */ 2435 } bit; /*!< Structure used for bit access */ 2436 uint32_t reg; /*!< Type used for register access */ 2437 } USBC_UECON4_Type; 2438 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2439 2440 #define USBC_UECON4_OFFSET 0x1D0 /**< \brief (USBC_UECON4 offset) Endpoint Control Register */ 2441 #define USBC_UECON4_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON4 reset_value) Endpoint Control Register */ 2442 2443 #define USBC_UECON4_TXINE_Pos 0 /**< \brief (USBC_UECON4) TXIN Interrupt Enable */ 2444 #define USBC_UECON4_TXINE (_U_(0x1) << USBC_UECON4_TXINE_Pos) 2445 #define USBC_UECON4_RXOUTE_Pos 1 /**< \brief (USBC_UECON4) RXOUT Interrupt Enable */ 2446 #define USBC_UECON4_RXOUTE (_U_(0x1) << USBC_UECON4_RXOUTE_Pos) 2447 #define USBC_UECON4_RXSTPE_Pos 2 /**< \brief (USBC_UECON4) RXSTP Interrupt Enable */ 2448 #define USBC_UECON4_RXSTPE (_U_(0x1) << USBC_UECON4_RXSTPE_Pos) 2449 #define USBC_UECON4_NAKOUTE_Pos 3 /**< \brief (USBC_UECON4) NAKOUT Interrupt Enable */ 2450 #define USBC_UECON4_NAKOUTE (_U_(0x1) << USBC_UECON4_NAKOUTE_Pos) 2451 #define USBC_UECON4_NAKINE_Pos 4 /**< \brief (USBC_UECON4) NAKIN Interrupt Enable */ 2452 #define USBC_UECON4_NAKINE (_U_(0x1) << USBC_UECON4_NAKINE_Pos) 2453 #define USBC_UECON4_STALLEDE_Pos 6 /**< \brief (USBC_UECON4) STALLED Interrupt Enable */ 2454 #define USBC_UECON4_STALLEDE (_U_(0x1) << USBC_UECON4_STALLEDE_Pos) 2455 #define USBC_UECON4_NREPLY_Pos 8 /**< \brief (USBC_UECON4) No Reply */ 2456 #define USBC_UECON4_NREPLY (_U_(0x1) << USBC_UECON4_NREPLY_Pos) 2457 #define USBC_UECON4_RAMACERE_Pos 11 /**< \brief (USBC_UECON4) RAMACER Interrupt Enable */ 2458 #define USBC_UECON4_RAMACERE (_U_(0x1) << USBC_UECON4_RAMACERE_Pos) 2459 #define USBC_UECON4_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON4) Number of Busy Banks Interrupt Enable */ 2460 #define USBC_UECON4_NBUSYBKE (_U_(0x1) << USBC_UECON4_NBUSYBKE_Pos) 2461 #define USBC_UECON4_KILLBK_Pos 13 /**< \brief (USBC_UECON4) Kill IN Bank */ 2462 #define USBC_UECON4_KILLBK (_U_(0x1) << USBC_UECON4_KILLBK_Pos) 2463 #define USBC_UECON4_FIFOCON_Pos 14 /**< \brief (USBC_UECON4) FIFO Control */ 2464 #define USBC_UECON4_FIFOCON (_U_(0x1) << USBC_UECON4_FIFOCON_Pos) 2465 #define USBC_UECON4_NYETDIS_Pos 17 /**< \brief (USBC_UECON4) NYET Token Enable */ 2466 #define USBC_UECON4_NYETDIS (_U_(0x1) << USBC_UECON4_NYETDIS_Pos) 2467 #define USBC_UECON4_RSTDT_Pos 18 /**< \brief (USBC_UECON4) Reset Data Toggle */ 2468 #define USBC_UECON4_RSTDT (_U_(0x1) << USBC_UECON4_RSTDT_Pos) 2469 #define USBC_UECON4_STALLRQ_Pos 19 /**< \brief (USBC_UECON4) STALL Request */ 2470 #define USBC_UECON4_STALLRQ (_U_(0x1) << USBC_UECON4_STALLRQ_Pos) 2471 #define USBC_UECON4_BUSY0_Pos 24 /**< \brief (USBC_UECON4) Busy Bank1 Enable */ 2472 #define USBC_UECON4_BUSY0 (_U_(0x1) << USBC_UECON4_BUSY0_Pos) 2473 #define USBC_UECON4_BUSY1_Pos 25 /**< \brief (USBC_UECON4) Busy Bank0 Enable */ 2474 #define USBC_UECON4_BUSY1 (_U_(0x1) << USBC_UECON4_BUSY1_Pos) 2475 #define USBC_UECON4_MASK _U_(0x030E795F) /**< \brief (USBC_UECON4) MASK Register */ 2476 2477 /* -------- USBC_UECON5 : (USBC Offset: 0x1D4) (R/ 32) Endpoint Control Register -------- */ 2478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2479 typedef union { 2480 struct { 2481 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2482 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2483 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2484 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2485 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2486 uint32_t :1; /*!< bit: 5 Reserved */ 2487 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2488 uint32_t :1; /*!< bit: 7 Reserved */ 2489 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2490 uint32_t :2; /*!< bit: 9..10 Reserved */ 2491 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2492 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2493 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2494 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2495 uint32_t :2; /*!< bit: 15..16 Reserved */ 2496 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2497 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2498 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2499 uint32_t :4; /*!< bit: 20..23 Reserved */ 2500 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2501 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2502 uint32_t :6; /*!< bit: 26..31 Reserved */ 2503 } bit; /*!< Structure used for bit access */ 2504 uint32_t reg; /*!< Type used for register access */ 2505 } USBC_UECON5_Type; 2506 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2507 2508 #define USBC_UECON5_OFFSET 0x1D4 /**< \brief (USBC_UECON5 offset) Endpoint Control Register */ 2509 #define USBC_UECON5_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON5 reset_value) Endpoint Control Register */ 2510 2511 #define USBC_UECON5_TXINE_Pos 0 /**< \brief (USBC_UECON5) TXIN Interrupt Enable */ 2512 #define USBC_UECON5_TXINE (_U_(0x1) << USBC_UECON5_TXINE_Pos) 2513 #define USBC_UECON5_RXOUTE_Pos 1 /**< \brief (USBC_UECON5) RXOUT Interrupt Enable */ 2514 #define USBC_UECON5_RXOUTE (_U_(0x1) << USBC_UECON5_RXOUTE_Pos) 2515 #define USBC_UECON5_RXSTPE_Pos 2 /**< \brief (USBC_UECON5) RXSTP Interrupt Enable */ 2516 #define USBC_UECON5_RXSTPE (_U_(0x1) << USBC_UECON5_RXSTPE_Pos) 2517 #define USBC_UECON5_NAKOUTE_Pos 3 /**< \brief (USBC_UECON5) NAKOUT Interrupt Enable */ 2518 #define USBC_UECON5_NAKOUTE (_U_(0x1) << USBC_UECON5_NAKOUTE_Pos) 2519 #define USBC_UECON5_NAKINE_Pos 4 /**< \brief (USBC_UECON5) NAKIN Interrupt Enable */ 2520 #define USBC_UECON5_NAKINE (_U_(0x1) << USBC_UECON5_NAKINE_Pos) 2521 #define USBC_UECON5_STALLEDE_Pos 6 /**< \brief (USBC_UECON5) STALLED Interrupt Enable */ 2522 #define USBC_UECON5_STALLEDE (_U_(0x1) << USBC_UECON5_STALLEDE_Pos) 2523 #define USBC_UECON5_NREPLY_Pos 8 /**< \brief (USBC_UECON5) No Reply */ 2524 #define USBC_UECON5_NREPLY (_U_(0x1) << USBC_UECON5_NREPLY_Pos) 2525 #define USBC_UECON5_RAMACERE_Pos 11 /**< \brief (USBC_UECON5) RAMACER Interrupt Enable */ 2526 #define USBC_UECON5_RAMACERE (_U_(0x1) << USBC_UECON5_RAMACERE_Pos) 2527 #define USBC_UECON5_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON5) Number of Busy Banks Interrupt Enable */ 2528 #define USBC_UECON5_NBUSYBKE (_U_(0x1) << USBC_UECON5_NBUSYBKE_Pos) 2529 #define USBC_UECON5_KILLBK_Pos 13 /**< \brief (USBC_UECON5) Kill IN Bank */ 2530 #define USBC_UECON5_KILLBK (_U_(0x1) << USBC_UECON5_KILLBK_Pos) 2531 #define USBC_UECON5_FIFOCON_Pos 14 /**< \brief (USBC_UECON5) FIFO Control */ 2532 #define USBC_UECON5_FIFOCON (_U_(0x1) << USBC_UECON5_FIFOCON_Pos) 2533 #define USBC_UECON5_NYETDIS_Pos 17 /**< \brief (USBC_UECON5) NYET Token Enable */ 2534 #define USBC_UECON5_NYETDIS (_U_(0x1) << USBC_UECON5_NYETDIS_Pos) 2535 #define USBC_UECON5_RSTDT_Pos 18 /**< \brief (USBC_UECON5) Reset Data Toggle */ 2536 #define USBC_UECON5_RSTDT (_U_(0x1) << USBC_UECON5_RSTDT_Pos) 2537 #define USBC_UECON5_STALLRQ_Pos 19 /**< \brief (USBC_UECON5) STALL Request */ 2538 #define USBC_UECON5_STALLRQ (_U_(0x1) << USBC_UECON5_STALLRQ_Pos) 2539 #define USBC_UECON5_BUSY0_Pos 24 /**< \brief (USBC_UECON5) Busy Bank1 Enable */ 2540 #define USBC_UECON5_BUSY0 (_U_(0x1) << USBC_UECON5_BUSY0_Pos) 2541 #define USBC_UECON5_BUSY1_Pos 25 /**< \brief (USBC_UECON5) Busy Bank0 Enable */ 2542 #define USBC_UECON5_BUSY1 (_U_(0x1) << USBC_UECON5_BUSY1_Pos) 2543 #define USBC_UECON5_MASK _U_(0x030E795F) /**< \brief (USBC_UECON5) MASK Register */ 2544 2545 /* -------- USBC_UECON6 : (USBC Offset: 0x1D8) (R/ 32) Endpoint Control Register -------- */ 2546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2547 typedef union { 2548 struct { 2549 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2550 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2551 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2552 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2553 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2554 uint32_t :1; /*!< bit: 5 Reserved */ 2555 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2556 uint32_t :1; /*!< bit: 7 Reserved */ 2557 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2558 uint32_t :2; /*!< bit: 9..10 Reserved */ 2559 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2560 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2561 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2562 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2563 uint32_t :2; /*!< bit: 15..16 Reserved */ 2564 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2565 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2566 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2567 uint32_t :4; /*!< bit: 20..23 Reserved */ 2568 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2569 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2570 uint32_t :6; /*!< bit: 26..31 Reserved */ 2571 } bit; /*!< Structure used for bit access */ 2572 uint32_t reg; /*!< Type used for register access */ 2573 } USBC_UECON6_Type; 2574 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2575 2576 #define USBC_UECON6_OFFSET 0x1D8 /**< \brief (USBC_UECON6 offset) Endpoint Control Register */ 2577 #define USBC_UECON6_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON6 reset_value) Endpoint Control Register */ 2578 2579 #define USBC_UECON6_TXINE_Pos 0 /**< \brief (USBC_UECON6) TXIN Interrupt Enable */ 2580 #define USBC_UECON6_TXINE (_U_(0x1) << USBC_UECON6_TXINE_Pos) 2581 #define USBC_UECON6_RXOUTE_Pos 1 /**< \brief (USBC_UECON6) RXOUT Interrupt Enable */ 2582 #define USBC_UECON6_RXOUTE (_U_(0x1) << USBC_UECON6_RXOUTE_Pos) 2583 #define USBC_UECON6_RXSTPE_Pos 2 /**< \brief (USBC_UECON6) RXSTP Interrupt Enable */ 2584 #define USBC_UECON6_RXSTPE (_U_(0x1) << USBC_UECON6_RXSTPE_Pos) 2585 #define USBC_UECON6_NAKOUTE_Pos 3 /**< \brief (USBC_UECON6) NAKOUT Interrupt Enable */ 2586 #define USBC_UECON6_NAKOUTE (_U_(0x1) << USBC_UECON6_NAKOUTE_Pos) 2587 #define USBC_UECON6_NAKINE_Pos 4 /**< \brief (USBC_UECON6) NAKIN Interrupt Enable */ 2588 #define USBC_UECON6_NAKINE (_U_(0x1) << USBC_UECON6_NAKINE_Pos) 2589 #define USBC_UECON6_STALLEDE_Pos 6 /**< \brief (USBC_UECON6) STALLED Interrupt Enable */ 2590 #define USBC_UECON6_STALLEDE (_U_(0x1) << USBC_UECON6_STALLEDE_Pos) 2591 #define USBC_UECON6_NREPLY_Pos 8 /**< \brief (USBC_UECON6) No Reply */ 2592 #define USBC_UECON6_NREPLY (_U_(0x1) << USBC_UECON6_NREPLY_Pos) 2593 #define USBC_UECON6_RAMACERE_Pos 11 /**< \brief (USBC_UECON6) RAMACER Interrupt Enable */ 2594 #define USBC_UECON6_RAMACERE (_U_(0x1) << USBC_UECON6_RAMACERE_Pos) 2595 #define USBC_UECON6_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON6) Number of Busy Banks Interrupt Enable */ 2596 #define USBC_UECON6_NBUSYBKE (_U_(0x1) << USBC_UECON6_NBUSYBKE_Pos) 2597 #define USBC_UECON6_KILLBK_Pos 13 /**< \brief (USBC_UECON6) Kill IN Bank */ 2598 #define USBC_UECON6_KILLBK (_U_(0x1) << USBC_UECON6_KILLBK_Pos) 2599 #define USBC_UECON6_FIFOCON_Pos 14 /**< \brief (USBC_UECON6) FIFO Control */ 2600 #define USBC_UECON6_FIFOCON (_U_(0x1) << USBC_UECON6_FIFOCON_Pos) 2601 #define USBC_UECON6_NYETDIS_Pos 17 /**< \brief (USBC_UECON6) NYET Token Enable */ 2602 #define USBC_UECON6_NYETDIS (_U_(0x1) << USBC_UECON6_NYETDIS_Pos) 2603 #define USBC_UECON6_RSTDT_Pos 18 /**< \brief (USBC_UECON6) Reset Data Toggle */ 2604 #define USBC_UECON6_RSTDT (_U_(0x1) << USBC_UECON6_RSTDT_Pos) 2605 #define USBC_UECON6_STALLRQ_Pos 19 /**< \brief (USBC_UECON6) STALL Request */ 2606 #define USBC_UECON6_STALLRQ (_U_(0x1) << USBC_UECON6_STALLRQ_Pos) 2607 #define USBC_UECON6_BUSY0_Pos 24 /**< \brief (USBC_UECON6) Busy Bank1 Enable */ 2608 #define USBC_UECON6_BUSY0 (_U_(0x1) << USBC_UECON6_BUSY0_Pos) 2609 #define USBC_UECON6_BUSY1_Pos 25 /**< \brief (USBC_UECON6) Busy Bank0 Enable */ 2610 #define USBC_UECON6_BUSY1 (_U_(0x1) << USBC_UECON6_BUSY1_Pos) 2611 #define USBC_UECON6_MASK _U_(0x030E795F) /**< \brief (USBC_UECON6) MASK Register */ 2612 2613 /* -------- USBC_UECON7 : (USBC Offset: 0x1DC) (R/ 32) Endpoint Control Register -------- */ 2614 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2615 typedef union { 2616 struct { 2617 uint32_t TXINE:1; /*!< bit: 0 TXIN Interrupt Enable */ 2618 uint32_t RXOUTE:1; /*!< bit: 1 RXOUT Interrupt Enable */ 2619 uint32_t RXSTPE:1; /*!< bit: 2 RXSTP Interrupt Enable */ 2620 uint32_t NAKOUTE:1; /*!< bit: 3 NAKOUT Interrupt Enable */ 2621 uint32_t NAKINE:1; /*!< bit: 4 NAKIN Interrupt Enable */ 2622 uint32_t :1; /*!< bit: 5 Reserved */ 2623 uint32_t STALLEDE:1; /*!< bit: 6 STALLED Interrupt Enable */ 2624 uint32_t :1; /*!< bit: 7 Reserved */ 2625 uint32_t NREPLY:1; /*!< bit: 8 No Reply */ 2626 uint32_t :2; /*!< bit: 9..10 Reserved */ 2627 uint32_t RAMACERE:1; /*!< bit: 11 RAMACER Interrupt Enable */ 2628 uint32_t NBUSYBKE:1; /*!< bit: 12 Number of Busy Banks Interrupt Enable */ 2629 uint32_t KILLBK:1; /*!< bit: 13 Kill IN Bank */ 2630 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 2631 uint32_t :2; /*!< bit: 15..16 Reserved */ 2632 uint32_t NYETDIS:1; /*!< bit: 17 NYET Token Enable */ 2633 uint32_t RSTDT:1; /*!< bit: 18 Reset Data Toggle */ 2634 uint32_t STALLRQ:1; /*!< bit: 19 STALL Request */ 2635 uint32_t :4; /*!< bit: 20..23 Reserved */ 2636 uint32_t BUSY0:1; /*!< bit: 24 Busy Bank1 Enable */ 2637 uint32_t BUSY1:1; /*!< bit: 25 Busy Bank0 Enable */ 2638 uint32_t :6; /*!< bit: 26..31 Reserved */ 2639 } bit; /*!< Structure used for bit access */ 2640 uint32_t reg; /*!< Type used for register access */ 2641 } USBC_UECON7_Type; 2642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2643 2644 #define USBC_UECON7_OFFSET 0x1DC /**< \brief (USBC_UECON7 offset) Endpoint Control Register */ 2645 #define USBC_UECON7_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON7 reset_value) Endpoint Control Register */ 2646 2647 #define USBC_UECON7_TXINE_Pos 0 /**< \brief (USBC_UECON7) TXIN Interrupt Enable */ 2648 #define USBC_UECON7_TXINE (_U_(0x1) << USBC_UECON7_TXINE_Pos) 2649 #define USBC_UECON7_RXOUTE_Pos 1 /**< \brief (USBC_UECON7) RXOUT Interrupt Enable */ 2650 #define USBC_UECON7_RXOUTE (_U_(0x1) << USBC_UECON7_RXOUTE_Pos) 2651 #define USBC_UECON7_RXSTPE_Pos 2 /**< \brief (USBC_UECON7) RXSTP Interrupt Enable */ 2652 #define USBC_UECON7_RXSTPE (_U_(0x1) << USBC_UECON7_RXSTPE_Pos) 2653 #define USBC_UECON7_NAKOUTE_Pos 3 /**< \brief (USBC_UECON7) NAKOUT Interrupt Enable */ 2654 #define USBC_UECON7_NAKOUTE (_U_(0x1) << USBC_UECON7_NAKOUTE_Pos) 2655 #define USBC_UECON7_NAKINE_Pos 4 /**< \brief (USBC_UECON7) NAKIN Interrupt Enable */ 2656 #define USBC_UECON7_NAKINE (_U_(0x1) << USBC_UECON7_NAKINE_Pos) 2657 #define USBC_UECON7_STALLEDE_Pos 6 /**< \brief (USBC_UECON7) STALLED Interrupt Enable */ 2658 #define USBC_UECON7_STALLEDE (_U_(0x1) << USBC_UECON7_STALLEDE_Pos) 2659 #define USBC_UECON7_NREPLY_Pos 8 /**< \brief (USBC_UECON7) No Reply */ 2660 #define USBC_UECON7_NREPLY (_U_(0x1) << USBC_UECON7_NREPLY_Pos) 2661 #define USBC_UECON7_RAMACERE_Pos 11 /**< \brief (USBC_UECON7) RAMACER Interrupt Enable */ 2662 #define USBC_UECON7_RAMACERE (_U_(0x1) << USBC_UECON7_RAMACERE_Pos) 2663 #define USBC_UECON7_NBUSYBKE_Pos 12 /**< \brief (USBC_UECON7) Number of Busy Banks Interrupt Enable */ 2664 #define USBC_UECON7_NBUSYBKE (_U_(0x1) << USBC_UECON7_NBUSYBKE_Pos) 2665 #define USBC_UECON7_KILLBK_Pos 13 /**< \brief (USBC_UECON7) Kill IN Bank */ 2666 #define USBC_UECON7_KILLBK (_U_(0x1) << USBC_UECON7_KILLBK_Pos) 2667 #define USBC_UECON7_FIFOCON_Pos 14 /**< \brief (USBC_UECON7) FIFO Control */ 2668 #define USBC_UECON7_FIFOCON (_U_(0x1) << USBC_UECON7_FIFOCON_Pos) 2669 #define USBC_UECON7_NYETDIS_Pos 17 /**< \brief (USBC_UECON7) NYET Token Enable */ 2670 #define USBC_UECON7_NYETDIS (_U_(0x1) << USBC_UECON7_NYETDIS_Pos) 2671 #define USBC_UECON7_RSTDT_Pos 18 /**< \brief (USBC_UECON7) Reset Data Toggle */ 2672 #define USBC_UECON7_RSTDT (_U_(0x1) << USBC_UECON7_RSTDT_Pos) 2673 #define USBC_UECON7_STALLRQ_Pos 19 /**< \brief (USBC_UECON7) STALL Request */ 2674 #define USBC_UECON7_STALLRQ (_U_(0x1) << USBC_UECON7_STALLRQ_Pos) 2675 #define USBC_UECON7_BUSY0_Pos 24 /**< \brief (USBC_UECON7) Busy Bank1 Enable */ 2676 #define USBC_UECON7_BUSY0 (_U_(0x1) << USBC_UECON7_BUSY0_Pos) 2677 #define USBC_UECON7_BUSY1_Pos 25 /**< \brief (USBC_UECON7) Busy Bank0 Enable */ 2678 #define USBC_UECON7_BUSY1 (_U_(0x1) << USBC_UECON7_BUSY1_Pos) 2679 #define USBC_UECON7_MASK _U_(0x030E795F) /**< \brief (USBC_UECON7) MASK Register */ 2680 2681 /* -------- USBC_UECON0SET : (USBC Offset: 0x1F0) ( /W 32) Endpoint Control Set Register -------- */ 2682 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2683 typedef union { 2684 struct { 2685 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 2686 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 2687 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 2688 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 2689 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 2690 uint32_t :1; /*!< bit: 5 Reserved */ 2691 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 2692 uint32_t :1; /*!< bit: 7 Reserved */ 2693 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 2694 uint32_t :2; /*!< bit: 9..10 Reserved */ 2695 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 2696 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 2697 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 2698 uint32_t :3; /*!< bit: 14..16 Reserved */ 2699 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 2700 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 2701 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 2702 uint32_t :4; /*!< bit: 20..23 Reserved */ 2703 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 2704 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 2705 uint32_t :6; /*!< bit: 26..31 Reserved */ 2706 } bit; /*!< Structure used for bit access */ 2707 uint32_t reg; /*!< Type used for register access */ 2708 } USBC_UECON0SET_Type; 2709 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2710 2711 #define USBC_UECON0SET_OFFSET 0x1F0 /**< \brief (USBC_UECON0SET offset) Endpoint Control Set Register */ 2712 #define USBC_UECON0SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON0SET reset_value) Endpoint Control Set Register */ 2713 2714 #define USBC_UECON0SET_TXINES_Pos 0 /**< \brief (USBC_UECON0SET) TXINE Set */ 2715 #define USBC_UECON0SET_TXINES (_U_(0x1) << USBC_UECON0SET_TXINES_Pos) 2716 #define USBC_UECON0SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON0SET) RXOUTE Set */ 2717 #define USBC_UECON0SET_RXOUTES (_U_(0x1) << USBC_UECON0SET_RXOUTES_Pos) 2718 #define USBC_UECON0SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON0SET) RXSTPE Set */ 2719 #define USBC_UECON0SET_RXSTPES (_U_(0x1) << USBC_UECON0SET_RXSTPES_Pos) 2720 #define USBC_UECON0SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON0SET) NAKOUTE Set */ 2721 #define USBC_UECON0SET_NAKOUTES (_U_(0x1) << USBC_UECON0SET_NAKOUTES_Pos) 2722 #define USBC_UECON0SET_NAKINES_Pos 4 /**< \brief (USBC_UECON0SET) NAKINE Set */ 2723 #define USBC_UECON0SET_NAKINES (_U_(0x1) << USBC_UECON0SET_NAKINES_Pos) 2724 #define USBC_UECON0SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON0SET) STALLEDE Set */ 2725 #define USBC_UECON0SET_STALLEDES (_U_(0x1) << USBC_UECON0SET_STALLEDES_Pos) 2726 #define USBC_UECON0SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON0SET) NREPLY Set */ 2727 #define USBC_UECON0SET_NREPLYS (_U_(0x1) << USBC_UECON0SET_NREPLYS_Pos) 2728 #define USBC_UECON0SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON0SET) RAMACERE Set */ 2729 #define USBC_UECON0SET_RAMACERES (_U_(0x1) << USBC_UECON0SET_RAMACERES_Pos) 2730 #define USBC_UECON0SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON0SET) NBUSYBKE Set */ 2731 #define USBC_UECON0SET_NBUSYBKES (_U_(0x1) << USBC_UECON0SET_NBUSYBKES_Pos) 2732 #define USBC_UECON0SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON0SET) KILLBK Set */ 2733 #define USBC_UECON0SET_KILLBKS (_U_(0x1) << USBC_UECON0SET_KILLBKS_Pos) 2734 #define USBC_UECON0SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON0SET) NYETDIS Set */ 2735 #define USBC_UECON0SET_NYETDISS (_U_(0x1) << USBC_UECON0SET_NYETDISS_Pos) 2736 #define USBC_UECON0SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON0SET) RSTDT Set */ 2737 #define USBC_UECON0SET_RSTDTS (_U_(0x1) << USBC_UECON0SET_RSTDTS_Pos) 2738 #define USBC_UECON0SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON0SET) STALLRQ Set */ 2739 #define USBC_UECON0SET_STALLRQS (_U_(0x1) << USBC_UECON0SET_STALLRQS_Pos) 2740 #define USBC_UECON0SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON0SET) BUSY0 Set */ 2741 #define USBC_UECON0SET_BUSY0S (_U_(0x1) << USBC_UECON0SET_BUSY0S_Pos) 2742 #define USBC_UECON0SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON0SET) BUSY1 Set */ 2743 #define USBC_UECON0SET_BUSY1S (_U_(0x1) << USBC_UECON0SET_BUSY1S_Pos) 2744 #define USBC_UECON0SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON0SET) MASK Register */ 2745 2746 /* -------- USBC_UECON1SET : (USBC Offset: 0x1F4) ( /W 32) Endpoint Control Set Register -------- */ 2747 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2748 typedef union { 2749 struct { 2750 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 2751 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 2752 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 2753 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 2754 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 2755 uint32_t :1; /*!< bit: 5 Reserved */ 2756 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 2757 uint32_t :1; /*!< bit: 7 Reserved */ 2758 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 2759 uint32_t :2; /*!< bit: 9..10 Reserved */ 2760 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 2761 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 2762 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 2763 uint32_t :3; /*!< bit: 14..16 Reserved */ 2764 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 2765 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 2766 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 2767 uint32_t :4; /*!< bit: 20..23 Reserved */ 2768 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 2769 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 2770 uint32_t :6; /*!< bit: 26..31 Reserved */ 2771 } bit; /*!< Structure used for bit access */ 2772 uint32_t reg; /*!< Type used for register access */ 2773 } USBC_UECON1SET_Type; 2774 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2775 2776 #define USBC_UECON1SET_OFFSET 0x1F4 /**< \brief (USBC_UECON1SET offset) Endpoint Control Set Register */ 2777 #define USBC_UECON1SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON1SET reset_value) Endpoint Control Set Register */ 2778 2779 #define USBC_UECON1SET_TXINES_Pos 0 /**< \brief (USBC_UECON1SET) TXINE Set */ 2780 #define USBC_UECON1SET_TXINES (_U_(0x1) << USBC_UECON1SET_TXINES_Pos) 2781 #define USBC_UECON1SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON1SET) RXOUTE Set */ 2782 #define USBC_UECON1SET_RXOUTES (_U_(0x1) << USBC_UECON1SET_RXOUTES_Pos) 2783 #define USBC_UECON1SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON1SET) RXSTPE Set */ 2784 #define USBC_UECON1SET_RXSTPES (_U_(0x1) << USBC_UECON1SET_RXSTPES_Pos) 2785 #define USBC_UECON1SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON1SET) NAKOUTE Set */ 2786 #define USBC_UECON1SET_NAKOUTES (_U_(0x1) << USBC_UECON1SET_NAKOUTES_Pos) 2787 #define USBC_UECON1SET_NAKINES_Pos 4 /**< \brief (USBC_UECON1SET) NAKINE Set */ 2788 #define USBC_UECON1SET_NAKINES (_U_(0x1) << USBC_UECON1SET_NAKINES_Pos) 2789 #define USBC_UECON1SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON1SET) STALLEDE Set */ 2790 #define USBC_UECON1SET_STALLEDES (_U_(0x1) << USBC_UECON1SET_STALLEDES_Pos) 2791 #define USBC_UECON1SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON1SET) NREPLY Set */ 2792 #define USBC_UECON1SET_NREPLYS (_U_(0x1) << USBC_UECON1SET_NREPLYS_Pos) 2793 #define USBC_UECON1SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON1SET) RAMACERE Set */ 2794 #define USBC_UECON1SET_RAMACERES (_U_(0x1) << USBC_UECON1SET_RAMACERES_Pos) 2795 #define USBC_UECON1SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON1SET) NBUSYBKE Set */ 2796 #define USBC_UECON1SET_NBUSYBKES (_U_(0x1) << USBC_UECON1SET_NBUSYBKES_Pos) 2797 #define USBC_UECON1SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON1SET) KILLBK Set */ 2798 #define USBC_UECON1SET_KILLBKS (_U_(0x1) << USBC_UECON1SET_KILLBKS_Pos) 2799 #define USBC_UECON1SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON1SET) NYETDIS Set */ 2800 #define USBC_UECON1SET_NYETDISS (_U_(0x1) << USBC_UECON1SET_NYETDISS_Pos) 2801 #define USBC_UECON1SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON1SET) RSTDT Set */ 2802 #define USBC_UECON1SET_RSTDTS (_U_(0x1) << USBC_UECON1SET_RSTDTS_Pos) 2803 #define USBC_UECON1SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON1SET) STALLRQ Set */ 2804 #define USBC_UECON1SET_STALLRQS (_U_(0x1) << USBC_UECON1SET_STALLRQS_Pos) 2805 #define USBC_UECON1SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON1SET) BUSY0 Set */ 2806 #define USBC_UECON1SET_BUSY0S (_U_(0x1) << USBC_UECON1SET_BUSY0S_Pos) 2807 #define USBC_UECON1SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON1SET) BUSY1 Set */ 2808 #define USBC_UECON1SET_BUSY1S (_U_(0x1) << USBC_UECON1SET_BUSY1S_Pos) 2809 #define USBC_UECON1SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON1SET) MASK Register */ 2810 2811 /* -------- USBC_UECON2SET : (USBC Offset: 0x1F8) ( /W 32) Endpoint Control Set Register -------- */ 2812 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2813 typedef union { 2814 struct { 2815 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 2816 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 2817 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 2818 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 2819 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 2820 uint32_t :1; /*!< bit: 5 Reserved */ 2821 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 2822 uint32_t :1; /*!< bit: 7 Reserved */ 2823 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 2824 uint32_t :2; /*!< bit: 9..10 Reserved */ 2825 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 2826 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 2827 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 2828 uint32_t :3; /*!< bit: 14..16 Reserved */ 2829 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 2830 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 2831 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 2832 uint32_t :4; /*!< bit: 20..23 Reserved */ 2833 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 2834 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 2835 uint32_t :6; /*!< bit: 26..31 Reserved */ 2836 } bit; /*!< Structure used for bit access */ 2837 uint32_t reg; /*!< Type used for register access */ 2838 } USBC_UECON2SET_Type; 2839 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2840 2841 #define USBC_UECON2SET_OFFSET 0x1F8 /**< \brief (USBC_UECON2SET offset) Endpoint Control Set Register */ 2842 #define USBC_UECON2SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON2SET reset_value) Endpoint Control Set Register */ 2843 2844 #define USBC_UECON2SET_TXINES_Pos 0 /**< \brief (USBC_UECON2SET) TXINE Set */ 2845 #define USBC_UECON2SET_TXINES (_U_(0x1) << USBC_UECON2SET_TXINES_Pos) 2846 #define USBC_UECON2SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON2SET) RXOUTE Set */ 2847 #define USBC_UECON2SET_RXOUTES (_U_(0x1) << USBC_UECON2SET_RXOUTES_Pos) 2848 #define USBC_UECON2SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON2SET) RXSTPE Set */ 2849 #define USBC_UECON2SET_RXSTPES (_U_(0x1) << USBC_UECON2SET_RXSTPES_Pos) 2850 #define USBC_UECON2SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON2SET) NAKOUTE Set */ 2851 #define USBC_UECON2SET_NAKOUTES (_U_(0x1) << USBC_UECON2SET_NAKOUTES_Pos) 2852 #define USBC_UECON2SET_NAKINES_Pos 4 /**< \brief (USBC_UECON2SET) NAKINE Set */ 2853 #define USBC_UECON2SET_NAKINES (_U_(0x1) << USBC_UECON2SET_NAKINES_Pos) 2854 #define USBC_UECON2SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON2SET) STALLEDE Set */ 2855 #define USBC_UECON2SET_STALLEDES (_U_(0x1) << USBC_UECON2SET_STALLEDES_Pos) 2856 #define USBC_UECON2SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON2SET) NREPLY Set */ 2857 #define USBC_UECON2SET_NREPLYS (_U_(0x1) << USBC_UECON2SET_NREPLYS_Pos) 2858 #define USBC_UECON2SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON2SET) RAMACERE Set */ 2859 #define USBC_UECON2SET_RAMACERES (_U_(0x1) << USBC_UECON2SET_RAMACERES_Pos) 2860 #define USBC_UECON2SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON2SET) NBUSYBKE Set */ 2861 #define USBC_UECON2SET_NBUSYBKES (_U_(0x1) << USBC_UECON2SET_NBUSYBKES_Pos) 2862 #define USBC_UECON2SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON2SET) KILLBK Set */ 2863 #define USBC_UECON2SET_KILLBKS (_U_(0x1) << USBC_UECON2SET_KILLBKS_Pos) 2864 #define USBC_UECON2SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON2SET) NYETDIS Set */ 2865 #define USBC_UECON2SET_NYETDISS (_U_(0x1) << USBC_UECON2SET_NYETDISS_Pos) 2866 #define USBC_UECON2SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON2SET) RSTDT Set */ 2867 #define USBC_UECON2SET_RSTDTS (_U_(0x1) << USBC_UECON2SET_RSTDTS_Pos) 2868 #define USBC_UECON2SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON2SET) STALLRQ Set */ 2869 #define USBC_UECON2SET_STALLRQS (_U_(0x1) << USBC_UECON2SET_STALLRQS_Pos) 2870 #define USBC_UECON2SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON2SET) BUSY0 Set */ 2871 #define USBC_UECON2SET_BUSY0S (_U_(0x1) << USBC_UECON2SET_BUSY0S_Pos) 2872 #define USBC_UECON2SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON2SET) BUSY1 Set */ 2873 #define USBC_UECON2SET_BUSY1S (_U_(0x1) << USBC_UECON2SET_BUSY1S_Pos) 2874 #define USBC_UECON2SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON2SET) MASK Register */ 2875 2876 /* -------- USBC_UECON3SET : (USBC Offset: 0x1FC) ( /W 32) Endpoint Control Set Register -------- */ 2877 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2878 typedef union { 2879 struct { 2880 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 2881 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 2882 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 2883 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 2884 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 2885 uint32_t :1; /*!< bit: 5 Reserved */ 2886 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 2887 uint32_t :1; /*!< bit: 7 Reserved */ 2888 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 2889 uint32_t :2; /*!< bit: 9..10 Reserved */ 2890 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 2891 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 2892 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 2893 uint32_t :3; /*!< bit: 14..16 Reserved */ 2894 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 2895 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 2896 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 2897 uint32_t :4; /*!< bit: 20..23 Reserved */ 2898 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 2899 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 2900 uint32_t :6; /*!< bit: 26..31 Reserved */ 2901 } bit; /*!< Structure used for bit access */ 2902 uint32_t reg; /*!< Type used for register access */ 2903 } USBC_UECON3SET_Type; 2904 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2905 2906 #define USBC_UECON3SET_OFFSET 0x1FC /**< \brief (USBC_UECON3SET offset) Endpoint Control Set Register */ 2907 #define USBC_UECON3SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON3SET reset_value) Endpoint Control Set Register */ 2908 2909 #define USBC_UECON3SET_TXINES_Pos 0 /**< \brief (USBC_UECON3SET) TXINE Set */ 2910 #define USBC_UECON3SET_TXINES (_U_(0x1) << USBC_UECON3SET_TXINES_Pos) 2911 #define USBC_UECON3SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON3SET) RXOUTE Set */ 2912 #define USBC_UECON3SET_RXOUTES (_U_(0x1) << USBC_UECON3SET_RXOUTES_Pos) 2913 #define USBC_UECON3SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON3SET) RXSTPE Set */ 2914 #define USBC_UECON3SET_RXSTPES (_U_(0x1) << USBC_UECON3SET_RXSTPES_Pos) 2915 #define USBC_UECON3SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON3SET) NAKOUTE Set */ 2916 #define USBC_UECON3SET_NAKOUTES (_U_(0x1) << USBC_UECON3SET_NAKOUTES_Pos) 2917 #define USBC_UECON3SET_NAKINES_Pos 4 /**< \brief (USBC_UECON3SET) NAKINE Set */ 2918 #define USBC_UECON3SET_NAKINES (_U_(0x1) << USBC_UECON3SET_NAKINES_Pos) 2919 #define USBC_UECON3SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON3SET) STALLEDE Set */ 2920 #define USBC_UECON3SET_STALLEDES (_U_(0x1) << USBC_UECON3SET_STALLEDES_Pos) 2921 #define USBC_UECON3SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON3SET) NREPLY Set */ 2922 #define USBC_UECON3SET_NREPLYS (_U_(0x1) << USBC_UECON3SET_NREPLYS_Pos) 2923 #define USBC_UECON3SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON3SET) RAMACERE Set */ 2924 #define USBC_UECON3SET_RAMACERES (_U_(0x1) << USBC_UECON3SET_RAMACERES_Pos) 2925 #define USBC_UECON3SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON3SET) NBUSYBKE Set */ 2926 #define USBC_UECON3SET_NBUSYBKES (_U_(0x1) << USBC_UECON3SET_NBUSYBKES_Pos) 2927 #define USBC_UECON3SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON3SET) KILLBK Set */ 2928 #define USBC_UECON3SET_KILLBKS (_U_(0x1) << USBC_UECON3SET_KILLBKS_Pos) 2929 #define USBC_UECON3SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON3SET) NYETDIS Set */ 2930 #define USBC_UECON3SET_NYETDISS (_U_(0x1) << USBC_UECON3SET_NYETDISS_Pos) 2931 #define USBC_UECON3SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON3SET) RSTDT Set */ 2932 #define USBC_UECON3SET_RSTDTS (_U_(0x1) << USBC_UECON3SET_RSTDTS_Pos) 2933 #define USBC_UECON3SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON3SET) STALLRQ Set */ 2934 #define USBC_UECON3SET_STALLRQS (_U_(0x1) << USBC_UECON3SET_STALLRQS_Pos) 2935 #define USBC_UECON3SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON3SET) BUSY0 Set */ 2936 #define USBC_UECON3SET_BUSY0S (_U_(0x1) << USBC_UECON3SET_BUSY0S_Pos) 2937 #define USBC_UECON3SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON3SET) BUSY1 Set */ 2938 #define USBC_UECON3SET_BUSY1S (_U_(0x1) << USBC_UECON3SET_BUSY1S_Pos) 2939 #define USBC_UECON3SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON3SET) MASK Register */ 2940 2941 /* -------- USBC_UECON4SET : (USBC Offset: 0x200) ( /W 32) Endpoint Control Set Register -------- */ 2942 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 2943 typedef union { 2944 struct { 2945 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 2946 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 2947 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 2948 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 2949 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 2950 uint32_t :1; /*!< bit: 5 Reserved */ 2951 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 2952 uint32_t :1; /*!< bit: 7 Reserved */ 2953 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 2954 uint32_t :2; /*!< bit: 9..10 Reserved */ 2955 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 2956 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 2957 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 2958 uint32_t :3; /*!< bit: 14..16 Reserved */ 2959 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 2960 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 2961 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 2962 uint32_t :4; /*!< bit: 20..23 Reserved */ 2963 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 2964 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 2965 uint32_t :6; /*!< bit: 26..31 Reserved */ 2966 } bit; /*!< Structure used for bit access */ 2967 uint32_t reg; /*!< Type used for register access */ 2968 } USBC_UECON4SET_Type; 2969 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 2970 2971 #define USBC_UECON4SET_OFFSET 0x200 /**< \brief (USBC_UECON4SET offset) Endpoint Control Set Register */ 2972 #define USBC_UECON4SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON4SET reset_value) Endpoint Control Set Register */ 2973 2974 #define USBC_UECON4SET_TXINES_Pos 0 /**< \brief (USBC_UECON4SET) TXINE Set */ 2975 #define USBC_UECON4SET_TXINES (_U_(0x1) << USBC_UECON4SET_TXINES_Pos) 2976 #define USBC_UECON4SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON4SET) RXOUTE Set */ 2977 #define USBC_UECON4SET_RXOUTES (_U_(0x1) << USBC_UECON4SET_RXOUTES_Pos) 2978 #define USBC_UECON4SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON4SET) RXSTPE Set */ 2979 #define USBC_UECON4SET_RXSTPES (_U_(0x1) << USBC_UECON4SET_RXSTPES_Pos) 2980 #define USBC_UECON4SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON4SET) NAKOUTE Set */ 2981 #define USBC_UECON4SET_NAKOUTES (_U_(0x1) << USBC_UECON4SET_NAKOUTES_Pos) 2982 #define USBC_UECON4SET_NAKINES_Pos 4 /**< \brief (USBC_UECON4SET) NAKINE Set */ 2983 #define USBC_UECON4SET_NAKINES (_U_(0x1) << USBC_UECON4SET_NAKINES_Pos) 2984 #define USBC_UECON4SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON4SET) STALLEDE Set */ 2985 #define USBC_UECON4SET_STALLEDES (_U_(0x1) << USBC_UECON4SET_STALLEDES_Pos) 2986 #define USBC_UECON4SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON4SET) NREPLY Set */ 2987 #define USBC_UECON4SET_NREPLYS (_U_(0x1) << USBC_UECON4SET_NREPLYS_Pos) 2988 #define USBC_UECON4SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON4SET) RAMACERE Set */ 2989 #define USBC_UECON4SET_RAMACERES (_U_(0x1) << USBC_UECON4SET_RAMACERES_Pos) 2990 #define USBC_UECON4SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON4SET) NBUSYBKE Set */ 2991 #define USBC_UECON4SET_NBUSYBKES (_U_(0x1) << USBC_UECON4SET_NBUSYBKES_Pos) 2992 #define USBC_UECON4SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON4SET) KILLBK Set */ 2993 #define USBC_UECON4SET_KILLBKS (_U_(0x1) << USBC_UECON4SET_KILLBKS_Pos) 2994 #define USBC_UECON4SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON4SET) NYETDIS Set */ 2995 #define USBC_UECON4SET_NYETDISS (_U_(0x1) << USBC_UECON4SET_NYETDISS_Pos) 2996 #define USBC_UECON4SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON4SET) RSTDT Set */ 2997 #define USBC_UECON4SET_RSTDTS (_U_(0x1) << USBC_UECON4SET_RSTDTS_Pos) 2998 #define USBC_UECON4SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON4SET) STALLRQ Set */ 2999 #define USBC_UECON4SET_STALLRQS (_U_(0x1) << USBC_UECON4SET_STALLRQS_Pos) 3000 #define USBC_UECON4SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON4SET) BUSY0 Set */ 3001 #define USBC_UECON4SET_BUSY0S (_U_(0x1) << USBC_UECON4SET_BUSY0S_Pos) 3002 #define USBC_UECON4SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON4SET) BUSY1 Set */ 3003 #define USBC_UECON4SET_BUSY1S (_U_(0x1) << USBC_UECON4SET_BUSY1S_Pos) 3004 #define USBC_UECON4SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON4SET) MASK Register */ 3005 3006 /* -------- USBC_UECON5SET : (USBC Offset: 0x204) ( /W 32) Endpoint Control Set Register -------- */ 3007 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3008 typedef union { 3009 struct { 3010 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 3011 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 3012 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 3013 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 3014 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 3015 uint32_t :1; /*!< bit: 5 Reserved */ 3016 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 3017 uint32_t :1; /*!< bit: 7 Reserved */ 3018 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 3019 uint32_t :2; /*!< bit: 9..10 Reserved */ 3020 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 3021 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 3022 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 3023 uint32_t :3; /*!< bit: 14..16 Reserved */ 3024 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 3025 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 3026 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 3027 uint32_t :4; /*!< bit: 20..23 Reserved */ 3028 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 3029 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 3030 uint32_t :6; /*!< bit: 26..31 Reserved */ 3031 } bit; /*!< Structure used for bit access */ 3032 uint32_t reg; /*!< Type used for register access */ 3033 } USBC_UECON5SET_Type; 3034 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3035 3036 #define USBC_UECON5SET_OFFSET 0x204 /**< \brief (USBC_UECON5SET offset) Endpoint Control Set Register */ 3037 #define USBC_UECON5SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON5SET reset_value) Endpoint Control Set Register */ 3038 3039 #define USBC_UECON5SET_TXINES_Pos 0 /**< \brief (USBC_UECON5SET) TXINE Set */ 3040 #define USBC_UECON5SET_TXINES (_U_(0x1) << USBC_UECON5SET_TXINES_Pos) 3041 #define USBC_UECON5SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON5SET) RXOUTE Set */ 3042 #define USBC_UECON5SET_RXOUTES (_U_(0x1) << USBC_UECON5SET_RXOUTES_Pos) 3043 #define USBC_UECON5SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON5SET) RXSTPE Set */ 3044 #define USBC_UECON5SET_RXSTPES (_U_(0x1) << USBC_UECON5SET_RXSTPES_Pos) 3045 #define USBC_UECON5SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON5SET) NAKOUTE Set */ 3046 #define USBC_UECON5SET_NAKOUTES (_U_(0x1) << USBC_UECON5SET_NAKOUTES_Pos) 3047 #define USBC_UECON5SET_NAKINES_Pos 4 /**< \brief (USBC_UECON5SET) NAKINE Set */ 3048 #define USBC_UECON5SET_NAKINES (_U_(0x1) << USBC_UECON5SET_NAKINES_Pos) 3049 #define USBC_UECON5SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON5SET) STALLEDE Set */ 3050 #define USBC_UECON5SET_STALLEDES (_U_(0x1) << USBC_UECON5SET_STALLEDES_Pos) 3051 #define USBC_UECON5SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON5SET) NREPLY Set */ 3052 #define USBC_UECON5SET_NREPLYS (_U_(0x1) << USBC_UECON5SET_NREPLYS_Pos) 3053 #define USBC_UECON5SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON5SET) RAMACERE Set */ 3054 #define USBC_UECON5SET_RAMACERES (_U_(0x1) << USBC_UECON5SET_RAMACERES_Pos) 3055 #define USBC_UECON5SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON5SET) NBUSYBKE Set */ 3056 #define USBC_UECON5SET_NBUSYBKES (_U_(0x1) << USBC_UECON5SET_NBUSYBKES_Pos) 3057 #define USBC_UECON5SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON5SET) KILLBK Set */ 3058 #define USBC_UECON5SET_KILLBKS (_U_(0x1) << USBC_UECON5SET_KILLBKS_Pos) 3059 #define USBC_UECON5SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON5SET) NYETDIS Set */ 3060 #define USBC_UECON5SET_NYETDISS (_U_(0x1) << USBC_UECON5SET_NYETDISS_Pos) 3061 #define USBC_UECON5SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON5SET) RSTDT Set */ 3062 #define USBC_UECON5SET_RSTDTS (_U_(0x1) << USBC_UECON5SET_RSTDTS_Pos) 3063 #define USBC_UECON5SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON5SET) STALLRQ Set */ 3064 #define USBC_UECON5SET_STALLRQS (_U_(0x1) << USBC_UECON5SET_STALLRQS_Pos) 3065 #define USBC_UECON5SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON5SET) BUSY0 Set */ 3066 #define USBC_UECON5SET_BUSY0S (_U_(0x1) << USBC_UECON5SET_BUSY0S_Pos) 3067 #define USBC_UECON5SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON5SET) BUSY1 Set */ 3068 #define USBC_UECON5SET_BUSY1S (_U_(0x1) << USBC_UECON5SET_BUSY1S_Pos) 3069 #define USBC_UECON5SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON5SET) MASK Register */ 3070 3071 /* -------- USBC_UECON6SET : (USBC Offset: 0x208) ( /W 32) Endpoint Control Set Register -------- */ 3072 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3073 typedef union { 3074 struct { 3075 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 3076 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 3077 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 3078 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 3079 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 3080 uint32_t :1; /*!< bit: 5 Reserved */ 3081 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 3082 uint32_t :1; /*!< bit: 7 Reserved */ 3083 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 3084 uint32_t :2; /*!< bit: 9..10 Reserved */ 3085 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 3086 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 3087 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 3088 uint32_t :3; /*!< bit: 14..16 Reserved */ 3089 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 3090 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 3091 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 3092 uint32_t :4; /*!< bit: 20..23 Reserved */ 3093 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 3094 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 3095 uint32_t :6; /*!< bit: 26..31 Reserved */ 3096 } bit; /*!< Structure used for bit access */ 3097 uint32_t reg; /*!< Type used for register access */ 3098 } USBC_UECON6SET_Type; 3099 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3100 3101 #define USBC_UECON6SET_OFFSET 0x208 /**< \brief (USBC_UECON6SET offset) Endpoint Control Set Register */ 3102 #define USBC_UECON6SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON6SET reset_value) Endpoint Control Set Register */ 3103 3104 #define USBC_UECON6SET_TXINES_Pos 0 /**< \brief (USBC_UECON6SET) TXINE Set */ 3105 #define USBC_UECON6SET_TXINES (_U_(0x1) << USBC_UECON6SET_TXINES_Pos) 3106 #define USBC_UECON6SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON6SET) RXOUTE Set */ 3107 #define USBC_UECON6SET_RXOUTES (_U_(0x1) << USBC_UECON6SET_RXOUTES_Pos) 3108 #define USBC_UECON6SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON6SET) RXSTPE Set */ 3109 #define USBC_UECON6SET_RXSTPES (_U_(0x1) << USBC_UECON6SET_RXSTPES_Pos) 3110 #define USBC_UECON6SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON6SET) NAKOUTE Set */ 3111 #define USBC_UECON6SET_NAKOUTES (_U_(0x1) << USBC_UECON6SET_NAKOUTES_Pos) 3112 #define USBC_UECON6SET_NAKINES_Pos 4 /**< \brief (USBC_UECON6SET) NAKINE Set */ 3113 #define USBC_UECON6SET_NAKINES (_U_(0x1) << USBC_UECON6SET_NAKINES_Pos) 3114 #define USBC_UECON6SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON6SET) STALLEDE Set */ 3115 #define USBC_UECON6SET_STALLEDES (_U_(0x1) << USBC_UECON6SET_STALLEDES_Pos) 3116 #define USBC_UECON6SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON6SET) NREPLY Set */ 3117 #define USBC_UECON6SET_NREPLYS (_U_(0x1) << USBC_UECON6SET_NREPLYS_Pos) 3118 #define USBC_UECON6SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON6SET) RAMACERE Set */ 3119 #define USBC_UECON6SET_RAMACERES (_U_(0x1) << USBC_UECON6SET_RAMACERES_Pos) 3120 #define USBC_UECON6SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON6SET) NBUSYBKE Set */ 3121 #define USBC_UECON6SET_NBUSYBKES (_U_(0x1) << USBC_UECON6SET_NBUSYBKES_Pos) 3122 #define USBC_UECON6SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON6SET) KILLBK Set */ 3123 #define USBC_UECON6SET_KILLBKS (_U_(0x1) << USBC_UECON6SET_KILLBKS_Pos) 3124 #define USBC_UECON6SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON6SET) NYETDIS Set */ 3125 #define USBC_UECON6SET_NYETDISS (_U_(0x1) << USBC_UECON6SET_NYETDISS_Pos) 3126 #define USBC_UECON6SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON6SET) RSTDT Set */ 3127 #define USBC_UECON6SET_RSTDTS (_U_(0x1) << USBC_UECON6SET_RSTDTS_Pos) 3128 #define USBC_UECON6SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON6SET) STALLRQ Set */ 3129 #define USBC_UECON6SET_STALLRQS (_U_(0x1) << USBC_UECON6SET_STALLRQS_Pos) 3130 #define USBC_UECON6SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON6SET) BUSY0 Set */ 3131 #define USBC_UECON6SET_BUSY0S (_U_(0x1) << USBC_UECON6SET_BUSY0S_Pos) 3132 #define USBC_UECON6SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON6SET) BUSY1 Set */ 3133 #define USBC_UECON6SET_BUSY1S (_U_(0x1) << USBC_UECON6SET_BUSY1S_Pos) 3134 #define USBC_UECON6SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON6SET) MASK Register */ 3135 3136 /* -------- USBC_UECON7SET : (USBC Offset: 0x20C) ( /W 32) Endpoint Control Set Register -------- */ 3137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3138 typedef union { 3139 struct { 3140 uint32_t TXINES:1; /*!< bit: 0 TXINE Set */ 3141 uint32_t RXOUTES:1; /*!< bit: 1 RXOUTE Set */ 3142 uint32_t RXSTPES:1; /*!< bit: 2 RXSTPE Set */ 3143 uint32_t NAKOUTES:1; /*!< bit: 3 NAKOUTE Set */ 3144 uint32_t NAKINES:1; /*!< bit: 4 NAKINE Set */ 3145 uint32_t :1; /*!< bit: 5 Reserved */ 3146 uint32_t STALLEDES:1; /*!< bit: 6 STALLEDE Set */ 3147 uint32_t :1; /*!< bit: 7 Reserved */ 3148 uint32_t NREPLYS:1; /*!< bit: 8 NREPLY Set */ 3149 uint32_t :2; /*!< bit: 9..10 Reserved */ 3150 uint32_t RAMACERES:1; /*!< bit: 11 RAMACERE Set */ 3151 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 3152 uint32_t KILLBKS:1; /*!< bit: 13 KILLBK Set */ 3153 uint32_t :3; /*!< bit: 14..16 Reserved */ 3154 uint32_t NYETDISS:1; /*!< bit: 17 NYETDIS Set */ 3155 uint32_t RSTDTS:1; /*!< bit: 18 RSTDT Set */ 3156 uint32_t STALLRQS:1; /*!< bit: 19 STALLRQ Set */ 3157 uint32_t :4; /*!< bit: 20..23 Reserved */ 3158 uint32_t BUSY0S:1; /*!< bit: 24 BUSY0 Set */ 3159 uint32_t BUSY1S:1; /*!< bit: 25 BUSY1 Set */ 3160 uint32_t :6; /*!< bit: 26..31 Reserved */ 3161 } bit; /*!< Structure used for bit access */ 3162 uint32_t reg; /*!< Type used for register access */ 3163 } USBC_UECON7SET_Type; 3164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3165 3166 #define USBC_UECON7SET_OFFSET 0x20C /**< \brief (USBC_UECON7SET offset) Endpoint Control Set Register */ 3167 #define USBC_UECON7SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON7SET reset_value) Endpoint Control Set Register */ 3168 3169 #define USBC_UECON7SET_TXINES_Pos 0 /**< \brief (USBC_UECON7SET) TXINE Set */ 3170 #define USBC_UECON7SET_TXINES (_U_(0x1) << USBC_UECON7SET_TXINES_Pos) 3171 #define USBC_UECON7SET_RXOUTES_Pos 1 /**< \brief (USBC_UECON7SET) RXOUTE Set */ 3172 #define USBC_UECON7SET_RXOUTES (_U_(0x1) << USBC_UECON7SET_RXOUTES_Pos) 3173 #define USBC_UECON7SET_RXSTPES_Pos 2 /**< \brief (USBC_UECON7SET) RXSTPE Set */ 3174 #define USBC_UECON7SET_RXSTPES (_U_(0x1) << USBC_UECON7SET_RXSTPES_Pos) 3175 #define USBC_UECON7SET_NAKOUTES_Pos 3 /**< \brief (USBC_UECON7SET) NAKOUTE Set */ 3176 #define USBC_UECON7SET_NAKOUTES (_U_(0x1) << USBC_UECON7SET_NAKOUTES_Pos) 3177 #define USBC_UECON7SET_NAKINES_Pos 4 /**< \brief (USBC_UECON7SET) NAKINE Set */ 3178 #define USBC_UECON7SET_NAKINES (_U_(0x1) << USBC_UECON7SET_NAKINES_Pos) 3179 #define USBC_UECON7SET_STALLEDES_Pos 6 /**< \brief (USBC_UECON7SET) STALLEDE Set */ 3180 #define USBC_UECON7SET_STALLEDES (_U_(0x1) << USBC_UECON7SET_STALLEDES_Pos) 3181 #define USBC_UECON7SET_NREPLYS_Pos 8 /**< \brief (USBC_UECON7SET) NREPLY Set */ 3182 #define USBC_UECON7SET_NREPLYS (_U_(0x1) << USBC_UECON7SET_NREPLYS_Pos) 3183 #define USBC_UECON7SET_RAMACERES_Pos 11 /**< \brief (USBC_UECON7SET) RAMACERE Set */ 3184 #define USBC_UECON7SET_RAMACERES (_U_(0x1) << USBC_UECON7SET_RAMACERES_Pos) 3185 #define USBC_UECON7SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UECON7SET) NBUSYBKE Set */ 3186 #define USBC_UECON7SET_NBUSYBKES (_U_(0x1) << USBC_UECON7SET_NBUSYBKES_Pos) 3187 #define USBC_UECON7SET_KILLBKS_Pos 13 /**< \brief (USBC_UECON7SET) KILLBK Set */ 3188 #define USBC_UECON7SET_KILLBKS (_U_(0x1) << USBC_UECON7SET_KILLBKS_Pos) 3189 #define USBC_UECON7SET_NYETDISS_Pos 17 /**< \brief (USBC_UECON7SET) NYETDIS Set */ 3190 #define USBC_UECON7SET_NYETDISS (_U_(0x1) << USBC_UECON7SET_NYETDISS_Pos) 3191 #define USBC_UECON7SET_RSTDTS_Pos 18 /**< \brief (USBC_UECON7SET) RSTDT Set */ 3192 #define USBC_UECON7SET_RSTDTS (_U_(0x1) << USBC_UECON7SET_RSTDTS_Pos) 3193 #define USBC_UECON7SET_STALLRQS_Pos 19 /**< \brief (USBC_UECON7SET) STALLRQ Set */ 3194 #define USBC_UECON7SET_STALLRQS (_U_(0x1) << USBC_UECON7SET_STALLRQS_Pos) 3195 #define USBC_UECON7SET_BUSY0S_Pos 24 /**< \brief (USBC_UECON7SET) BUSY0 Set */ 3196 #define USBC_UECON7SET_BUSY0S (_U_(0x1) << USBC_UECON7SET_BUSY0S_Pos) 3197 #define USBC_UECON7SET_BUSY1S_Pos 25 /**< \brief (USBC_UECON7SET) BUSY1 Set */ 3198 #define USBC_UECON7SET_BUSY1S (_U_(0x1) << USBC_UECON7SET_BUSY1S_Pos) 3199 #define USBC_UECON7SET_MASK _U_(0x030E395F) /**< \brief (USBC_UECON7SET) MASK Register */ 3200 3201 /* -------- USBC_UECON0CLR : (USBC Offset: 0x220) ( /W 32) Endpoint Control Clear Register -------- */ 3202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3203 typedef union { 3204 struct { 3205 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3206 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3207 uint32_t RXSTPEC:1; /*!< bit: 2 RXSTPE Clear */ 3208 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3209 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3210 uint32_t :1; /*!< bit: 5 Reserved */ 3211 uint32_t STALLEDEC:1; /*!< bit: 6 STALLEDE Clear */ 3212 uint32_t :1; /*!< bit: 7 Reserved */ 3213 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3214 uint32_t :2; /*!< bit: 9..10 Reserved */ 3215 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3216 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3217 uint32_t :1; /*!< bit: 13 Reserved */ 3218 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3219 uint32_t :2; /*!< bit: 15..16 Reserved */ 3220 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3221 uint32_t :1; /*!< bit: 18 Reserved */ 3222 uint32_t STALLRQC:1; /*!< bit: 19 STALLRQ Clear */ 3223 uint32_t :4; /*!< bit: 20..23 Reserved */ 3224 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3225 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3226 uint32_t :6; /*!< bit: 26..31 Reserved */ 3227 } bit; /*!< Structure used for bit access */ 3228 uint32_t reg; /*!< Type used for register access */ 3229 } USBC_UECON0CLR_Type; 3230 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3231 3232 #define USBC_UECON0CLR_OFFSET 0x220 /**< \brief (USBC_UECON0CLR offset) Endpoint Control Clear Register */ 3233 #define USBC_UECON0CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON0CLR reset_value) Endpoint Control Clear Register */ 3234 3235 #define USBC_UECON0CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON0CLR) TXINE Clear */ 3236 #define USBC_UECON0CLR_TXINEC (_U_(0x1) << USBC_UECON0CLR_TXINEC_Pos) 3237 #define USBC_UECON0CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON0CLR) RXOUTE Clear */ 3238 #define USBC_UECON0CLR_RXOUTEC (_U_(0x1) << USBC_UECON0CLR_RXOUTEC_Pos) 3239 #define USBC_UECON0CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON0CLR) RXSTPE Clear */ 3240 #define USBC_UECON0CLR_RXSTPEC (_U_(0x1) << USBC_UECON0CLR_RXSTPEC_Pos) 3241 #define USBC_UECON0CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON0CLR) NAKOUTE Clear */ 3242 #define USBC_UECON0CLR_NAKOUTEC (_U_(0x1) << USBC_UECON0CLR_NAKOUTEC_Pos) 3243 #define USBC_UECON0CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON0CLR) NAKINE Clear */ 3244 #define USBC_UECON0CLR_NAKINEC (_U_(0x1) << USBC_UECON0CLR_NAKINEC_Pos) 3245 #define USBC_UECON0CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON0CLR) STALLEDE Clear */ 3246 #define USBC_UECON0CLR_STALLEDEC (_U_(0x1) << USBC_UECON0CLR_STALLEDEC_Pos) 3247 #define USBC_UECON0CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON0CLR) NREPLY Clear */ 3248 #define USBC_UECON0CLR_NREPLYC (_U_(0x1) << USBC_UECON0CLR_NREPLYC_Pos) 3249 #define USBC_UECON0CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON0CLR) RAMACERE Clear */ 3250 #define USBC_UECON0CLR_RAMACEREC (_U_(0x1) << USBC_UECON0CLR_RAMACEREC_Pos) 3251 #define USBC_UECON0CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON0CLR) NBUSYBKE Clear */ 3252 #define USBC_UECON0CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON0CLR_NBUSYBKEC_Pos) 3253 #define USBC_UECON0CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON0CLR) FIFOCON Clear */ 3254 #define USBC_UECON0CLR_FIFOCONC (_U_(0x1) << USBC_UECON0CLR_FIFOCONC_Pos) 3255 #define USBC_UECON0CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON0CLR) NYETDIS Clear */ 3256 #define USBC_UECON0CLR_NYETDISC (_U_(0x1) << USBC_UECON0CLR_NYETDISC_Pos) 3257 #define USBC_UECON0CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON0CLR) STALLRQ Clear */ 3258 #define USBC_UECON0CLR_STALLRQC (_U_(0x1) << USBC_UECON0CLR_STALLRQC_Pos) 3259 #define USBC_UECON0CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON0CLR) BUSY0 Clear */ 3260 #define USBC_UECON0CLR_BUSY0C (_U_(0x1) << USBC_UECON0CLR_BUSY0C_Pos) 3261 #define USBC_UECON0CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON0CLR) BUSY1 Clear */ 3262 #define USBC_UECON0CLR_BUSY1C (_U_(0x1) << USBC_UECON0CLR_BUSY1C_Pos) 3263 #define USBC_UECON0CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON0CLR) MASK Register */ 3264 3265 /* -------- USBC_UECON1CLR : (USBC Offset: 0x224) ( /W 32) TXINE Clear -------- */ 3266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3267 typedef union { 3268 struct { 3269 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3270 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3271 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3272 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3273 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3274 uint32_t :1; /*!< bit: 5 Reserved */ 3275 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3276 uint32_t :1; /*!< bit: 7 Reserved */ 3277 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3278 uint32_t :2; /*!< bit: 9..10 Reserved */ 3279 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3280 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3281 uint32_t :1; /*!< bit: 13 Reserved */ 3282 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3283 uint32_t :2; /*!< bit: 15..16 Reserved */ 3284 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3285 uint32_t :1; /*!< bit: 18 Reserved */ 3286 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3287 uint32_t :4; /*!< bit: 20..23 Reserved */ 3288 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3289 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3290 uint32_t :6; /*!< bit: 26..31 Reserved */ 3291 } bit; /*!< Structure used for bit access */ 3292 uint32_t reg; /*!< Type used for register access */ 3293 } USBC_UECON1CLR_Type; 3294 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3295 3296 #define USBC_UECON1CLR_OFFSET 0x224 /**< \brief (USBC_UECON1CLR offset) TXINE Clear */ 3297 #define USBC_UECON1CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON1CLR reset_value) TXINE Clear */ 3298 3299 #define USBC_UECON1CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON1CLR) TXINE Clear */ 3300 #define USBC_UECON1CLR_TXINEC (_U_(0x1) << USBC_UECON1CLR_TXINEC_Pos) 3301 #define USBC_UECON1CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON1CLR) RXOUTE Clear */ 3302 #define USBC_UECON1CLR_RXOUTEC (_U_(0x1) << USBC_UECON1CLR_RXOUTEC_Pos) 3303 #define USBC_UECON1CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON1CLR) RXOUTE Clear */ 3304 #define USBC_UECON1CLR_RXSTPEC (_U_(0x1) << USBC_UECON1CLR_RXSTPEC_Pos) 3305 #define USBC_UECON1CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON1CLR) NAKOUTE Clear */ 3306 #define USBC_UECON1CLR_NAKOUTEC (_U_(0x1) << USBC_UECON1CLR_NAKOUTEC_Pos) 3307 #define USBC_UECON1CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON1CLR) NAKINE Clear */ 3308 #define USBC_UECON1CLR_NAKINEC (_U_(0x1) << USBC_UECON1CLR_NAKINEC_Pos) 3309 #define USBC_UECON1CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON1CLR) RXSTPE Clear */ 3310 #define USBC_UECON1CLR_STALLEDEC (_U_(0x1) << USBC_UECON1CLR_STALLEDEC_Pos) 3311 #define USBC_UECON1CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON1CLR) NREPLY Clear */ 3312 #define USBC_UECON1CLR_NREPLYC (_U_(0x1) << USBC_UECON1CLR_NREPLYC_Pos) 3313 #define USBC_UECON1CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON1CLR) RAMACERE Clear */ 3314 #define USBC_UECON1CLR_RAMACEREC (_U_(0x1) << USBC_UECON1CLR_RAMACEREC_Pos) 3315 #define USBC_UECON1CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON1CLR) NBUSYBKE Clear */ 3316 #define USBC_UECON1CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON1CLR_NBUSYBKEC_Pos) 3317 #define USBC_UECON1CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON1CLR) FIFOCON Clear */ 3318 #define USBC_UECON1CLR_FIFOCONC (_U_(0x1) << USBC_UECON1CLR_FIFOCONC_Pos) 3319 #define USBC_UECON1CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON1CLR) NYETDIS Clear */ 3320 #define USBC_UECON1CLR_NYETDISC (_U_(0x1) << USBC_UECON1CLR_NYETDISC_Pos) 3321 #define USBC_UECON1CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON1CLR) STALLEDE Clear */ 3322 #define USBC_UECON1CLR_STALLRQC (_U_(0x1) << USBC_UECON1CLR_STALLRQC_Pos) 3323 #define USBC_UECON1CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON1CLR) BUSY0 Clear */ 3324 #define USBC_UECON1CLR_BUSY0C (_U_(0x1) << USBC_UECON1CLR_BUSY0C_Pos) 3325 #define USBC_UECON1CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON1CLR) BUSY1 Clear */ 3326 #define USBC_UECON1CLR_BUSY1C (_U_(0x1) << USBC_UECON1CLR_BUSY1C_Pos) 3327 #define USBC_UECON1CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON1CLR) MASK Register */ 3328 3329 /* -------- USBC_UECON2CLR : (USBC Offset: 0x228) ( /W 32) TXINE Clear -------- */ 3330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3331 typedef union { 3332 struct { 3333 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3334 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3335 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3336 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3337 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3338 uint32_t :1; /*!< bit: 5 Reserved */ 3339 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3340 uint32_t :1; /*!< bit: 7 Reserved */ 3341 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3342 uint32_t :2; /*!< bit: 9..10 Reserved */ 3343 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3344 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3345 uint32_t :1; /*!< bit: 13 Reserved */ 3346 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3347 uint32_t :2; /*!< bit: 15..16 Reserved */ 3348 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3349 uint32_t :1; /*!< bit: 18 Reserved */ 3350 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3351 uint32_t :4; /*!< bit: 20..23 Reserved */ 3352 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3353 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3354 uint32_t :6; /*!< bit: 26..31 Reserved */ 3355 } bit; /*!< Structure used for bit access */ 3356 uint32_t reg; /*!< Type used for register access */ 3357 } USBC_UECON2CLR_Type; 3358 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3359 3360 #define USBC_UECON2CLR_OFFSET 0x228 /**< \brief (USBC_UECON2CLR offset) TXINE Clear */ 3361 #define USBC_UECON2CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON2CLR reset_value) TXINE Clear */ 3362 3363 #define USBC_UECON2CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON2CLR) TXINE Clear */ 3364 #define USBC_UECON2CLR_TXINEC (_U_(0x1) << USBC_UECON2CLR_TXINEC_Pos) 3365 #define USBC_UECON2CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON2CLR) RXOUTE Clear */ 3366 #define USBC_UECON2CLR_RXOUTEC (_U_(0x1) << USBC_UECON2CLR_RXOUTEC_Pos) 3367 #define USBC_UECON2CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON2CLR) RXOUTE Clear */ 3368 #define USBC_UECON2CLR_RXSTPEC (_U_(0x1) << USBC_UECON2CLR_RXSTPEC_Pos) 3369 #define USBC_UECON2CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON2CLR) NAKOUTE Clear */ 3370 #define USBC_UECON2CLR_NAKOUTEC (_U_(0x1) << USBC_UECON2CLR_NAKOUTEC_Pos) 3371 #define USBC_UECON2CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON2CLR) NAKINE Clear */ 3372 #define USBC_UECON2CLR_NAKINEC (_U_(0x1) << USBC_UECON2CLR_NAKINEC_Pos) 3373 #define USBC_UECON2CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON2CLR) RXSTPE Clear */ 3374 #define USBC_UECON2CLR_STALLEDEC (_U_(0x1) << USBC_UECON2CLR_STALLEDEC_Pos) 3375 #define USBC_UECON2CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON2CLR) NREPLY Clear */ 3376 #define USBC_UECON2CLR_NREPLYC (_U_(0x1) << USBC_UECON2CLR_NREPLYC_Pos) 3377 #define USBC_UECON2CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON2CLR) RAMACERE Clear */ 3378 #define USBC_UECON2CLR_RAMACEREC (_U_(0x1) << USBC_UECON2CLR_RAMACEREC_Pos) 3379 #define USBC_UECON2CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON2CLR) NBUSYBKE Clear */ 3380 #define USBC_UECON2CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON2CLR_NBUSYBKEC_Pos) 3381 #define USBC_UECON2CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON2CLR) FIFOCON Clear */ 3382 #define USBC_UECON2CLR_FIFOCONC (_U_(0x1) << USBC_UECON2CLR_FIFOCONC_Pos) 3383 #define USBC_UECON2CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON2CLR) NYETDIS Clear */ 3384 #define USBC_UECON2CLR_NYETDISC (_U_(0x1) << USBC_UECON2CLR_NYETDISC_Pos) 3385 #define USBC_UECON2CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON2CLR) STALLEDE Clear */ 3386 #define USBC_UECON2CLR_STALLRQC (_U_(0x1) << USBC_UECON2CLR_STALLRQC_Pos) 3387 #define USBC_UECON2CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON2CLR) BUSY0 Clear */ 3388 #define USBC_UECON2CLR_BUSY0C (_U_(0x1) << USBC_UECON2CLR_BUSY0C_Pos) 3389 #define USBC_UECON2CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON2CLR) BUSY1 Clear */ 3390 #define USBC_UECON2CLR_BUSY1C (_U_(0x1) << USBC_UECON2CLR_BUSY1C_Pos) 3391 #define USBC_UECON2CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON2CLR) MASK Register */ 3392 3393 /* -------- USBC_UECON3CLR : (USBC Offset: 0x22C) ( /W 32) TXINE Clear -------- */ 3394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3395 typedef union { 3396 struct { 3397 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3398 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3399 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3400 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3401 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3402 uint32_t :1; /*!< bit: 5 Reserved */ 3403 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3404 uint32_t :1; /*!< bit: 7 Reserved */ 3405 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3406 uint32_t :2; /*!< bit: 9..10 Reserved */ 3407 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3408 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3409 uint32_t :1; /*!< bit: 13 Reserved */ 3410 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3411 uint32_t :2; /*!< bit: 15..16 Reserved */ 3412 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3413 uint32_t :1; /*!< bit: 18 Reserved */ 3414 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3415 uint32_t :4; /*!< bit: 20..23 Reserved */ 3416 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3417 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3418 uint32_t :6; /*!< bit: 26..31 Reserved */ 3419 } bit; /*!< Structure used for bit access */ 3420 uint32_t reg; /*!< Type used for register access */ 3421 } USBC_UECON3CLR_Type; 3422 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3423 3424 #define USBC_UECON3CLR_OFFSET 0x22C /**< \brief (USBC_UECON3CLR offset) TXINE Clear */ 3425 #define USBC_UECON3CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON3CLR reset_value) TXINE Clear */ 3426 3427 #define USBC_UECON3CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON3CLR) TXINE Clear */ 3428 #define USBC_UECON3CLR_TXINEC (_U_(0x1) << USBC_UECON3CLR_TXINEC_Pos) 3429 #define USBC_UECON3CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON3CLR) RXOUTE Clear */ 3430 #define USBC_UECON3CLR_RXOUTEC (_U_(0x1) << USBC_UECON3CLR_RXOUTEC_Pos) 3431 #define USBC_UECON3CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON3CLR) RXOUTE Clear */ 3432 #define USBC_UECON3CLR_RXSTPEC (_U_(0x1) << USBC_UECON3CLR_RXSTPEC_Pos) 3433 #define USBC_UECON3CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON3CLR) NAKOUTE Clear */ 3434 #define USBC_UECON3CLR_NAKOUTEC (_U_(0x1) << USBC_UECON3CLR_NAKOUTEC_Pos) 3435 #define USBC_UECON3CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON3CLR) NAKINE Clear */ 3436 #define USBC_UECON3CLR_NAKINEC (_U_(0x1) << USBC_UECON3CLR_NAKINEC_Pos) 3437 #define USBC_UECON3CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON3CLR) RXSTPE Clear */ 3438 #define USBC_UECON3CLR_STALLEDEC (_U_(0x1) << USBC_UECON3CLR_STALLEDEC_Pos) 3439 #define USBC_UECON3CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON3CLR) NREPLY Clear */ 3440 #define USBC_UECON3CLR_NREPLYC (_U_(0x1) << USBC_UECON3CLR_NREPLYC_Pos) 3441 #define USBC_UECON3CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON3CLR) RAMACERE Clear */ 3442 #define USBC_UECON3CLR_RAMACEREC (_U_(0x1) << USBC_UECON3CLR_RAMACEREC_Pos) 3443 #define USBC_UECON3CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON3CLR) NBUSYBKE Clear */ 3444 #define USBC_UECON3CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON3CLR_NBUSYBKEC_Pos) 3445 #define USBC_UECON3CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON3CLR) FIFOCON Clear */ 3446 #define USBC_UECON3CLR_FIFOCONC (_U_(0x1) << USBC_UECON3CLR_FIFOCONC_Pos) 3447 #define USBC_UECON3CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON3CLR) NYETDIS Clear */ 3448 #define USBC_UECON3CLR_NYETDISC (_U_(0x1) << USBC_UECON3CLR_NYETDISC_Pos) 3449 #define USBC_UECON3CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON3CLR) STALLEDE Clear */ 3450 #define USBC_UECON3CLR_STALLRQC (_U_(0x1) << USBC_UECON3CLR_STALLRQC_Pos) 3451 #define USBC_UECON3CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON3CLR) BUSY0 Clear */ 3452 #define USBC_UECON3CLR_BUSY0C (_U_(0x1) << USBC_UECON3CLR_BUSY0C_Pos) 3453 #define USBC_UECON3CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON3CLR) BUSY1 Clear */ 3454 #define USBC_UECON3CLR_BUSY1C (_U_(0x1) << USBC_UECON3CLR_BUSY1C_Pos) 3455 #define USBC_UECON3CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON3CLR) MASK Register */ 3456 3457 /* -------- USBC_UECON4CLR : (USBC Offset: 0x230) ( /W 32) TXINE Clear -------- */ 3458 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3459 typedef union { 3460 struct { 3461 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3462 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3463 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3464 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3465 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3466 uint32_t :1; /*!< bit: 5 Reserved */ 3467 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3468 uint32_t :1; /*!< bit: 7 Reserved */ 3469 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3470 uint32_t :2; /*!< bit: 9..10 Reserved */ 3471 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3472 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3473 uint32_t :1; /*!< bit: 13 Reserved */ 3474 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3475 uint32_t :2; /*!< bit: 15..16 Reserved */ 3476 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3477 uint32_t :1; /*!< bit: 18 Reserved */ 3478 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3479 uint32_t :4; /*!< bit: 20..23 Reserved */ 3480 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3481 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3482 uint32_t :6; /*!< bit: 26..31 Reserved */ 3483 } bit; /*!< Structure used for bit access */ 3484 uint32_t reg; /*!< Type used for register access */ 3485 } USBC_UECON4CLR_Type; 3486 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3487 3488 #define USBC_UECON4CLR_OFFSET 0x230 /**< \brief (USBC_UECON4CLR offset) TXINE Clear */ 3489 #define USBC_UECON4CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON4CLR reset_value) TXINE Clear */ 3490 3491 #define USBC_UECON4CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON4CLR) TXINE Clear */ 3492 #define USBC_UECON4CLR_TXINEC (_U_(0x1) << USBC_UECON4CLR_TXINEC_Pos) 3493 #define USBC_UECON4CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON4CLR) RXOUTE Clear */ 3494 #define USBC_UECON4CLR_RXOUTEC (_U_(0x1) << USBC_UECON4CLR_RXOUTEC_Pos) 3495 #define USBC_UECON4CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON4CLR) RXOUTE Clear */ 3496 #define USBC_UECON4CLR_RXSTPEC (_U_(0x1) << USBC_UECON4CLR_RXSTPEC_Pos) 3497 #define USBC_UECON4CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON4CLR) NAKOUTE Clear */ 3498 #define USBC_UECON4CLR_NAKOUTEC (_U_(0x1) << USBC_UECON4CLR_NAKOUTEC_Pos) 3499 #define USBC_UECON4CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON4CLR) NAKINE Clear */ 3500 #define USBC_UECON4CLR_NAKINEC (_U_(0x1) << USBC_UECON4CLR_NAKINEC_Pos) 3501 #define USBC_UECON4CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON4CLR) RXSTPE Clear */ 3502 #define USBC_UECON4CLR_STALLEDEC (_U_(0x1) << USBC_UECON4CLR_STALLEDEC_Pos) 3503 #define USBC_UECON4CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON4CLR) NREPLY Clear */ 3504 #define USBC_UECON4CLR_NREPLYC (_U_(0x1) << USBC_UECON4CLR_NREPLYC_Pos) 3505 #define USBC_UECON4CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON4CLR) RAMACERE Clear */ 3506 #define USBC_UECON4CLR_RAMACEREC (_U_(0x1) << USBC_UECON4CLR_RAMACEREC_Pos) 3507 #define USBC_UECON4CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON4CLR) NBUSYBKE Clear */ 3508 #define USBC_UECON4CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON4CLR_NBUSYBKEC_Pos) 3509 #define USBC_UECON4CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON4CLR) FIFOCON Clear */ 3510 #define USBC_UECON4CLR_FIFOCONC (_U_(0x1) << USBC_UECON4CLR_FIFOCONC_Pos) 3511 #define USBC_UECON4CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON4CLR) NYETDIS Clear */ 3512 #define USBC_UECON4CLR_NYETDISC (_U_(0x1) << USBC_UECON4CLR_NYETDISC_Pos) 3513 #define USBC_UECON4CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON4CLR) STALLEDE Clear */ 3514 #define USBC_UECON4CLR_STALLRQC (_U_(0x1) << USBC_UECON4CLR_STALLRQC_Pos) 3515 #define USBC_UECON4CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON4CLR) BUSY0 Clear */ 3516 #define USBC_UECON4CLR_BUSY0C (_U_(0x1) << USBC_UECON4CLR_BUSY0C_Pos) 3517 #define USBC_UECON4CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON4CLR) BUSY1 Clear */ 3518 #define USBC_UECON4CLR_BUSY1C (_U_(0x1) << USBC_UECON4CLR_BUSY1C_Pos) 3519 #define USBC_UECON4CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON4CLR) MASK Register */ 3520 3521 /* -------- USBC_UECON5CLR : (USBC Offset: 0x234) ( /W 32) TXINE Clear -------- */ 3522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3523 typedef union { 3524 struct { 3525 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3526 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3527 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3528 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3529 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3530 uint32_t :1; /*!< bit: 5 Reserved */ 3531 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3532 uint32_t :1; /*!< bit: 7 Reserved */ 3533 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3534 uint32_t :2; /*!< bit: 9..10 Reserved */ 3535 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3536 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3537 uint32_t :1; /*!< bit: 13 Reserved */ 3538 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3539 uint32_t :2; /*!< bit: 15..16 Reserved */ 3540 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3541 uint32_t :1; /*!< bit: 18 Reserved */ 3542 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3543 uint32_t :4; /*!< bit: 20..23 Reserved */ 3544 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3545 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3546 uint32_t :6; /*!< bit: 26..31 Reserved */ 3547 } bit; /*!< Structure used for bit access */ 3548 uint32_t reg; /*!< Type used for register access */ 3549 } USBC_UECON5CLR_Type; 3550 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3551 3552 #define USBC_UECON5CLR_OFFSET 0x234 /**< \brief (USBC_UECON5CLR offset) TXINE Clear */ 3553 #define USBC_UECON5CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON5CLR reset_value) TXINE Clear */ 3554 3555 #define USBC_UECON5CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON5CLR) TXINE Clear */ 3556 #define USBC_UECON5CLR_TXINEC (_U_(0x1) << USBC_UECON5CLR_TXINEC_Pos) 3557 #define USBC_UECON5CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON5CLR) RXOUTE Clear */ 3558 #define USBC_UECON5CLR_RXOUTEC (_U_(0x1) << USBC_UECON5CLR_RXOUTEC_Pos) 3559 #define USBC_UECON5CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON5CLR) RXOUTE Clear */ 3560 #define USBC_UECON5CLR_RXSTPEC (_U_(0x1) << USBC_UECON5CLR_RXSTPEC_Pos) 3561 #define USBC_UECON5CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON5CLR) NAKOUTE Clear */ 3562 #define USBC_UECON5CLR_NAKOUTEC (_U_(0x1) << USBC_UECON5CLR_NAKOUTEC_Pos) 3563 #define USBC_UECON5CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON5CLR) NAKINE Clear */ 3564 #define USBC_UECON5CLR_NAKINEC (_U_(0x1) << USBC_UECON5CLR_NAKINEC_Pos) 3565 #define USBC_UECON5CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON5CLR) RXSTPE Clear */ 3566 #define USBC_UECON5CLR_STALLEDEC (_U_(0x1) << USBC_UECON5CLR_STALLEDEC_Pos) 3567 #define USBC_UECON5CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON5CLR) NREPLY Clear */ 3568 #define USBC_UECON5CLR_NREPLYC (_U_(0x1) << USBC_UECON5CLR_NREPLYC_Pos) 3569 #define USBC_UECON5CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON5CLR) RAMACERE Clear */ 3570 #define USBC_UECON5CLR_RAMACEREC (_U_(0x1) << USBC_UECON5CLR_RAMACEREC_Pos) 3571 #define USBC_UECON5CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON5CLR) NBUSYBKE Clear */ 3572 #define USBC_UECON5CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON5CLR_NBUSYBKEC_Pos) 3573 #define USBC_UECON5CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON5CLR) FIFOCON Clear */ 3574 #define USBC_UECON5CLR_FIFOCONC (_U_(0x1) << USBC_UECON5CLR_FIFOCONC_Pos) 3575 #define USBC_UECON5CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON5CLR) NYETDIS Clear */ 3576 #define USBC_UECON5CLR_NYETDISC (_U_(0x1) << USBC_UECON5CLR_NYETDISC_Pos) 3577 #define USBC_UECON5CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON5CLR) STALLEDE Clear */ 3578 #define USBC_UECON5CLR_STALLRQC (_U_(0x1) << USBC_UECON5CLR_STALLRQC_Pos) 3579 #define USBC_UECON5CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON5CLR) BUSY0 Clear */ 3580 #define USBC_UECON5CLR_BUSY0C (_U_(0x1) << USBC_UECON5CLR_BUSY0C_Pos) 3581 #define USBC_UECON5CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON5CLR) BUSY1 Clear */ 3582 #define USBC_UECON5CLR_BUSY1C (_U_(0x1) << USBC_UECON5CLR_BUSY1C_Pos) 3583 #define USBC_UECON5CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON5CLR) MASK Register */ 3584 3585 /* -------- USBC_UECON6CLR : (USBC Offset: 0x238) ( /W 32) TXINE Clear -------- */ 3586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3587 typedef union { 3588 struct { 3589 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3590 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3591 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3592 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3593 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3594 uint32_t :1; /*!< bit: 5 Reserved */ 3595 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3596 uint32_t :1; /*!< bit: 7 Reserved */ 3597 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3598 uint32_t :2; /*!< bit: 9..10 Reserved */ 3599 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3600 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3601 uint32_t :1; /*!< bit: 13 Reserved */ 3602 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3603 uint32_t :2; /*!< bit: 15..16 Reserved */ 3604 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3605 uint32_t :1; /*!< bit: 18 Reserved */ 3606 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3607 uint32_t :4; /*!< bit: 20..23 Reserved */ 3608 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3609 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3610 uint32_t :6; /*!< bit: 26..31 Reserved */ 3611 } bit; /*!< Structure used for bit access */ 3612 uint32_t reg; /*!< Type used for register access */ 3613 } USBC_UECON6CLR_Type; 3614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3615 3616 #define USBC_UECON6CLR_OFFSET 0x238 /**< \brief (USBC_UECON6CLR offset) TXINE Clear */ 3617 #define USBC_UECON6CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON6CLR reset_value) TXINE Clear */ 3618 3619 #define USBC_UECON6CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON6CLR) TXINE Clear */ 3620 #define USBC_UECON6CLR_TXINEC (_U_(0x1) << USBC_UECON6CLR_TXINEC_Pos) 3621 #define USBC_UECON6CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON6CLR) RXOUTE Clear */ 3622 #define USBC_UECON6CLR_RXOUTEC (_U_(0x1) << USBC_UECON6CLR_RXOUTEC_Pos) 3623 #define USBC_UECON6CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON6CLR) RXOUTE Clear */ 3624 #define USBC_UECON6CLR_RXSTPEC (_U_(0x1) << USBC_UECON6CLR_RXSTPEC_Pos) 3625 #define USBC_UECON6CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON6CLR) NAKOUTE Clear */ 3626 #define USBC_UECON6CLR_NAKOUTEC (_U_(0x1) << USBC_UECON6CLR_NAKOUTEC_Pos) 3627 #define USBC_UECON6CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON6CLR) NAKINE Clear */ 3628 #define USBC_UECON6CLR_NAKINEC (_U_(0x1) << USBC_UECON6CLR_NAKINEC_Pos) 3629 #define USBC_UECON6CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON6CLR) RXSTPE Clear */ 3630 #define USBC_UECON6CLR_STALLEDEC (_U_(0x1) << USBC_UECON6CLR_STALLEDEC_Pos) 3631 #define USBC_UECON6CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON6CLR) NREPLY Clear */ 3632 #define USBC_UECON6CLR_NREPLYC (_U_(0x1) << USBC_UECON6CLR_NREPLYC_Pos) 3633 #define USBC_UECON6CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON6CLR) RAMACERE Clear */ 3634 #define USBC_UECON6CLR_RAMACEREC (_U_(0x1) << USBC_UECON6CLR_RAMACEREC_Pos) 3635 #define USBC_UECON6CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON6CLR) NBUSYBKE Clear */ 3636 #define USBC_UECON6CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON6CLR_NBUSYBKEC_Pos) 3637 #define USBC_UECON6CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON6CLR) FIFOCON Clear */ 3638 #define USBC_UECON6CLR_FIFOCONC (_U_(0x1) << USBC_UECON6CLR_FIFOCONC_Pos) 3639 #define USBC_UECON6CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON6CLR) NYETDIS Clear */ 3640 #define USBC_UECON6CLR_NYETDISC (_U_(0x1) << USBC_UECON6CLR_NYETDISC_Pos) 3641 #define USBC_UECON6CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON6CLR) STALLEDE Clear */ 3642 #define USBC_UECON6CLR_STALLRQC (_U_(0x1) << USBC_UECON6CLR_STALLRQC_Pos) 3643 #define USBC_UECON6CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON6CLR) BUSY0 Clear */ 3644 #define USBC_UECON6CLR_BUSY0C (_U_(0x1) << USBC_UECON6CLR_BUSY0C_Pos) 3645 #define USBC_UECON6CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON6CLR) BUSY1 Clear */ 3646 #define USBC_UECON6CLR_BUSY1C (_U_(0x1) << USBC_UECON6CLR_BUSY1C_Pos) 3647 #define USBC_UECON6CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON6CLR) MASK Register */ 3648 3649 /* -------- USBC_UECON7CLR : (USBC Offset: 0x23C) ( /W 32) TXINE Clear -------- */ 3650 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3651 typedef union { 3652 struct { 3653 uint32_t TXINEC:1; /*!< bit: 0 TXINE Clear */ 3654 uint32_t RXOUTEC:1; /*!< bit: 1 RXOUTE Clear */ 3655 uint32_t RXSTPEC:1; /*!< bit: 2 RXOUTE Clear */ 3656 uint32_t NAKOUTEC:1; /*!< bit: 3 NAKOUTE Clear */ 3657 uint32_t NAKINEC:1; /*!< bit: 4 NAKINE Clear */ 3658 uint32_t :1; /*!< bit: 5 Reserved */ 3659 uint32_t STALLEDEC:1; /*!< bit: 6 RXSTPE Clear */ 3660 uint32_t :1; /*!< bit: 7 Reserved */ 3661 uint32_t NREPLYC:1; /*!< bit: 8 NREPLY Clear */ 3662 uint32_t :2; /*!< bit: 9..10 Reserved */ 3663 uint32_t RAMACEREC:1; /*!< bit: 11 RAMACERE Clear */ 3664 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 3665 uint32_t :1; /*!< bit: 13 Reserved */ 3666 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 3667 uint32_t :2; /*!< bit: 15..16 Reserved */ 3668 uint32_t NYETDISC:1; /*!< bit: 17 NYETDIS Clear */ 3669 uint32_t :1; /*!< bit: 18 Reserved */ 3670 uint32_t STALLRQC:1; /*!< bit: 19 STALLEDE Clear */ 3671 uint32_t :4; /*!< bit: 20..23 Reserved */ 3672 uint32_t BUSY0C:1; /*!< bit: 24 BUSY0 Clear */ 3673 uint32_t BUSY1C:1; /*!< bit: 25 BUSY1 Clear */ 3674 uint32_t :6; /*!< bit: 26..31 Reserved */ 3675 } bit; /*!< Structure used for bit access */ 3676 uint32_t reg; /*!< Type used for register access */ 3677 } USBC_UECON7CLR_Type; 3678 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3679 3680 #define USBC_UECON7CLR_OFFSET 0x23C /**< \brief (USBC_UECON7CLR offset) TXINE Clear */ 3681 #define USBC_UECON7CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UECON7CLR reset_value) TXINE Clear */ 3682 3683 #define USBC_UECON7CLR_TXINEC_Pos 0 /**< \brief (USBC_UECON7CLR) TXINE Clear */ 3684 #define USBC_UECON7CLR_TXINEC (_U_(0x1) << USBC_UECON7CLR_TXINEC_Pos) 3685 #define USBC_UECON7CLR_RXOUTEC_Pos 1 /**< \brief (USBC_UECON7CLR) RXOUTE Clear */ 3686 #define USBC_UECON7CLR_RXOUTEC (_U_(0x1) << USBC_UECON7CLR_RXOUTEC_Pos) 3687 #define USBC_UECON7CLR_RXSTPEC_Pos 2 /**< \brief (USBC_UECON7CLR) RXOUTE Clear */ 3688 #define USBC_UECON7CLR_RXSTPEC (_U_(0x1) << USBC_UECON7CLR_RXSTPEC_Pos) 3689 #define USBC_UECON7CLR_NAKOUTEC_Pos 3 /**< \brief (USBC_UECON7CLR) NAKOUTE Clear */ 3690 #define USBC_UECON7CLR_NAKOUTEC (_U_(0x1) << USBC_UECON7CLR_NAKOUTEC_Pos) 3691 #define USBC_UECON7CLR_NAKINEC_Pos 4 /**< \brief (USBC_UECON7CLR) NAKINE Clear */ 3692 #define USBC_UECON7CLR_NAKINEC (_U_(0x1) << USBC_UECON7CLR_NAKINEC_Pos) 3693 #define USBC_UECON7CLR_STALLEDEC_Pos 6 /**< \brief (USBC_UECON7CLR) RXSTPE Clear */ 3694 #define USBC_UECON7CLR_STALLEDEC (_U_(0x1) << USBC_UECON7CLR_STALLEDEC_Pos) 3695 #define USBC_UECON7CLR_NREPLYC_Pos 8 /**< \brief (USBC_UECON7CLR) NREPLY Clear */ 3696 #define USBC_UECON7CLR_NREPLYC (_U_(0x1) << USBC_UECON7CLR_NREPLYC_Pos) 3697 #define USBC_UECON7CLR_RAMACEREC_Pos 11 /**< \brief (USBC_UECON7CLR) RAMACERE Clear */ 3698 #define USBC_UECON7CLR_RAMACEREC (_U_(0x1) << USBC_UECON7CLR_RAMACEREC_Pos) 3699 #define USBC_UECON7CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UECON7CLR) NBUSYBKE Clear */ 3700 #define USBC_UECON7CLR_NBUSYBKEC (_U_(0x1) << USBC_UECON7CLR_NBUSYBKEC_Pos) 3701 #define USBC_UECON7CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UECON7CLR) FIFOCON Clear */ 3702 #define USBC_UECON7CLR_FIFOCONC (_U_(0x1) << USBC_UECON7CLR_FIFOCONC_Pos) 3703 #define USBC_UECON7CLR_NYETDISC_Pos 17 /**< \brief (USBC_UECON7CLR) NYETDIS Clear */ 3704 #define USBC_UECON7CLR_NYETDISC (_U_(0x1) << USBC_UECON7CLR_NYETDISC_Pos) 3705 #define USBC_UECON7CLR_STALLRQC_Pos 19 /**< \brief (USBC_UECON7CLR) STALLEDE Clear */ 3706 #define USBC_UECON7CLR_STALLRQC (_U_(0x1) << USBC_UECON7CLR_STALLRQC_Pos) 3707 #define USBC_UECON7CLR_BUSY0C_Pos 24 /**< \brief (USBC_UECON7CLR) BUSY0 Clear */ 3708 #define USBC_UECON7CLR_BUSY0C (_U_(0x1) << USBC_UECON7CLR_BUSY0C_Pos) 3709 #define USBC_UECON7CLR_BUSY1C_Pos 25 /**< \brief (USBC_UECON7CLR) BUSY1 Clear */ 3710 #define USBC_UECON7CLR_BUSY1C (_U_(0x1) << USBC_UECON7CLR_BUSY1C_Pos) 3711 #define USBC_UECON7CLR_MASK _U_(0x030A595F) /**< \brief (USBC_UECON7CLR) MASK Register */ 3712 3713 /* -------- USBC_UHCON : (USBC Offset: 0x400) (R/W 32) Host General Control Register -------- */ 3714 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3715 typedef union { 3716 struct { 3717 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 3718 uint32_t SOFE:1; /*!< bit: 8 SOF Enable */ 3719 uint32_t RESET:1; /*!< bit: 9 Send USB Reset */ 3720 uint32_t RESUME:1; /*!< bit: 10 Send USB Resume */ 3721 uint32_t :1; /*!< bit: 11 Reserved */ 3722 uint32_t SPDCONF:2; /*!< bit: 12..13 Speed Configuration */ 3723 uint32_t :2; /*!< bit: 14..15 Reserved */ 3724 uint32_t TSTJ:1; /*!< bit: 16 Test J */ 3725 uint32_t TSTK:1; /*!< bit: 17 Test K */ 3726 uint32_t :14; /*!< bit: 18..31 Reserved */ 3727 } bit; /*!< Structure used for bit access */ 3728 uint32_t reg; /*!< Type used for register access */ 3729 } USBC_UHCON_Type; 3730 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3731 3732 #define USBC_UHCON_OFFSET 0x400 /**< \brief (USBC_UHCON offset) Host General Control Register */ 3733 #define USBC_UHCON_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHCON reset_value) Host General Control Register */ 3734 3735 #define USBC_UHCON_SOFE_Pos 8 /**< \brief (USBC_UHCON) SOF Enable */ 3736 #define USBC_UHCON_SOFE (_U_(0x1) << USBC_UHCON_SOFE_Pos) 3737 #define USBC_UHCON_RESET_Pos 9 /**< \brief (USBC_UHCON) Send USB Reset */ 3738 #define USBC_UHCON_RESET (_U_(0x1) << USBC_UHCON_RESET_Pos) 3739 #define USBC_UHCON_RESUME_Pos 10 /**< \brief (USBC_UHCON) Send USB Resume */ 3740 #define USBC_UHCON_RESUME (_U_(0x1) << USBC_UHCON_RESUME_Pos) 3741 #define USBC_UHCON_SPDCONF_Pos 12 /**< \brief (USBC_UHCON) Speed Configuration */ 3742 #define USBC_UHCON_SPDCONF_Msk (_U_(0x3) << USBC_UHCON_SPDCONF_Pos) 3743 #define USBC_UHCON_SPDCONF(value) (USBC_UHCON_SPDCONF_Msk & ((value) << USBC_UHCON_SPDCONF_Pos)) 3744 #define USBC_UHCON_TSTJ_Pos 16 /**< \brief (USBC_UHCON) Test J */ 3745 #define USBC_UHCON_TSTJ (_U_(0x1) << USBC_UHCON_TSTJ_Pos) 3746 #define USBC_UHCON_TSTK_Pos 17 /**< \brief (USBC_UHCON) Test K */ 3747 #define USBC_UHCON_TSTK (_U_(0x1) << USBC_UHCON_TSTK_Pos) 3748 #define USBC_UHCON_MASK _U_(0x00033700) /**< \brief (USBC_UHCON) MASK Register */ 3749 3750 /* -------- USBC_UHINT : (USBC Offset: 0x404) (R/ 32) Host Global Interrupt Register -------- */ 3751 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3752 typedef union { 3753 struct { 3754 uint32_t DCONNI:1; /*!< bit: 0 Device Connection Interrupt */ 3755 uint32_t DDISCI:1; /*!< bit: 1 Device Disconnection Interrupt */ 3756 uint32_t RSTI:1; /*!< bit: 2 USB Reset Sent Interrupt */ 3757 uint32_t RSMEDI:1; /*!< bit: 3 Downstream Resume Sent Interrupt */ 3758 uint32_t RXRSMI:1; /*!< bit: 4 Upstream Resume Received Interrupt */ 3759 uint32_t HSOFI:1; /*!< bit: 5 Host SOF Interrupt */ 3760 uint32_t HWUPI:1; /*!< bit: 6 Host Wake-Up Interrupt */ 3761 uint32_t :1; /*!< bit: 7 Reserved */ 3762 uint32_t P0INT:1; /*!< bit: 8 Pipe 0 Interrupt */ 3763 uint32_t P1INT:1; /*!< bit: 9 Pipe 1 Interrupt */ 3764 uint32_t P2INT:1; /*!< bit: 10 Pipe 2 Interrupt */ 3765 uint32_t P3INT:1; /*!< bit: 11 Pipe 3 Interrupt */ 3766 uint32_t P4INT:1; /*!< bit: 12 Pipe 4 Interrupt */ 3767 uint32_t P5INT:1; /*!< bit: 13 Pipe 5 Interrupt */ 3768 uint32_t P6INT:1; /*!< bit: 14 Pipe 6 Interrupt */ 3769 uint32_t :17; /*!< bit: 15..31 Reserved */ 3770 } bit; /*!< Structure used for bit access */ 3771 uint32_t reg; /*!< Type used for register access */ 3772 } USBC_UHINT_Type; 3773 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3774 3775 #define USBC_UHINT_OFFSET 0x404 /**< \brief (USBC_UHINT offset) Host Global Interrupt Register */ 3776 #define USBC_UHINT_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINT reset_value) Host Global Interrupt Register */ 3777 3778 #define USBC_UHINT_DCONNI_Pos 0 /**< \brief (USBC_UHINT) Device Connection Interrupt */ 3779 #define USBC_UHINT_DCONNI (_U_(0x1) << USBC_UHINT_DCONNI_Pos) 3780 #define USBC_UHINT_DDISCI_Pos 1 /**< \brief (USBC_UHINT) Device Disconnection Interrupt */ 3781 #define USBC_UHINT_DDISCI (_U_(0x1) << USBC_UHINT_DDISCI_Pos) 3782 #define USBC_UHINT_RSTI_Pos 2 /**< \brief (USBC_UHINT) USB Reset Sent Interrupt */ 3783 #define USBC_UHINT_RSTI (_U_(0x1) << USBC_UHINT_RSTI_Pos) 3784 #define USBC_UHINT_RSMEDI_Pos 3 /**< \brief (USBC_UHINT) Downstream Resume Sent Interrupt */ 3785 #define USBC_UHINT_RSMEDI (_U_(0x1) << USBC_UHINT_RSMEDI_Pos) 3786 #define USBC_UHINT_RXRSMI_Pos 4 /**< \brief (USBC_UHINT) Upstream Resume Received Interrupt */ 3787 #define USBC_UHINT_RXRSMI (_U_(0x1) << USBC_UHINT_RXRSMI_Pos) 3788 #define USBC_UHINT_HSOFI_Pos 5 /**< \brief (USBC_UHINT) Host SOF Interrupt */ 3789 #define USBC_UHINT_HSOFI (_U_(0x1) << USBC_UHINT_HSOFI_Pos) 3790 #define USBC_UHINT_HWUPI_Pos 6 /**< \brief (USBC_UHINT) Host Wake-Up Interrupt */ 3791 #define USBC_UHINT_HWUPI (_U_(0x1) << USBC_UHINT_HWUPI_Pos) 3792 #define USBC_UHINT_P0INT_Pos 8 /**< \brief (USBC_UHINT) Pipe 0 Interrupt */ 3793 #define USBC_UHINT_P0INT (_U_(0x1) << USBC_UHINT_P0INT_Pos) 3794 #define USBC_UHINT_P1INT_Pos 9 /**< \brief (USBC_UHINT) Pipe 1 Interrupt */ 3795 #define USBC_UHINT_P1INT (_U_(0x1) << USBC_UHINT_P1INT_Pos) 3796 #define USBC_UHINT_P2INT_Pos 10 /**< \brief (USBC_UHINT) Pipe 2 Interrupt */ 3797 #define USBC_UHINT_P2INT (_U_(0x1) << USBC_UHINT_P2INT_Pos) 3798 #define USBC_UHINT_P3INT_Pos 11 /**< \brief (USBC_UHINT) Pipe 3 Interrupt */ 3799 #define USBC_UHINT_P3INT (_U_(0x1) << USBC_UHINT_P3INT_Pos) 3800 #define USBC_UHINT_P4INT_Pos 12 /**< \brief (USBC_UHINT) Pipe 4 Interrupt */ 3801 #define USBC_UHINT_P4INT (_U_(0x1) << USBC_UHINT_P4INT_Pos) 3802 #define USBC_UHINT_P5INT_Pos 13 /**< \brief (USBC_UHINT) Pipe 5 Interrupt */ 3803 #define USBC_UHINT_P5INT (_U_(0x1) << USBC_UHINT_P5INT_Pos) 3804 #define USBC_UHINT_P6INT_Pos 14 /**< \brief (USBC_UHINT) Pipe 6 Interrupt */ 3805 #define USBC_UHINT_P6INT (_U_(0x1) << USBC_UHINT_P6INT_Pos) 3806 #define USBC_UHINT_MASK _U_(0x00007F7F) /**< \brief (USBC_UHINT) MASK Register */ 3807 3808 /* -------- USBC_UHINTCLR : (USBC Offset: 0x408) ( /W 32) Host Global Interrrupt Clear Register -------- */ 3809 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3810 typedef union { 3811 struct { 3812 uint32_t DCONNIC:1; /*!< bit: 0 DCONNI Clear */ 3813 uint32_t DDISCIC:1; /*!< bit: 1 DDISCI Clear */ 3814 uint32_t RSTIC:1; /*!< bit: 2 RSTI Clear */ 3815 uint32_t RSMEDIC:1; /*!< bit: 3 RSMEDI Clear */ 3816 uint32_t RXRSMIC:1; /*!< bit: 4 RXRSMI Clear */ 3817 uint32_t HSOFIC:1; /*!< bit: 5 HSOFI Clear */ 3818 uint32_t HWUPIC:1; /*!< bit: 6 HWUPI Clear */ 3819 uint32_t :25; /*!< bit: 7..31 Reserved */ 3820 } bit; /*!< Structure used for bit access */ 3821 uint32_t reg; /*!< Type used for register access */ 3822 } USBC_UHINTCLR_Type; 3823 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3824 3825 #define USBC_UHINTCLR_OFFSET 0x408 /**< \brief (USBC_UHINTCLR offset) Host Global Interrrupt Clear Register */ 3826 #define USBC_UHINTCLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINTCLR reset_value) Host Global Interrrupt Clear Register */ 3827 3828 #define USBC_UHINTCLR_DCONNIC_Pos 0 /**< \brief (USBC_UHINTCLR) DCONNI Clear */ 3829 #define USBC_UHINTCLR_DCONNIC (_U_(0x1) << USBC_UHINTCLR_DCONNIC_Pos) 3830 #define USBC_UHINTCLR_DDISCIC_Pos 1 /**< \brief (USBC_UHINTCLR) DDISCI Clear */ 3831 #define USBC_UHINTCLR_DDISCIC (_U_(0x1) << USBC_UHINTCLR_DDISCIC_Pos) 3832 #define USBC_UHINTCLR_RSTIC_Pos 2 /**< \brief (USBC_UHINTCLR) RSTI Clear */ 3833 #define USBC_UHINTCLR_RSTIC (_U_(0x1) << USBC_UHINTCLR_RSTIC_Pos) 3834 #define USBC_UHINTCLR_RSMEDIC_Pos 3 /**< \brief (USBC_UHINTCLR) RSMEDI Clear */ 3835 #define USBC_UHINTCLR_RSMEDIC (_U_(0x1) << USBC_UHINTCLR_RSMEDIC_Pos) 3836 #define USBC_UHINTCLR_RXRSMIC_Pos 4 /**< \brief (USBC_UHINTCLR) RXRSMI Clear */ 3837 #define USBC_UHINTCLR_RXRSMIC (_U_(0x1) << USBC_UHINTCLR_RXRSMIC_Pos) 3838 #define USBC_UHINTCLR_HSOFIC_Pos 5 /**< \brief (USBC_UHINTCLR) HSOFI Clear */ 3839 #define USBC_UHINTCLR_HSOFIC (_U_(0x1) << USBC_UHINTCLR_HSOFIC_Pos) 3840 #define USBC_UHINTCLR_HWUPIC_Pos 6 /**< \brief (USBC_UHINTCLR) HWUPI Clear */ 3841 #define USBC_UHINTCLR_HWUPIC (_U_(0x1) << USBC_UHINTCLR_HWUPIC_Pos) 3842 #define USBC_UHINTCLR_MASK _U_(0x0000007F) /**< \brief (USBC_UHINTCLR) MASK Register */ 3843 3844 /* -------- USBC_UHINTSET : (USBC Offset: 0x40C) ( /W 32) Host Global Interrupt Set Register -------- */ 3845 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3846 typedef union { 3847 struct { 3848 uint32_t DCONNIS:1; /*!< bit: 0 DCONNI Set */ 3849 uint32_t DDISCIS:1; /*!< bit: 1 DDISCI Set */ 3850 uint32_t RSTIS:1; /*!< bit: 2 RSTI Set */ 3851 uint32_t RSMEDIS:1; /*!< bit: 3 RSMEDI Set */ 3852 uint32_t RXRSMIS:1; /*!< bit: 4 RXRSMI Set */ 3853 uint32_t HSOFIS:1; /*!< bit: 5 HSOFI Set */ 3854 uint32_t HWUPIS:1; /*!< bit: 6 HWUPI Set */ 3855 uint32_t :25; /*!< bit: 7..31 Reserved */ 3856 } bit; /*!< Structure used for bit access */ 3857 uint32_t reg; /*!< Type used for register access */ 3858 } USBC_UHINTSET_Type; 3859 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3860 3861 #define USBC_UHINTSET_OFFSET 0x40C /**< \brief (USBC_UHINTSET offset) Host Global Interrupt Set Register */ 3862 #define USBC_UHINTSET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINTSET reset_value) Host Global Interrupt Set Register */ 3863 3864 #define USBC_UHINTSET_DCONNIS_Pos 0 /**< \brief (USBC_UHINTSET) DCONNI Set */ 3865 #define USBC_UHINTSET_DCONNIS (_U_(0x1) << USBC_UHINTSET_DCONNIS_Pos) 3866 #define USBC_UHINTSET_DDISCIS_Pos 1 /**< \brief (USBC_UHINTSET) DDISCI Set */ 3867 #define USBC_UHINTSET_DDISCIS (_U_(0x1) << USBC_UHINTSET_DDISCIS_Pos) 3868 #define USBC_UHINTSET_RSTIS_Pos 2 /**< \brief (USBC_UHINTSET) RSTI Set */ 3869 #define USBC_UHINTSET_RSTIS (_U_(0x1) << USBC_UHINTSET_RSTIS_Pos) 3870 #define USBC_UHINTSET_RSMEDIS_Pos 3 /**< \brief (USBC_UHINTSET) RSMEDI Set */ 3871 #define USBC_UHINTSET_RSMEDIS (_U_(0x1) << USBC_UHINTSET_RSMEDIS_Pos) 3872 #define USBC_UHINTSET_RXRSMIS_Pos 4 /**< \brief (USBC_UHINTSET) RXRSMI Set */ 3873 #define USBC_UHINTSET_RXRSMIS (_U_(0x1) << USBC_UHINTSET_RXRSMIS_Pos) 3874 #define USBC_UHINTSET_HSOFIS_Pos 5 /**< \brief (USBC_UHINTSET) HSOFI Set */ 3875 #define USBC_UHINTSET_HSOFIS (_U_(0x1) << USBC_UHINTSET_HSOFIS_Pos) 3876 #define USBC_UHINTSET_HWUPIS_Pos 6 /**< \brief (USBC_UHINTSET) HWUPI Set */ 3877 #define USBC_UHINTSET_HWUPIS (_U_(0x1) << USBC_UHINTSET_HWUPIS_Pos) 3878 #define USBC_UHINTSET_MASK _U_(0x0000007F) /**< \brief (USBC_UHINTSET) MASK Register */ 3879 3880 /* -------- USBC_UHINTE : (USBC Offset: 0x410) (R/ 32) Host Global Interrupt Enable Register -------- */ 3881 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3882 typedef union { 3883 struct { 3884 uint32_t DCONNIE:1; /*!< bit: 0 DCONNI Enable */ 3885 uint32_t DDISCIE:1; /*!< bit: 1 DDISCI Enable */ 3886 uint32_t RSTIE:1; /*!< bit: 2 RSTI Enable */ 3887 uint32_t RSMEDIE:1; /*!< bit: 3 RSMEDI Enable */ 3888 uint32_t RXRSMIE:1; /*!< bit: 4 RXRSMI Enable */ 3889 uint32_t HSOFIE:1; /*!< bit: 5 HSOFI Enable */ 3890 uint32_t HWUPIE:1; /*!< bit: 6 HWUPI Enable */ 3891 uint32_t :1; /*!< bit: 7 Reserved */ 3892 uint32_t P0INTE:1; /*!< bit: 8 P0INT Enable */ 3893 uint32_t P1INTE:1; /*!< bit: 9 P1INT Enable */ 3894 uint32_t P2INTE:1; /*!< bit: 10 P2INT Enable */ 3895 uint32_t P3INTE:1; /*!< bit: 11 P3INT Enable */ 3896 uint32_t P4INTE:1; /*!< bit: 12 P4INT Enable */ 3897 uint32_t P5INTE:1; /*!< bit: 13 P5INT Enable */ 3898 uint32_t P6INTE:1; /*!< bit: 14 P6INT Enable */ 3899 uint32_t P7INTE:1; /*!< bit: 15 P7INT Enable */ 3900 uint32_t :16; /*!< bit: 16..31 Reserved */ 3901 } bit; /*!< Structure used for bit access */ 3902 uint32_t reg; /*!< Type used for register access */ 3903 } USBC_UHINTE_Type; 3904 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3905 3906 #define USBC_UHINTE_OFFSET 0x410 /**< \brief (USBC_UHINTE offset) Host Global Interrupt Enable Register */ 3907 #define USBC_UHINTE_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINTE reset_value) Host Global Interrupt Enable Register */ 3908 3909 #define USBC_UHINTE_DCONNIE_Pos 0 /**< \brief (USBC_UHINTE) DCONNI Enable */ 3910 #define USBC_UHINTE_DCONNIE (_U_(0x1) << USBC_UHINTE_DCONNIE_Pos) 3911 #define USBC_UHINTE_DDISCIE_Pos 1 /**< \brief (USBC_UHINTE) DDISCI Enable */ 3912 #define USBC_UHINTE_DDISCIE (_U_(0x1) << USBC_UHINTE_DDISCIE_Pos) 3913 #define USBC_UHINTE_RSTIE_Pos 2 /**< \brief (USBC_UHINTE) RSTI Enable */ 3914 #define USBC_UHINTE_RSTIE (_U_(0x1) << USBC_UHINTE_RSTIE_Pos) 3915 #define USBC_UHINTE_RSMEDIE_Pos 3 /**< \brief (USBC_UHINTE) RSMEDI Enable */ 3916 #define USBC_UHINTE_RSMEDIE (_U_(0x1) << USBC_UHINTE_RSMEDIE_Pos) 3917 #define USBC_UHINTE_RXRSMIE_Pos 4 /**< \brief (USBC_UHINTE) RXRSMI Enable */ 3918 #define USBC_UHINTE_RXRSMIE (_U_(0x1) << USBC_UHINTE_RXRSMIE_Pos) 3919 #define USBC_UHINTE_HSOFIE_Pos 5 /**< \brief (USBC_UHINTE) HSOFI Enable */ 3920 #define USBC_UHINTE_HSOFIE (_U_(0x1) << USBC_UHINTE_HSOFIE_Pos) 3921 #define USBC_UHINTE_HWUPIE_Pos 6 /**< \brief (USBC_UHINTE) HWUPI Enable */ 3922 #define USBC_UHINTE_HWUPIE (_U_(0x1) << USBC_UHINTE_HWUPIE_Pos) 3923 #define USBC_UHINTE_P0INTE_Pos 8 /**< \brief (USBC_UHINTE) P0INT Enable */ 3924 #define USBC_UHINTE_P0INTE (_U_(0x1) << USBC_UHINTE_P0INTE_Pos) 3925 #define USBC_UHINTE_P1INTE_Pos 9 /**< \brief (USBC_UHINTE) P1INT Enable */ 3926 #define USBC_UHINTE_P1INTE (_U_(0x1) << USBC_UHINTE_P1INTE_Pos) 3927 #define USBC_UHINTE_P2INTE_Pos 10 /**< \brief (USBC_UHINTE) P2INT Enable */ 3928 #define USBC_UHINTE_P2INTE (_U_(0x1) << USBC_UHINTE_P2INTE_Pos) 3929 #define USBC_UHINTE_P3INTE_Pos 11 /**< \brief (USBC_UHINTE) P3INT Enable */ 3930 #define USBC_UHINTE_P3INTE (_U_(0x1) << USBC_UHINTE_P3INTE_Pos) 3931 #define USBC_UHINTE_P4INTE_Pos 12 /**< \brief (USBC_UHINTE) P4INT Enable */ 3932 #define USBC_UHINTE_P4INTE (_U_(0x1) << USBC_UHINTE_P4INTE_Pos) 3933 #define USBC_UHINTE_P5INTE_Pos 13 /**< \brief (USBC_UHINTE) P5INT Enable */ 3934 #define USBC_UHINTE_P5INTE (_U_(0x1) << USBC_UHINTE_P5INTE_Pos) 3935 #define USBC_UHINTE_P6INTE_Pos 14 /**< \brief (USBC_UHINTE) P6INT Enable */ 3936 #define USBC_UHINTE_P6INTE (_U_(0x1) << USBC_UHINTE_P6INTE_Pos) 3937 #define USBC_UHINTE_P7INTE_Pos 15 /**< \brief (USBC_UHINTE) P7INT Enable */ 3938 #define USBC_UHINTE_P7INTE (_U_(0x1) << USBC_UHINTE_P7INTE_Pos) 3939 #define USBC_UHINTE_MASK _U_(0x0000FF7F) /**< \brief (USBC_UHINTE) MASK Register */ 3940 3941 /* -------- USBC_UHINTECLR : (USBC Offset: 0x414) ( /W 32) Host Global Interrupt Enable Clear Register -------- */ 3942 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 3943 typedef union { 3944 struct { 3945 uint32_t DCONNIEC:1; /*!< bit: 0 DCONNIE Clear */ 3946 uint32_t DDISCIEC:1; /*!< bit: 1 DDISCIE Clear */ 3947 uint32_t RSTIEC:1; /*!< bit: 2 RSTIE Clear */ 3948 uint32_t RSMEDIEC:1; /*!< bit: 3 RSMEDIE Clear */ 3949 uint32_t RXRSMIEC:1; /*!< bit: 4 RXRSMIE Clear */ 3950 uint32_t HSOFIEC:1; /*!< bit: 5 HSOFIE Clear */ 3951 uint32_t HWUPIEC:1; /*!< bit: 6 HWUPIE Clear */ 3952 uint32_t :1; /*!< bit: 7 Reserved */ 3953 uint32_t P0INTEC:1; /*!< bit: 8 P0INTE Clear */ 3954 uint32_t P1INTEC:1; /*!< bit: 9 P1INTE Clear */ 3955 uint32_t P2INTEC:1; /*!< bit: 10 P2INTE Clear */ 3956 uint32_t P3INTEC:1; /*!< bit: 11 P3INTE Clear */ 3957 uint32_t P4INTEC:1; /*!< bit: 12 P4INTE Clear */ 3958 uint32_t P5INTEC:1; /*!< bit: 13 P5INTE Clear */ 3959 uint32_t P6INTEC:1; /*!< bit: 14 P6INTE Clear */ 3960 uint32_t P7INTEC:1; /*!< bit: 15 P7INTE Clear */ 3961 uint32_t :16; /*!< bit: 16..31 Reserved */ 3962 } bit; /*!< Structure used for bit access */ 3963 uint32_t reg; /*!< Type used for register access */ 3964 } USBC_UHINTECLR_Type; 3965 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 3966 3967 #define USBC_UHINTECLR_OFFSET 0x414 /**< \brief (USBC_UHINTECLR offset) Host Global Interrupt Enable Clear Register */ 3968 #define USBC_UHINTECLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINTECLR reset_value) Host Global Interrupt Enable Clear Register */ 3969 3970 #define USBC_UHINTECLR_DCONNIEC_Pos 0 /**< \brief (USBC_UHINTECLR) DCONNIE Clear */ 3971 #define USBC_UHINTECLR_DCONNIEC (_U_(0x1) << USBC_UHINTECLR_DCONNIEC_Pos) 3972 #define USBC_UHINTECLR_DDISCIEC_Pos 1 /**< \brief (USBC_UHINTECLR) DDISCIE Clear */ 3973 #define USBC_UHINTECLR_DDISCIEC (_U_(0x1) << USBC_UHINTECLR_DDISCIEC_Pos) 3974 #define USBC_UHINTECLR_RSTIEC_Pos 2 /**< \brief (USBC_UHINTECLR) RSTIE Clear */ 3975 #define USBC_UHINTECLR_RSTIEC (_U_(0x1) << USBC_UHINTECLR_RSTIEC_Pos) 3976 #define USBC_UHINTECLR_RSMEDIEC_Pos 3 /**< \brief (USBC_UHINTECLR) RSMEDIE Clear */ 3977 #define USBC_UHINTECLR_RSMEDIEC (_U_(0x1) << USBC_UHINTECLR_RSMEDIEC_Pos) 3978 #define USBC_UHINTECLR_RXRSMIEC_Pos 4 /**< \brief (USBC_UHINTECLR) RXRSMIE Clear */ 3979 #define USBC_UHINTECLR_RXRSMIEC (_U_(0x1) << USBC_UHINTECLR_RXRSMIEC_Pos) 3980 #define USBC_UHINTECLR_HSOFIEC_Pos 5 /**< \brief (USBC_UHINTECLR) HSOFIE Clear */ 3981 #define USBC_UHINTECLR_HSOFIEC (_U_(0x1) << USBC_UHINTECLR_HSOFIEC_Pos) 3982 #define USBC_UHINTECLR_HWUPIEC_Pos 6 /**< \brief (USBC_UHINTECLR) HWUPIE Clear */ 3983 #define USBC_UHINTECLR_HWUPIEC (_U_(0x1) << USBC_UHINTECLR_HWUPIEC_Pos) 3984 #define USBC_UHINTECLR_P0INTEC_Pos 8 /**< \brief (USBC_UHINTECLR) P0INTE Clear */ 3985 #define USBC_UHINTECLR_P0INTEC (_U_(0x1) << USBC_UHINTECLR_P0INTEC_Pos) 3986 #define USBC_UHINTECLR_P1INTEC_Pos 9 /**< \brief (USBC_UHINTECLR) P1INTE Clear */ 3987 #define USBC_UHINTECLR_P1INTEC (_U_(0x1) << USBC_UHINTECLR_P1INTEC_Pos) 3988 #define USBC_UHINTECLR_P2INTEC_Pos 10 /**< \brief (USBC_UHINTECLR) P2INTE Clear */ 3989 #define USBC_UHINTECLR_P2INTEC (_U_(0x1) << USBC_UHINTECLR_P2INTEC_Pos) 3990 #define USBC_UHINTECLR_P3INTEC_Pos 11 /**< \brief (USBC_UHINTECLR) P3INTE Clear */ 3991 #define USBC_UHINTECLR_P3INTEC (_U_(0x1) << USBC_UHINTECLR_P3INTEC_Pos) 3992 #define USBC_UHINTECLR_P4INTEC_Pos 12 /**< \brief (USBC_UHINTECLR) P4INTE Clear */ 3993 #define USBC_UHINTECLR_P4INTEC (_U_(0x1) << USBC_UHINTECLR_P4INTEC_Pos) 3994 #define USBC_UHINTECLR_P5INTEC_Pos 13 /**< \brief (USBC_UHINTECLR) P5INTE Clear */ 3995 #define USBC_UHINTECLR_P5INTEC (_U_(0x1) << USBC_UHINTECLR_P5INTEC_Pos) 3996 #define USBC_UHINTECLR_P6INTEC_Pos 14 /**< \brief (USBC_UHINTECLR) P6INTE Clear */ 3997 #define USBC_UHINTECLR_P6INTEC (_U_(0x1) << USBC_UHINTECLR_P6INTEC_Pos) 3998 #define USBC_UHINTECLR_P7INTEC_Pos 15 /**< \brief (USBC_UHINTECLR) P7INTE Clear */ 3999 #define USBC_UHINTECLR_P7INTEC (_U_(0x1) << USBC_UHINTECLR_P7INTEC_Pos) 4000 #define USBC_UHINTECLR_MASK _U_(0x0000FF7F) /**< \brief (USBC_UHINTECLR) MASK Register */ 4001 4002 /* -------- USBC_UHINTESET : (USBC Offset: 0x418) ( /W 32) Host Global Interrupt Enable Set Register -------- */ 4003 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4004 typedef union { 4005 struct { 4006 uint32_t DCONNIES:1; /*!< bit: 0 DCONNIE Set */ 4007 uint32_t DDISCIES:1; /*!< bit: 1 DDISCIE Set */ 4008 uint32_t RSTIES:1; /*!< bit: 2 RSTIE Set */ 4009 uint32_t RSMEDIES:1; /*!< bit: 3 RSMEDIE Set */ 4010 uint32_t RXRSMIES:1; /*!< bit: 4 RXRSMIE Set */ 4011 uint32_t HSOFIES:1; /*!< bit: 5 HSOFIE Set */ 4012 uint32_t HWUPIES:1; /*!< bit: 6 HWUPIE Set */ 4013 uint32_t :1; /*!< bit: 7 Reserved */ 4014 uint32_t P0INTES:1; /*!< bit: 8 P0INTE Set */ 4015 uint32_t P1INTES:1; /*!< bit: 9 P1INTE Set */ 4016 uint32_t P2INTES:1; /*!< bit: 10 P2INTE Set */ 4017 uint32_t P3INTES:1; /*!< bit: 11 P3INTE Set */ 4018 uint32_t P4INTES:1; /*!< bit: 12 P4INTE Set */ 4019 uint32_t P5INTES:1; /*!< bit: 13 P5INTE Set */ 4020 uint32_t P6INTES:1; /*!< bit: 14 P6INTE Set */ 4021 uint32_t P7INTES:1; /*!< bit: 15 P7INTE Set */ 4022 uint32_t :16; /*!< bit: 16..31 Reserved */ 4023 } bit; /*!< Structure used for bit access */ 4024 uint32_t reg; /*!< Type used for register access */ 4025 } USBC_UHINTESET_Type; 4026 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4027 4028 #define USBC_UHINTESET_OFFSET 0x418 /**< \brief (USBC_UHINTESET offset) Host Global Interrupt Enable Set Register */ 4029 #define USBC_UHINTESET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHINTESET reset_value) Host Global Interrupt Enable Set Register */ 4030 4031 #define USBC_UHINTESET_DCONNIES_Pos 0 /**< \brief (USBC_UHINTESET) DCONNIE Set */ 4032 #define USBC_UHINTESET_DCONNIES (_U_(0x1) << USBC_UHINTESET_DCONNIES_Pos) 4033 #define USBC_UHINTESET_DDISCIES_Pos 1 /**< \brief (USBC_UHINTESET) DDISCIE Set */ 4034 #define USBC_UHINTESET_DDISCIES (_U_(0x1) << USBC_UHINTESET_DDISCIES_Pos) 4035 #define USBC_UHINTESET_RSTIES_Pos 2 /**< \brief (USBC_UHINTESET) RSTIE Set */ 4036 #define USBC_UHINTESET_RSTIES (_U_(0x1) << USBC_UHINTESET_RSTIES_Pos) 4037 #define USBC_UHINTESET_RSMEDIES_Pos 3 /**< \brief (USBC_UHINTESET) RSMEDIE Set */ 4038 #define USBC_UHINTESET_RSMEDIES (_U_(0x1) << USBC_UHINTESET_RSMEDIES_Pos) 4039 #define USBC_UHINTESET_RXRSMIES_Pos 4 /**< \brief (USBC_UHINTESET) RXRSMIE Set */ 4040 #define USBC_UHINTESET_RXRSMIES (_U_(0x1) << USBC_UHINTESET_RXRSMIES_Pos) 4041 #define USBC_UHINTESET_HSOFIES_Pos 5 /**< \brief (USBC_UHINTESET) HSOFIE Set */ 4042 #define USBC_UHINTESET_HSOFIES (_U_(0x1) << USBC_UHINTESET_HSOFIES_Pos) 4043 #define USBC_UHINTESET_HWUPIES_Pos 6 /**< \brief (USBC_UHINTESET) HWUPIE Set */ 4044 #define USBC_UHINTESET_HWUPIES (_U_(0x1) << USBC_UHINTESET_HWUPIES_Pos) 4045 #define USBC_UHINTESET_P0INTES_Pos 8 /**< \brief (USBC_UHINTESET) P0INTE Set */ 4046 #define USBC_UHINTESET_P0INTES (_U_(0x1) << USBC_UHINTESET_P0INTES_Pos) 4047 #define USBC_UHINTESET_P1INTES_Pos 9 /**< \brief (USBC_UHINTESET) P1INTE Set */ 4048 #define USBC_UHINTESET_P1INTES (_U_(0x1) << USBC_UHINTESET_P1INTES_Pos) 4049 #define USBC_UHINTESET_P2INTES_Pos 10 /**< \brief (USBC_UHINTESET) P2INTE Set */ 4050 #define USBC_UHINTESET_P2INTES (_U_(0x1) << USBC_UHINTESET_P2INTES_Pos) 4051 #define USBC_UHINTESET_P3INTES_Pos 11 /**< \brief (USBC_UHINTESET) P3INTE Set */ 4052 #define USBC_UHINTESET_P3INTES (_U_(0x1) << USBC_UHINTESET_P3INTES_Pos) 4053 #define USBC_UHINTESET_P4INTES_Pos 12 /**< \brief (USBC_UHINTESET) P4INTE Set */ 4054 #define USBC_UHINTESET_P4INTES (_U_(0x1) << USBC_UHINTESET_P4INTES_Pos) 4055 #define USBC_UHINTESET_P5INTES_Pos 13 /**< \brief (USBC_UHINTESET) P5INTE Set */ 4056 #define USBC_UHINTESET_P5INTES (_U_(0x1) << USBC_UHINTESET_P5INTES_Pos) 4057 #define USBC_UHINTESET_P6INTES_Pos 14 /**< \brief (USBC_UHINTESET) P6INTE Set */ 4058 #define USBC_UHINTESET_P6INTES (_U_(0x1) << USBC_UHINTESET_P6INTES_Pos) 4059 #define USBC_UHINTESET_P7INTES_Pos 15 /**< \brief (USBC_UHINTESET) P7INTE Set */ 4060 #define USBC_UHINTESET_P7INTES (_U_(0x1) << USBC_UHINTESET_P7INTES_Pos) 4061 #define USBC_UHINTESET_MASK _U_(0x0000FF7F) /**< \brief (USBC_UHINTESET) MASK Register */ 4062 4063 /* -------- USBC_UPRST : (USBC Offset: 0x41C) (R/W 32) Pipe Reset Register -------- */ 4064 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4065 typedef union { 4066 struct { 4067 uint32_t PEN0:1; /*!< bit: 0 Pipe0 Enable */ 4068 uint32_t PEN1:1; /*!< bit: 1 Pipe1 Enable */ 4069 uint32_t PEN2:1; /*!< bit: 2 Pipe2 Enable */ 4070 uint32_t PEN3:1; /*!< bit: 3 Pipe3 Enable */ 4071 uint32_t PEN4:1; /*!< bit: 4 Pipe4 Enable */ 4072 uint32_t PEN5:1; /*!< bit: 5 Pipe5 Enable */ 4073 uint32_t PEN6:1; /*!< bit: 6 Pipe6 Enable */ 4074 uint32_t PEN7:1; /*!< bit: 7 Pipe7 Enable */ 4075 uint32_t :24; /*!< bit: 8..31 Reserved */ 4076 } bit; /*!< Structure used for bit access */ 4077 uint32_t reg; /*!< Type used for register access */ 4078 } USBC_UPRST_Type; 4079 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4080 4081 #define USBC_UPRST_OFFSET 0x41C /**< \brief (USBC_UPRST offset) Pipe Reset Register */ 4082 #define USBC_UPRST_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPRST reset_value) Pipe Reset Register */ 4083 4084 #define USBC_UPRST_PEN0_Pos 0 /**< \brief (USBC_UPRST) Pipe0 Enable */ 4085 #define USBC_UPRST_PEN0 (_U_(0x1) << USBC_UPRST_PEN0_Pos) 4086 #define USBC_UPRST_PEN1_Pos 1 /**< \brief (USBC_UPRST) Pipe1 Enable */ 4087 #define USBC_UPRST_PEN1 (_U_(0x1) << USBC_UPRST_PEN1_Pos) 4088 #define USBC_UPRST_PEN2_Pos 2 /**< \brief (USBC_UPRST) Pipe2 Enable */ 4089 #define USBC_UPRST_PEN2 (_U_(0x1) << USBC_UPRST_PEN2_Pos) 4090 #define USBC_UPRST_PEN3_Pos 3 /**< \brief (USBC_UPRST) Pipe3 Enable */ 4091 #define USBC_UPRST_PEN3 (_U_(0x1) << USBC_UPRST_PEN3_Pos) 4092 #define USBC_UPRST_PEN4_Pos 4 /**< \brief (USBC_UPRST) Pipe4 Enable */ 4093 #define USBC_UPRST_PEN4 (_U_(0x1) << USBC_UPRST_PEN4_Pos) 4094 #define USBC_UPRST_PEN5_Pos 5 /**< \brief (USBC_UPRST) Pipe5 Enable */ 4095 #define USBC_UPRST_PEN5 (_U_(0x1) << USBC_UPRST_PEN5_Pos) 4096 #define USBC_UPRST_PEN6_Pos 6 /**< \brief (USBC_UPRST) Pipe6 Enable */ 4097 #define USBC_UPRST_PEN6 (_U_(0x1) << USBC_UPRST_PEN6_Pos) 4098 #define USBC_UPRST_PEN7_Pos 7 /**< \brief (USBC_UPRST) Pipe7 Enable */ 4099 #define USBC_UPRST_PEN7 (_U_(0x1) << USBC_UPRST_PEN7_Pos) 4100 #define USBC_UPRST_MASK _U_(0x000000FF) /**< \brief (USBC_UPRST) MASK Register */ 4101 4102 /* -------- USBC_UHFNUM : (USBC Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ 4103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4104 typedef union { 4105 struct { 4106 uint32_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 4107 uint32_t FNUM:11; /*!< bit: 3..13 Frame Number */ 4108 uint32_t :2; /*!< bit: 14..15 Reserved */ 4109 uint32_t FLENHIGH:8; /*!< bit: 16..23 Frame Length */ 4110 uint32_t :8; /*!< bit: 24..31 Reserved */ 4111 } bit; /*!< Structure used for bit access */ 4112 uint32_t reg; /*!< Type used for register access */ 4113 } USBC_UHFNUM_Type; 4114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4115 4116 #define USBC_UHFNUM_OFFSET 0x420 /**< \brief (USBC_UHFNUM offset) Host Frame Number Register */ 4117 #define USBC_UHFNUM_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHFNUM reset_value) Host Frame Number Register */ 4118 4119 #define USBC_UHFNUM_MFNUM_Pos 0 /**< \brief (USBC_UHFNUM) Micro Frame Number */ 4120 #define USBC_UHFNUM_MFNUM_Msk (_U_(0x7) << USBC_UHFNUM_MFNUM_Pos) 4121 #define USBC_UHFNUM_MFNUM(value) (USBC_UHFNUM_MFNUM_Msk & ((value) << USBC_UHFNUM_MFNUM_Pos)) 4122 #define USBC_UHFNUM_FNUM_Pos 3 /**< \brief (USBC_UHFNUM) Frame Number */ 4123 #define USBC_UHFNUM_FNUM_Msk (_U_(0x7FF) << USBC_UHFNUM_FNUM_Pos) 4124 #define USBC_UHFNUM_FNUM(value) (USBC_UHFNUM_FNUM_Msk & ((value) << USBC_UHFNUM_FNUM_Pos)) 4125 #define USBC_UHFNUM_FLENHIGH_Pos 16 /**< \brief (USBC_UHFNUM) Frame Length */ 4126 #define USBC_UHFNUM_FLENHIGH_Msk (_U_(0xFF) << USBC_UHFNUM_FLENHIGH_Pos) 4127 #define USBC_UHFNUM_FLENHIGH(value) (USBC_UHFNUM_FLENHIGH_Msk & ((value) << USBC_UHFNUM_FLENHIGH_Pos)) 4128 #define USBC_UHFNUM_MASK _U_(0x00FF3FFF) /**< \brief (USBC_UHFNUM) MASK Register */ 4129 4130 /* -------- USBC_UHSOFC : (USBC Offset: 0x424) (R/W 32) Host Start of Frame Control Register -------- */ 4131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4132 typedef union { 4133 struct { 4134 uint32_t FLENC:14; /*!< bit: 0..13 Frame Length Control */ 4135 uint32_t :2; /*!< bit: 14..15 Reserved */ 4136 uint32_t FLENCE:1; /*!< bit: 16 Frame Length Control Enable */ 4137 uint32_t :15; /*!< bit: 17..31 Reserved */ 4138 } bit; /*!< Structure used for bit access */ 4139 uint32_t reg; /*!< Type used for register access */ 4140 } USBC_UHSOFC_Type; 4141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4142 4143 #define USBC_UHSOFC_OFFSET 0x424 /**< \brief (USBC_UHSOFC offset) Host Start of Frame Control Register */ 4144 #define USBC_UHSOFC_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UHSOFC reset_value) Host Start of Frame Control Register */ 4145 4146 #define USBC_UHSOFC_FLENC_Pos 0 /**< \brief (USBC_UHSOFC) Frame Length Control */ 4147 #define USBC_UHSOFC_FLENC_Msk (_U_(0x3FFF) << USBC_UHSOFC_FLENC_Pos) 4148 #define USBC_UHSOFC_FLENC(value) (USBC_UHSOFC_FLENC_Msk & ((value) << USBC_UHSOFC_FLENC_Pos)) 4149 #define USBC_UHSOFC_FLENCE_Pos 16 /**< \brief (USBC_UHSOFC) Frame Length Control Enable */ 4150 #define USBC_UHSOFC_FLENCE (_U_(0x1) << USBC_UHSOFC_FLENCE_Pos) 4151 #define USBC_UHSOFC_MASK _U_(0x00013FFF) /**< \brief (USBC_UHSOFC) MASK Register */ 4152 4153 /* -------- USBC_UPCFG0 : (USBC Offset: 0x500) (R/W 32) Pipe Configuration Register -------- */ 4154 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4155 typedef union { 4156 struct { 4157 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4158 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4159 uint32_t :1; /*!< bit: 3 Reserved */ 4160 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4161 uint32_t :1; /*!< bit: 7 Reserved */ 4162 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4163 uint32_t :2; /*!< bit: 10..11 Reserved */ 4164 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4165 uint32_t :6; /*!< bit: 14..19 Reserved */ 4166 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4167 uint32_t :3; /*!< bit: 21..23 Reserved */ 4168 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4169 } bit; /*!< Structure used for bit access */ 4170 uint32_t reg; /*!< Type used for register access */ 4171 } USBC_UPCFG0_Type; 4172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4173 4174 #define USBC_UPCFG0_OFFSET 0x500 /**< \brief (USBC_UPCFG0 offset) Pipe Configuration Register */ 4175 #define USBC_UPCFG0_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG0 reset_value) Pipe Configuration Register */ 4176 4177 #define USBC_UPCFG0_PBK_Pos 2 /**< \brief (USBC_UPCFG0) Pipe Banks */ 4178 #define USBC_UPCFG0_PBK (_U_(0x1) << USBC_UPCFG0_PBK_Pos) 4179 #define USBC_UPCFG0_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG0) */ 4180 #define USBC_UPCFG0_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG0) */ 4181 #define USBC_UPCFG0_PBK_SINGLE (USBC_UPCFG0_PBK_SINGLE_Val << USBC_UPCFG0_PBK_Pos) 4182 #define USBC_UPCFG0_PBK_DOUBLE (USBC_UPCFG0_PBK_DOUBLE_Val << USBC_UPCFG0_PBK_Pos) 4183 #define USBC_UPCFG0_PSIZE_Pos 4 /**< \brief (USBC_UPCFG0) Pipe Size */ 4184 #define USBC_UPCFG0_PSIZE_Msk (_U_(0x7) << USBC_UPCFG0_PSIZE_Pos) 4185 #define USBC_UPCFG0_PSIZE(value) (USBC_UPCFG0_PSIZE_Msk & ((value) << USBC_UPCFG0_PSIZE_Pos)) 4186 #define USBC_UPCFG0_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG0) */ 4187 #define USBC_UPCFG0_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG0) */ 4188 #define USBC_UPCFG0_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG0) */ 4189 #define USBC_UPCFG0_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG0) */ 4190 #define USBC_UPCFG0_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG0) */ 4191 #define USBC_UPCFG0_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG0) */ 4192 #define USBC_UPCFG0_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG0) */ 4193 #define USBC_UPCFG0_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG0) */ 4194 #define USBC_UPCFG0_PSIZE_8 (USBC_UPCFG0_PSIZE_8_Val << USBC_UPCFG0_PSIZE_Pos) 4195 #define USBC_UPCFG0_PSIZE_16 (USBC_UPCFG0_PSIZE_16_Val << USBC_UPCFG0_PSIZE_Pos) 4196 #define USBC_UPCFG0_PSIZE_32 (USBC_UPCFG0_PSIZE_32_Val << USBC_UPCFG0_PSIZE_Pos) 4197 #define USBC_UPCFG0_PSIZE_64 (USBC_UPCFG0_PSIZE_64_Val << USBC_UPCFG0_PSIZE_Pos) 4198 #define USBC_UPCFG0_PSIZE_128 (USBC_UPCFG0_PSIZE_128_Val << USBC_UPCFG0_PSIZE_Pos) 4199 #define USBC_UPCFG0_PSIZE_256 (USBC_UPCFG0_PSIZE_256_Val << USBC_UPCFG0_PSIZE_Pos) 4200 #define USBC_UPCFG0_PSIZE_512 (USBC_UPCFG0_PSIZE_512_Val << USBC_UPCFG0_PSIZE_Pos) 4201 #define USBC_UPCFG0_PSIZE_1024 (USBC_UPCFG0_PSIZE_1024_Val << USBC_UPCFG0_PSIZE_Pos) 4202 #define USBC_UPCFG0_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG0) Pipe Token */ 4203 #define USBC_UPCFG0_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG0_PTOKEN_Pos) 4204 #define USBC_UPCFG0_PTOKEN(value) (USBC_UPCFG0_PTOKEN_Msk & ((value) << USBC_UPCFG0_PTOKEN_Pos)) 4205 #define USBC_UPCFG0_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG0) */ 4206 #define USBC_UPCFG0_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG0) */ 4207 #define USBC_UPCFG0_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG0) */ 4208 #define USBC_UPCFG0_PTOKEN_SETUP (USBC_UPCFG0_PTOKEN_SETUP_Val << USBC_UPCFG0_PTOKEN_Pos) 4209 #define USBC_UPCFG0_PTOKEN_IN (USBC_UPCFG0_PTOKEN_IN_Val << USBC_UPCFG0_PTOKEN_Pos) 4210 #define USBC_UPCFG0_PTOKEN_OUT (USBC_UPCFG0_PTOKEN_OUT_Val << USBC_UPCFG0_PTOKEN_Pos) 4211 #define USBC_UPCFG0_PTYPE_Pos 12 /**< \brief (USBC_UPCFG0) Pipe Type */ 4212 #define USBC_UPCFG0_PTYPE_Msk (_U_(0x3) << USBC_UPCFG0_PTYPE_Pos) 4213 #define USBC_UPCFG0_PTYPE(value) (USBC_UPCFG0_PTYPE_Msk & ((value) << USBC_UPCFG0_PTYPE_Pos)) 4214 #define USBC_UPCFG0_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG0) */ 4215 #define USBC_UPCFG0_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG0) */ 4216 #define USBC_UPCFG0_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG0) */ 4217 #define USBC_UPCFG0_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG0) */ 4218 #define USBC_UPCFG0_PTYPE_CONTROL (USBC_UPCFG0_PTYPE_CONTROL_Val << USBC_UPCFG0_PTYPE_Pos) 4219 #define USBC_UPCFG0_PTYPE_ISOCHRONOUS (USBC_UPCFG0_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG0_PTYPE_Pos) 4220 #define USBC_UPCFG0_PTYPE_BULK (USBC_UPCFG0_PTYPE_BULK_Val << USBC_UPCFG0_PTYPE_Pos) 4221 #define USBC_UPCFG0_PTYPE_INTERRUPT (USBC_UPCFG0_PTYPE_INTERRUPT_Val << USBC_UPCFG0_PTYPE_Pos) 4222 #define USBC_UPCFG0_PINGEN_Pos 20 /**< \brief (USBC_UPCFG0) Ping Enable */ 4223 #define USBC_UPCFG0_PINGEN (_U_(0x1) << USBC_UPCFG0_PINGEN_Pos) 4224 #define USBC_UPCFG0_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG0) binterval parameter */ 4225 #define USBC_UPCFG0_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG0_BINTERVAL_Pos) 4226 #define USBC_UPCFG0_BINTERVAL(value) (USBC_UPCFG0_BINTERVAL_Msk & ((value) << USBC_UPCFG0_BINTERVAL_Pos)) 4227 #define USBC_UPCFG0_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG0) MASK Register */ 4228 4229 /* -------- USBC_UPCFG1 : (USBC Offset: 0x504) (R/W 32) Pipe Configuration Register -------- */ 4230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4231 typedef union { 4232 struct { 4233 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4234 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4235 uint32_t :1; /*!< bit: 3 Reserved */ 4236 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4237 uint32_t :1; /*!< bit: 7 Reserved */ 4238 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4239 uint32_t :2; /*!< bit: 10..11 Reserved */ 4240 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4241 uint32_t :6; /*!< bit: 14..19 Reserved */ 4242 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4243 uint32_t :3; /*!< bit: 21..23 Reserved */ 4244 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4245 } bit; /*!< Structure used for bit access */ 4246 uint32_t reg; /*!< Type used for register access */ 4247 } USBC_UPCFG1_Type; 4248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4249 4250 #define USBC_UPCFG1_OFFSET 0x504 /**< \brief (USBC_UPCFG1 offset) Pipe Configuration Register */ 4251 #define USBC_UPCFG1_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG1 reset_value) Pipe Configuration Register */ 4252 4253 #define USBC_UPCFG1_PBK_Pos 2 /**< \brief (USBC_UPCFG1) Pipe Banks */ 4254 #define USBC_UPCFG1_PBK (_U_(0x1) << USBC_UPCFG1_PBK_Pos) 4255 #define USBC_UPCFG1_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG1) */ 4256 #define USBC_UPCFG1_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG1) */ 4257 #define USBC_UPCFG1_PBK_SINGLE (USBC_UPCFG1_PBK_SINGLE_Val << USBC_UPCFG1_PBK_Pos) 4258 #define USBC_UPCFG1_PBK_DOUBLE (USBC_UPCFG1_PBK_DOUBLE_Val << USBC_UPCFG1_PBK_Pos) 4259 #define USBC_UPCFG1_PSIZE_Pos 4 /**< \brief (USBC_UPCFG1) Pipe Size */ 4260 #define USBC_UPCFG1_PSIZE_Msk (_U_(0x7) << USBC_UPCFG1_PSIZE_Pos) 4261 #define USBC_UPCFG1_PSIZE(value) (USBC_UPCFG1_PSIZE_Msk & ((value) << USBC_UPCFG1_PSIZE_Pos)) 4262 #define USBC_UPCFG1_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG1) */ 4263 #define USBC_UPCFG1_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG1) */ 4264 #define USBC_UPCFG1_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG1) */ 4265 #define USBC_UPCFG1_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG1) */ 4266 #define USBC_UPCFG1_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG1) */ 4267 #define USBC_UPCFG1_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG1) */ 4268 #define USBC_UPCFG1_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG1) */ 4269 #define USBC_UPCFG1_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG1) */ 4270 #define USBC_UPCFG1_PSIZE_8 (USBC_UPCFG1_PSIZE_8_Val << USBC_UPCFG1_PSIZE_Pos) 4271 #define USBC_UPCFG1_PSIZE_16 (USBC_UPCFG1_PSIZE_16_Val << USBC_UPCFG1_PSIZE_Pos) 4272 #define USBC_UPCFG1_PSIZE_32 (USBC_UPCFG1_PSIZE_32_Val << USBC_UPCFG1_PSIZE_Pos) 4273 #define USBC_UPCFG1_PSIZE_64 (USBC_UPCFG1_PSIZE_64_Val << USBC_UPCFG1_PSIZE_Pos) 4274 #define USBC_UPCFG1_PSIZE_128 (USBC_UPCFG1_PSIZE_128_Val << USBC_UPCFG1_PSIZE_Pos) 4275 #define USBC_UPCFG1_PSIZE_256 (USBC_UPCFG1_PSIZE_256_Val << USBC_UPCFG1_PSIZE_Pos) 4276 #define USBC_UPCFG1_PSIZE_512 (USBC_UPCFG1_PSIZE_512_Val << USBC_UPCFG1_PSIZE_Pos) 4277 #define USBC_UPCFG1_PSIZE_1024 (USBC_UPCFG1_PSIZE_1024_Val << USBC_UPCFG1_PSIZE_Pos) 4278 #define USBC_UPCFG1_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG1) Pipe Token */ 4279 #define USBC_UPCFG1_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG1_PTOKEN_Pos) 4280 #define USBC_UPCFG1_PTOKEN(value) (USBC_UPCFG1_PTOKEN_Msk & ((value) << USBC_UPCFG1_PTOKEN_Pos)) 4281 #define USBC_UPCFG1_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG1) */ 4282 #define USBC_UPCFG1_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG1) */ 4283 #define USBC_UPCFG1_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG1) */ 4284 #define USBC_UPCFG1_PTOKEN_SETUP (USBC_UPCFG1_PTOKEN_SETUP_Val << USBC_UPCFG1_PTOKEN_Pos) 4285 #define USBC_UPCFG1_PTOKEN_IN (USBC_UPCFG1_PTOKEN_IN_Val << USBC_UPCFG1_PTOKEN_Pos) 4286 #define USBC_UPCFG1_PTOKEN_OUT (USBC_UPCFG1_PTOKEN_OUT_Val << USBC_UPCFG1_PTOKEN_Pos) 4287 #define USBC_UPCFG1_PTYPE_Pos 12 /**< \brief (USBC_UPCFG1) Pipe Type */ 4288 #define USBC_UPCFG1_PTYPE_Msk (_U_(0x3) << USBC_UPCFG1_PTYPE_Pos) 4289 #define USBC_UPCFG1_PTYPE(value) (USBC_UPCFG1_PTYPE_Msk & ((value) << USBC_UPCFG1_PTYPE_Pos)) 4290 #define USBC_UPCFG1_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG1) */ 4291 #define USBC_UPCFG1_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG1) */ 4292 #define USBC_UPCFG1_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG1) */ 4293 #define USBC_UPCFG1_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG1) */ 4294 #define USBC_UPCFG1_PTYPE_CONTROL (USBC_UPCFG1_PTYPE_CONTROL_Val << USBC_UPCFG1_PTYPE_Pos) 4295 #define USBC_UPCFG1_PTYPE_ISOCHRONOUS (USBC_UPCFG1_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG1_PTYPE_Pos) 4296 #define USBC_UPCFG1_PTYPE_BULK (USBC_UPCFG1_PTYPE_BULK_Val << USBC_UPCFG1_PTYPE_Pos) 4297 #define USBC_UPCFG1_PTYPE_INTERRUPT (USBC_UPCFG1_PTYPE_INTERRUPT_Val << USBC_UPCFG1_PTYPE_Pos) 4298 #define USBC_UPCFG1_PINGEN_Pos 20 /**< \brief (USBC_UPCFG1) Ping Enable */ 4299 #define USBC_UPCFG1_PINGEN (_U_(0x1) << USBC_UPCFG1_PINGEN_Pos) 4300 #define USBC_UPCFG1_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG1) binterval parameter */ 4301 #define USBC_UPCFG1_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG1_BINTERVAL_Pos) 4302 #define USBC_UPCFG1_BINTERVAL(value) (USBC_UPCFG1_BINTERVAL_Msk & ((value) << USBC_UPCFG1_BINTERVAL_Pos)) 4303 #define USBC_UPCFG1_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG1) MASK Register */ 4304 4305 /* -------- USBC_UPCFG2 : (USBC Offset: 0x508) (R/W 32) Pipe Configuration Register -------- */ 4306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4307 typedef union { 4308 struct { 4309 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4310 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4311 uint32_t :1; /*!< bit: 3 Reserved */ 4312 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4313 uint32_t :1; /*!< bit: 7 Reserved */ 4314 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4315 uint32_t :2; /*!< bit: 10..11 Reserved */ 4316 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4317 uint32_t :6; /*!< bit: 14..19 Reserved */ 4318 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4319 uint32_t :3; /*!< bit: 21..23 Reserved */ 4320 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4321 } bit; /*!< Structure used for bit access */ 4322 uint32_t reg; /*!< Type used for register access */ 4323 } USBC_UPCFG2_Type; 4324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4325 4326 #define USBC_UPCFG2_OFFSET 0x508 /**< \brief (USBC_UPCFG2 offset) Pipe Configuration Register */ 4327 #define USBC_UPCFG2_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG2 reset_value) Pipe Configuration Register */ 4328 4329 #define USBC_UPCFG2_PBK_Pos 2 /**< \brief (USBC_UPCFG2) Pipe Banks */ 4330 #define USBC_UPCFG2_PBK (_U_(0x1) << USBC_UPCFG2_PBK_Pos) 4331 #define USBC_UPCFG2_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG2) */ 4332 #define USBC_UPCFG2_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG2) */ 4333 #define USBC_UPCFG2_PBK_SINGLE (USBC_UPCFG2_PBK_SINGLE_Val << USBC_UPCFG2_PBK_Pos) 4334 #define USBC_UPCFG2_PBK_DOUBLE (USBC_UPCFG2_PBK_DOUBLE_Val << USBC_UPCFG2_PBK_Pos) 4335 #define USBC_UPCFG2_PSIZE_Pos 4 /**< \brief (USBC_UPCFG2) Pipe Size */ 4336 #define USBC_UPCFG2_PSIZE_Msk (_U_(0x7) << USBC_UPCFG2_PSIZE_Pos) 4337 #define USBC_UPCFG2_PSIZE(value) (USBC_UPCFG2_PSIZE_Msk & ((value) << USBC_UPCFG2_PSIZE_Pos)) 4338 #define USBC_UPCFG2_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG2) */ 4339 #define USBC_UPCFG2_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG2) */ 4340 #define USBC_UPCFG2_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG2) */ 4341 #define USBC_UPCFG2_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG2) */ 4342 #define USBC_UPCFG2_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG2) */ 4343 #define USBC_UPCFG2_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG2) */ 4344 #define USBC_UPCFG2_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG2) */ 4345 #define USBC_UPCFG2_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG2) */ 4346 #define USBC_UPCFG2_PSIZE_8 (USBC_UPCFG2_PSIZE_8_Val << USBC_UPCFG2_PSIZE_Pos) 4347 #define USBC_UPCFG2_PSIZE_16 (USBC_UPCFG2_PSIZE_16_Val << USBC_UPCFG2_PSIZE_Pos) 4348 #define USBC_UPCFG2_PSIZE_32 (USBC_UPCFG2_PSIZE_32_Val << USBC_UPCFG2_PSIZE_Pos) 4349 #define USBC_UPCFG2_PSIZE_64 (USBC_UPCFG2_PSIZE_64_Val << USBC_UPCFG2_PSIZE_Pos) 4350 #define USBC_UPCFG2_PSIZE_128 (USBC_UPCFG2_PSIZE_128_Val << USBC_UPCFG2_PSIZE_Pos) 4351 #define USBC_UPCFG2_PSIZE_256 (USBC_UPCFG2_PSIZE_256_Val << USBC_UPCFG2_PSIZE_Pos) 4352 #define USBC_UPCFG2_PSIZE_512 (USBC_UPCFG2_PSIZE_512_Val << USBC_UPCFG2_PSIZE_Pos) 4353 #define USBC_UPCFG2_PSIZE_1024 (USBC_UPCFG2_PSIZE_1024_Val << USBC_UPCFG2_PSIZE_Pos) 4354 #define USBC_UPCFG2_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG2) Pipe Token */ 4355 #define USBC_UPCFG2_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG2_PTOKEN_Pos) 4356 #define USBC_UPCFG2_PTOKEN(value) (USBC_UPCFG2_PTOKEN_Msk & ((value) << USBC_UPCFG2_PTOKEN_Pos)) 4357 #define USBC_UPCFG2_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG2) */ 4358 #define USBC_UPCFG2_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG2) */ 4359 #define USBC_UPCFG2_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG2) */ 4360 #define USBC_UPCFG2_PTOKEN_SETUP (USBC_UPCFG2_PTOKEN_SETUP_Val << USBC_UPCFG2_PTOKEN_Pos) 4361 #define USBC_UPCFG2_PTOKEN_IN (USBC_UPCFG2_PTOKEN_IN_Val << USBC_UPCFG2_PTOKEN_Pos) 4362 #define USBC_UPCFG2_PTOKEN_OUT (USBC_UPCFG2_PTOKEN_OUT_Val << USBC_UPCFG2_PTOKEN_Pos) 4363 #define USBC_UPCFG2_PTYPE_Pos 12 /**< \brief (USBC_UPCFG2) Pipe Type */ 4364 #define USBC_UPCFG2_PTYPE_Msk (_U_(0x3) << USBC_UPCFG2_PTYPE_Pos) 4365 #define USBC_UPCFG2_PTYPE(value) (USBC_UPCFG2_PTYPE_Msk & ((value) << USBC_UPCFG2_PTYPE_Pos)) 4366 #define USBC_UPCFG2_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG2) */ 4367 #define USBC_UPCFG2_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG2) */ 4368 #define USBC_UPCFG2_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG2) */ 4369 #define USBC_UPCFG2_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG2) */ 4370 #define USBC_UPCFG2_PTYPE_CONTROL (USBC_UPCFG2_PTYPE_CONTROL_Val << USBC_UPCFG2_PTYPE_Pos) 4371 #define USBC_UPCFG2_PTYPE_ISOCHRONOUS (USBC_UPCFG2_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG2_PTYPE_Pos) 4372 #define USBC_UPCFG2_PTYPE_BULK (USBC_UPCFG2_PTYPE_BULK_Val << USBC_UPCFG2_PTYPE_Pos) 4373 #define USBC_UPCFG2_PTYPE_INTERRUPT (USBC_UPCFG2_PTYPE_INTERRUPT_Val << USBC_UPCFG2_PTYPE_Pos) 4374 #define USBC_UPCFG2_PINGEN_Pos 20 /**< \brief (USBC_UPCFG2) Ping Enable */ 4375 #define USBC_UPCFG2_PINGEN (_U_(0x1) << USBC_UPCFG2_PINGEN_Pos) 4376 #define USBC_UPCFG2_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG2) binterval parameter */ 4377 #define USBC_UPCFG2_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG2_BINTERVAL_Pos) 4378 #define USBC_UPCFG2_BINTERVAL(value) (USBC_UPCFG2_BINTERVAL_Msk & ((value) << USBC_UPCFG2_BINTERVAL_Pos)) 4379 #define USBC_UPCFG2_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG2) MASK Register */ 4380 4381 /* -------- USBC_UPCFG3 : (USBC Offset: 0x50C) (R/W 32) Pipe Configuration Register -------- */ 4382 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4383 typedef union { 4384 struct { 4385 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4386 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4387 uint32_t :1; /*!< bit: 3 Reserved */ 4388 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4389 uint32_t :1; /*!< bit: 7 Reserved */ 4390 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4391 uint32_t :2; /*!< bit: 10..11 Reserved */ 4392 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4393 uint32_t :6; /*!< bit: 14..19 Reserved */ 4394 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4395 uint32_t :3; /*!< bit: 21..23 Reserved */ 4396 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4397 } bit; /*!< Structure used for bit access */ 4398 uint32_t reg; /*!< Type used for register access */ 4399 } USBC_UPCFG3_Type; 4400 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4401 4402 #define USBC_UPCFG3_OFFSET 0x50C /**< \brief (USBC_UPCFG3 offset) Pipe Configuration Register */ 4403 #define USBC_UPCFG3_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG3 reset_value) Pipe Configuration Register */ 4404 4405 #define USBC_UPCFG3_PBK_Pos 2 /**< \brief (USBC_UPCFG3) Pipe Banks */ 4406 #define USBC_UPCFG3_PBK (_U_(0x1) << USBC_UPCFG3_PBK_Pos) 4407 #define USBC_UPCFG3_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG3) */ 4408 #define USBC_UPCFG3_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG3) */ 4409 #define USBC_UPCFG3_PBK_SINGLE (USBC_UPCFG3_PBK_SINGLE_Val << USBC_UPCFG3_PBK_Pos) 4410 #define USBC_UPCFG3_PBK_DOUBLE (USBC_UPCFG3_PBK_DOUBLE_Val << USBC_UPCFG3_PBK_Pos) 4411 #define USBC_UPCFG3_PSIZE_Pos 4 /**< \brief (USBC_UPCFG3) Pipe Size */ 4412 #define USBC_UPCFG3_PSIZE_Msk (_U_(0x7) << USBC_UPCFG3_PSIZE_Pos) 4413 #define USBC_UPCFG3_PSIZE(value) (USBC_UPCFG3_PSIZE_Msk & ((value) << USBC_UPCFG3_PSIZE_Pos)) 4414 #define USBC_UPCFG3_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG3) */ 4415 #define USBC_UPCFG3_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG3) */ 4416 #define USBC_UPCFG3_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG3) */ 4417 #define USBC_UPCFG3_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG3) */ 4418 #define USBC_UPCFG3_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG3) */ 4419 #define USBC_UPCFG3_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG3) */ 4420 #define USBC_UPCFG3_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG3) */ 4421 #define USBC_UPCFG3_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG3) */ 4422 #define USBC_UPCFG3_PSIZE_8 (USBC_UPCFG3_PSIZE_8_Val << USBC_UPCFG3_PSIZE_Pos) 4423 #define USBC_UPCFG3_PSIZE_16 (USBC_UPCFG3_PSIZE_16_Val << USBC_UPCFG3_PSIZE_Pos) 4424 #define USBC_UPCFG3_PSIZE_32 (USBC_UPCFG3_PSIZE_32_Val << USBC_UPCFG3_PSIZE_Pos) 4425 #define USBC_UPCFG3_PSIZE_64 (USBC_UPCFG3_PSIZE_64_Val << USBC_UPCFG3_PSIZE_Pos) 4426 #define USBC_UPCFG3_PSIZE_128 (USBC_UPCFG3_PSIZE_128_Val << USBC_UPCFG3_PSIZE_Pos) 4427 #define USBC_UPCFG3_PSIZE_256 (USBC_UPCFG3_PSIZE_256_Val << USBC_UPCFG3_PSIZE_Pos) 4428 #define USBC_UPCFG3_PSIZE_512 (USBC_UPCFG3_PSIZE_512_Val << USBC_UPCFG3_PSIZE_Pos) 4429 #define USBC_UPCFG3_PSIZE_1024 (USBC_UPCFG3_PSIZE_1024_Val << USBC_UPCFG3_PSIZE_Pos) 4430 #define USBC_UPCFG3_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG3) Pipe Token */ 4431 #define USBC_UPCFG3_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG3_PTOKEN_Pos) 4432 #define USBC_UPCFG3_PTOKEN(value) (USBC_UPCFG3_PTOKEN_Msk & ((value) << USBC_UPCFG3_PTOKEN_Pos)) 4433 #define USBC_UPCFG3_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG3) */ 4434 #define USBC_UPCFG3_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG3) */ 4435 #define USBC_UPCFG3_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG3) */ 4436 #define USBC_UPCFG3_PTOKEN_SETUP (USBC_UPCFG3_PTOKEN_SETUP_Val << USBC_UPCFG3_PTOKEN_Pos) 4437 #define USBC_UPCFG3_PTOKEN_IN (USBC_UPCFG3_PTOKEN_IN_Val << USBC_UPCFG3_PTOKEN_Pos) 4438 #define USBC_UPCFG3_PTOKEN_OUT (USBC_UPCFG3_PTOKEN_OUT_Val << USBC_UPCFG3_PTOKEN_Pos) 4439 #define USBC_UPCFG3_PTYPE_Pos 12 /**< \brief (USBC_UPCFG3) Pipe Type */ 4440 #define USBC_UPCFG3_PTYPE_Msk (_U_(0x3) << USBC_UPCFG3_PTYPE_Pos) 4441 #define USBC_UPCFG3_PTYPE(value) (USBC_UPCFG3_PTYPE_Msk & ((value) << USBC_UPCFG3_PTYPE_Pos)) 4442 #define USBC_UPCFG3_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG3) */ 4443 #define USBC_UPCFG3_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG3) */ 4444 #define USBC_UPCFG3_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG3) */ 4445 #define USBC_UPCFG3_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG3) */ 4446 #define USBC_UPCFG3_PTYPE_CONTROL (USBC_UPCFG3_PTYPE_CONTROL_Val << USBC_UPCFG3_PTYPE_Pos) 4447 #define USBC_UPCFG3_PTYPE_ISOCHRONOUS (USBC_UPCFG3_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG3_PTYPE_Pos) 4448 #define USBC_UPCFG3_PTYPE_BULK (USBC_UPCFG3_PTYPE_BULK_Val << USBC_UPCFG3_PTYPE_Pos) 4449 #define USBC_UPCFG3_PTYPE_INTERRUPT (USBC_UPCFG3_PTYPE_INTERRUPT_Val << USBC_UPCFG3_PTYPE_Pos) 4450 #define USBC_UPCFG3_PINGEN_Pos 20 /**< \brief (USBC_UPCFG3) Ping Enable */ 4451 #define USBC_UPCFG3_PINGEN (_U_(0x1) << USBC_UPCFG3_PINGEN_Pos) 4452 #define USBC_UPCFG3_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG3) binterval parameter */ 4453 #define USBC_UPCFG3_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG3_BINTERVAL_Pos) 4454 #define USBC_UPCFG3_BINTERVAL(value) (USBC_UPCFG3_BINTERVAL_Msk & ((value) << USBC_UPCFG3_BINTERVAL_Pos)) 4455 #define USBC_UPCFG3_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG3) MASK Register */ 4456 4457 /* -------- USBC_UPCFG4 : (USBC Offset: 0x510) (R/W 32) Pipe Configuration Register -------- */ 4458 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4459 typedef union { 4460 struct { 4461 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4462 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4463 uint32_t :1; /*!< bit: 3 Reserved */ 4464 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4465 uint32_t :1; /*!< bit: 7 Reserved */ 4466 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4467 uint32_t :2; /*!< bit: 10..11 Reserved */ 4468 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4469 uint32_t :6; /*!< bit: 14..19 Reserved */ 4470 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4471 uint32_t :3; /*!< bit: 21..23 Reserved */ 4472 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4473 } bit; /*!< Structure used for bit access */ 4474 uint32_t reg; /*!< Type used for register access */ 4475 } USBC_UPCFG4_Type; 4476 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4477 4478 #define USBC_UPCFG4_OFFSET 0x510 /**< \brief (USBC_UPCFG4 offset) Pipe Configuration Register */ 4479 #define USBC_UPCFG4_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG4 reset_value) Pipe Configuration Register */ 4480 4481 #define USBC_UPCFG4_PBK_Pos 2 /**< \brief (USBC_UPCFG4) Pipe Banks */ 4482 #define USBC_UPCFG4_PBK (_U_(0x1) << USBC_UPCFG4_PBK_Pos) 4483 #define USBC_UPCFG4_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG4) */ 4484 #define USBC_UPCFG4_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG4) */ 4485 #define USBC_UPCFG4_PBK_SINGLE (USBC_UPCFG4_PBK_SINGLE_Val << USBC_UPCFG4_PBK_Pos) 4486 #define USBC_UPCFG4_PBK_DOUBLE (USBC_UPCFG4_PBK_DOUBLE_Val << USBC_UPCFG4_PBK_Pos) 4487 #define USBC_UPCFG4_PSIZE_Pos 4 /**< \brief (USBC_UPCFG4) Pipe Size */ 4488 #define USBC_UPCFG4_PSIZE_Msk (_U_(0x7) << USBC_UPCFG4_PSIZE_Pos) 4489 #define USBC_UPCFG4_PSIZE(value) (USBC_UPCFG4_PSIZE_Msk & ((value) << USBC_UPCFG4_PSIZE_Pos)) 4490 #define USBC_UPCFG4_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG4) */ 4491 #define USBC_UPCFG4_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG4) */ 4492 #define USBC_UPCFG4_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG4) */ 4493 #define USBC_UPCFG4_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG4) */ 4494 #define USBC_UPCFG4_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG4) */ 4495 #define USBC_UPCFG4_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG4) */ 4496 #define USBC_UPCFG4_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG4) */ 4497 #define USBC_UPCFG4_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG4) */ 4498 #define USBC_UPCFG4_PSIZE_8 (USBC_UPCFG4_PSIZE_8_Val << USBC_UPCFG4_PSIZE_Pos) 4499 #define USBC_UPCFG4_PSIZE_16 (USBC_UPCFG4_PSIZE_16_Val << USBC_UPCFG4_PSIZE_Pos) 4500 #define USBC_UPCFG4_PSIZE_32 (USBC_UPCFG4_PSIZE_32_Val << USBC_UPCFG4_PSIZE_Pos) 4501 #define USBC_UPCFG4_PSIZE_64 (USBC_UPCFG4_PSIZE_64_Val << USBC_UPCFG4_PSIZE_Pos) 4502 #define USBC_UPCFG4_PSIZE_128 (USBC_UPCFG4_PSIZE_128_Val << USBC_UPCFG4_PSIZE_Pos) 4503 #define USBC_UPCFG4_PSIZE_256 (USBC_UPCFG4_PSIZE_256_Val << USBC_UPCFG4_PSIZE_Pos) 4504 #define USBC_UPCFG4_PSIZE_512 (USBC_UPCFG4_PSIZE_512_Val << USBC_UPCFG4_PSIZE_Pos) 4505 #define USBC_UPCFG4_PSIZE_1024 (USBC_UPCFG4_PSIZE_1024_Val << USBC_UPCFG4_PSIZE_Pos) 4506 #define USBC_UPCFG4_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG4) Pipe Token */ 4507 #define USBC_UPCFG4_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG4_PTOKEN_Pos) 4508 #define USBC_UPCFG4_PTOKEN(value) (USBC_UPCFG4_PTOKEN_Msk & ((value) << USBC_UPCFG4_PTOKEN_Pos)) 4509 #define USBC_UPCFG4_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG4) */ 4510 #define USBC_UPCFG4_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG4) */ 4511 #define USBC_UPCFG4_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG4) */ 4512 #define USBC_UPCFG4_PTOKEN_SETUP (USBC_UPCFG4_PTOKEN_SETUP_Val << USBC_UPCFG4_PTOKEN_Pos) 4513 #define USBC_UPCFG4_PTOKEN_IN (USBC_UPCFG4_PTOKEN_IN_Val << USBC_UPCFG4_PTOKEN_Pos) 4514 #define USBC_UPCFG4_PTOKEN_OUT (USBC_UPCFG4_PTOKEN_OUT_Val << USBC_UPCFG4_PTOKEN_Pos) 4515 #define USBC_UPCFG4_PTYPE_Pos 12 /**< \brief (USBC_UPCFG4) Pipe Type */ 4516 #define USBC_UPCFG4_PTYPE_Msk (_U_(0x3) << USBC_UPCFG4_PTYPE_Pos) 4517 #define USBC_UPCFG4_PTYPE(value) (USBC_UPCFG4_PTYPE_Msk & ((value) << USBC_UPCFG4_PTYPE_Pos)) 4518 #define USBC_UPCFG4_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG4) */ 4519 #define USBC_UPCFG4_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG4) */ 4520 #define USBC_UPCFG4_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG4) */ 4521 #define USBC_UPCFG4_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG4) */ 4522 #define USBC_UPCFG4_PTYPE_CONTROL (USBC_UPCFG4_PTYPE_CONTROL_Val << USBC_UPCFG4_PTYPE_Pos) 4523 #define USBC_UPCFG4_PTYPE_ISOCHRONOUS (USBC_UPCFG4_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG4_PTYPE_Pos) 4524 #define USBC_UPCFG4_PTYPE_BULK (USBC_UPCFG4_PTYPE_BULK_Val << USBC_UPCFG4_PTYPE_Pos) 4525 #define USBC_UPCFG4_PTYPE_INTERRUPT (USBC_UPCFG4_PTYPE_INTERRUPT_Val << USBC_UPCFG4_PTYPE_Pos) 4526 #define USBC_UPCFG4_PINGEN_Pos 20 /**< \brief (USBC_UPCFG4) Ping Enable */ 4527 #define USBC_UPCFG4_PINGEN (_U_(0x1) << USBC_UPCFG4_PINGEN_Pos) 4528 #define USBC_UPCFG4_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG4) binterval parameter */ 4529 #define USBC_UPCFG4_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG4_BINTERVAL_Pos) 4530 #define USBC_UPCFG4_BINTERVAL(value) (USBC_UPCFG4_BINTERVAL_Msk & ((value) << USBC_UPCFG4_BINTERVAL_Pos)) 4531 #define USBC_UPCFG4_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG4) MASK Register */ 4532 4533 /* -------- USBC_UPCFG5 : (USBC Offset: 0x514) (R/W 32) Pipe Configuration Register -------- */ 4534 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4535 typedef union { 4536 struct { 4537 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4538 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4539 uint32_t :1; /*!< bit: 3 Reserved */ 4540 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4541 uint32_t :1; /*!< bit: 7 Reserved */ 4542 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4543 uint32_t :2; /*!< bit: 10..11 Reserved */ 4544 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4545 uint32_t :6; /*!< bit: 14..19 Reserved */ 4546 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4547 uint32_t :3; /*!< bit: 21..23 Reserved */ 4548 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4549 } bit; /*!< Structure used for bit access */ 4550 uint32_t reg; /*!< Type used for register access */ 4551 } USBC_UPCFG5_Type; 4552 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4553 4554 #define USBC_UPCFG5_OFFSET 0x514 /**< \brief (USBC_UPCFG5 offset) Pipe Configuration Register */ 4555 #define USBC_UPCFG5_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG5 reset_value) Pipe Configuration Register */ 4556 4557 #define USBC_UPCFG5_PBK_Pos 2 /**< \brief (USBC_UPCFG5) Pipe Banks */ 4558 #define USBC_UPCFG5_PBK (_U_(0x1) << USBC_UPCFG5_PBK_Pos) 4559 #define USBC_UPCFG5_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG5) */ 4560 #define USBC_UPCFG5_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG5) */ 4561 #define USBC_UPCFG5_PBK_SINGLE (USBC_UPCFG5_PBK_SINGLE_Val << USBC_UPCFG5_PBK_Pos) 4562 #define USBC_UPCFG5_PBK_DOUBLE (USBC_UPCFG5_PBK_DOUBLE_Val << USBC_UPCFG5_PBK_Pos) 4563 #define USBC_UPCFG5_PSIZE_Pos 4 /**< \brief (USBC_UPCFG5) Pipe Size */ 4564 #define USBC_UPCFG5_PSIZE_Msk (_U_(0x7) << USBC_UPCFG5_PSIZE_Pos) 4565 #define USBC_UPCFG5_PSIZE(value) (USBC_UPCFG5_PSIZE_Msk & ((value) << USBC_UPCFG5_PSIZE_Pos)) 4566 #define USBC_UPCFG5_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG5) */ 4567 #define USBC_UPCFG5_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG5) */ 4568 #define USBC_UPCFG5_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG5) */ 4569 #define USBC_UPCFG5_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG5) */ 4570 #define USBC_UPCFG5_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG5) */ 4571 #define USBC_UPCFG5_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG5) */ 4572 #define USBC_UPCFG5_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG5) */ 4573 #define USBC_UPCFG5_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG5) */ 4574 #define USBC_UPCFG5_PSIZE_8 (USBC_UPCFG5_PSIZE_8_Val << USBC_UPCFG5_PSIZE_Pos) 4575 #define USBC_UPCFG5_PSIZE_16 (USBC_UPCFG5_PSIZE_16_Val << USBC_UPCFG5_PSIZE_Pos) 4576 #define USBC_UPCFG5_PSIZE_32 (USBC_UPCFG5_PSIZE_32_Val << USBC_UPCFG5_PSIZE_Pos) 4577 #define USBC_UPCFG5_PSIZE_64 (USBC_UPCFG5_PSIZE_64_Val << USBC_UPCFG5_PSIZE_Pos) 4578 #define USBC_UPCFG5_PSIZE_128 (USBC_UPCFG5_PSIZE_128_Val << USBC_UPCFG5_PSIZE_Pos) 4579 #define USBC_UPCFG5_PSIZE_256 (USBC_UPCFG5_PSIZE_256_Val << USBC_UPCFG5_PSIZE_Pos) 4580 #define USBC_UPCFG5_PSIZE_512 (USBC_UPCFG5_PSIZE_512_Val << USBC_UPCFG5_PSIZE_Pos) 4581 #define USBC_UPCFG5_PSIZE_1024 (USBC_UPCFG5_PSIZE_1024_Val << USBC_UPCFG5_PSIZE_Pos) 4582 #define USBC_UPCFG5_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG5) Pipe Token */ 4583 #define USBC_UPCFG5_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG5_PTOKEN_Pos) 4584 #define USBC_UPCFG5_PTOKEN(value) (USBC_UPCFG5_PTOKEN_Msk & ((value) << USBC_UPCFG5_PTOKEN_Pos)) 4585 #define USBC_UPCFG5_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG5) */ 4586 #define USBC_UPCFG5_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG5) */ 4587 #define USBC_UPCFG5_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG5) */ 4588 #define USBC_UPCFG5_PTOKEN_SETUP (USBC_UPCFG5_PTOKEN_SETUP_Val << USBC_UPCFG5_PTOKEN_Pos) 4589 #define USBC_UPCFG5_PTOKEN_IN (USBC_UPCFG5_PTOKEN_IN_Val << USBC_UPCFG5_PTOKEN_Pos) 4590 #define USBC_UPCFG5_PTOKEN_OUT (USBC_UPCFG5_PTOKEN_OUT_Val << USBC_UPCFG5_PTOKEN_Pos) 4591 #define USBC_UPCFG5_PTYPE_Pos 12 /**< \brief (USBC_UPCFG5) Pipe Type */ 4592 #define USBC_UPCFG5_PTYPE_Msk (_U_(0x3) << USBC_UPCFG5_PTYPE_Pos) 4593 #define USBC_UPCFG5_PTYPE(value) (USBC_UPCFG5_PTYPE_Msk & ((value) << USBC_UPCFG5_PTYPE_Pos)) 4594 #define USBC_UPCFG5_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG5) */ 4595 #define USBC_UPCFG5_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG5) */ 4596 #define USBC_UPCFG5_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG5) */ 4597 #define USBC_UPCFG5_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG5) */ 4598 #define USBC_UPCFG5_PTYPE_CONTROL (USBC_UPCFG5_PTYPE_CONTROL_Val << USBC_UPCFG5_PTYPE_Pos) 4599 #define USBC_UPCFG5_PTYPE_ISOCHRONOUS (USBC_UPCFG5_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG5_PTYPE_Pos) 4600 #define USBC_UPCFG5_PTYPE_BULK (USBC_UPCFG5_PTYPE_BULK_Val << USBC_UPCFG5_PTYPE_Pos) 4601 #define USBC_UPCFG5_PTYPE_INTERRUPT (USBC_UPCFG5_PTYPE_INTERRUPT_Val << USBC_UPCFG5_PTYPE_Pos) 4602 #define USBC_UPCFG5_PINGEN_Pos 20 /**< \brief (USBC_UPCFG5) Ping Enable */ 4603 #define USBC_UPCFG5_PINGEN (_U_(0x1) << USBC_UPCFG5_PINGEN_Pos) 4604 #define USBC_UPCFG5_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG5) binterval parameter */ 4605 #define USBC_UPCFG5_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG5_BINTERVAL_Pos) 4606 #define USBC_UPCFG5_BINTERVAL(value) (USBC_UPCFG5_BINTERVAL_Msk & ((value) << USBC_UPCFG5_BINTERVAL_Pos)) 4607 #define USBC_UPCFG5_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG5) MASK Register */ 4608 4609 /* -------- USBC_UPCFG6 : (USBC Offset: 0x518) (R/W 32) Pipe Configuration Register -------- */ 4610 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4611 typedef union { 4612 struct { 4613 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4614 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4615 uint32_t :1; /*!< bit: 3 Reserved */ 4616 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4617 uint32_t :1; /*!< bit: 7 Reserved */ 4618 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4619 uint32_t :2; /*!< bit: 10..11 Reserved */ 4620 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4621 uint32_t :6; /*!< bit: 14..19 Reserved */ 4622 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4623 uint32_t :3; /*!< bit: 21..23 Reserved */ 4624 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4625 } bit; /*!< Structure used for bit access */ 4626 uint32_t reg; /*!< Type used for register access */ 4627 } USBC_UPCFG6_Type; 4628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4629 4630 #define USBC_UPCFG6_OFFSET 0x518 /**< \brief (USBC_UPCFG6 offset) Pipe Configuration Register */ 4631 #define USBC_UPCFG6_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG6 reset_value) Pipe Configuration Register */ 4632 4633 #define USBC_UPCFG6_PBK_Pos 2 /**< \brief (USBC_UPCFG6) Pipe Banks */ 4634 #define USBC_UPCFG6_PBK (_U_(0x1) << USBC_UPCFG6_PBK_Pos) 4635 #define USBC_UPCFG6_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG6) */ 4636 #define USBC_UPCFG6_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG6) */ 4637 #define USBC_UPCFG6_PBK_SINGLE (USBC_UPCFG6_PBK_SINGLE_Val << USBC_UPCFG6_PBK_Pos) 4638 #define USBC_UPCFG6_PBK_DOUBLE (USBC_UPCFG6_PBK_DOUBLE_Val << USBC_UPCFG6_PBK_Pos) 4639 #define USBC_UPCFG6_PSIZE_Pos 4 /**< \brief (USBC_UPCFG6) Pipe Size */ 4640 #define USBC_UPCFG6_PSIZE_Msk (_U_(0x7) << USBC_UPCFG6_PSIZE_Pos) 4641 #define USBC_UPCFG6_PSIZE(value) (USBC_UPCFG6_PSIZE_Msk & ((value) << USBC_UPCFG6_PSIZE_Pos)) 4642 #define USBC_UPCFG6_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG6) */ 4643 #define USBC_UPCFG6_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG6) */ 4644 #define USBC_UPCFG6_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG6) */ 4645 #define USBC_UPCFG6_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG6) */ 4646 #define USBC_UPCFG6_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG6) */ 4647 #define USBC_UPCFG6_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG6) */ 4648 #define USBC_UPCFG6_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG6) */ 4649 #define USBC_UPCFG6_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG6) */ 4650 #define USBC_UPCFG6_PSIZE_8 (USBC_UPCFG6_PSIZE_8_Val << USBC_UPCFG6_PSIZE_Pos) 4651 #define USBC_UPCFG6_PSIZE_16 (USBC_UPCFG6_PSIZE_16_Val << USBC_UPCFG6_PSIZE_Pos) 4652 #define USBC_UPCFG6_PSIZE_32 (USBC_UPCFG6_PSIZE_32_Val << USBC_UPCFG6_PSIZE_Pos) 4653 #define USBC_UPCFG6_PSIZE_64 (USBC_UPCFG6_PSIZE_64_Val << USBC_UPCFG6_PSIZE_Pos) 4654 #define USBC_UPCFG6_PSIZE_128 (USBC_UPCFG6_PSIZE_128_Val << USBC_UPCFG6_PSIZE_Pos) 4655 #define USBC_UPCFG6_PSIZE_256 (USBC_UPCFG6_PSIZE_256_Val << USBC_UPCFG6_PSIZE_Pos) 4656 #define USBC_UPCFG6_PSIZE_512 (USBC_UPCFG6_PSIZE_512_Val << USBC_UPCFG6_PSIZE_Pos) 4657 #define USBC_UPCFG6_PSIZE_1024 (USBC_UPCFG6_PSIZE_1024_Val << USBC_UPCFG6_PSIZE_Pos) 4658 #define USBC_UPCFG6_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG6) Pipe Token */ 4659 #define USBC_UPCFG6_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG6_PTOKEN_Pos) 4660 #define USBC_UPCFG6_PTOKEN(value) (USBC_UPCFG6_PTOKEN_Msk & ((value) << USBC_UPCFG6_PTOKEN_Pos)) 4661 #define USBC_UPCFG6_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG6) */ 4662 #define USBC_UPCFG6_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG6) */ 4663 #define USBC_UPCFG6_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG6) */ 4664 #define USBC_UPCFG6_PTOKEN_SETUP (USBC_UPCFG6_PTOKEN_SETUP_Val << USBC_UPCFG6_PTOKEN_Pos) 4665 #define USBC_UPCFG6_PTOKEN_IN (USBC_UPCFG6_PTOKEN_IN_Val << USBC_UPCFG6_PTOKEN_Pos) 4666 #define USBC_UPCFG6_PTOKEN_OUT (USBC_UPCFG6_PTOKEN_OUT_Val << USBC_UPCFG6_PTOKEN_Pos) 4667 #define USBC_UPCFG6_PTYPE_Pos 12 /**< \brief (USBC_UPCFG6) Pipe Type */ 4668 #define USBC_UPCFG6_PTYPE_Msk (_U_(0x3) << USBC_UPCFG6_PTYPE_Pos) 4669 #define USBC_UPCFG6_PTYPE(value) (USBC_UPCFG6_PTYPE_Msk & ((value) << USBC_UPCFG6_PTYPE_Pos)) 4670 #define USBC_UPCFG6_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG6) */ 4671 #define USBC_UPCFG6_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG6) */ 4672 #define USBC_UPCFG6_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG6) */ 4673 #define USBC_UPCFG6_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG6) */ 4674 #define USBC_UPCFG6_PTYPE_CONTROL (USBC_UPCFG6_PTYPE_CONTROL_Val << USBC_UPCFG6_PTYPE_Pos) 4675 #define USBC_UPCFG6_PTYPE_ISOCHRONOUS (USBC_UPCFG6_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG6_PTYPE_Pos) 4676 #define USBC_UPCFG6_PTYPE_BULK (USBC_UPCFG6_PTYPE_BULK_Val << USBC_UPCFG6_PTYPE_Pos) 4677 #define USBC_UPCFG6_PTYPE_INTERRUPT (USBC_UPCFG6_PTYPE_INTERRUPT_Val << USBC_UPCFG6_PTYPE_Pos) 4678 #define USBC_UPCFG6_PINGEN_Pos 20 /**< \brief (USBC_UPCFG6) Ping Enable */ 4679 #define USBC_UPCFG6_PINGEN (_U_(0x1) << USBC_UPCFG6_PINGEN_Pos) 4680 #define USBC_UPCFG6_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG6) binterval parameter */ 4681 #define USBC_UPCFG6_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG6_BINTERVAL_Pos) 4682 #define USBC_UPCFG6_BINTERVAL(value) (USBC_UPCFG6_BINTERVAL_Msk & ((value) << USBC_UPCFG6_BINTERVAL_Pos)) 4683 #define USBC_UPCFG6_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG6) MASK Register */ 4684 4685 /* -------- USBC_UPCFG7 : (USBC Offset: 0x51C) (R/W 32) Pipe Configuration Register -------- */ 4686 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4687 typedef union { 4688 struct { 4689 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 4690 uint32_t PBK:1; /*!< bit: 2 Pipe Banks */ 4691 uint32_t :1; /*!< bit: 3 Reserved */ 4692 uint32_t PSIZE:3; /*!< bit: 4.. 6 Pipe Size */ 4693 uint32_t :1; /*!< bit: 7 Reserved */ 4694 uint32_t PTOKEN:2; /*!< bit: 8.. 9 Pipe Token */ 4695 uint32_t :2; /*!< bit: 10..11 Reserved */ 4696 uint32_t PTYPE:2; /*!< bit: 12..13 Pipe Type */ 4697 uint32_t :6; /*!< bit: 14..19 Reserved */ 4698 uint32_t PINGEN:1; /*!< bit: 20 Ping Enable */ 4699 uint32_t :3; /*!< bit: 21..23 Reserved */ 4700 uint32_t BINTERVAL:8; /*!< bit: 24..31 binterval parameter */ 4701 } bit; /*!< Structure used for bit access */ 4702 uint32_t reg; /*!< Type used for register access */ 4703 } USBC_UPCFG7_Type; 4704 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4705 4706 #define USBC_UPCFG7_OFFSET 0x51C /**< \brief (USBC_UPCFG7 offset) Pipe Configuration Register */ 4707 #define USBC_UPCFG7_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCFG7 reset_value) Pipe Configuration Register */ 4708 4709 #define USBC_UPCFG7_PBK_Pos 2 /**< \brief (USBC_UPCFG7) Pipe Banks */ 4710 #define USBC_UPCFG7_PBK (_U_(0x1) << USBC_UPCFG7_PBK_Pos) 4711 #define USBC_UPCFG7_PBK_SINGLE_Val _U_(0x0) /**< \brief (USBC_UPCFG7) */ 4712 #define USBC_UPCFG7_PBK_DOUBLE_Val _U_(0x1) /**< \brief (USBC_UPCFG7) */ 4713 #define USBC_UPCFG7_PBK_SINGLE (USBC_UPCFG7_PBK_SINGLE_Val << USBC_UPCFG7_PBK_Pos) 4714 #define USBC_UPCFG7_PBK_DOUBLE (USBC_UPCFG7_PBK_DOUBLE_Val << USBC_UPCFG7_PBK_Pos) 4715 #define USBC_UPCFG7_PSIZE_Pos 4 /**< \brief (USBC_UPCFG7) Pipe Size */ 4716 #define USBC_UPCFG7_PSIZE_Msk (_U_(0x7) << USBC_UPCFG7_PSIZE_Pos) 4717 #define USBC_UPCFG7_PSIZE(value) (USBC_UPCFG7_PSIZE_Msk & ((value) << USBC_UPCFG7_PSIZE_Pos)) 4718 #define USBC_UPCFG7_PSIZE_8_Val _U_(0x0) /**< \brief (USBC_UPCFG7) */ 4719 #define USBC_UPCFG7_PSIZE_16_Val _U_(0x1) /**< \brief (USBC_UPCFG7) */ 4720 #define USBC_UPCFG7_PSIZE_32_Val _U_(0x2) /**< \brief (USBC_UPCFG7) */ 4721 #define USBC_UPCFG7_PSIZE_64_Val _U_(0x3) /**< \brief (USBC_UPCFG7) */ 4722 #define USBC_UPCFG7_PSIZE_128_Val _U_(0x4) /**< \brief (USBC_UPCFG7) */ 4723 #define USBC_UPCFG7_PSIZE_256_Val _U_(0x5) /**< \brief (USBC_UPCFG7) */ 4724 #define USBC_UPCFG7_PSIZE_512_Val _U_(0x6) /**< \brief (USBC_UPCFG7) */ 4725 #define USBC_UPCFG7_PSIZE_1024_Val _U_(0x7) /**< \brief (USBC_UPCFG7) */ 4726 #define USBC_UPCFG7_PSIZE_8 (USBC_UPCFG7_PSIZE_8_Val << USBC_UPCFG7_PSIZE_Pos) 4727 #define USBC_UPCFG7_PSIZE_16 (USBC_UPCFG7_PSIZE_16_Val << USBC_UPCFG7_PSIZE_Pos) 4728 #define USBC_UPCFG7_PSIZE_32 (USBC_UPCFG7_PSIZE_32_Val << USBC_UPCFG7_PSIZE_Pos) 4729 #define USBC_UPCFG7_PSIZE_64 (USBC_UPCFG7_PSIZE_64_Val << USBC_UPCFG7_PSIZE_Pos) 4730 #define USBC_UPCFG7_PSIZE_128 (USBC_UPCFG7_PSIZE_128_Val << USBC_UPCFG7_PSIZE_Pos) 4731 #define USBC_UPCFG7_PSIZE_256 (USBC_UPCFG7_PSIZE_256_Val << USBC_UPCFG7_PSIZE_Pos) 4732 #define USBC_UPCFG7_PSIZE_512 (USBC_UPCFG7_PSIZE_512_Val << USBC_UPCFG7_PSIZE_Pos) 4733 #define USBC_UPCFG7_PSIZE_1024 (USBC_UPCFG7_PSIZE_1024_Val << USBC_UPCFG7_PSIZE_Pos) 4734 #define USBC_UPCFG7_PTOKEN_Pos 8 /**< \brief (USBC_UPCFG7) Pipe Token */ 4735 #define USBC_UPCFG7_PTOKEN_Msk (_U_(0x3) << USBC_UPCFG7_PTOKEN_Pos) 4736 #define USBC_UPCFG7_PTOKEN(value) (USBC_UPCFG7_PTOKEN_Msk & ((value) << USBC_UPCFG7_PTOKEN_Pos)) 4737 #define USBC_UPCFG7_PTOKEN_SETUP_Val _U_(0x0) /**< \brief (USBC_UPCFG7) */ 4738 #define USBC_UPCFG7_PTOKEN_IN_Val _U_(0x1) /**< \brief (USBC_UPCFG7) */ 4739 #define USBC_UPCFG7_PTOKEN_OUT_Val _U_(0x2) /**< \brief (USBC_UPCFG7) */ 4740 #define USBC_UPCFG7_PTOKEN_SETUP (USBC_UPCFG7_PTOKEN_SETUP_Val << USBC_UPCFG7_PTOKEN_Pos) 4741 #define USBC_UPCFG7_PTOKEN_IN (USBC_UPCFG7_PTOKEN_IN_Val << USBC_UPCFG7_PTOKEN_Pos) 4742 #define USBC_UPCFG7_PTOKEN_OUT (USBC_UPCFG7_PTOKEN_OUT_Val << USBC_UPCFG7_PTOKEN_Pos) 4743 #define USBC_UPCFG7_PTYPE_Pos 12 /**< \brief (USBC_UPCFG7) Pipe Type */ 4744 #define USBC_UPCFG7_PTYPE_Msk (_U_(0x3) << USBC_UPCFG7_PTYPE_Pos) 4745 #define USBC_UPCFG7_PTYPE(value) (USBC_UPCFG7_PTYPE_Msk & ((value) << USBC_UPCFG7_PTYPE_Pos)) 4746 #define USBC_UPCFG7_PTYPE_CONTROL_Val _U_(0x0) /**< \brief (USBC_UPCFG7) */ 4747 #define USBC_UPCFG7_PTYPE_ISOCHRONOUS_Val _U_(0x1) /**< \brief (USBC_UPCFG7) */ 4748 #define USBC_UPCFG7_PTYPE_BULK_Val _U_(0x2) /**< \brief (USBC_UPCFG7) */ 4749 #define USBC_UPCFG7_PTYPE_INTERRUPT_Val _U_(0x3) /**< \brief (USBC_UPCFG7) */ 4750 #define USBC_UPCFG7_PTYPE_CONTROL (USBC_UPCFG7_PTYPE_CONTROL_Val << USBC_UPCFG7_PTYPE_Pos) 4751 #define USBC_UPCFG7_PTYPE_ISOCHRONOUS (USBC_UPCFG7_PTYPE_ISOCHRONOUS_Val << USBC_UPCFG7_PTYPE_Pos) 4752 #define USBC_UPCFG7_PTYPE_BULK (USBC_UPCFG7_PTYPE_BULK_Val << USBC_UPCFG7_PTYPE_Pos) 4753 #define USBC_UPCFG7_PTYPE_INTERRUPT (USBC_UPCFG7_PTYPE_INTERRUPT_Val << USBC_UPCFG7_PTYPE_Pos) 4754 #define USBC_UPCFG7_PINGEN_Pos 20 /**< \brief (USBC_UPCFG7) Ping Enable */ 4755 #define USBC_UPCFG7_PINGEN (_U_(0x1) << USBC_UPCFG7_PINGEN_Pos) 4756 #define USBC_UPCFG7_BINTERVAL_Pos 24 /**< \brief (USBC_UPCFG7) binterval parameter */ 4757 #define USBC_UPCFG7_BINTERVAL_Msk (_U_(0xFF) << USBC_UPCFG7_BINTERVAL_Pos) 4758 #define USBC_UPCFG7_BINTERVAL(value) (USBC_UPCFG7_BINTERVAL_Msk & ((value) << USBC_UPCFG7_BINTERVAL_Pos)) 4759 #define USBC_UPCFG7_MASK _U_(0xFF103374) /**< \brief (USBC_UPCFG7) MASK Register */ 4760 4761 /* -------- USBC_UPSTA0 : (USBC Offset: 0x530) (R/ 32) Pipe Status Register -------- */ 4762 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4763 typedef union { 4764 struct { 4765 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 4766 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 4767 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 4768 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 4769 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 4770 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 4771 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 4772 uint32_t :1; /*!< bit: 7 Reserved */ 4773 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 4774 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 4775 uint32_t :1; /*!< bit: 11 Reserved */ 4776 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 4777 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 4778 uint32_t :16; /*!< bit: 16..31 Reserved */ 4779 } bit; /*!< Structure used for bit access */ 4780 uint32_t reg; /*!< Type used for register access */ 4781 } USBC_UPSTA0_Type; 4782 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4783 4784 #define USBC_UPSTA0_OFFSET 0x530 /**< \brief (USBC_UPSTA0 offset) Pipe Status Register */ 4785 #define USBC_UPSTA0_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA0 reset_value) Pipe Status Register */ 4786 4787 #define USBC_UPSTA0_RXINI_Pos 0 /**< \brief (USBC_UPSTA0) Received IN Data Interrupt */ 4788 #define USBC_UPSTA0_RXINI (_U_(0x1) << USBC_UPSTA0_RXINI_Pos) 4789 #define USBC_UPSTA0_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA0) Transmitted OUT Data Interrupt */ 4790 #define USBC_UPSTA0_TXOUTI (_U_(0x1) << USBC_UPSTA0_TXOUTI_Pos) 4791 #define USBC_UPSTA0_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA0) Transmitted SETUP Interrupt */ 4792 #define USBC_UPSTA0_TXSTPI (_U_(0x1) << USBC_UPSTA0_TXSTPI_Pos) 4793 #define USBC_UPSTA0_PERRI_Pos 3 /**< \brief (USBC_UPSTA0) Pipe Error Interrupt */ 4794 #define USBC_UPSTA0_PERRI (_U_(0x1) << USBC_UPSTA0_PERRI_Pos) 4795 #define USBC_UPSTA0_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA0) NAKed Interrupt */ 4796 #define USBC_UPSTA0_NAKEDI (_U_(0x1) << USBC_UPSTA0_NAKEDI_Pos) 4797 #define USBC_UPSTA0_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA0) Errorflow Interrupt */ 4798 #define USBC_UPSTA0_ERRORFI (_U_(0x1) << USBC_UPSTA0_ERRORFI_Pos) 4799 #define USBC_UPSTA0_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA0) Received STALLed Interrupt */ 4800 #define USBC_UPSTA0_RXSTALLDI (_U_(0x1) << USBC_UPSTA0_RXSTALLDI_Pos) 4801 #define USBC_UPSTA0_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA0) Data Toggle Sequence */ 4802 #define USBC_UPSTA0_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA0_DTSEQ_Pos) 4803 #define USBC_UPSTA0_DTSEQ(value) (USBC_UPSTA0_DTSEQ_Msk & ((value) << USBC_UPSTA0_DTSEQ_Pos)) 4804 #define USBC_UPSTA0_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA0) Ram Access Error Interrupt */ 4805 #define USBC_UPSTA0_RAMACERI (_U_(0x1) << USBC_UPSTA0_RAMACERI_Pos) 4806 #define USBC_UPSTA0_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA0) Number of Busy Bank */ 4807 #define USBC_UPSTA0_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA0_NBUSYBK_Pos) 4808 #define USBC_UPSTA0_NBUSYBK(value) (USBC_UPSTA0_NBUSYBK_Msk & ((value) << USBC_UPSTA0_NBUSYBK_Pos)) 4809 #define USBC_UPSTA0_CURRBK_Pos 14 /**< \brief (USBC_UPSTA0) Current Bank */ 4810 #define USBC_UPSTA0_CURRBK_Msk (_U_(0x3) << USBC_UPSTA0_CURRBK_Pos) 4811 #define USBC_UPSTA0_CURRBK(value) (USBC_UPSTA0_CURRBK_Msk & ((value) << USBC_UPSTA0_CURRBK_Pos)) 4812 #define USBC_UPSTA0_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA0) MASK Register */ 4813 4814 /* -------- USBC_UPSTA1 : (USBC Offset: 0x534) (R/ 32) Pipe Status Register -------- */ 4815 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4816 typedef union { 4817 struct { 4818 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 4819 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 4820 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 4821 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 4822 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 4823 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 4824 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 4825 uint32_t :1; /*!< bit: 7 Reserved */ 4826 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 4827 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 4828 uint32_t :1; /*!< bit: 11 Reserved */ 4829 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 4830 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 4831 uint32_t :16; /*!< bit: 16..31 Reserved */ 4832 } bit; /*!< Structure used for bit access */ 4833 uint32_t reg; /*!< Type used for register access */ 4834 } USBC_UPSTA1_Type; 4835 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4836 4837 #define USBC_UPSTA1_OFFSET 0x534 /**< \brief (USBC_UPSTA1 offset) Pipe Status Register */ 4838 #define USBC_UPSTA1_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA1 reset_value) Pipe Status Register */ 4839 4840 #define USBC_UPSTA1_RXINI_Pos 0 /**< \brief (USBC_UPSTA1) Received IN Data Interrupt */ 4841 #define USBC_UPSTA1_RXINI (_U_(0x1) << USBC_UPSTA1_RXINI_Pos) 4842 #define USBC_UPSTA1_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA1) Transmitted OUT Data Interrupt */ 4843 #define USBC_UPSTA1_TXOUTI (_U_(0x1) << USBC_UPSTA1_TXOUTI_Pos) 4844 #define USBC_UPSTA1_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA1) Transmitted SETUP Interrupt */ 4845 #define USBC_UPSTA1_TXSTPI (_U_(0x1) << USBC_UPSTA1_TXSTPI_Pos) 4846 #define USBC_UPSTA1_PERRI_Pos 3 /**< \brief (USBC_UPSTA1) Pipe Error Interrupt */ 4847 #define USBC_UPSTA1_PERRI (_U_(0x1) << USBC_UPSTA1_PERRI_Pos) 4848 #define USBC_UPSTA1_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA1) NAKed Interrupt */ 4849 #define USBC_UPSTA1_NAKEDI (_U_(0x1) << USBC_UPSTA1_NAKEDI_Pos) 4850 #define USBC_UPSTA1_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA1) Errorflow Interrupt */ 4851 #define USBC_UPSTA1_ERRORFI (_U_(0x1) << USBC_UPSTA1_ERRORFI_Pos) 4852 #define USBC_UPSTA1_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA1) Received STALLed Interrupt */ 4853 #define USBC_UPSTA1_RXSTALLDI (_U_(0x1) << USBC_UPSTA1_RXSTALLDI_Pos) 4854 #define USBC_UPSTA1_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA1) Data Toggle Sequence */ 4855 #define USBC_UPSTA1_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA1_DTSEQ_Pos) 4856 #define USBC_UPSTA1_DTSEQ(value) (USBC_UPSTA1_DTSEQ_Msk & ((value) << USBC_UPSTA1_DTSEQ_Pos)) 4857 #define USBC_UPSTA1_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA1) Ram Access Error Interrupt */ 4858 #define USBC_UPSTA1_RAMACERI (_U_(0x1) << USBC_UPSTA1_RAMACERI_Pos) 4859 #define USBC_UPSTA1_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA1) Number of Busy Bank */ 4860 #define USBC_UPSTA1_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA1_NBUSYBK_Pos) 4861 #define USBC_UPSTA1_NBUSYBK(value) (USBC_UPSTA1_NBUSYBK_Msk & ((value) << USBC_UPSTA1_NBUSYBK_Pos)) 4862 #define USBC_UPSTA1_CURRBK_Pos 14 /**< \brief (USBC_UPSTA1) Current Bank */ 4863 #define USBC_UPSTA1_CURRBK_Msk (_U_(0x3) << USBC_UPSTA1_CURRBK_Pos) 4864 #define USBC_UPSTA1_CURRBK(value) (USBC_UPSTA1_CURRBK_Msk & ((value) << USBC_UPSTA1_CURRBK_Pos)) 4865 #define USBC_UPSTA1_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA1) MASK Register */ 4866 4867 /* -------- USBC_UPSTA2 : (USBC Offset: 0x538) (R/ 32) Pipe Status Register -------- */ 4868 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4869 typedef union { 4870 struct { 4871 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 4872 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 4873 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 4874 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 4875 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 4876 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 4877 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 4878 uint32_t :1; /*!< bit: 7 Reserved */ 4879 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 4880 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 4881 uint32_t :1; /*!< bit: 11 Reserved */ 4882 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 4883 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 4884 uint32_t :16; /*!< bit: 16..31 Reserved */ 4885 } bit; /*!< Structure used for bit access */ 4886 uint32_t reg; /*!< Type used for register access */ 4887 } USBC_UPSTA2_Type; 4888 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4889 4890 #define USBC_UPSTA2_OFFSET 0x538 /**< \brief (USBC_UPSTA2 offset) Pipe Status Register */ 4891 #define USBC_UPSTA2_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA2 reset_value) Pipe Status Register */ 4892 4893 #define USBC_UPSTA2_RXINI_Pos 0 /**< \brief (USBC_UPSTA2) Received IN Data Interrupt */ 4894 #define USBC_UPSTA2_RXINI (_U_(0x1) << USBC_UPSTA2_RXINI_Pos) 4895 #define USBC_UPSTA2_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA2) Transmitted OUT Data Interrupt */ 4896 #define USBC_UPSTA2_TXOUTI (_U_(0x1) << USBC_UPSTA2_TXOUTI_Pos) 4897 #define USBC_UPSTA2_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA2) Transmitted SETUP Interrupt */ 4898 #define USBC_UPSTA2_TXSTPI (_U_(0x1) << USBC_UPSTA2_TXSTPI_Pos) 4899 #define USBC_UPSTA2_PERRI_Pos 3 /**< \brief (USBC_UPSTA2) Pipe Error Interrupt */ 4900 #define USBC_UPSTA2_PERRI (_U_(0x1) << USBC_UPSTA2_PERRI_Pos) 4901 #define USBC_UPSTA2_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA2) NAKed Interrupt */ 4902 #define USBC_UPSTA2_NAKEDI (_U_(0x1) << USBC_UPSTA2_NAKEDI_Pos) 4903 #define USBC_UPSTA2_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA2) Errorflow Interrupt */ 4904 #define USBC_UPSTA2_ERRORFI (_U_(0x1) << USBC_UPSTA2_ERRORFI_Pos) 4905 #define USBC_UPSTA2_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA2) Received STALLed Interrupt */ 4906 #define USBC_UPSTA2_RXSTALLDI (_U_(0x1) << USBC_UPSTA2_RXSTALLDI_Pos) 4907 #define USBC_UPSTA2_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA2) Data Toggle Sequence */ 4908 #define USBC_UPSTA2_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA2_DTSEQ_Pos) 4909 #define USBC_UPSTA2_DTSEQ(value) (USBC_UPSTA2_DTSEQ_Msk & ((value) << USBC_UPSTA2_DTSEQ_Pos)) 4910 #define USBC_UPSTA2_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA2) Ram Access Error Interrupt */ 4911 #define USBC_UPSTA2_RAMACERI (_U_(0x1) << USBC_UPSTA2_RAMACERI_Pos) 4912 #define USBC_UPSTA2_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA2) Number of Busy Bank */ 4913 #define USBC_UPSTA2_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA2_NBUSYBK_Pos) 4914 #define USBC_UPSTA2_NBUSYBK(value) (USBC_UPSTA2_NBUSYBK_Msk & ((value) << USBC_UPSTA2_NBUSYBK_Pos)) 4915 #define USBC_UPSTA2_CURRBK_Pos 14 /**< \brief (USBC_UPSTA2) Current Bank */ 4916 #define USBC_UPSTA2_CURRBK_Msk (_U_(0x3) << USBC_UPSTA2_CURRBK_Pos) 4917 #define USBC_UPSTA2_CURRBK(value) (USBC_UPSTA2_CURRBK_Msk & ((value) << USBC_UPSTA2_CURRBK_Pos)) 4918 #define USBC_UPSTA2_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA2) MASK Register */ 4919 4920 /* -------- USBC_UPSTA3 : (USBC Offset: 0x53C) (R/ 32) Pipe Status Register -------- */ 4921 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4922 typedef union { 4923 struct { 4924 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 4925 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 4926 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 4927 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 4928 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 4929 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 4930 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 4931 uint32_t :1; /*!< bit: 7 Reserved */ 4932 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 4933 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 4934 uint32_t :1; /*!< bit: 11 Reserved */ 4935 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 4936 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 4937 uint32_t :16; /*!< bit: 16..31 Reserved */ 4938 } bit; /*!< Structure used for bit access */ 4939 uint32_t reg; /*!< Type used for register access */ 4940 } USBC_UPSTA3_Type; 4941 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4942 4943 #define USBC_UPSTA3_OFFSET 0x53C /**< \brief (USBC_UPSTA3 offset) Pipe Status Register */ 4944 #define USBC_UPSTA3_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA3 reset_value) Pipe Status Register */ 4945 4946 #define USBC_UPSTA3_RXINI_Pos 0 /**< \brief (USBC_UPSTA3) Received IN Data Interrupt */ 4947 #define USBC_UPSTA3_RXINI (_U_(0x1) << USBC_UPSTA3_RXINI_Pos) 4948 #define USBC_UPSTA3_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA3) Transmitted OUT Data Interrupt */ 4949 #define USBC_UPSTA3_TXOUTI (_U_(0x1) << USBC_UPSTA3_TXOUTI_Pos) 4950 #define USBC_UPSTA3_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA3) Transmitted SETUP Interrupt */ 4951 #define USBC_UPSTA3_TXSTPI (_U_(0x1) << USBC_UPSTA3_TXSTPI_Pos) 4952 #define USBC_UPSTA3_PERRI_Pos 3 /**< \brief (USBC_UPSTA3) Pipe Error Interrupt */ 4953 #define USBC_UPSTA3_PERRI (_U_(0x1) << USBC_UPSTA3_PERRI_Pos) 4954 #define USBC_UPSTA3_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA3) NAKed Interrupt */ 4955 #define USBC_UPSTA3_NAKEDI (_U_(0x1) << USBC_UPSTA3_NAKEDI_Pos) 4956 #define USBC_UPSTA3_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA3) Errorflow Interrupt */ 4957 #define USBC_UPSTA3_ERRORFI (_U_(0x1) << USBC_UPSTA3_ERRORFI_Pos) 4958 #define USBC_UPSTA3_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA3) Received STALLed Interrupt */ 4959 #define USBC_UPSTA3_RXSTALLDI (_U_(0x1) << USBC_UPSTA3_RXSTALLDI_Pos) 4960 #define USBC_UPSTA3_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA3) Data Toggle Sequence */ 4961 #define USBC_UPSTA3_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA3_DTSEQ_Pos) 4962 #define USBC_UPSTA3_DTSEQ(value) (USBC_UPSTA3_DTSEQ_Msk & ((value) << USBC_UPSTA3_DTSEQ_Pos)) 4963 #define USBC_UPSTA3_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA3) Ram Access Error Interrupt */ 4964 #define USBC_UPSTA3_RAMACERI (_U_(0x1) << USBC_UPSTA3_RAMACERI_Pos) 4965 #define USBC_UPSTA3_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA3) Number of Busy Bank */ 4966 #define USBC_UPSTA3_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA3_NBUSYBK_Pos) 4967 #define USBC_UPSTA3_NBUSYBK(value) (USBC_UPSTA3_NBUSYBK_Msk & ((value) << USBC_UPSTA3_NBUSYBK_Pos)) 4968 #define USBC_UPSTA3_CURRBK_Pos 14 /**< \brief (USBC_UPSTA3) Current Bank */ 4969 #define USBC_UPSTA3_CURRBK_Msk (_U_(0x3) << USBC_UPSTA3_CURRBK_Pos) 4970 #define USBC_UPSTA3_CURRBK(value) (USBC_UPSTA3_CURRBK_Msk & ((value) << USBC_UPSTA3_CURRBK_Pos)) 4971 #define USBC_UPSTA3_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA3) MASK Register */ 4972 4973 /* -------- USBC_UPSTA4 : (USBC Offset: 0x540) (R/ 32) Pipe Status Register -------- */ 4974 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 4975 typedef union { 4976 struct { 4977 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 4978 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 4979 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 4980 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 4981 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 4982 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 4983 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 4984 uint32_t :1; /*!< bit: 7 Reserved */ 4985 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 4986 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 4987 uint32_t :1; /*!< bit: 11 Reserved */ 4988 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 4989 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 4990 uint32_t :16; /*!< bit: 16..31 Reserved */ 4991 } bit; /*!< Structure used for bit access */ 4992 uint32_t reg; /*!< Type used for register access */ 4993 } USBC_UPSTA4_Type; 4994 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 4995 4996 #define USBC_UPSTA4_OFFSET 0x540 /**< \brief (USBC_UPSTA4 offset) Pipe Status Register */ 4997 #define USBC_UPSTA4_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA4 reset_value) Pipe Status Register */ 4998 4999 #define USBC_UPSTA4_RXINI_Pos 0 /**< \brief (USBC_UPSTA4) Received IN Data Interrupt */ 5000 #define USBC_UPSTA4_RXINI (_U_(0x1) << USBC_UPSTA4_RXINI_Pos) 5001 #define USBC_UPSTA4_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA4) Transmitted OUT Data Interrupt */ 5002 #define USBC_UPSTA4_TXOUTI (_U_(0x1) << USBC_UPSTA4_TXOUTI_Pos) 5003 #define USBC_UPSTA4_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA4) Transmitted SETUP Interrupt */ 5004 #define USBC_UPSTA4_TXSTPI (_U_(0x1) << USBC_UPSTA4_TXSTPI_Pos) 5005 #define USBC_UPSTA4_PERRI_Pos 3 /**< \brief (USBC_UPSTA4) Pipe Error Interrupt */ 5006 #define USBC_UPSTA4_PERRI (_U_(0x1) << USBC_UPSTA4_PERRI_Pos) 5007 #define USBC_UPSTA4_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA4) NAKed Interrupt */ 5008 #define USBC_UPSTA4_NAKEDI (_U_(0x1) << USBC_UPSTA4_NAKEDI_Pos) 5009 #define USBC_UPSTA4_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA4) Errorflow Interrupt */ 5010 #define USBC_UPSTA4_ERRORFI (_U_(0x1) << USBC_UPSTA4_ERRORFI_Pos) 5011 #define USBC_UPSTA4_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA4) Received STALLed Interrupt */ 5012 #define USBC_UPSTA4_RXSTALLDI (_U_(0x1) << USBC_UPSTA4_RXSTALLDI_Pos) 5013 #define USBC_UPSTA4_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA4) Data Toggle Sequence */ 5014 #define USBC_UPSTA4_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA4_DTSEQ_Pos) 5015 #define USBC_UPSTA4_DTSEQ(value) (USBC_UPSTA4_DTSEQ_Msk & ((value) << USBC_UPSTA4_DTSEQ_Pos)) 5016 #define USBC_UPSTA4_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA4) Ram Access Error Interrupt */ 5017 #define USBC_UPSTA4_RAMACERI (_U_(0x1) << USBC_UPSTA4_RAMACERI_Pos) 5018 #define USBC_UPSTA4_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA4) Number of Busy Bank */ 5019 #define USBC_UPSTA4_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA4_NBUSYBK_Pos) 5020 #define USBC_UPSTA4_NBUSYBK(value) (USBC_UPSTA4_NBUSYBK_Msk & ((value) << USBC_UPSTA4_NBUSYBK_Pos)) 5021 #define USBC_UPSTA4_CURRBK_Pos 14 /**< \brief (USBC_UPSTA4) Current Bank */ 5022 #define USBC_UPSTA4_CURRBK_Msk (_U_(0x3) << USBC_UPSTA4_CURRBK_Pos) 5023 #define USBC_UPSTA4_CURRBK(value) (USBC_UPSTA4_CURRBK_Msk & ((value) << USBC_UPSTA4_CURRBK_Pos)) 5024 #define USBC_UPSTA4_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA4) MASK Register */ 5025 5026 /* -------- USBC_UPSTA5 : (USBC Offset: 0x544) (R/ 32) Pipe Status Register -------- */ 5027 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5028 typedef union { 5029 struct { 5030 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 5031 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 5032 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 5033 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 5034 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 5035 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 5036 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 5037 uint32_t :1; /*!< bit: 7 Reserved */ 5038 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 5039 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 5040 uint32_t :1; /*!< bit: 11 Reserved */ 5041 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 5042 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 5043 uint32_t :16; /*!< bit: 16..31 Reserved */ 5044 } bit; /*!< Structure used for bit access */ 5045 uint32_t reg; /*!< Type used for register access */ 5046 } USBC_UPSTA5_Type; 5047 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5048 5049 #define USBC_UPSTA5_OFFSET 0x544 /**< \brief (USBC_UPSTA5 offset) Pipe Status Register */ 5050 #define USBC_UPSTA5_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA5 reset_value) Pipe Status Register */ 5051 5052 #define USBC_UPSTA5_RXINI_Pos 0 /**< \brief (USBC_UPSTA5) Received IN Data Interrupt */ 5053 #define USBC_UPSTA5_RXINI (_U_(0x1) << USBC_UPSTA5_RXINI_Pos) 5054 #define USBC_UPSTA5_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA5) Transmitted OUT Data Interrupt */ 5055 #define USBC_UPSTA5_TXOUTI (_U_(0x1) << USBC_UPSTA5_TXOUTI_Pos) 5056 #define USBC_UPSTA5_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA5) Transmitted SETUP Interrupt */ 5057 #define USBC_UPSTA5_TXSTPI (_U_(0x1) << USBC_UPSTA5_TXSTPI_Pos) 5058 #define USBC_UPSTA5_PERRI_Pos 3 /**< \brief (USBC_UPSTA5) Pipe Error Interrupt */ 5059 #define USBC_UPSTA5_PERRI (_U_(0x1) << USBC_UPSTA5_PERRI_Pos) 5060 #define USBC_UPSTA5_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA5) NAKed Interrupt */ 5061 #define USBC_UPSTA5_NAKEDI (_U_(0x1) << USBC_UPSTA5_NAKEDI_Pos) 5062 #define USBC_UPSTA5_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA5) Errorflow Interrupt */ 5063 #define USBC_UPSTA5_ERRORFI (_U_(0x1) << USBC_UPSTA5_ERRORFI_Pos) 5064 #define USBC_UPSTA5_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA5) Received STALLed Interrupt */ 5065 #define USBC_UPSTA5_RXSTALLDI (_U_(0x1) << USBC_UPSTA5_RXSTALLDI_Pos) 5066 #define USBC_UPSTA5_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA5) Data Toggle Sequence */ 5067 #define USBC_UPSTA5_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA5_DTSEQ_Pos) 5068 #define USBC_UPSTA5_DTSEQ(value) (USBC_UPSTA5_DTSEQ_Msk & ((value) << USBC_UPSTA5_DTSEQ_Pos)) 5069 #define USBC_UPSTA5_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA5) Ram Access Error Interrupt */ 5070 #define USBC_UPSTA5_RAMACERI (_U_(0x1) << USBC_UPSTA5_RAMACERI_Pos) 5071 #define USBC_UPSTA5_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA5) Number of Busy Bank */ 5072 #define USBC_UPSTA5_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA5_NBUSYBK_Pos) 5073 #define USBC_UPSTA5_NBUSYBK(value) (USBC_UPSTA5_NBUSYBK_Msk & ((value) << USBC_UPSTA5_NBUSYBK_Pos)) 5074 #define USBC_UPSTA5_CURRBK_Pos 14 /**< \brief (USBC_UPSTA5) Current Bank */ 5075 #define USBC_UPSTA5_CURRBK_Msk (_U_(0x3) << USBC_UPSTA5_CURRBK_Pos) 5076 #define USBC_UPSTA5_CURRBK(value) (USBC_UPSTA5_CURRBK_Msk & ((value) << USBC_UPSTA5_CURRBK_Pos)) 5077 #define USBC_UPSTA5_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA5) MASK Register */ 5078 5079 /* -------- USBC_UPSTA6 : (USBC Offset: 0x548) (R/ 32) Pipe Status Register -------- */ 5080 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5081 typedef union { 5082 struct { 5083 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 5084 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 5085 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 5086 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 5087 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 5088 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 5089 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 5090 uint32_t :1; /*!< bit: 7 Reserved */ 5091 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 5092 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 5093 uint32_t :1; /*!< bit: 11 Reserved */ 5094 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 5095 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 5096 uint32_t :16; /*!< bit: 16..31 Reserved */ 5097 } bit; /*!< Structure used for bit access */ 5098 uint32_t reg; /*!< Type used for register access */ 5099 } USBC_UPSTA6_Type; 5100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5101 5102 #define USBC_UPSTA6_OFFSET 0x548 /**< \brief (USBC_UPSTA6 offset) Pipe Status Register */ 5103 #define USBC_UPSTA6_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA6 reset_value) Pipe Status Register */ 5104 5105 #define USBC_UPSTA6_RXINI_Pos 0 /**< \brief (USBC_UPSTA6) Received IN Data Interrupt */ 5106 #define USBC_UPSTA6_RXINI (_U_(0x1) << USBC_UPSTA6_RXINI_Pos) 5107 #define USBC_UPSTA6_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA6) Transmitted OUT Data Interrupt */ 5108 #define USBC_UPSTA6_TXOUTI (_U_(0x1) << USBC_UPSTA6_TXOUTI_Pos) 5109 #define USBC_UPSTA6_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA6) Transmitted SETUP Interrupt */ 5110 #define USBC_UPSTA6_TXSTPI (_U_(0x1) << USBC_UPSTA6_TXSTPI_Pos) 5111 #define USBC_UPSTA6_PERRI_Pos 3 /**< \brief (USBC_UPSTA6) Pipe Error Interrupt */ 5112 #define USBC_UPSTA6_PERRI (_U_(0x1) << USBC_UPSTA6_PERRI_Pos) 5113 #define USBC_UPSTA6_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA6) NAKed Interrupt */ 5114 #define USBC_UPSTA6_NAKEDI (_U_(0x1) << USBC_UPSTA6_NAKEDI_Pos) 5115 #define USBC_UPSTA6_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA6) Errorflow Interrupt */ 5116 #define USBC_UPSTA6_ERRORFI (_U_(0x1) << USBC_UPSTA6_ERRORFI_Pos) 5117 #define USBC_UPSTA6_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA6) Received STALLed Interrupt */ 5118 #define USBC_UPSTA6_RXSTALLDI (_U_(0x1) << USBC_UPSTA6_RXSTALLDI_Pos) 5119 #define USBC_UPSTA6_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA6) Data Toggle Sequence */ 5120 #define USBC_UPSTA6_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA6_DTSEQ_Pos) 5121 #define USBC_UPSTA6_DTSEQ(value) (USBC_UPSTA6_DTSEQ_Msk & ((value) << USBC_UPSTA6_DTSEQ_Pos)) 5122 #define USBC_UPSTA6_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA6) Ram Access Error Interrupt */ 5123 #define USBC_UPSTA6_RAMACERI (_U_(0x1) << USBC_UPSTA6_RAMACERI_Pos) 5124 #define USBC_UPSTA6_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA6) Number of Busy Bank */ 5125 #define USBC_UPSTA6_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA6_NBUSYBK_Pos) 5126 #define USBC_UPSTA6_NBUSYBK(value) (USBC_UPSTA6_NBUSYBK_Msk & ((value) << USBC_UPSTA6_NBUSYBK_Pos)) 5127 #define USBC_UPSTA6_CURRBK_Pos 14 /**< \brief (USBC_UPSTA6) Current Bank */ 5128 #define USBC_UPSTA6_CURRBK_Msk (_U_(0x3) << USBC_UPSTA6_CURRBK_Pos) 5129 #define USBC_UPSTA6_CURRBK(value) (USBC_UPSTA6_CURRBK_Msk & ((value) << USBC_UPSTA6_CURRBK_Pos)) 5130 #define USBC_UPSTA6_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA6) MASK Register */ 5131 5132 /* -------- USBC_UPSTA7 : (USBC Offset: 0x54C) (R/ 32) Pipe Status Register -------- */ 5133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5134 typedef union { 5135 struct { 5136 uint32_t RXINI:1; /*!< bit: 0 Received IN Data Interrupt */ 5137 uint32_t TXOUTI:1; /*!< bit: 1 Transmitted OUT Data Interrupt */ 5138 uint32_t TXSTPI:1; /*!< bit: 2 Transmitted SETUP Interrupt */ 5139 uint32_t PERRI:1; /*!< bit: 3 Pipe Error Interrupt */ 5140 uint32_t NAKEDI:1; /*!< bit: 4 NAKed Interrupt */ 5141 uint32_t ERRORFI:1; /*!< bit: 5 Errorflow Interrupt */ 5142 uint32_t RXSTALLDI:1; /*!< bit: 6 Received STALLed Interrupt */ 5143 uint32_t :1; /*!< bit: 7 Reserved */ 5144 uint32_t DTSEQ:2; /*!< bit: 8.. 9 Data Toggle Sequence */ 5145 uint32_t RAMACERI:1; /*!< bit: 10 Ram Access Error Interrupt */ 5146 uint32_t :1; /*!< bit: 11 Reserved */ 5147 uint32_t NBUSYBK:2; /*!< bit: 12..13 Number of Busy Bank */ 5148 uint32_t CURRBK:2; /*!< bit: 14..15 Current Bank */ 5149 uint32_t :16; /*!< bit: 16..31 Reserved */ 5150 } bit; /*!< Structure used for bit access */ 5151 uint32_t reg; /*!< Type used for register access */ 5152 } USBC_UPSTA7_Type; 5153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5154 5155 #define USBC_UPSTA7_OFFSET 0x54C /**< \brief (USBC_UPSTA7 offset) Pipe Status Register */ 5156 #define USBC_UPSTA7_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA7 reset_value) Pipe Status Register */ 5157 5158 #define USBC_UPSTA7_RXINI_Pos 0 /**< \brief (USBC_UPSTA7) Received IN Data Interrupt */ 5159 #define USBC_UPSTA7_RXINI (_U_(0x1) << USBC_UPSTA7_RXINI_Pos) 5160 #define USBC_UPSTA7_TXOUTI_Pos 1 /**< \brief (USBC_UPSTA7) Transmitted OUT Data Interrupt */ 5161 #define USBC_UPSTA7_TXOUTI (_U_(0x1) << USBC_UPSTA7_TXOUTI_Pos) 5162 #define USBC_UPSTA7_TXSTPI_Pos 2 /**< \brief (USBC_UPSTA7) Transmitted SETUP Interrupt */ 5163 #define USBC_UPSTA7_TXSTPI (_U_(0x1) << USBC_UPSTA7_TXSTPI_Pos) 5164 #define USBC_UPSTA7_PERRI_Pos 3 /**< \brief (USBC_UPSTA7) Pipe Error Interrupt */ 5165 #define USBC_UPSTA7_PERRI (_U_(0x1) << USBC_UPSTA7_PERRI_Pos) 5166 #define USBC_UPSTA7_NAKEDI_Pos 4 /**< \brief (USBC_UPSTA7) NAKed Interrupt */ 5167 #define USBC_UPSTA7_NAKEDI (_U_(0x1) << USBC_UPSTA7_NAKEDI_Pos) 5168 #define USBC_UPSTA7_ERRORFI_Pos 5 /**< \brief (USBC_UPSTA7) Errorflow Interrupt */ 5169 #define USBC_UPSTA7_ERRORFI (_U_(0x1) << USBC_UPSTA7_ERRORFI_Pos) 5170 #define USBC_UPSTA7_RXSTALLDI_Pos 6 /**< \brief (USBC_UPSTA7) Received STALLed Interrupt */ 5171 #define USBC_UPSTA7_RXSTALLDI (_U_(0x1) << USBC_UPSTA7_RXSTALLDI_Pos) 5172 #define USBC_UPSTA7_DTSEQ_Pos 8 /**< \brief (USBC_UPSTA7) Data Toggle Sequence */ 5173 #define USBC_UPSTA7_DTSEQ_Msk (_U_(0x3) << USBC_UPSTA7_DTSEQ_Pos) 5174 #define USBC_UPSTA7_DTSEQ(value) (USBC_UPSTA7_DTSEQ_Msk & ((value) << USBC_UPSTA7_DTSEQ_Pos)) 5175 #define USBC_UPSTA7_RAMACERI_Pos 10 /**< \brief (USBC_UPSTA7) Ram Access Error Interrupt */ 5176 #define USBC_UPSTA7_RAMACERI (_U_(0x1) << USBC_UPSTA7_RAMACERI_Pos) 5177 #define USBC_UPSTA7_NBUSYBK_Pos 12 /**< \brief (USBC_UPSTA7) Number of Busy Bank */ 5178 #define USBC_UPSTA7_NBUSYBK_Msk (_U_(0x3) << USBC_UPSTA7_NBUSYBK_Pos) 5179 #define USBC_UPSTA7_NBUSYBK(value) (USBC_UPSTA7_NBUSYBK_Msk & ((value) << USBC_UPSTA7_NBUSYBK_Pos)) 5180 #define USBC_UPSTA7_CURRBK_Pos 14 /**< \brief (USBC_UPSTA7) Current Bank */ 5181 #define USBC_UPSTA7_CURRBK_Msk (_U_(0x3) << USBC_UPSTA7_CURRBK_Pos) 5182 #define USBC_UPSTA7_CURRBK(value) (USBC_UPSTA7_CURRBK_Msk & ((value) << USBC_UPSTA7_CURRBK_Pos)) 5183 #define USBC_UPSTA7_MASK _U_(0x0000F77F) /**< \brief (USBC_UPSTA7) MASK Register */ 5184 5185 /* -------- USBC_UPSTA0CLR : (USBC Offset: 0x560) ( /W 32) Pipe Status Clear Register -------- */ 5186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5187 typedef union { 5188 struct { 5189 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5190 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5191 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5192 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5193 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5194 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5195 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5196 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5197 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5198 uint32_t :21; /*!< bit: 11..31 Reserved */ 5199 } bit; /*!< Structure used for bit access */ 5200 uint32_t reg; /*!< Type used for register access */ 5201 } USBC_UPSTA0CLR_Type; 5202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5203 5204 #define USBC_UPSTA0CLR_OFFSET 0x560 /**< \brief (USBC_UPSTA0CLR offset) Pipe Status Clear Register */ 5205 #define USBC_UPSTA0CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA0CLR reset_value) Pipe Status Clear Register */ 5206 5207 #define USBC_UPSTA0CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA0CLR) RXINI Clear */ 5208 #define USBC_UPSTA0CLR_RXINIC (_U_(0x1) << USBC_UPSTA0CLR_RXINIC_Pos) 5209 #define USBC_UPSTA0CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA0CLR) TXOUTI Clear */ 5210 #define USBC_UPSTA0CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA0CLR_TXOUTIC_Pos) 5211 #define USBC_UPSTA0CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA0CLR) TXSTPI Clear */ 5212 #define USBC_UPSTA0CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA0CLR_TXSTPIC_Pos) 5213 #define USBC_UPSTA0CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA0CLR) PERRI Clear */ 5214 #define USBC_UPSTA0CLR_PERRIC (_U_(0x1) << USBC_UPSTA0CLR_PERRIC_Pos) 5215 #define USBC_UPSTA0CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA0CLR) NAKEDI Clear */ 5216 #define USBC_UPSTA0CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA0CLR_NAKEDIC_Pos) 5217 #define USBC_UPSTA0CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA0CLR) ERRORFI Clear */ 5218 #define USBC_UPSTA0CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA0CLR_ERRORFIC_Pos) 5219 #define USBC_UPSTA0CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA0CLR) RXSTALLDI Clear */ 5220 #define USBC_UPSTA0CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA0CLR_RXSTALLDIC_Pos) 5221 #define USBC_UPSTA0CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA0CLR) RAMACERI Clear */ 5222 #define USBC_UPSTA0CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA0CLR_RAMACERIC_Pos) 5223 #define USBC_UPSTA0CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA0CLR) MASK Register */ 5224 5225 /* -------- USBC_UPSTA1CLR : (USBC Offset: 0x564) ( /W 32) Pipe Status Clear Register -------- */ 5226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5227 typedef union { 5228 struct { 5229 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5230 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5231 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5232 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5233 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5234 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5235 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5236 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5237 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5238 uint32_t :21; /*!< bit: 11..31 Reserved */ 5239 } bit; /*!< Structure used for bit access */ 5240 uint32_t reg; /*!< Type used for register access */ 5241 } USBC_UPSTA1CLR_Type; 5242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5243 5244 #define USBC_UPSTA1CLR_OFFSET 0x564 /**< \brief (USBC_UPSTA1CLR offset) Pipe Status Clear Register */ 5245 #define USBC_UPSTA1CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA1CLR reset_value) Pipe Status Clear Register */ 5246 5247 #define USBC_UPSTA1CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA1CLR) RXINI Clear */ 5248 #define USBC_UPSTA1CLR_RXINIC (_U_(0x1) << USBC_UPSTA1CLR_RXINIC_Pos) 5249 #define USBC_UPSTA1CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA1CLR) TXOUTI Clear */ 5250 #define USBC_UPSTA1CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA1CLR_TXOUTIC_Pos) 5251 #define USBC_UPSTA1CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA1CLR) TXSTPI Clear */ 5252 #define USBC_UPSTA1CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA1CLR_TXSTPIC_Pos) 5253 #define USBC_UPSTA1CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA1CLR) PERRI Clear */ 5254 #define USBC_UPSTA1CLR_PERRIC (_U_(0x1) << USBC_UPSTA1CLR_PERRIC_Pos) 5255 #define USBC_UPSTA1CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA1CLR) NAKEDI Clear */ 5256 #define USBC_UPSTA1CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA1CLR_NAKEDIC_Pos) 5257 #define USBC_UPSTA1CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA1CLR) ERRORFI Clear */ 5258 #define USBC_UPSTA1CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA1CLR_ERRORFIC_Pos) 5259 #define USBC_UPSTA1CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA1CLR) RXSTALLDI Clear */ 5260 #define USBC_UPSTA1CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA1CLR_RXSTALLDIC_Pos) 5261 #define USBC_UPSTA1CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA1CLR) RAMACERI Clear */ 5262 #define USBC_UPSTA1CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA1CLR_RAMACERIC_Pos) 5263 #define USBC_UPSTA1CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA1CLR) MASK Register */ 5264 5265 /* -------- USBC_UPSTA2CLR : (USBC Offset: 0x568) ( /W 32) Pipe Status Clear Register -------- */ 5266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5267 typedef union { 5268 struct { 5269 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5270 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5271 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5272 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5273 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5274 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5275 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5276 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5277 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5278 uint32_t :21; /*!< bit: 11..31 Reserved */ 5279 } bit; /*!< Structure used for bit access */ 5280 uint32_t reg; /*!< Type used for register access */ 5281 } USBC_UPSTA2CLR_Type; 5282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5283 5284 #define USBC_UPSTA2CLR_OFFSET 0x568 /**< \brief (USBC_UPSTA2CLR offset) Pipe Status Clear Register */ 5285 #define USBC_UPSTA2CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA2CLR reset_value) Pipe Status Clear Register */ 5286 5287 #define USBC_UPSTA2CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA2CLR) RXINI Clear */ 5288 #define USBC_UPSTA2CLR_RXINIC (_U_(0x1) << USBC_UPSTA2CLR_RXINIC_Pos) 5289 #define USBC_UPSTA2CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA2CLR) TXOUTI Clear */ 5290 #define USBC_UPSTA2CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA2CLR_TXOUTIC_Pos) 5291 #define USBC_UPSTA2CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA2CLR) TXSTPI Clear */ 5292 #define USBC_UPSTA2CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA2CLR_TXSTPIC_Pos) 5293 #define USBC_UPSTA2CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA2CLR) PERRI Clear */ 5294 #define USBC_UPSTA2CLR_PERRIC (_U_(0x1) << USBC_UPSTA2CLR_PERRIC_Pos) 5295 #define USBC_UPSTA2CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA2CLR) NAKEDI Clear */ 5296 #define USBC_UPSTA2CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA2CLR_NAKEDIC_Pos) 5297 #define USBC_UPSTA2CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA2CLR) ERRORFI Clear */ 5298 #define USBC_UPSTA2CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA2CLR_ERRORFIC_Pos) 5299 #define USBC_UPSTA2CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA2CLR) RXSTALLDI Clear */ 5300 #define USBC_UPSTA2CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA2CLR_RXSTALLDIC_Pos) 5301 #define USBC_UPSTA2CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA2CLR) RAMACERI Clear */ 5302 #define USBC_UPSTA2CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA2CLR_RAMACERIC_Pos) 5303 #define USBC_UPSTA2CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA2CLR) MASK Register */ 5304 5305 /* -------- USBC_UPSTA3CLR : (USBC Offset: 0x56C) ( /W 32) Pipe Status Clear Register -------- */ 5306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5307 typedef union { 5308 struct { 5309 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5310 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5311 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5312 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5313 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5314 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5315 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5316 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5317 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5318 uint32_t :21; /*!< bit: 11..31 Reserved */ 5319 } bit; /*!< Structure used for bit access */ 5320 uint32_t reg; /*!< Type used for register access */ 5321 } USBC_UPSTA3CLR_Type; 5322 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5323 5324 #define USBC_UPSTA3CLR_OFFSET 0x56C /**< \brief (USBC_UPSTA3CLR offset) Pipe Status Clear Register */ 5325 #define USBC_UPSTA3CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA3CLR reset_value) Pipe Status Clear Register */ 5326 5327 #define USBC_UPSTA3CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA3CLR) RXINI Clear */ 5328 #define USBC_UPSTA3CLR_RXINIC (_U_(0x1) << USBC_UPSTA3CLR_RXINIC_Pos) 5329 #define USBC_UPSTA3CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA3CLR) TXOUTI Clear */ 5330 #define USBC_UPSTA3CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA3CLR_TXOUTIC_Pos) 5331 #define USBC_UPSTA3CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA3CLR) TXSTPI Clear */ 5332 #define USBC_UPSTA3CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA3CLR_TXSTPIC_Pos) 5333 #define USBC_UPSTA3CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA3CLR) PERRI Clear */ 5334 #define USBC_UPSTA3CLR_PERRIC (_U_(0x1) << USBC_UPSTA3CLR_PERRIC_Pos) 5335 #define USBC_UPSTA3CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA3CLR) NAKEDI Clear */ 5336 #define USBC_UPSTA3CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA3CLR_NAKEDIC_Pos) 5337 #define USBC_UPSTA3CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA3CLR) ERRORFI Clear */ 5338 #define USBC_UPSTA3CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA3CLR_ERRORFIC_Pos) 5339 #define USBC_UPSTA3CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA3CLR) RXSTALLDI Clear */ 5340 #define USBC_UPSTA3CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA3CLR_RXSTALLDIC_Pos) 5341 #define USBC_UPSTA3CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA3CLR) RAMACERI Clear */ 5342 #define USBC_UPSTA3CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA3CLR_RAMACERIC_Pos) 5343 #define USBC_UPSTA3CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA3CLR) MASK Register */ 5344 5345 /* -------- USBC_UPSTA4CLR : (USBC Offset: 0x570) ( /W 32) Pipe Status Clear Register -------- */ 5346 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5347 typedef union { 5348 struct { 5349 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5350 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5351 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5352 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5353 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5354 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5355 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5356 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5357 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5358 uint32_t :21; /*!< bit: 11..31 Reserved */ 5359 } bit; /*!< Structure used for bit access */ 5360 uint32_t reg; /*!< Type used for register access */ 5361 } USBC_UPSTA4CLR_Type; 5362 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5363 5364 #define USBC_UPSTA4CLR_OFFSET 0x570 /**< \brief (USBC_UPSTA4CLR offset) Pipe Status Clear Register */ 5365 #define USBC_UPSTA4CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA4CLR reset_value) Pipe Status Clear Register */ 5366 5367 #define USBC_UPSTA4CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA4CLR) RXINI Clear */ 5368 #define USBC_UPSTA4CLR_RXINIC (_U_(0x1) << USBC_UPSTA4CLR_RXINIC_Pos) 5369 #define USBC_UPSTA4CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA4CLR) TXOUTI Clear */ 5370 #define USBC_UPSTA4CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA4CLR_TXOUTIC_Pos) 5371 #define USBC_UPSTA4CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA4CLR) TXSTPI Clear */ 5372 #define USBC_UPSTA4CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA4CLR_TXSTPIC_Pos) 5373 #define USBC_UPSTA4CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA4CLR) PERRI Clear */ 5374 #define USBC_UPSTA4CLR_PERRIC (_U_(0x1) << USBC_UPSTA4CLR_PERRIC_Pos) 5375 #define USBC_UPSTA4CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA4CLR) NAKEDI Clear */ 5376 #define USBC_UPSTA4CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA4CLR_NAKEDIC_Pos) 5377 #define USBC_UPSTA4CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA4CLR) ERRORFI Clear */ 5378 #define USBC_UPSTA4CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA4CLR_ERRORFIC_Pos) 5379 #define USBC_UPSTA4CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA4CLR) RXSTALLDI Clear */ 5380 #define USBC_UPSTA4CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA4CLR_RXSTALLDIC_Pos) 5381 #define USBC_UPSTA4CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA4CLR) RAMACERI Clear */ 5382 #define USBC_UPSTA4CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA4CLR_RAMACERIC_Pos) 5383 #define USBC_UPSTA4CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA4CLR) MASK Register */ 5384 5385 /* -------- USBC_UPSTA5CLR : (USBC Offset: 0x574) ( /W 32) Pipe Status Clear Register -------- */ 5386 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5387 typedef union { 5388 struct { 5389 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5390 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5391 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5392 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5393 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5394 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5395 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5396 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5397 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5398 uint32_t :21; /*!< bit: 11..31 Reserved */ 5399 } bit; /*!< Structure used for bit access */ 5400 uint32_t reg; /*!< Type used for register access */ 5401 } USBC_UPSTA5CLR_Type; 5402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5403 5404 #define USBC_UPSTA5CLR_OFFSET 0x574 /**< \brief (USBC_UPSTA5CLR offset) Pipe Status Clear Register */ 5405 #define USBC_UPSTA5CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA5CLR reset_value) Pipe Status Clear Register */ 5406 5407 #define USBC_UPSTA5CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA5CLR) RXINI Clear */ 5408 #define USBC_UPSTA5CLR_RXINIC (_U_(0x1) << USBC_UPSTA5CLR_RXINIC_Pos) 5409 #define USBC_UPSTA5CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA5CLR) TXOUTI Clear */ 5410 #define USBC_UPSTA5CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA5CLR_TXOUTIC_Pos) 5411 #define USBC_UPSTA5CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA5CLR) TXSTPI Clear */ 5412 #define USBC_UPSTA5CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA5CLR_TXSTPIC_Pos) 5413 #define USBC_UPSTA5CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA5CLR) PERRI Clear */ 5414 #define USBC_UPSTA5CLR_PERRIC (_U_(0x1) << USBC_UPSTA5CLR_PERRIC_Pos) 5415 #define USBC_UPSTA5CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA5CLR) NAKEDI Clear */ 5416 #define USBC_UPSTA5CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA5CLR_NAKEDIC_Pos) 5417 #define USBC_UPSTA5CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA5CLR) ERRORFI Clear */ 5418 #define USBC_UPSTA5CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA5CLR_ERRORFIC_Pos) 5419 #define USBC_UPSTA5CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA5CLR) RXSTALLDI Clear */ 5420 #define USBC_UPSTA5CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA5CLR_RXSTALLDIC_Pos) 5421 #define USBC_UPSTA5CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA5CLR) RAMACERI Clear */ 5422 #define USBC_UPSTA5CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA5CLR_RAMACERIC_Pos) 5423 #define USBC_UPSTA5CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA5CLR) MASK Register */ 5424 5425 /* -------- USBC_UPSTA6CLR : (USBC Offset: 0x578) ( /W 32) Pipe Status Clear Register -------- */ 5426 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5427 typedef union { 5428 struct { 5429 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5430 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5431 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5432 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5433 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5434 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5435 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5436 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5437 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5438 uint32_t :21; /*!< bit: 11..31 Reserved */ 5439 } bit; /*!< Structure used for bit access */ 5440 uint32_t reg; /*!< Type used for register access */ 5441 } USBC_UPSTA6CLR_Type; 5442 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5443 5444 #define USBC_UPSTA6CLR_OFFSET 0x578 /**< \brief (USBC_UPSTA6CLR offset) Pipe Status Clear Register */ 5445 #define USBC_UPSTA6CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA6CLR reset_value) Pipe Status Clear Register */ 5446 5447 #define USBC_UPSTA6CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA6CLR) RXINI Clear */ 5448 #define USBC_UPSTA6CLR_RXINIC (_U_(0x1) << USBC_UPSTA6CLR_RXINIC_Pos) 5449 #define USBC_UPSTA6CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA6CLR) TXOUTI Clear */ 5450 #define USBC_UPSTA6CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA6CLR_TXOUTIC_Pos) 5451 #define USBC_UPSTA6CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA6CLR) TXSTPI Clear */ 5452 #define USBC_UPSTA6CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA6CLR_TXSTPIC_Pos) 5453 #define USBC_UPSTA6CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA6CLR) PERRI Clear */ 5454 #define USBC_UPSTA6CLR_PERRIC (_U_(0x1) << USBC_UPSTA6CLR_PERRIC_Pos) 5455 #define USBC_UPSTA6CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA6CLR) NAKEDI Clear */ 5456 #define USBC_UPSTA6CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA6CLR_NAKEDIC_Pos) 5457 #define USBC_UPSTA6CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA6CLR) ERRORFI Clear */ 5458 #define USBC_UPSTA6CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA6CLR_ERRORFIC_Pos) 5459 #define USBC_UPSTA6CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA6CLR) RXSTALLDI Clear */ 5460 #define USBC_UPSTA6CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA6CLR_RXSTALLDIC_Pos) 5461 #define USBC_UPSTA6CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA6CLR) RAMACERI Clear */ 5462 #define USBC_UPSTA6CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA6CLR_RAMACERIC_Pos) 5463 #define USBC_UPSTA6CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA6CLR) MASK Register */ 5464 5465 /* -------- USBC_UPSTA7CLR : (USBC Offset: 0x57C) ( /W 32) Pipe Status Clear Register -------- */ 5466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5467 typedef union { 5468 struct { 5469 uint32_t RXINIC:1; /*!< bit: 0 RXINI Clear */ 5470 uint32_t TXOUTIC:1; /*!< bit: 1 TXOUTI Clear */ 5471 uint32_t TXSTPIC:1; /*!< bit: 2 TXSTPI Clear */ 5472 uint32_t PERRIC:1; /*!< bit: 3 PERRI Clear */ 5473 uint32_t NAKEDIC:1; /*!< bit: 4 NAKEDI Clear */ 5474 uint32_t ERRORFIC:1; /*!< bit: 5 ERRORFI Clear */ 5475 uint32_t RXSTALLDIC:1; /*!< bit: 6 RXSTALLDI Clear */ 5476 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5477 uint32_t RAMACERIC:1; /*!< bit: 10 RAMACERI Clear */ 5478 uint32_t :21; /*!< bit: 11..31 Reserved */ 5479 } bit; /*!< Structure used for bit access */ 5480 uint32_t reg; /*!< Type used for register access */ 5481 } USBC_UPSTA7CLR_Type; 5482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5483 5484 #define USBC_UPSTA7CLR_OFFSET 0x57C /**< \brief (USBC_UPSTA7CLR offset) Pipe Status Clear Register */ 5485 #define USBC_UPSTA7CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA7CLR reset_value) Pipe Status Clear Register */ 5486 5487 #define USBC_UPSTA7CLR_RXINIC_Pos 0 /**< \brief (USBC_UPSTA7CLR) RXINI Clear */ 5488 #define USBC_UPSTA7CLR_RXINIC (_U_(0x1) << USBC_UPSTA7CLR_RXINIC_Pos) 5489 #define USBC_UPSTA7CLR_TXOUTIC_Pos 1 /**< \brief (USBC_UPSTA7CLR) TXOUTI Clear */ 5490 #define USBC_UPSTA7CLR_TXOUTIC (_U_(0x1) << USBC_UPSTA7CLR_TXOUTIC_Pos) 5491 #define USBC_UPSTA7CLR_TXSTPIC_Pos 2 /**< \brief (USBC_UPSTA7CLR) TXSTPI Clear */ 5492 #define USBC_UPSTA7CLR_TXSTPIC (_U_(0x1) << USBC_UPSTA7CLR_TXSTPIC_Pos) 5493 #define USBC_UPSTA7CLR_PERRIC_Pos 3 /**< \brief (USBC_UPSTA7CLR) PERRI Clear */ 5494 #define USBC_UPSTA7CLR_PERRIC (_U_(0x1) << USBC_UPSTA7CLR_PERRIC_Pos) 5495 #define USBC_UPSTA7CLR_NAKEDIC_Pos 4 /**< \brief (USBC_UPSTA7CLR) NAKEDI Clear */ 5496 #define USBC_UPSTA7CLR_NAKEDIC (_U_(0x1) << USBC_UPSTA7CLR_NAKEDIC_Pos) 5497 #define USBC_UPSTA7CLR_ERRORFIC_Pos 5 /**< \brief (USBC_UPSTA7CLR) ERRORFI Clear */ 5498 #define USBC_UPSTA7CLR_ERRORFIC (_U_(0x1) << USBC_UPSTA7CLR_ERRORFIC_Pos) 5499 #define USBC_UPSTA7CLR_RXSTALLDIC_Pos 6 /**< \brief (USBC_UPSTA7CLR) RXSTALLDI Clear */ 5500 #define USBC_UPSTA7CLR_RXSTALLDIC (_U_(0x1) << USBC_UPSTA7CLR_RXSTALLDIC_Pos) 5501 #define USBC_UPSTA7CLR_RAMACERIC_Pos 10 /**< \brief (USBC_UPSTA7CLR) RAMACERI Clear */ 5502 #define USBC_UPSTA7CLR_RAMACERIC (_U_(0x1) << USBC_UPSTA7CLR_RAMACERIC_Pos) 5503 #define USBC_UPSTA7CLR_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA7CLR) MASK Register */ 5504 5505 /* -------- USBC_UPSTA0SET : (USBC Offset: 0x590) ( /W 32) Pipe Status Set Register -------- */ 5506 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5507 typedef union { 5508 struct { 5509 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5510 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5511 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5512 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5513 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5514 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5515 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5516 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5517 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5518 uint32_t :21; /*!< bit: 11..31 Reserved */ 5519 } bit; /*!< Structure used for bit access */ 5520 uint32_t reg; /*!< Type used for register access */ 5521 } USBC_UPSTA0SET_Type; 5522 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5523 5524 #define USBC_UPSTA0SET_OFFSET 0x590 /**< \brief (USBC_UPSTA0SET offset) Pipe Status Set Register */ 5525 #define USBC_UPSTA0SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA0SET reset_value) Pipe Status Set Register */ 5526 5527 #define USBC_UPSTA0SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA0SET) RXINI Set */ 5528 #define USBC_UPSTA0SET_RXINIS (_U_(0x1) << USBC_UPSTA0SET_RXINIS_Pos) 5529 #define USBC_UPSTA0SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA0SET) TXOUTI Set */ 5530 #define USBC_UPSTA0SET_TXOUTIS (_U_(0x1) << USBC_UPSTA0SET_TXOUTIS_Pos) 5531 #define USBC_UPSTA0SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA0SET) TXSTPI Set */ 5532 #define USBC_UPSTA0SET_TXSTPIS (_U_(0x1) << USBC_UPSTA0SET_TXSTPIS_Pos) 5533 #define USBC_UPSTA0SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA0SET) PERRI Set */ 5534 #define USBC_UPSTA0SET_PERRIS (_U_(0x1) << USBC_UPSTA0SET_PERRIS_Pos) 5535 #define USBC_UPSTA0SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA0SET) NAKEDI Set */ 5536 #define USBC_UPSTA0SET_NAKEDIS (_U_(0x1) << USBC_UPSTA0SET_NAKEDIS_Pos) 5537 #define USBC_UPSTA0SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA0SET) ERRORFI Set */ 5538 #define USBC_UPSTA0SET_ERRORFIS (_U_(0x1) << USBC_UPSTA0SET_ERRORFIS_Pos) 5539 #define USBC_UPSTA0SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA0SET) RXSTALLDI Set */ 5540 #define USBC_UPSTA0SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA0SET_RXSTALLDIS_Pos) 5541 #define USBC_UPSTA0SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA0SET) RAMACERI Set */ 5542 #define USBC_UPSTA0SET_RAMACERIS (_U_(0x1) << USBC_UPSTA0SET_RAMACERIS_Pos) 5543 #define USBC_UPSTA0SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA0SET) MASK Register */ 5544 5545 /* -------- USBC_UPSTA1SET : (USBC Offset: 0x594) ( /W 32) Pipe Status Set Register -------- */ 5546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5547 typedef union { 5548 struct { 5549 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5550 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5551 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5552 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5553 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5554 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5555 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5556 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5557 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5558 uint32_t :21; /*!< bit: 11..31 Reserved */ 5559 } bit; /*!< Structure used for bit access */ 5560 uint32_t reg; /*!< Type used for register access */ 5561 } USBC_UPSTA1SET_Type; 5562 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5563 5564 #define USBC_UPSTA1SET_OFFSET 0x594 /**< \brief (USBC_UPSTA1SET offset) Pipe Status Set Register */ 5565 #define USBC_UPSTA1SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA1SET reset_value) Pipe Status Set Register */ 5566 5567 #define USBC_UPSTA1SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA1SET) RXINI Set */ 5568 #define USBC_UPSTA1SET_RXINIS (_U_(0x1) << USBC_UPSTA1SET_RXINIS_Pos) 5569 #define USBC_UPSTA1SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA1SET) TXOUTI Set */ 5570 #define USBC_UPSTA1SET_TXOUTIS (_U_(0x1) << USBC_UPSTA1SET_TXOUTIS_Pos) 5571 #define USBC_UPSTA1SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA1SET) TXSTPI Set */ 5572 #define USBC_UPSTA1SET_TXSTPIS (_U_(0x1) << USBC_UPSTA1SET_TXSTPIS_Pos) 5573 #define USBC_UPSTA1SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA1SET) PERRI Set */ 5574 #define USBC_UPSTA1SET_PERRIS (_U_(0x1) << USBC_UPSTA1SET_PERRIS_Pos) 5575 #define USBC_UPSTA1SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA1SET) NAKEDI Set */ 5576 #define USBC_UPSTA1SET_NAKEDIS (_U_(0x1) << USBC_UPSTA1SET_NAKEDIS_Pos) 5577 #define USBC_UPSTA1SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA1SET) ERRORFI Set */ 5578 #define USBC_UPSTA1SET_ERRORFIS (_U_(0x1) << USBC_UPSTA1SET_ERRORFIS_Pos) 5579 #define USBC_UPSTA1SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA1SET) RXSTALLDI Set */ 5580 #define USBC_UPSTA1SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA1SET_RXSTALLDIS_Pos) 5581 #define USBC_UPSTA1SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA1SET) RAMACERI Set */ 5582 #define USBC_UPSTA1SET_RAMACERIS (_U_(0x1) << USBC_UPSTA1SET_RAMACERIS_Pos) 5583 #define USBC_UPSTA1SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA1SET) MASK Register */ 5584 5585 /* -------- USBC_UPSTA2SET : (USBC Offset: 0x598) ( /W 32) Pipe Status Set Register -------- */ 5586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5587 typedef union { 5588 struct { 5589 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5590 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5591 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5592 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5593 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5594 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5595 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5596 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5597 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5598 uint32_t :21; /*!< bit: 11..31 Reserved */ 5599 } bit; /*!< Structure used for bit access */ 5600 uint32_t reg; /*!< Type used for register access */ 5601 } USBC_UPSTA2SET_Type; 5602 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5603 5604 #define USBC_UPSTA2SET_OFFSET 0x598 /**< \brief (USBC_UPSTA2SET offset) Pipe Status Set Register */ 5605 #define USBC_UPSTA2SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA2SET reset_value) Pipe Status Set Register */ 5606 5607 #define USBC_UPSTA2SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA2SET) RXINI Set */ 5608 #define USBC_UPSTA2SET_RXINIS (_U_(0x1) << USBC_UPSTA2SET_RXINIS_Pos) 5609 #define USBC_UPSTA2SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA2SET) TXOUTI Set */ 5610 #define USBC_UPSTA2SET_TXOUTIS (_U_(0x1) << USBC_UPSTA2SET_TXOUTIS_Pos) 5611 #define USBC_UPSTA2SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA2SET) TXSTPI Set */ 5612 #define USBC_UPSTA2SET_TXSTPIS (_U_(0x1) << USBC_UPSTA2SET_TXSTPIS_Pos) 5613 #define USBC_UPSTA2SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA2SET) PERRI Set */ 5614 #define USBC_UPSTA2SET_PERRIS (_U_(0x1) << USBC_UPSTA2SET_PERRIS_Pos) 5615 #define USBC_UPSTA2SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA2SET) NAKEDI Set */ 5616 #define USBC_UPSTA2SET_NAKEDIS (_U_(0x1) << USBC_UPSTA2SET_NAKEDIS_Pos) 5617 #define USBC_UPSTA2SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA2SET) ERRORFI Set */ 5618 #define USBC_UPSTA2SET_ERRORFIS (_U_(0x1) << USBC_UPSTA2SET_ERRORFIS_Pos) 5619 #define USBC_UPSTA2SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA2SET) RXSTALLDI Set */ 5620 #define USBC_UPSTA2SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA2SET_RXSTALLDIS_Pos) 5621 #define USBC_UPSTA2SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA2SET) RAMACERI Set */ 5622 #define USBC_UPSTA2SET_RAMACERIS (_U_(0x1) << USBC_UPSTA2SET_RAMACERIS_Pos) 5623 #define USBC_UPSTA2SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA2SET) MASK Register */ 5624 5625 /* -------- USBC_UPSTA3SET : (USBC Offset: 0x59C) ( /W 32) Pipe Status Set Register -------- */ 5626 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5627 typedef union { 5628 struct { 5629 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5630 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5631 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5632 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5633 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5634 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5635 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5636 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5637 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5638 uint32_t :21; /*!< bit: 11..31 Reserved */ 5639 } bit; /*!< Structure used for bit access */ 5640 uint32_t reg; /*!< Type used for register access */ 5641 } USBC_UPSTA3SET_Type; 5642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5643 5644 #define USBC_UPSTA3SET_OFFSET 0x59C /**< \brief (USBC_UPSTA3SET offset) Pipe Status Set Register */ 5645 #define USBC_UPSTA3SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA3SET reset_value) Pipe Status Set Register */ 5646 5647 #define USBC_UPSTA3SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA3SET) RXINI Set */ 5648 #define USBC_UPSTA3SET_RXINIS (_U_(0x1) << USBC_UPSTA3SET_RXINIS_Pos) 5649 #define USBC_UPSTA3SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA3SET) TXOUTI Set */ 5650 #define USBC_UPSTA3SET_TXOUTIS (_U_(0x1) << USBC_UPSTA3SET_TXOUTIS_Pos) 5651 #define USBC_UPSTA3SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA3SET) TXSTPI Set */ 5652 #define USBC_UPSTA3SET_TXSTPIS (_U_(0x1) << USBC_UPSTA3SET_TXSTPIS_Pos) 5653 #define USBC_UPSTA3SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA3SET) PERRI Set */ 5654 #define USBC_UPSTA3SET_PERRIS (_U_(0x1) << USBC_UPSTA3SET_PERRIS_Pos) 5655 #define USBC_UPSTA3SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA3SET) NAKEDI Set */ 5656 #define USBC_UPSTA3SET_NAKEDIS (_U_(0x1) << USBC_UPSTA3SET_NAKEDIS_Pos) 5657 #define USBC_UPSTA3SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA3SET) ERRORFI Set */ 5658 #define USBC_UPSTA3SET_ERRORFIS (_U_(0x1) << USBC_UPSTA3SET_ERRORFIS_Pos) 5659 #define USBC_UPSTA3SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA3SET) RXSTALLDI Set */ 5660 #define USBC_UPSTA3SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA3SET_RXSTALLDIS_Pos) 5661 #define USBC_UPSTA3SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA3SET) RAMACERI Set */ 5662 #define USBC_UPSTA3SET_RAMACERIS (_U_(0x1) << USBC_UPSTA3SET_RAMACERIS_Pos) 5663 #define USBC_UPSTA3SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA3SET) MASK Register */ 5664 5665 /* -------- USBC_UPSTA4SET : (USBC Offset: 0x5A0) ( /W 32) Pipe Status Set Register -------- */ 5666 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5667 typedef union { 5668 struct { 5669 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5670 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5671 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5672 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5673 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5674 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5675 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5676 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5677 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5678 uint32_t :21; /*!< bit: 11..31 Reserved */ 5679 } bit; /*!< Structure used for bit access */ 5680 uint32_t reg; /*!< Type used for register access */ 5681 } USBC_UPSTA4SET_Type; 5682 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5683 5684 #define USBC_UPSTA4SET_OFFSET 0x5A0 /**< \brief (USBC_UPSTA4SET offset) Pipe Status Set Register */ 5685 #define USBC_UPSTA4SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA4SET reset_value) Pipe Status Set Register */ 5686 5687 #define USBC_UPSTA4SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA4SET) RXINI Set */ 5688 #define USBC_UPSTA4SET_RXINIS (_U_(0x1) << USBC_UPSTA4SET_RXINIS_Pos) 5689 #define USBC_UPSTA4SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA4SET) TXOUTI Set */ 5690 #define USBC_UPSTA4SET_TXOUTIS (_U_(0x1) << USBC_UPSTA4SET_TXOUTIS_Pos) 5691 #define USBC_UPSTA4SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA4SET) TXSTPI Set */ 5692 #define USBC_UPSTA4SET_TXSTPIS (_U_(0x1) << USBC_UPSTA4SET_TXSTPIS_Pos) 5693 #define USBC_UPSTA4SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA4SET) PERRI Set */ 5694 #define USBC_UPSTA4SET_PERRIS (_U_(0x1) << USBC_UPSTA4SET_PERRIS_Pos) 5695 #define USBC_UPSTA4SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA4SET) NAKEDI Set */ 5696 #define USBC_UPSTA4SET_NAKEDIS (_U_(0x1) << USBC_UPSTA4SET_NAKEDIS_Pos) 5697 #define USBC_UPSTA4SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA4SET) ERRORFI Set */ 5698 #define USBC_UPSTA4SET_ERRORFIS (_U_(0x1) << USBC_UPSTA4SET_ERRORFIS_Pos) 5699 #define USBC_UPSTA4SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA4SET) RXSTALLDI Set */ 5700 #define USBC_UPSTA4SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA4SET_RXSTALLDIS_Pos) 5701 #define USBC_UPSTA4SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA4SET) RAMACERI Set */ 5702 #define USBC_UPSTA4SET_RAMACERIS (_U_(0x1) << USBC_UPSTA4SET_RAMACERIS_Pos) 5703 #define USBC_UPSTA4SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA4SET) MASK Register */ 5704 5705 /* -------- USBC_UPSTA5SET : (USBC Offset: 0x5A4) ( /W 32) Pipe Status Set Register -------- */ 5706 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5707 typedef union { 5708 struct { 5709 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5710 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5711 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5712 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5713 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5714 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5715 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5716 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5717 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5718 uint32_t :21; /*!< bit: 11..31 Reserved */ 5719 } bit; /*!< Structure used for bit access */ 5720 uint32_t reg; /*!< Type used for register access */ 5721 } USBC_UPSTA5SET_Type; 5722 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5723 5724 #define USBC_UPSTA5SET_OFFSET 0x5A4 /**< \brief (USBC_UPSTA5SET offset) Pipe Status Set Register */ 5725 #define USBC_UPSTA5SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA5SET reset_value) Pipe Status Set Register */ 5726 5727 #define USBC_UPSTA5SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA5SET) RXINI Set */ 5728 #define USBC_UPSTA5SET_RXINIS (_U_(0x1) << USBC_UPSTA5SET_RXINIS_Pos) 5729 #define USBC_UPSTA5SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA5SET) TXOUTI Set */ 5730 #define USBC_UPSTA5SET_TXOUTIS (_U_(0x1) << USBC_UPSTA5SET_TXOUTIS_Pos) 5731 #define USBC_UPSTA5SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA5SET) TXSTPI Set */ 5732 #define USBC_UPSTA5SET_TXSTPIS (_U_(0x1) << USBC_UPSTA5SET_TXSTPIS_Pos) 5733 #define USBC_UPSTA5SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA5SET) PERRI Set */ 5734 #define USBC_UPSTA5SET_PERRIS (_U_(0x1) << USBC_UPSTA5SET_PERRIS_Pos) 5735 #define USBC_UPSTA5SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA5SET) NAKEDI Set */ 5736 #define USBC_UPSTA5SET_NAKEDIS (_U_(0x1) << USBC_UPSTA5SET_NAKEDIS_Pos) 5737 #define USBC_UPSTA5SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA5SET) ERRORFI Set */ 5738 #define USBC_UPSTA5SET_ERRORFIS (_U_(0x1) << USBC_UPSTA5SET_ERRORFIS_Pos) 5739 #define USBC_UPSTA5SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA5SET) RXSTALLDI Set */ 5740 #define USBC_UPSTA5SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA5SET_RXSTALLDIS_Pos) 5741 #define USBC_UPSTA5SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA5SET) RAMACERI Set */ 5742 #define USBC_UPSTA5SET_RAMACERIS (_U_(0x1) << USBC_UPSTA5SET_RAMACERIS_Pos) 5743 #define USBC_UPSTA5SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA5SET) MASK Register */ 5744 5745 /* -------- USBC_UPSTA6SET : (USBC Offset: 0x5A8) ( /W 32) Pipe Status Set Register -------- */ 5746 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5747 typedef union { 5748 struct { 5749 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5750 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5751 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5752 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5753 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5754 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5755 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5756 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5757 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5758 uint32_t :21; /*!< bit: 11..31 Reserved */ 5759 } bit; /*!< Structure used for bit access */ 5760 uint32_t reg; /*!< Type used for register access */ 5761 } USBC_UPSTA6SET_Type; 5762 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5763 5764 #define USBC_UPSTA6SET_OFFSET 0x5A8 /**< \brief (USBC_UPSTA6SET offset) Pipe Status Set Register */ 5765 #define USBC_UPSTA6SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA6SET reset_value) Pipe Status Set Register */ 5766 5767 #define USBC_UPSTA6SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA6SET) RXINI Set */ 5768 #define USBC_UPSTA6SET_RXINIS (_U_(0x1) << USBC_UPSTA6SET_RXINIS_Pos) 5769 #define USBC_UPSTA6SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA6SET) TXOUTI Set */ 5770 #define USBC_UPSTA6SET_TXOUTIS (_U_(0x1) << USBC_UPSTA6SET_TXOUTIS_Pos) 5771 #define USBC_UPSTA6SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA6SET) TXSTPI Set */ 5772 #define USBC_UPSTA6SET_TXSTPIS (_U_(0x1) << USBC_UPSTA6SET_TXSTPIS_Pos) 5773 #define USBC_UPSTA6SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA6SET) PERRI Set */ 5774 #define USBC_UPSTA6SET_PERRIS (_U_(0x1) << USBC_UPSTA6SET_PERRIS_Pos) 5775 #define USBC_UPSTA6SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA6SET) NAKEDI Set */ 5776 #define USBC_UPSTA6SET_NAKEDIS (_U_(0x1) << USBC_UPSTA6SET_NAKEDIS_Pos) 5777 #define USBC_UPSTA6SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA6SET) ERRORFI Set */ 5778 #define USBC_UPSTA6SET_ERRORFIS (_U_(0x1) << USBC_UPSTA6SET_ERRORFIS_Pos) 5779 #define USBC_UPSTA6SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA6SET) RXSTALLDI Set */ 5780 #define USBC_UPSTA6SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA6SET_RXSTALLDIS_Pos) 5781 #define USBC_UPSTA6SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA6SET) RAMACERI Set */ 5782 #define USBC_UPSTA6SET_RAMACERIS (_U_(0x1) << USBC_UPSTA6SET_RAMACERIS_Pos) 5783 #define USBC_UPSTA6SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA6SET) MASK Register */ 5784 5785 /* -------- USBC_UPSTA7SET : (USBC Offset: 0x5AC) ( /W 32) Pipe Status Set Register -------- */ 5786 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5787 typedef union { 5788 struct { 5789 uint32_t RXINIS:1; /*!< bit: 0 RXINI Set */ 5790 uint32_t TXOUTIS:1; /*!< bit: 1 TXOUTI Set */ 5791 uint32_t TXSTPIS:1; /*!< bit: 2 TXSTPI Set */ 5792 uint32_t PERRIS:1; /*!< bit: 3 PERRI Set */ 5793 uint32_t NAKEDIS:1; /*!< bit: 4 NAKEDI Set */ 5794 uint32_t ERRORFIS:1; /*!< bit: 5 ERRORFI Set */ 5795 uint32_t RXSTALLDIS:1; /*!< bit: 6 RXSTALLDI Set */ 5796 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5797 uint32_t RAMACERIS:1; /*!< bit: 10 RAMACERI Set */ 5798 uint32_t :21; /*!< bit: 11..31 Reserved */ 5799 } bit; /*!< Structure used for bit access */ 5800 uint32_t reg; /*!< Type used for register access */ 5801 } USBC_UPSTA7SET_Type; 5802 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5803 5804 #define USBC_UPSTA7SET_OFFSET 0x5AC /**< \brief (USBC_UPSTA7SET offset) Pipe Status Set Register */ 5805 #define USBC_UPSTA7SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPSTA7SET reset_value) Pipe Status Set Register */ 5806 5807 #define USBC_UPSTA7SET_RXINIS_Pos 0 /**< \brief (USBC_UPSTA7SET) RXINI Set */ 5808 #define USBC_UPSTA7SET_RXINIS (_U_(0x1) << USBC_UPSTA7SET_RXINIS_Pos) 5809 #define USBC_UPSTA7SET_TXOUTIS_Pos 1 /**< \brief (USBC_UPSTA7SET) TXOUTI Set */ 5810 #define USBC_UPSTA7SET_TXOUTIS (_U_(0x1) << USBC_UPSTA7SET_TXOUTIS_Pos) 5811 #define USBC_UPSTA7SET_TXSTPIS_Pos 2 /**< \brief (USBC_UPSTA7SET) TXSTPI Set */ 5812 #define USBC_UPSTA7SET_TXSTPIS (_U_(0x1) << USBC_UPSTA7SET_TXSTPIS_Pos) 5813 #define USBC_UPSTA7SET_PERRIS_Pos 3 /**< \brief (USBC_UPSTA7SET) PERRI Set */ 5814 #define USBC_UPSTA7SET_PERRIS (_U_(0x1) << USBC_UPSTA7SET_PERRIS_Pos) 5815 #define USBC_UPSTA7SET_NAKEDIS_Pos 4 /**< \brief (USBC_UPSTA7SET) NAKEDI Set */ 5816 #define USBC_UPSTA7SET_NAKEDIS (_U_(0x1) << USBC_UPSTA7SET_NAKEDIS_Pos) 5817 #define USBC_UPSTA7SET_ERRORFIS_Pos 5 /**< \brief (USBC_UPSTA7SET) ERRORFI Set */ 5818 #define USBC_UPSTA7SET_ERRORFIS (_U_(0x1) << USBC_UPSTA7SET_ERRORFIS_Pos) 5819 #define USBC_UPSTA7SET_RXSTALLDIS_Pos 6 /**< \brief (USBC_UPSTA7SET) RXSTALLDI Set */ 5820 #define USBC_UPSTA7SET_RXSTALLDIS (_U_(0x1) << USBC_UPSTA7SET_RXSTALLDIS_Pos) 5821 #define USBC_UPSTA7SET_RAMACERIS_Pos 10 /**< \brief (USBC_UPSTA7SET) RAMACERI Set */ 5822 #define USBC_UPSTA7SET_RAMACERIS (_U_(0x1) << USBC_UPSTA7SET_RAMACERIS_Pos) 5823 #define USBC_UPSTA7SET_MASK _U_(0x0000047F) /**< \brief (USBC_UPSTA7SET) MASK Register */ 5824 5825 /* -------- USBC_UPCON0 : (USBC Offset: 0x5C0) (R/ 32) Pipe Control Register -------- */ 5826 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5827 typedef union { 5828 struct { 5829 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 5830 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 5831 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 5832 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 5833 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 5834 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 5835 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 5836 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5837 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 5838 uint32_t :1; /*!< bit: 11 Reserved */ 5839 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 5840 uint32_t :1; /*!< bit: 13 Reserved */ 5841 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 5842 uint32_t :2; /*!< bit: 15..16 Reserved */ 5843 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 5844 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 5845 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 5846 uint32_t :12; /*!< bit: 20..31 Reserved */ 5847 } bit; /*!< Structure used for bit access */ 5848 uint32_t reg; /*!< Type used for register access */ 5849 } USBC_UPCON0_Type; 5850 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5851 5852 #define USBC_UPCON0_OFFSET 0x5C0 /**< \brief (USBC_UPCON0 offset) Pipe Control Register */ 5853 #define USBC_UPCON0_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON0 reset_value) Pipe Control Register */ 5854 5855 #define USBC_UPCON0_RXINE_Pos 0 /**< \brief (USBC_UPCON0) RXIN Interrupt Enable */ 5856 #define USBC_UPCON0_RXINE (_U_(0x1) << USBC_UPCON0_RXINE_Pos) 5857 #define USBC_UPCON0_TXOUTE_Pos 1 /**< \brief (USBC_UPCON0) TXOUT Interrupt Enable */ 5858 #define USBC_UPCON0_TXOUTE (_U_(0x1) << USBC_UPCON0_TXOUTE_Pos) 5859 #define USBC_UPCON0_TXSTPE_Pos 2 /**< \brief (USBC_UPCON0) TXSTP Interrupt Enable */ 5860 #define USBC_UPCON0_TXSTPE (_U_(0x1) << USBC_UPCON0_TXSTPE_Pos) 5861 #define USBC_UPCON0_PERRE_Pos 3 /**< \brief (USBC_UPCON0) PERR Interrupt Enable */ 5862 #define USBC_UPCON0_PERRE (_U_(0x1) << USBC_UPCON0_PERRE_Pos) 5863 #define USBC_UPCON0_NAKEDE_Pos 4 /**< \brief (USBC_UPCON0) NAKED Interrupt Enable */ 5864 #define USBC_UPCON0_NAKEDE (_U_(0x1) << USBC_UPCON0_NAKEDE_Pos) 5865 #define USBC_UPCON0_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON0) ERRORFI Interrupt Enable */ 5866 #define USBC_UPCON0_ERRORFIE (_U_(0x1) << USBC_UPCON0_ERRORFIE_Pos) 5867 #define USBC_UPCON0_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON0) RXTALLD Interrupt Enable */ 5868 #define USBC_UPCON0_RXSTALLDE (_U_(0x1) << USBC_UPCON0_RXSTALLDE_Pos) 5869 #define USBC_UPCON0_RAMACERE_Pos 10 /**< \brief (USBC_UPCON0) RAMACER Interrupt Enable */ 5870 #define USBC_UPCON0_RAMACERE (_U_(0x1) << USBC_UPCON0_RAMACERE_Pos) 5871 #define USBC_UPCON0_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON0) NBUSYBKInterrupt Enable */ 5872 #define USBC_UPCON0_NBUSYBKE (_U_(0x1) << USBC_UPCON0_NBUSYBKE_Pos) 5873 #define USBC_UPCON0_FIFOCON_Pos 14 /**< \brief (USBC_UPCON0) FIFO Control */ 5874 #define USBC_UPCON0_FIFOCON (_U_(0x1) << USBC_UPCON0_FIFOCON_Pos) 5875 #define USBC_UPCON0_PFREEZE_Pos 17 /**< \brief (USBC_UPCON0) Pipe Freeze */ 5876 #define USBC_UPCON0_PFREEZE (_U_(0x1) << USBC_UPCON0_PFREEZE_Pos) 5877 #define USBC_UPCON0_INITDTGL_Pos 18 /**< \brief (USBC_UPCON0) Data Toggle Initialization */ 5878 #define USBC_UPCON0_INITDTGL (_U_(0x1) << USBC_UPCON0_INITDTGL_Pos) 5879 #define USBC_UPCON0_INITBK_Pos 19 /**< \brief (USBC_UPCON0) Bank Initialization */ 5880 #define USBC_UPCON0_INITBK (_U_(0x1) << USBC_UPCON0_INITBK_Pos) 5881 #define USBC_UPCON0_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON0) MASK Register */ 5882 5883 /* -------- USBC_UPCON1 : (USBC Offset: 0x5C4) (R/ 32) Pipe Control Register -------- */ 5884 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5885 typedef union { 5886 struct { 5887 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 5888 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 5889 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 5890 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 5891 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 5892 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 5893 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 5894 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5895 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 5896 uint32_t :1; /*!< bit: 11 Reserved */ 5897 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 5898 uint32_t :1; /*!< bit: 13 Reserved */ 5899 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 5900 uint32_t :2; /*!< bit: 15..16 Reserved */ 5901 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 5902 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 5903 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 5904 uint32_t :12; /*!< bit: 20..31 Reserved */ 5905 } bit; /*!< Structure used for bit access */ 5906 uint32_t reg; /*!< Type used for register access */ 5907 } USBC_UPCON1_Type; 5908 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5909 5910 #define USBC_UPCON1_OFFSET 0x5C4 /**< \brief (USBC_UPCON1 offset) Pipe Control Register */ 5911 #define USBC_UPCON1_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON1 reset_value) Pipe Control Register */ 5912 5913 #define USBC_UPCON1_RXINE_Pos 0 /**< \brief (USBC_UPCON1) RXIN Interrupt Enable */ 5914 #define USBC_UPCON1_RXINE (_U_(0x1) << USBC_UPCON1_RXINE_Pos) 5915 #define USBC_UPCON1_TXOUTE_Pos 1 /**< \brief (USBC_UPCON1) TXOUT Interrupt Enable */ 5916 #define USBC_UPCON1_TXOUTE (_U_(0x1) << USBC_UPCON1_TXOUTE_Pos) 5917 #define USBC_UPCON1_TXSTPE_Pos 2 /**< \brief (USBC_UPCON1) TXSTP Interrupt Enable */ 5918 #define USBC_UPCON1_TXSTPE (_U_(0x1) << USBC_UPCON1_TXSTPE_Pos) 5919 #define USBC_UPCON1_PERRE_Pos 3 /**< \brief (USBC_UPCON1) PERR Interrupt Enable */ 5920 #define USBC_UPCON1_PERRE (_U_(0x1) << USBC_UPCON1_PERRE_Pos) 5921 #define USBC_UPCON1_NAKEDE_Pos 4 /**< \brief (USBC_UPCON1) NAKED Interrupt Enable */ 5922 #define USBC_UPCON1_NAKEDE (_U_(0x1) << USBC_UPCON1_NAKEDE_Pos) 5923 #define USBC_UPCON1_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON1) ERRORFI Interrupt Enable */ 5924 #define USBC_UPCON1_ERRORFIE (_U_(0x1) << USBC_UPCON1_ERRORFIE_Pos) 5925 #define USBC_UPCON1_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON1) RXTALLD Interrupt Enable */ 5926 #define USBC_UPCON1_RXSTALLDE (_U_(0x1) << USBC_UPCON1_RXSTALLDE_Pos) 5927 #define USBC_UPCON1_RAMACERE_Pos 10 /**< \brief (USBC_UPCON1) RAMACER Interrupt Enable */ 5928 #define USBC_UPCON1_RAMACERE (_U_(0x1) << USBC_UPCON1_RAMACERE_Pos) 5929 #define USBC_UPCON1_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON1) NBUSYBKInterrupt Enable */ 5930 #define USBC_UPCON1_NBUSYBKE (_U_(0x1) << USBC_UPCON1_NBUSYBKE_Pos) 5931 #define USBC_UPCON1_FIFOCON_Pos 14 /**< \brief (USBC_UPCON1) FIFO Control */ 5932 #define USBC_UPCON1_FIFOCON (_U_(0x1) << USBC_UPCON1_FIFOCON_Pos) 5933 #define USBC_UPCON1_PFREEZE_Pos 17 /**< \brief (USBC_UPCON1) Pipe Freeze */ 5934 #define USBC_UPCON1_PFREEZE (_U_(0x1) << USBC_UPCON1_PFREEZE_Pos) 5935 #define USBC_UPCON1_INITDTGL_Pos 18 /**< \brief (USBC_UPCON1) Data Toggle Initialization */ 5936 #define USBC_UPCON1_INITDTGL (_U_(0x1) << USBC_UPCON1_INITDTGL_Pos) 5937 #define USBC_UPCON1_INITBK_Pos 19 /**< \brief (USBC_UPCON1) Bank Initialization */ 5938 #define USBC_UPCON1_INITBK (_U_(0x1) << USBC_UPCON1_INITBK_Pos) 5939 #define USBC_UPCON1_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON1) MASK Register */ 5940 5941 /* -------- USBC_UPCON2 : (USBC Offset: 0x5C8) (R/ 32) Pipe Control Register -------- */ 5942 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 5943 typedef union { 5944 struct { 5945 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 5946 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 5947 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 5948 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 5949 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 5950 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 5951 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 5952 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 5953 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 5954 uint32_t :1; /*!< bit: 11 Reserved */ 5955 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 5956 uint32_t :1; /*!< bit: 13 Reserved */ 5957 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 5958 uint32_t :2; /*!< bit: 15..16 Reserved */ 5959 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 5960 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 5961 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 5962 uint32_t :12; /*!< bit: 20..31 Reserved */ 5963 } bit; /*!< Structure used for bit access */ 5964 uint32_t reg; /*!< Type used for register access */ 5965 } USBC_UPCON2_Type; 5966 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 5967 5968 #define USBC_UPCON2_OFFSET 0x5C8 /**< \brief (USBC_UPCON2 offset) Pipe Control Register */ 5969 #define USBC_UPCON2_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON2 reset_value) Pipe Control Register */ 5970 5971 #define USBC_UPCON2_RXINE_Pos 0 /**< \brief (USBC_UPCON2) RXIN Interrupt Enable */ 5972 #define USBC_UPCON2_RXINE (_U_(0x1) << USBC_UPCON2_RXINE_Pos) 5973 #define USBC_UPCON2_TXOUTE_Pos 1 /**< \brief (USBC_UPCON2) TXOUT Interrupt Enable */ 5974 #define USBC_UPCON2_TXOUTE (_U_(0x1) << USBC_UPCON2_TXOUTE_Pos) 5975 #define USBC_UPCON2_TXSTPE_Pos 2 /**< \brief (USBC_UPCON2) TXSTP Interrupt Enable */ 5976 #define USBC_UPCON2_TXSTPE (_U_(0x1) << USBC_UPCON2_TXSTPE_Pos) 5977 #define USBC_UPCON2_PERRE_Pos 3 /**< \brief (USBC_UPCON2) PERR Interrupt Enable */ 5978 #define USBC_UPCON2_PERRE (_U_(0x1) << USBC_UPCON2_PERRE_Pos) 5979 #define USBC_UPCON2_NAKEDE_Pos 4 /**< \brief (USBC_UPCON2) NAKED Interrupt Enable */ 5980 #define USBC_UPCON2_NAKEDE (_U_(0x1) << USBC_UPCON2_NAKEDE_Pos) 5981 #define USBC_UPCON2_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON2) ERRORFI Interrupt Enable */ 5982 #define USBC_UPCON2_ERRORFIE (_U_(0x1) << USBC_UPCON2_ERRORFIE_Pos) 5983 #define USBC_UPCON2_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON2) RXTALLD Interrupt Enable */ 5984 #define USBC_UPCON2_RXSTALLDE (_U_(0x1) << USBC_UPCON2_RXSTALLDE_Pos) 5985 #define USBC_UPCON2_RAMACERE_Pos 10 /**< \brief (USBC_UPCON2) RAMACER Interrupt Enable */ 5986 #define USBC_UPCON2_RAMACERE (_U_(0x1) << USBC_UPCON2_RAMACERE_Pos) 5987 #define USBC_UPCON2_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON2) NBUSYBKInterrupt Enable */ 5988 #define USBC_UPCON2_NBUSYBKE (_U_(0x1) << USBC_UPCON2_NBUSYBKE_Pos) 5989 #define USBC_UPCON2_FIFOCON_Pos 14 /**< \brief (USBC_UPCON2) FIFO Control */ 5990 #define USBC_UPCON2_FIFOCON (_U_(0x1) << USBC_UPCON2_FIFOCON_Pos) 5991 #define USBC_UPCON2_PFREEZE_Pos 17 /**< \brief (USBC_UPCON2) Pipe Freeze */ 5992 #define USBC_UPCON2_PFREEZE (_U_(0x1) << USBC_UPCON2_PFREEZE_Pos) 5993 #define USBC_UPCON2_INITDTGL_Pos 18 /**< \brief (USBC_UPCON2) Data Toggle Initialization */ 5994 #define USBC_UPCON2_INITDTGL (_U_(0x1) << USBC_UPCON2_INITDTGL_Pos) 5995 #define USBC_UPCON2_INITBK_Pos 19 /**< \brief (USBC_UPCON2) Bank Initialization */ 5996 #define USBC_UPCON2_INITBK (_U_(0x1) << USBC_UPCON2_INITBK_Pos) 5997 #define USBC_UPCON2_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON2) MASK Register */ 5998 5999 /* -------- USBC_UPCON3 : (USBC Offset: 0x5CC) (R/ 32) Pipe Control Register -------- */ 6000 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6001 typedef union { 6002 struct { 6003 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 6004 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 6005 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 6006 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 6007 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 6008 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 6009 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 6010 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6011 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 6012 uint32_t :1; /*!< bit: 11 Reserved */ 6013 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 6014 uint32_t :1; /*!< bit: 13 Reserved */ 6015 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 6016 uint32_t :2; /*!< bit: 15..16 Reserved */ 6017 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 6018 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 6019 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 6020 uint32_t :12; /*!< bit: 20..31 Reserved */ 6021 } bit; /*!< Structure used for bit access */ 6022 uint32_t reg; /*!< Type used for register access */ 6023 } USBC_UPCON3_Type; 6024 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6025 6026 #define USBC_UPCON3_OFFSET 0x5CC /**< \brief (USBC_UPCON3 offset) Pipe Control Register */ 6027 #define USBC_UPCON3_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON3 reset_value) Pipe Control Register */ 6028 6029 #define USBC_UPCON3_RXINE_Pos 0 /**< \brief (USBC_UPCON3) RXIN Interrupt Enable */ 6030 #define USBC_UPCON3_RXINE (_U_(0x1) << USBC_UPCON3_RXINE_Pos) 6031 #define USBC_UPCON3_TXOUTE_Pos 1 /**< \brief (USBC_UPCON3) TXOUT Interrupt Enable */ 6032 #define USBC_UPCON3_TXOUTE (_U_(0x1) << USBC_UPCON3_TXOUTE_Pos) 6033 #define USBC_UPCON3_TXSTPE_Pos 2 /**< \brief (USBC_UPCON3) TXSTP Interrupt Enable */ 6034 #define USBC_UPCON3_TXSTPE (_U_(0x1) << USBC_UPCON3_TXSTPE_Pos) 6035 #define USBC_UPCON3_PERRE_Pos 3 /**< \brief (USBC_UPCON3) PERR Interrupt Enable */ 6036 #define USBC_UPCON3_PERRE (_U_(0x1) << USBC_UPCON3_PERRE_Pos) 6037 #define USBC_UPCON3_NAKEDE_Pos 4 /**< \brief (USBC_UPCON3) NAKED Interrupt Enable */ 6038 #define USBC_UPCON3_NAKEDE (_U_(0x1) << USBC_UPCON3_NAKEDE_Pos) 6039 #define USBC_UPCON3_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON3) ERRORFI Interrupt Enable */ 6040 #define USBC_UPCON3_ERRORFIE (_U_(0x1) << USBC_UPCON3_ERRORFIE_Pos) 6041 #define USBC_UPCON3_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON3) RXTALLD Interrupt Enable */ 6042 #define USBC_UPCON3_RXSTALLDE (_U_(0x1) << USBC_UPCON3_RXSTALLDE_Pos) 6043 #define USBC_UPCON3_RAMACERE_Pos 10 /**< \brief (USBC_UPCON3) RAMACER Interrupt Enable */ 6044 #define USBC_UPCON3_RAMACERE (_U_(0x1) << USBC_UPCON3_RAMACERE_Pos) 6045 #define USBC_UPCON3_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON3) NBUSYBKInterrupt Enable */ 6046 #define USBC_UPCON3_NBUSYBKE (_U_(0x1) << USBC_UPCON3_NBUSYBKE_Pos) 6047 #define USBC_UPCON3_FIFOCON_Pos 14 /**< \brief (USBC_UPCON3) FIFO Control */ 6048 #define USBC_UPCON3_FIFOCON (_U_(0x1) << USBC_UPCON3_FIFOCON_Pos) 6049 #define USBC_UPCON3_PFREEZE_Pos 17 /**< \brief (USBC_UPCON3) Pipe Freeze */ 6050 #define USBC_UPCON3_PFREEZE (_U_(0x1) << USBC_UPCON3_PFREEZE_Pos) 6051 #define USBC_UPCON3_INITDTGL_Pos 18 /**< \brief (USBC_UPCON3) Data Toggle Initialization */ 6052 #define USBC_UPCON3_INITDTGL (_U_(0x1) << USBC_UPCON3_INITDTGL_Pos) 6053 #define USBC_UPCON3_INITBK_Pos 19 /**< \brief (USBC_UPCON3) Bank Initialization */ 6054 #define USBC_UPCON3_INITBK (_U_(0x1) << USBC_UPCON3_INITBK_Pos) 6055 #define USBC_UPCON3_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON3) MASK Register */ 6056 6057 /* -------- USBC_UPCON4 : (USBC Offset: 0x5D0) (R/ 32) Pipe Control Register -------- */ 6058 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6059 typedef union { 6060 struct { 6061 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 6062 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 6063 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 6064 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 6065 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 6066 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 6067 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 6068 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6069 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 6070 uint32_t :1; /*!< bit: 11 Reserved */ 6071 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 6072 uint32_t :1; /*!< bit: 13 Reserved */ 6073 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 6074 uint32_t :2; /*!< bit: 15..16 Reserved */ 6075 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 6076 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 6077 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 6078 uint32_t :12; /*!< bit: 20..31 Reserved */ 6079 } bit; /*!< Structure used for bit access */ 6080 uint32_t reg; /*!< Type used for register access */ 6081 } USBC_UPCON4_Type; 6082 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6083 6084 #define USBC_UPCON4_OFFSET 0x5D0 /**< \brief (USBC_UPCON4 offset) Pipe Control Register */ 6085 #define USBC_UPCON4_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON4 reset_value) Pipe Control Register */ 6086 6087 #define USBC_UPCON4_RXINE_Pos 0 /**< \brief (USBC_UPCON4) RXIN Interrupt Enable */ 6088 #define USBC_UPCON4_RXINE (_U_(0x1) << USBC_UPCON4_RXINE_Pos) 6089 #define USBC_UPCON4_TXOUTE_Pos 1 /**< \brief (USBC_UPCON4) TXOUT Interrupt Enable */ 6090 #define USBC_UPCON4_TXOUTE (_U_(0x1) << USBC_UPCON4_TXOUTE_Pos) 6091 #define USBC_UPCON4_TXSTPE_Pos 2 /**< \brief (USBC_UPCON4) TXSTP Interrupt Enable */ 6092 #define USBC_UPCON4_TXSTPE (_U_(0x1) << USBC_UPCON4_TXSTPE_Pos) 6093 #define USBC_UPCON4_PERRE_Pos 3 /**< \brief (USBC_UPCON4) PERR Interrupt Enable */ 6094 #define USBC_UPCON4_PERRE (_U_(0x1) << USBC_UPCON4_PERRE_Pos) 6095 #define USBC_UPCON4_NAKEDE_Pos 4 /**< \brief (USBC_UPCON4) NAKED Interrupt Enable */ 6096 #define USBC_UPCON4_NAKEDE (_U_(0x1) << USBC_UPCON4_NAKEDE_Pos) 6097 #define USBC_UPCON4_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON4) ERRORFI Interrupt Enable */ 6098 #define USBC_UPCON4_ERRORFIE (_U_(0x1) << USBC_UPCON4_ERRORFIE_Pos) 6099 #define USBC_UPCON4_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON4) RXTALLD Interrupt Enable */ 6100 #define USBC_UPCON4_RXSTALLDE (_U_(0x1) << USBC_UPCON4_RXSTALLDE_Pos) 6101 #define USBC_UPCON4_RAMACERE_Pos 10 /**< \brief (USBC_UPCON4) RAMACER Interrupt Enable */ 6102 #define USBC_UPCON4_RAMACERE (_U_(0x1) << USBC_UPCON4_RAMACERE_Pos) 6103 #define USBC_UPCON4_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON4) NBUSYBKInterrupt Enable */ 6104 #define USBC_UPCON4_NBUSYBKE (_U_(0x1) << USBC_UPCON4_NBUSYBKE_Pos) 6105 #define USBC_UPCON4_FIFOCON_Pos 14 /**< \brief (USBC_UPCON4) FIFO Control */ 6106 #define USBC_UPCON4_FIFOCON (_U_(0x1) << USBC_UPCON4_FIFOCON_Pos) 6107 #define USBC_UPCON4_PFREEZE_Pos 17 /**< \brief (USBC_UPCON4) Pipe Freeze */ 6108 #define USBC_UPCON4_PFREEZE (_U_(0x1) << USBC_UPCON4_PFREEZE_Pos) 6109 #define USBC_UPCON4_INITDTGL_Pos 18 /**< \brief (USBC_UPCON4) Data Toggle Initialization */ 6110 #define USBC_UPCON4_INITDTGL (_U_(0x1) << USBC_UPCON4_INITDTGL_Pos) 6111 #define USBC_UPCON4_INITBK_Pos 19 /**< \brief (USBC_UPCON4) Bank Initialization */ 6112 #define USBC_UPCON4_INITBK (_U_(0x1) << USBC_UPCON4_INITBK_Pos) 6113 #define USBC_UPCON4_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON4) MASK Register */ 6114 6115 /* -------- USBC_UPCON5 : (USBC Offset: 0x5D4) (R/ 32) Pipe Control Register -------- */ 6116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6117 typedef union { 6118 struct { 6119 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 6120 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 6121 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 6122 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 6123 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 6124 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 6125 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 6126 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6127 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 6128 uint32_t :1; /*!< bit: 11 Reserved */ 6129 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 6130 uint32_t :1; /*!< bit: 13 Reserved */ 6131 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 6132 uint32_t :2; /*!< bit: 15..16 Reserved */ 6133 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 6134 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 6135 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 6136 uint32_t :12; /*!< bit: 20..31 Reserved */ 6137 } bit; /*!< Structure used for bit access */ 6138 uint32_t reg; /*!< Type used for register access */ 6139 } USBC_UPCON5_Type; 6140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6141 6142 #define USBC_UPCON5_OFFSET 0x5D4 /**< \brief (USBC_UPCON5 offset) Pipe Control Register */ 6143 #define USBC_UPCON5_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON5 reset_value) Pipe Control Register */ 6144 6145 #define USBC_UPCON5_RXINE_Pos 0 /**< \brief (USBC_UPCON5) RXIN Interrupt Enable */ 6146 #define USBC_UPCON5_RXINE (_U_(0x1) << USBC_UPCON5_RXINE_Pos) 6147 #define USBC_UPCON5_TXOUTE_Pos 1 /**< \brief (USBC_UPCON5) TXOUT Interrupt Enable */ 6148 #define USBC_UPCON5_TXOUTE (_U_(0x1) << USBC_UPCON5_TXOUTE_Pos) 6149 #define USBC_UPCON5_TXSTPE_Pos 2 /**< \brief (USBC_UPCON5) TXSTP Interrupt Enable */ 6150 #define USBC_UPCON5_TXSTPE (_U_(0x1) << USBC_UPCON5_TXSTPE_Pos) 6151 #define USBC_UPCON5_PERRE_Pos 3 /**< \brief (USBC_UPCON5) PERR Interrupt Enable */ 6152 #define USBC_UPCON5_PERRE (_U_(0x1) << USBC_UPCON5_PERRE_Pos) 6153 #define USBC_UPCON5_NAKEDE_Pos 4 /**< \brief (USBC_UPCON5) NAKED Interrupt Enable */ 6154 #define USBC_UPCON5_NAKEDE (_U_(0x1) << USBC_UPCON5_NAKEDE_Pos) 6155 #define USBC_UPCON5_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON5) ERRORFI Interrupt Enable */ 6156 #define USBC_UPCON5_ERRORFIE (_U_(0x1) << USBC_UPCON5_ERRORFIE_Pos) 6157 #define USBC_UPCON5_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON5) RXTALLD Interrupt Enable */ 6158 #define USBC_UPCON5_RXSTALLDE (_U_(0x1) << USBC_UPCON5_RXSTALLDE_Pos) 6159 #define USBC_UPCON5_RAMACERE_Pos 10 /**< \brief (USBC_UPCON5) RAMACER Interrupt Enable */ 6160 #define USBC_UPCON5_RAMACERE (_U_(0x1) << USBC_UPCON5_RAMACERE_Pos) 6161 #define USBC_UPCON5_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON5) NBUSYBKInterrupt Enable */ 6162 #define USBC_UPCON5_NBUSYBKE (_U_(0x1) << USBC_UPCON5_NBUSYBKE_Pos) 6163 #define USBC_UPCON5_FIFOCON_Pos 14 /**< \brief (USBC_UPCON5) FIFO Control */ 6164 #define USBC_UPCON5_FIFOCON (_U_(0x1) << USBC_UPCON5_FIFOCON_Pos) 6165 #define USBC_UPCON5_PFREEZE_Pos 17 /**< \brief (USBC_UPCON5) Pipe Freeze */ 6166 #define USBC_UPCON5_PFREEZE (_U_(0x1) << USBC_UPCON5_PFREEZE_Pos) 6167 #define USBC_UPCON5_INITDTGL_Pos 18 /**< \brief (USBC_UPCON5) Data Toggle Initialization */ 6168 #define USBC_UPCON5_INITDTGL (_U_(0x1) << USBC_UPCON5_INITDTGL_Pos) 6169 #define USBC_UPCON5_INITBK_Pos 19 /**< \brief (USBC_UPCON5) Bank Initialization */ 6170 #define USBC_UPCON5_INITBK (_U_(0x1) << USBC_UPCON5_INITBK_Pos) 6171 #define USBC_UPCON5_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON5) MASK Register */ 6172 6173 /* -------- USBC_UPCON6 : (USBC Offset: 0x5D8) (R/ 32) Pipe Control Register -------- */ 6174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6175 typedef union { 6176 struct { 6177 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 6178 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 6179 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 6180 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 6181 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 6182 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 6183 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 6184 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6185 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 6186 uint32_t :1; /*!< bit: 11 Reserved */ 6187 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 6188 uint32_t :1; /*!< bit: 13 Reserved */ 6189 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 6190 uint32_t :2; /*!< bit: 15..16 Reserved */ 6191 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 6192 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 6193 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 6194 uint32_t :12; /*!< bit: 20..31 Reserved */ 6195 } bit; /*!< Structure used for bit access */ 6196 uint32_t reg; /*!< Type used for register access */ 6197 } USBC_UPCON6_Type; 6198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6199 6200 #define USBC_UPCON6_OFFSET 0x5D8 /**< \brief (USBC_UPCON6 offset) Pipe Control Register */ 6201 #define USBC_UPCON6_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON6 reset_value) Pipe Control Register */ 6202 6203 #define USBC_UPCON6_RXINE_Pos 0 /**< \brief (USBC_UPCON6) RXIN Interrupt Enable */ 6204 #define USBC_UPCON6_RXINE (_U_(0x1) << USBC_UPCON6_RXINE_Pos) 6205 #define USBC_UPCON6_TXOUTE_Pos 1 /**< \brief (USBC_UPCON6) TXOUT Interrupt Enable */ 6206 #define USBC_UPCON6_TXOUTE (_U_(0x1) << USBC_UPCON6_TXOUTE_Pos) 6207 #define USBC_UPCON6_TXSTPE_Pos 2 /**< \brief (USBC_UPCON6) TXSTP Interrupt Enable */ 6208 #define USBC_UPCON6_TXSTPE (_U_(0x1) << USBC_UPCON6_TXSTPE_Pos) 6209 #define USBC_UPCON6_PERRE_Pos 3 /**< \brief (USBC_UPCON6) PERR Interrupt Enable */ 6210 #define USBC_UPCON6_PERRE (_U_(0x1) << USBC_UPCON6_PERRE_Pos) 6211 #define USBC_UPCON6_NAKEDE_Pos 4 /**< \brief (USBC_UPCON6) NAKED Interrupt Enable */ 6212 #define USBC_UPCON6_NAKEDE (_U_(0x1) << USBC_UPCON6_NAKEDE_Pos) 6213 #define USBC_UPCON6_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON6) ERRORFI Interrupt Enable */ 6214 #define USBC_UPCON6_ERRORFIE (_U_(0x1) << USBC_UPCON6_ERRORFIE_Pos) 6215 #define USBC_UPCON6_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON6) RXTALLD Interrupt Enable */ 6216 #define USBC_UPCON6_RXSTALLDE (_U_(0x1) << USBC_UPCON6_RXSTALLDE_Pos) 6217 #define USBC_UPCON6_RAMACERE_Pos 10 /**< \brief (USBC_UPCON6) RAMACER Interrupt Enable */ 6218 #define USBC_UPCON6_RAMACERE (_U_(0x1) << USBC_UPCON6_RAMACERE_Pos) 6219 #define USBC_UPCON6_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON6) NBUSYBKInterrupt Enable */ 6220 #define USBC_UPCON6_NBUSYBKE (_U_(0x1) << USBC_UPCON6_NBUSYBKE_Pos) 6221 #define USBC_UPCON6_FIFOCON_Pos 14 /**< \brief (USBC_UPCON6) FIFO Control */ 6222 #define USBC_UPCON6_FIFOCON (_U_(0x1) << USBC_UPCON6_FIFOCON_Pos) 6223 #define USBC_UPCON6_PFREEZE_Pos 17 /**< \brief (USBC_UPCON6) Pipe Freeze */ 6224 #define USBC_UPCON6_PFREEZE (_U_(0x1) << USBC_UPCON6_PFREEZE_Pos) 6225 #define USBC_UPCON6_INITDTGL_Pos 18 /**< \brief (USBC_UPCON6) Data Toggle Initialization */ 6226 #define USBC_UPCON6_INITDTGL (_U_(0x1) << USBC_UPCON6_INITDTGL_Pos) 6227 #define USBC_UPCON6_INITBK_Pos 19 /**< \brief (USBC_UPCON6) Bank Initialization */ 6228 #define USBC_UPCON6_INITBK (_U_(0x1) << USBC_UPCON6_INITBK_Pos) 6229 #define USBC_UPCON6_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON6) MASK Register */ 6230 6231 /* -------- USBC_UPCON7 : (USBC Offset: 0x5DC) (R/ 32) Pipe Control Register -------- */ 6232 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6233 typedef union { 6234 struct { 6235 uint32_t RXINE:1; /*!< bit: 0 RXIN Interrupt Enable */ 6236 uint32_t TXOUTE:1; /*!< bit: 1 TXOUT Interrupt Enable */ 6237 uint32_t TXSTPE:1; /*!< bit: 2 TXSTP Interrupt Enable */ 6238 uint32_t PERRE:1; /*!< bit: 3 PERR Interrupt Enable */ 6239 uint32_t NAKEDE:1; /*!< bit: 4 NAKED Interrupt Enable */ 6240 uint32_t ERRORFIE:1; /*!< bit: 5 ERRORFI Interrupt Enable */ 6241 uint32_t RXSTALLDE:1; /*!< bit: 6 RXTALLD Interrupt Enable */ 6242 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6243 uint32_t RAMACERE:1; /*!< bit: 10 RAMACER Interrupt Enable */ 6244 uint32_t :1; /*!< bit: 11 Reserved */ 6245 uint32_t NBUSYBKE:1; /*!< bit: 12 NBUSYBKInterrupt Enable */ 6246 uint32_t :1; /*!< bit: 13 Reserved */ 6247 uint32_t FIFOCON:1; /*!< bit: 14 FIFO Control */ 6248 uint32_t :2; /*!< bit: 15..16 Reserved */ 6249 uint32_t PFREEZE:1; /*!< bit: 17 Pipe Freeze */ 6250 uint32_t INITDTGL:1; /*!< bit: 18 Data Toggle Initialization */ 6251 uint32_t INITBK:1; /*!< bit: 19 Bank Initialization */ 6252 uint32_t :12; /*!< bit: 20..31 Reserved */ 6253 } bit; /*!< Structure used for bit access */ 6254 uint32_t reg; /*!< Type used for register access */ 6255 } USBC_UPCON7_Type; 6256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6257 6258 #define USBC_UPCON7_OFFSET 0x5DC /**< \brief (USBC_UPCON7 offset) Pipe Control Register */ 6259 #define USBC_UPCON7_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON7 reset_value) Pipe Control Register */ 6260 6261 #define USBC_UPCON7_RXINE_Pos 0 /**< \brief (USBC_UPCON7) RXIN Interrupt Enable */ 6262 #define USBC_UPCON7_RXINE (_U_(0x1) << USBC_UPCON7_RXINE_Pos) 6263 #define USBC_UPCON7_TXOUTE_Pos 1 /**< \brief (USBC_UPCON7) TXOUT Interrupt Enable */ 6264 #define USBC_UPCON7_TXOUTE (_U_(0x1) << USBC_UPCON7_TXOUTE_Pos) 6265 #define USBC_UPCON7_TXSTPE_Pos 2 /**< \brief (USBC_UPCON7) TXSTP Interrupt Enable */ 6266 #define USBC_UPCON7_TXSTPE (_U_(0x1) << USBC_UPCON7_TXSTPE_Pos) 6267 #define USBC_UPCON7_PERRE_Pos 3 /**< \brief (USBC_UPCON7) PERR Interrupt Enable */ 6268 #define USBC_UPCON7_PERRE (_U_(0x1) << USBC_UPCON7_PERRE_Pos) 6269 #define USBC_UPCON7_NAKEDE_Pos 4 /**< \brief (USBC_UPCON7) NAKED Interrupt Enable */ 6270 #define USBC_UPCON7_NAKEDE (_U_(0x1) << USBC_UPCON7_NAKEDE_Pos) 6271 #define USBC_UPCON7_ERRORFIE_Pos 5 /**< \brief (USBC_UPCON7) ERRORFI Interrupt Enable */ 6272 #define USBC_UPCON7_ERRORFIE (_U_(0x1) << USBC_UPCON7_ERRORFIE_Pos) 6273 #define USBC_UPCON7_RXSTALLDE_Pos 6 /**< \brief (USBC_UPCON7) RXTALLD Interrupt Enable */ 6274 #define USBC_UPCON7_RXSTALLDE (_U_(0x1) << USBC_UPCON7_RXSTALLDE_Pos) 6275 #define USBC_UPCON7_RAMACERE_Pos 10 /**< \brief (USBC_UPCON7) RAMACER Interrupt Enable */ 6276 #define USBC_UPCON7_RAMACERE (_U_(0x1) << USBC_UPCON7_RAMACERE_Pos) 6277 #define USBC_UPCON7_NBUSYBKE_Pos 12 /**< \brief (USBC_UPCON7) NBUSYBKInterrupt Enable */ 6278 #define USBC_UPCON7_NBUSYBKE (_U_(0x1) << USBC_UPCON7_NBUSYBKE_Pos) 6279 #define USBC_UPCON7_FIFOCON_Pos 14 /**< \brief (USBC_UPCON7) FIFO Control */ 6280 #define USBC_UPCON7_FIFOCON (_U_(0x1) << USBC_UPCON7_FIFOCON_Pos) 6281 #define USBC_UPCON7_PFREEZE_Pos 17 /**< \brief (USBC_UPCON7) Pipe Freeze */ 6282 #define USBC_UPCON7_PFREEZE (_U_(0x1) << USBC_UPCON7_PFREEZE_Pos) 6283 #define USBC_UPCON7_INITDTGL_Pos 18 /**< \brief (USBC_UPCON7) Data Toggle Initialization */ 6284 #define USBC_UPCON7_INITDTGL (_U_(0x1) << USBC_UPCON7_INITDTGL_Pos) 6285 #define USBC_UPCON7_INITBK_Pos 19 /**< \brief (USBC_UPCON7) Bank Initialization */ 6286 #define USBC_UPCON7_INITBK (_U_(0x1) << USBC_UPCON7_INITBK_Pos) 6287 #define USBC_UPCON7_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON7) MASK Register */ 6288 6289 /* -------- USBC_UPCON0SET : (USBC Offset: 0x5F0) ( /W 32) Pipe Control Set Register -------- */ 6290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6291 typedef union { 6292 struct { 6293 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6294 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6295 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6296 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6297 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6298 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6299 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6300 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6301 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6302 uint32_t :1; /*!< bit: 11 Reserved */ 6303 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6304 uint32_t :1; /*!< bit: 13 Reserved */ 6305 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6306 uint32_t :2; /*!< bit: 15..16 Reserved */ 6307 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6308 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6309 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6310 uint32_t :12; /*!< bit: 20..31 Reserved */ 6311 } bit; /*!< Structure used for bit access */ 6312 uint32_t reg; /*!< Type used for register access */ 6313 } USBC_UPCON0SET_Type; 6314 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6315 6316 #define USBC_UPCON0SET_OFFSET 0x5F0 /**< \brief (USBC_UPCON0SET offset) Pipe Control Set Register */ 6317 #define USBC_UPCON0SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON0SET reset_value) Pipe Control Set Register */ 6318 6319 #define USBC_UPCON0SET_RXINES_Pos 0 /**< \brief (USBC_UPCON0SET) RXINE Set */ 6320 #define USBC_UPCON0SET_RXINES (_U_(0x1) << USBC_UPCON0SET_RXINES_Pos) 6321 #define USBC_UPCON0SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON0SET) TXOUTE Set */ 6322 #define USBC_UPCON0SET_TXOUTES (_U_(0x1) << USBC_UPCON0SET_TXOUTES_Pos) 6323 #define USBC_UPCON0SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON0SET) TXSTPE Set */ 6324 #define USBC_UPCON0SET_TXSTPES (_U_(0x1) << USBC_UPCON0SET_TXSTPES_Pos) 6325 #define USBC_UPCON0SET_PERRES_Pos 3 /**< \brief (USBC_UPCON0SET) PERRE Set */ 6326 #define USBC_UPCON0SET_PERRES (_U_(0x1) << USBC_UPCON0SET_PERRES_Pos) 6327 #define USBC_UPCON0SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON0SET) NAKEDE Set */ 6328 #define USBC_UPCON0SET_NAKEDES (_U_(0x1) << USBC_UPCON0SET_NAKEDES_Pos) 6329 #define USBC_UPCON0SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON0SET) ERRORFIE Set */ 6330 #define USBC_UPCON0SET_ERRORFIES (_U_(0x1) << USBC_UPCON0SET_ERRORFIES_Pos) 6331 #define USBC_UPCON0SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON0SET) RXSTALLDE Set */ 6332 #define USBC_UPCON0SET_RXSTALLDES (_U_(0x1) << USBC_UPCON0SET_RXSTALLDES_Pos) 6333 #define USBC_UPCON0SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON0SET) RAMACERE Set */ 6334 #define USBC_UPCON0SET_RAMACERES (_U_(0x1) << USBC_UPCON0SET_RAMACERES_Pos) 6335 #define USBC_UPCON0SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON0SET) NBUSYBKE Set */ 6336 #define USBC_UPCON0SET_NBUSYBKES (_U_(0x1) << USBC_UPCON0SET_NBUSYBKES_Pos) 6337 #define USBC_UPCON0SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON0SET) FIFOCON Set */ 6338 #define USBC_UPCON0SET_FIFOCONS (_U_(0x1) << USBC_UPCON0SET_FIFOCONS_Pos) 6339 #define USBC_UPCON0SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON0SET) PFREEZE Set */ 6340 #define USBC_UPCON0SET_PFREEZES (_U_(0x1) << USBC_UPCON0SET_PFREEZES_Pos) 6341 #define USBC_UPCON0SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON0SET) INITDTGL Set */ 6342 #define USBC_UPCON0SET_INITDTGLS (_U_(0x1) << USBC_UPCON0SET_INITDTGLS_Pos) 6343 #define USBC_UPCON0SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON0SET) INITBK Set */ 6344 #define USBC_UPCON0SET_INITBKS (_U_(0x1) << USBC_UPCON0SET_INITBKS_Pos) 6345 #define USBC_UPCON0SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON0SET) MASK Register */ 6346 6347 /* -------- USBC_UPCON1SET : (USBC Offset: 0x5F4) ( /W 32) Pipe Control Set Register -------- */ 6348 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6349 typedef union { 6350 struct { 6351 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6352 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6353 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6354 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6355 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6356 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6357 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6358 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6359 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6360 uint32_t :1; /*!< bit: 11 Reserved */ 6361 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6362 uint32_t :1; /*!< bit: 13 Reserved */ 6363 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6364 uint32_t :2; /*!< bit: 15..16 Reserved */ 6365 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6366 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6367 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6368 uint32_t :12; /*!< bit: 20..31 Reserved */ 6369 } bit; /*!< Structure used for bit access */ 6370 uint32_t reg; /*!< Type used for register access */ 6371 } USBC_UPCON1SET_Type; 6372 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6373 6374 #define USBC_UPCON1SET_OFFSET 0x5F4 /**< \brief (USBC_UPCON1SET offset) Pipe Control Set Register */ 6375 #define USBC_UPCON1SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON1SET reset_value) Pipe Control Set Register */ 6376 6377 #define USBC_UPCON1SET_RXINES_Pos 0 /**< \brief (USBC_UPCON1SET) RXINE Set */ 6378 #define USBC_UPCON1SET_RXINES (_U_(0x1) << USBC_UPCON1SET_RXINES_Pos) 6379 #define USBC_UPCON1SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON1SET) TXOUTE Set */ 6380 #define USBC_UPCON1SET_TXOUTES (_U_(0x1) << USBC_UPCON1SET_TXOUTES_Pos) 6381 #define USBC_UPCON1SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON1SET) TXSTPE Set */ 6382 #define USBC_UPCON1SET_TXSTPES (_U_(0x1) << USBC_UPCON1SET_TXSTPES_Pos) 6383 #define USBC_UPCON1SET_PERRES_Pos 3 /**< \brief (USBC_UPCON1SET) PERRE Set */ 6384 #define USBC_UPCON1SET_PERRES (_U_(0x1) << USBC_UPCON1SET_PERRES_Pos) 6385 #define USBC_UPCON1SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON1SET) NAKEDE Set */ 6386 #define USBC_UPCON1SET_NAKEDES (_U_(0x1) << USBC_UPCON1SET_NAKEDES_Pos) 6387 #define USBC_UPCON1SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON1SET) ERRORFIE Set */ 6388 #define USBC_UPCON1SET_ERRORFIES (_U_(0x1) << USBC_UPCON1SET_ERRORFIES_Pos) 6389 #define USBC_UPCON1SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON1SET) RXSTALLDE Set */ 6390 #define USBC_UPCON1SET_RXSTALLDES (_U_(0x1) << USBC_UPCON1SET_RXSTALLDES_Pos) 6391 #define USBC_UPCON1SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON1SET) RAMACERE Set */ 6392 #define USBC_UPCON1SET_RAMACERES (_U_(0x1) << USBC_UPCON1SET_RAMACERES_Pos) 6393 #define USBC_UPCON1SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON1SET) NBUSYBKE Set */ 6394 #define USBC_UPCON1SET_NBUSYBKES (_U_(0x1) << USBC_UPCON1SET_NBUSYBKES_Pos) 6395 #define USBC_UPCON1SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON1SET) FIFOCON Set */ 6396 #define USBC_UPCON1SET_FIFOCONS (_U_(0x1) << USBC_UPCON1SET_FIFOCONS_Pos) 6397 #define USBC_UPCON1SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON1SET) PFREEZE Set */ 6398 #define USBC_UPCON1SET_PFREEZES (_U_(0x1) << USBC_UPCON1SET_PFREEZES_Pos) 6399 #define USBC_UPCON1SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON1SET) INITDTGL Set */ 6400 #define USBC_UPCON1SET_INITDTGLS (_U_(0x1) << USBC_UPCON1SET_INITDTGLS_Pos) 6401 #define USBC_UPCON1SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON1SET) INITBK Set */ 6402 #define USBC_UPCON1SET_INITBKS (_U_(0x1) << USBC_UPCON1SET_INITBKS_Pos) 6403 #define USBC_UPCON1SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON1SET) MASK Register */ 6404 6405 /* -------- USBC_UPCON2SET : (USBC Offset: 0x5F8) ( /W 32) Pipe Control Set Register -------- */ 6406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6407 typedef union { 6408 struct { 6409 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6410 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6411 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6412 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6413 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6414 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6415 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6416 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6417 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6418 uint32_t :1; /*!< bit: 11 Reserved */ 6419 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6420 uint32_t :1; /*!< bit: 13 Reserved */ 6421 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6422 uint32_t :2; /*!< bit: 15..16 Reserved */ 6423 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6424 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6425 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6426 uint32_t :12; /*!< bit: 20..31 Reserved */ 6427 } bit; /*!< Structure used for bit access */ 6428 uint32_t reg; /*!< Type used for register access */ 6429 } USBC_UPCON2SET_Type; 6430 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6431 6432 #define USBC_UPCON2SET_OFFSET 0x5F8 /**< \brief (USBC_UPCON2SET offset) Pipe Control Set Register */ 6433 #define USBC_UPCON2SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON2SET reset_value) Pipe Control Set Register */ 6434 6435 #define USBC_UPCON2SET_RXINES_Pos 0 /**< \brief (USBC_UPCON2SET) RXINE Set */ 6436 #define USBC_UPCON2SET_RXINES (_U_(0x1) << USBC_UPCON2SET_RXINES_Pos) 6437 #define USBC_UPCON2SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON2SET) TXOUTE Set */ 6438 #define USBC_UPCON2SET_TXOUTES (_U_(0x1) << USBC_UPCON2SET_TXOUTES_Pos) 6439 #define USBC_UPCON2SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON2SET) TXSTPE Set */ 6440 #define USBC_UPCON2SET_TXSTPES (_U_(0x1) << USBC_UPCON2SET_TXSTPES_Pos) 6441 #define USBC_UPCON2SET_PERRES_Pos 3 /**< \brief (USBC_UPCON2SET) PERRE Set */ 6442 #define USBC_UPCON2SET_PERRES (_U_(0x1) << USBC_UPCON2SET_PERRES_Pos) 6443 #define USBC_UPCON2SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON2SET) NAKEDE Set */ 6444 #define USBC_UPCON2SET_NAKEDES (_U_(0x1) << USBC_UPCON2SET_NAKEDES_Pos) 6445 #define USBC_UPCON2SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON2SET) ERRORFIE Set */ 6446 #define USBC_UPCON2SET_ERRORFIES (_U_(0x1) << USBC_UPCON2SET_ERRORFIES_Pos) 6447 #define USBC_UPCON2SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON2SET) RXSTALLDE Set */ 6448 #define USBC_UPCON2SET_RXSTALLDES (_U_(0x1) << USBC_UPCON2SET_RXSTALLDES_Pos) 6449 #define USBC_UPCON2SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON2SET) RAMACERE Set */ 6450 #define USBC_UPCON2SET_RAMACERES (_U_(0x1) << USBC_UPCON2SET_RAMACERES_Pos) 6451 #define USBC_UPCON2SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON2SET) NBUSYBKE Set */ 6452 #define USBC_UPCON2SET_NBUSYBKES (_U_(0x1) << USBC_UPCON2SET_NBUSYBKES_Pos) 6453 #define USBC_UPCON2SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON2SET) FIFOCON Set */ 6454 #define USBC_UPCON2SET_FIFOCONS (_U_(0x1) << USBC_UPCON2SET_FIFOCONS_Pos) 6455 #define USBC_UPCON2SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON2SET) PFREEZE Set */ 6456 #define USBC_UPCON2SET_PFREEZES (_U_(0x1) << USBC_UPCON2SET_PFREEZES_Pos) 6457 #define USBC_UPCON2SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON2SET) INITDTGL Set */ 6458 #define USBC_UPCON2SET_INITDTGLS (_U_(0x1) << USBC_UPCON2SET_INITDTGLS_Pos) 6459 #define USBC_UPCON2SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON2SET) INITBK Set */ 6460 #define USBC_UPCON2SET_INITBKS (_U_(0x1) << USBC_UPCON2SET_INITBKS_Pos) 6461 #define USBC_UPCON2SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON2SET) MASK Register */ 6462 6463 /* -------- USBC_UPCON3SET : (USBC Offset: 0x5FC) ( /W 32) Pipe Control Set Register -------- */ 6464 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6465 typedef union { 6466 struct { 6467 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6468 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6469 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6470 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6471 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6472 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6473 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6474 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6475 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6476 uint32_t :1; /*!< bit: 11 Reserved */ 6477 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6478 uint32_t :1; /*!< bit: 13 Reserved */ 6479 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6480 uint32_t :2; /*!< bit: 15..16 Reserved */ 6481 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6482 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6483 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6484 uint32_t :12; /*!< bit: 20..31 Reserved */ 6485 } bit; /*!< Structure used for bit access */ 6486 uint32_t reg; /*!< Type used for register access */ 6487 } USBC_UPCON3SET_Type; 6488 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6489 6490 #define USBC_UPCON3SET_OFFSET 0x5FC /**< \brief (USBC_UPCON3SET offset) Pipe Control Set Register */ 6491 #define USBC_UPCON3SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON3SET reset_value) Pipe Control Set Register */ 6492 6493 #define USBC_UPCON3SET_RXINES_Pos 0 /**< \brief (USBC_UPCON3SET) RXINE Set */ 6494 #define USBC_UPCON3SET_RXINES (_U_(0x1) << USBC_UPCON3SET_RXINES_Pos) 6495 #define USBC_UPCON3SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON3SET) TXOUTE Set */ 6496 #define USBC_UPCON3SET_TXOUTES (_U_(0x1) << USBC_UPCON3SET_TXOUTES_Pos) 6497 #define USBC_UPCON3SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON3SET) TXSTPE Set */ 6498 #define USBC_UPCON3SET_TXSTPES (_U_(0x1) << USBC_UPCON3SET_TXSTPES_Pos) 6499 #define USBC_UPCON3SET_PERRES_Pos 3 /**< \brief (USBC_UPCON3SET) PERRE Set */ 6500 #define USBC_UPCON3SET_PERRES (_U_(0x1) << USBC_UPCON3SET_PERRES_Pos) 6501 #define USBC_UPCON3SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON3SET) NAKEDE Set */ 6502 #define USBC_UPCON3SET_NAKEDES (_U_(0x1) << USBC_UPCON3SET_NAKEDES_Pos) 6503 #define USBC_UPCON3SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON3SET) ERRORFIE Set */ 6504 #define USBC_UPCON3SET_ERRORFIES (_U_(0x1) << USBC_UPCON3SET_ERRORFIES_Pos) 6505 #define USBC_UPCON3SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON3SET) RXSTALLDE Set */ 6506 #define USBC_UPCON3SET_RXSTALLDES (_U_(0x1) << USBC_UPCON3SET_RXSTALLDES_Pos) 6507 #define USBC_UPCON3SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON3SET) RAMACERE Set */ 6508 #define USBC_UPCON3SET_RAMACERES (_U_(0x1) << USBC_UPCON3SET_RAMACERES_Pos) 6509 #define USBC_UPCON3SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON3SET) NBUSYBKE Set */ 6510 #define USBC_UPCON3SET_NBUSYBKES (_U_(0x1) << USBC_UPCON3SET_NBUSYBKES_Pos) 6511 #define USBC_UPCON3SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON3SET) FIFOCON Set */ 6512 #define USBC_UPCON3SET_FIFOCONS (_U_(0x1) << USBC_UPCON3SET_FIFOCONS_Pos) 6513 #define USBC_UPCON3SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON3SET) PFREEZE Set */ 6514 #define USBC_UPCON3SET_PFREEZES (_U_(0x1) << USBC_UPCON3SET_PFREEZES_Pos) 6515 #define USBC_UPCON3SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON3SET) INITDTGL Set */ 6516 #define USBC_UPCON3SET_INITDTGLS (_U_(0x1) << USBC_UPCON3SET_INITDTGLS_Pos) 6517 #define USBC_UPCON3SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON3SET) INITBK Set */ 6518 #define USBC_UPCON3SET_INITBKS (_U_(0x1) << USBC_UPCON3SET_INITBKS_Pos) 6519 #define USBC_UPCON3SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON3SET) MASK Register */ 6520 6521 /* -------- USBC_UPCON4SET : (USBC Offset: 0x600) ( /W 32) Pipe Control Set Register -------- */ 6522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6523 typedef union { 6524 struct { 6525 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6526 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6527 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6528 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6529 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6530 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6531 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6532 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6533 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6534 uint32_t :1; /*!< bit: 11 Reserved */ 6535 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6536 uint32_t :1; /*!< bit: 13 Reserved */ 6537 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6538 uint32_t :2; /*!< bit: 15..16 Reserved */ 6539 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6540 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6541 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6542 uint32_t :12; /*!< bit: 20..31 Reserved */ 6543 } bit; /*!< Structure used for bit access */ 6544 uint32_t reg; /*!< Type used for register access */ 6545 } USBC_UPCON4SET_Type; 6546 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6547 6548 #define USBC_UPCON4SET_OFFSET 0x600 /**< \brief (USBC_UPCON4SET offset) Pipe Control Set Register */ 6549 #define USBC_UPCON4SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON4SET reset_value) Pipe Control Set Register */ 6550 6551 #define USBC_UPCON4SET_RXINES_Pos 0 /**< \brief (USBC_UPCON4SET) RXINE Set */ 6552 #define USBC_UPCON4SET_RXINES (_U_(0x1) << USBC_UPCON4SET_RXINES_Pos) 6553 #define USBC_UPCON4SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON4SET) TXOUTE Set */ 6554 #define USBC_UPCON4SET_TXOUTES (_U_(0x1) << USBC_UPCON4SET_TXOUTES_Pos) 6555 #define USBC_UPCON4SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON4SET) TXSTPE Set */ 6556 #define USBC_UPCON4SET_TXSTPES (_U_(0x1) << USBC_UPCON4SET_TXSTPES_Pos) 6557 #define USBC_UPCON4SET_PERRES_Pos 3 /**< \brief (USBC_UPCON4SET) PERRE Set */ 6558 #define USBC_UPCON4SET_PERRES (_U_(0x1) << USBC_UPCON4SET_PERRES_Pos) 6559 #define USBC_UPCON4SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON4SET) NAKEDE Set */ 6560 #define USBC_UPCON4SET_NAKEDES (_U_(0x1) << USBC_UPCON4SET_NAKEDES_Pos) 6561 #define USBC_UPCON4SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON4SET) ERRORFIE Set */ 6562 #define USBC_UPCON4SET_ERRORFIES (_U_(0x1) << USBC_UPCON4SET_ERRORFIES_Pos) 6563 #define USBC_UPCON4SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON4SET) RXSTALLDE Set */ 6564 #define USBC_UPCON4SET_RXSTALLDES (_U_(0x1) << USBC_UPCON4SET_RXSTALLDES_Pos) 6565 #define USBC_UPCON4SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON4SET) RAMACERE Set */ 6566 #define USBC_UPCON4SET_RAMACERES (_U_(0x1) << USBC_UPCON4SET_RAMACERES_Pos) 6567 #define USBC_UPCON4SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON4SET) NBUSYBKE Set */ 6568 #define USBC_UPCON4SET_NBUSYBKES (_U_(0x1) << USBC_UPCON4SET_NBUSYBKES_Pos) 6569 #define USBC_UPCON4SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON4SET) FIFOCON Set */ 6570 #define USBC_UPCON4SET_FIFOCONS (_U_(0x1) << USBC_UPCON4SET_FIFOCONS_Pos) 6571 #define USBC_UPCON4SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON4SET) PFREEZE Set */ 6572 #define USBC_UPCON4SET_PFREEZES (_U_(0x1) << USBC_UPCON4SET_PFREEZES_Pos) 6573 #define USBC_UPCON4SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON4SET) INITDTGL Set */ 6574 #define USBC_UPCON4SET_INITDTGLS (_U_(0x1) << USBC_UPCON4SET_INITDTGLS_Pos) 6575 #define USBC_UPCON4SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON4SET) INITBK Set */ 6576 #define USBC_UPCON4SET_INITBKS (_U_(0x1) << USBC_UPCON4SET_INITBKS_Pos) 6577 #define USBC_UPCON4SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON4SET) MASK Register */ 6578 6579 /* -------- USBC_UPCON5SET : (USBC Offset: 0x604) ( /W 32) Pipe Control Set Register -------- */ 6580 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6581 typedef union { 6582 struct { 6583 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6584 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6585 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6586 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6587 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6588 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6589 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6590 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6591 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6592 uint32_t :1; /*!< bit: 11 Reserved */ 6593 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6594 uint32_t :1; /*!< bit: 13 Reserved */ 6595 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6596 uint32_t :2; /*!< bit: 15..16 Reserved */ 6597 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6598 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6599 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6600 uint32_t :12; /*!< bit: 20..31 Reserved */ 6601 } bit; /*!< Structure used for bit access */ 6602 uint32_t reg; /*!< Type used for register access */ 6603 } USBC_UPCON5SET_Type; 6604 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6605 6606 #define USBC_UPCON5SET_OFFSET 0x604 /**< \brief (USBC_UPCON5SET offset) Pipe Control Set Register */ 6607 #define USBC_UPCON5SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON5SET reset_value) Pipe Control Set Register */ 6608 6609 #define USBC_UPCON5SET_RXINES_Pos 0 /**< \brief (USBC_UPCON5SET) RXINE Set */ 6610 #define USBC_UPCON5SET_RXINES (_U_(0x1) << USBC_UPCON5SET_RXINES_Pos) 6611 #define USBC_UPCON5SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON5SET) TXOUTE Set */ 6612 #define USBC_UPCON5SET_TXOUTES (_U_(0x1) << USBC_UPCON5SET_TXOUTES_Pos) 6613 #define USBC_UPCON5SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON5SET) TXSTPE Set */ 6614 #define USBC_UPCON5SET_TXSTPES (_U_(0x1) << USBC_UPCON5SET_TXSTPES_Pos) 6615 #define USBC_UPCON5SET_PERRES_Pos 3 /**< \brief (USBC_UPCON5SET) PERRE Set */ 6616 #define USBC_UPCON5SET_PERRES (_U_(0x1) << USBC_UPCON5SET_PERRES_Pos) 6617 #define USBC_UPCON5SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON5SET) NAKEDE Set */ 6618 #define USBC_UPCON5SET_NAKEDES (_U_(0x1) << USBC_UPCON5SET_NAKEDES_Pos) 6619 #define USBC_UPCON5SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON5SET) ERRORFIE Set */ 6620 #define USBC_UPCON5SET_ERRORFIES (_U_(0x1) << USBC_UPCON5SET_ERRORFIES_Pos) 6621 #define USBC_UPCON5SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON5SET) RXSTALLDE Set */ 6622 #define USBC_UPCON5SET_RXSTALLDES (_U_(0x1) << USBC_UPCON5SET_RXSTALLDES_Pos) 6623 #define USBC_UPCON5SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON5SET) RAMACERE Set */ 6624 #define USBC_UPCON5SET_RAMACERES (_U_(0x1) << USBC_UPCON5SET_RAMACERES_Pos) 6625 #define USBC_UPCON5SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON5SET) NBUSYBKE Set */ 6626 #define USBC_UPCON5SET_NBUSYBKES (_U_(0x1) << USBC_UPCON5SET_NBUSYBKES_Pos) 6627 #define USBC_UPCON5SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON5SET) FIFOCON Set */ 6628 #define USBC_UPCON5SET_FIFOCONS (_U_(0x1) << USBC_UPCON5SET_FIFOCONS_Pos) 6629 #define USBC_UPCON5SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON5SET) PFREEZE Set */ 6630 #define USBC_UPCON5SET_PFREEZES (_U_(0x1) << USBC_UPCON5SET_PFREEZES_Pos) 6631 #define USBC_UPCON5SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON5SET) INITDTGL Set */ 6632 #define USBC_UPCON5SET_INITDTGLS (_U_(0x1) << USBC_UPCON5SET_INITDTGLS_Pos) 6633 #define USBC_UPCON5SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON5SET) INITBK Set */ 6634 #define USBC_UPCON5SET_INITBKS (_U_(0x1) << USBC_UPCON5SET_INITBKS_Pos) 6635 #define USBC_UPCON5SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON5SET) MASK Register */ 6636 6637 /* -------- USBC_UPCON6SET : (USBC Offset: 0x608) ( /W 32) Pipe Control Set Register -------- */ 6638 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6639 typedef union { 6640 struct { 6641 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6642 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6643 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6644 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6645 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6646 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6647 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6648 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6649 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6650 uint32_t :1; /*!< bit: 11 Reserved */ 6651 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6652 uint32_t :1; /*!< bit: 13 Reserved */ 6653 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6654 uint32_t :2; /*!< bit: 15..16 Reserved */ 6655 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6656 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6657 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6658 uint32_t :12; /*!< bit: 20..31 Reserved */ 6659 } bit; /*!< Structure used for bit access */ 6660 uint32_t reg; /*!< Type used for register access */ 6661 } USBC_UPCON6SET_Type; 6662 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6663 6664 #define USBC_UPCON6SET_OFFSET 0x608 /**< \brief (USBC_UPCON6SET offset) Pipe Control Set Register */ 6665 #define USBC_UPCON6SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON6SET reset_value) Pipe Control Set Register */ 6666 6667 #define USBC_UPCON6SET_RXINES_Pos 0 /**< \brief (USBC_UPCON6SET) RXINE Set */ 6668 #define USBC_UPCON6SET_RXINES (_U_(0x1) << USBC_UPCON6SET_RXINES_Pos) 6669 #define USBC_UPCON6SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON6SET) TXOUTE Set */ 6670 #define USBC_UPCON6SET_TXOUTES (_U_(0x1) << USBC_UPCON6SET_TXOUTES_Pos) 6671 #define USBC_UPCON6SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON6SET) TXSTPE Set */ 6672 #define USBC_UPCON6SET_TXSTPES (_U_(0x1) << USBC_UPCON6SET_TXSTPES_Pos) 6673 #define USBC_UPCON6SET_PERRES_Pos 3 /**< \brief (USBC_UPCON6SET) PERRE Set */ 6674 #define USBC_UPCON6SET_PERRES (_U_(0x1) << USBC_UPCON6SET_PERRES_Pos) 6675 #define USBC_UPCON6SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON6SET) NAKEDE Set */ 6676 #define USBC_UPCON6SET_NAKEDES (_U_(0x1) << USBC_UPCON6SET_NAKEDES_Pos) 6677 #define USBC_UPCON6SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON6SET) ERRORFIE Set */ 6678 #define USBC_UPCON6SET_ERRORFIES (_U_(0x1) << USBC_UPCON6SET_ERRORFIES_Pos) 6679 #define USBC_UPCON6SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON6SET) RXSTALLDE Set */ 6680 #define USBC_UPCON6SET_RXSTALLDES (_U_(0x1) << USBC_UPCON6SET_RXSTALLDES_Pos) 6681 #define USBC_UPCON6SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON6SET) RAMACERE Set */ 6682 #define USBC_UPCON6SET_RAMACERES (_U_(0x1) << USBC_UPCON6SET_RAMACERES_Pos) 6683 #define USBC_UPCON6SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON6SET) NBUSYBKE Set */ 6684 #define USBC_UPCON6SET_NBUSYBKES (_U_(0x1) << USBC_UPCON6SET_NBUSYBKES_Pos) 6685 #define USBC_UPCON6SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON6SET) FIFOCON Set */ 6686 #define USBC_UPCON6SET_FIFOCONS (_U_(0x1) << USBC_UPCON6SET_FIFOCONS_Pos) 6687 #define USBC_UPCON6SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON6SET) PFREEZE Set */ 6688 #define USBC_UPCON6SET_PFREEZES (_U_(0x1) << USBC_UPCON6SET_PFREEZES_Pos) 6689 #define USBC_UPCON6SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON6SET) INITDTGL Set */ 6690 #define USBC_UPCON6SET_INITDTGLS (_U_(0x1) << USBC_UPCON6SET_INITDTGLS_Pos) 6691 #define USBC_UPCON6SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON6SET) INITBK Set */ 6692 #define USBC_UPCON6SET_INITBKS (_U_(0x1) << USBC_UPCON6SET_INITBKS_Pos) 6693 #define USBC_UPCON6SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON6SET) MASK Register */ 6694 6695 /* -------- USBC_UPCON7SET : (USBC Offset: 0x60C) ( /W 32) Pipe Control Set Register -------- */ 6696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6697 typedef union { 6698 struct { 6699 uint32_t RXINES:1; /*!< bit: 0 RXINE Set */ 6700 uint32_t TXOUTES:1; /*!< bit: 1 TXOUTE Set */ 6701 uint32_t TXSTPES:1; /*!< bit: 2 TXSTPE Set */ 6702 uint32_t PERRES:1; /*!< bit: 3 PERRE Set */ 6703 uint32_t NAKEDES:1; /*!< bit: 4 NAKEDE Set */ 6704 uint32_t ERRORFIES:1; /*!< bit: 5 ERRORFIE Set */ 6705 uint32_t RXSTALLDES:1; /*!< bit: 6 RXSTALLDE Set */ 6706 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6707 uint32_t RAMACERES:1; /*!< bit: 10 RAMACERE Set */ 6708 uint32_t :1; /*!< bit: 11 Reserved */ 6709 uint32_t NBUSYBKES:1; /*!< bit: 12 NBUSYBKE Set */ 6710 uint32_t :1; /*!< bit: 13 Reserved */ 6711 uint32_t FIFOCONS:1; /*!< bit: 14 FIFOCON Set */ 6712 uint32_t :2; /*!< bit: 15..16 Reserved */ 6713 uint32_t PFREEZES:1; /*!< bit: 17 PFREEZE Set */ 6714 uint32_t INITDTGLS:1; /*!< bit: 18 INITDTGL Set */ 6715 uint32_t INITBKS:1; /*!< bit: 19 INITBK Set */ 6716 uint32_t :12; /*!< bit: 20..31 Reserved */ 6717 } bit; /*!< Structure used for bit access */ 6718 uint32_t reg; /*!< Type used for register access */ 6719 } USBC_UPCON7SET_Type; 6720 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6721 6722 #define USBC_UPCON7SET_OFFSET 0x60C /**< \brief (USBC_UPCON7SET offset) Pipe Control Set Register */ 6723 #define USBC_UPCON7SET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON7SET reset_value) Pipe Control Set Register */ 6724 6725 #define USBC_UPCON7SET_RXINES_Pos 0 /**< \brief (USBC_UPCON7SET) RXINE Set */ 6726 #define USBC_UPCON7SET_RXINES (_U_(0x1) << USBC_UPCON7SET_RXINES_Pos) 6727 #define USBC_UPCON7SET_TXOUTES_Pos 1 /**< \brief (USBC_UPCON7SET) TXOUTE Set */ 6728 #define USBC_UPCON7SET_TXOUTES (_U_(0x1) << USBC_UPCON7SET_TXOUTES_Pos) 6729 #define USBC_UPCON7SET_TXSTPES_Pos 2 /**< \brief (USBC_UPCON7SET) TXSTPE Set */ 6730 #define USBC_UPCON7SET_TXSTPES (_U_(0x1) << USBC_UPCON7SET_TXSTPES_Pos) 6731 #define USBC_UPCON7SET_PERRES_Pos 3 /**< \brief (USBC_UPCON7SET) PERRE Set */ 6732 #define USBC_UPCON7SET_PERRES (_U_(0x1) << USBC_UPCON7SET_PERRES_Pos) 6733 #define USBC_UPCON7SET_NAKEDES_Pos 4 /**< \brief (USBC_UPCON7SET) NAKEDE Set */ 6734 #define USBC_UPCON7SET_NAKEDES (_U_(0x1) << USBC_UPCON7SET_NAKEDES_Pos) 6735 #define USBC_UPCON7SET_ERRORFIES_Pos 5 /**< \brief (USBC_UPCON7SET) ERRORFIE Set */ 6736 #define USBC_UPCON7SET_ERRORFIES (_U_(0x1) << USBC_UPCON7SET_ERRORFIES_Pos) 6737 #define USBC_UPCON7SET_RXSTALLDES_Pos 6 /**< \brief (USBC_UPCON7SET) RXSTALLDE Set */ 6738 #define USBC_UPCON7SET_RXSTALLDES (_U_(0x1) << USBC_UPCON7SET_RXSTALLDES_Pos) 6739 #define USBC_UPCON7SET_RAMACERES_Pos 10 /**< \brief (USBC_UPCON7SET) RAMACERE Set */ 6740 #define USBC_UPCON7SET_RAMACERES (_U_(0x1) << USBC_UPCON7SET_RAMACERES_Pos) 6741 #define USBC_UPCON7SET_NBUSYBKES_Pos 12 /**< \brief (USBC_UPCON7SET) NBUSYBKE Set */ 6742 #define USBC_UPCON7SET_NBUSYBKES (_U_(0x1) << USBC_UPCON7SET_NBUSYBKES_Pos) 6743 #define USBC_UPCON7SET_FIFOCONS_Pos 14 /**< \brief (USBC_UPCON7SET) FIFOCON Set */ 6744 #define USBC_UPCON7SET_FIFOCONS (_U_(0x1) << USBC_UPCON7SET_FIFOCONS_Pos) 6745 #define USBC_UPCON7SET_PFREEZES_Pos 17 /**< \brief (USBC_UPCON7SET) PFREEZE Set */ 6746 #define USBC_UPCON7SET_PFREEZES (_U_(0x1) << USBC_UPCON7SET_PFREEZES_Pos) 6747 #define USBC_UPCON7SET_INITDTGLS_Pos 18 /**< \brief (USBC_UPCON7SET) INITDTGL Set */ 6748 #define USBC_UPCON7SET_INITDTGLS (_U_(0x1) << USBC_UPCON7SET_INITDTGLS_Pos) 6749 #define USBC_UPCON7SET_INITBKS_Pos 19 /**< \brief (USBC_UPCON7SET) INITBK Set */ 6750 #define USBC_UPCON7SET_INITBKS (_U_(0x1) << USBC_UPCON7SET_INITBKS_Pos) 6751 #define USBC_UPCON7SET_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON7SET) MASK Register */ 6752 6753 /* -------- USBC_UPCON0CLR : (USBC Offset: 0x620) ( /W 32) Pipe Control Clear Register -------- */ 6754 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6755 typedef union { 6756 struct { 6757 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 6758 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 6759 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 6760 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 6761 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 6762 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 6763 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 6764 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6765 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 6766 uint32_t :1; /*!< bit: 11 Reserved */ 6767 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 6768 uint32_t :1; /*!< bit: 13 Reserved */ 6769 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 6770 uint32_t :2; /*!< bit: 15..16 Reserved */ 6771 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 6772 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 6773 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 6774 uint32_t :12; /*!< bit: 20..31 Reserved */ 6775 } bit; /*!< Structure used for bit access */ 6776 uint32_t reg; /*!< Type used for register access */ 6777 } USBC_UPCON0CLR_Type; 6778 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6779 6780 #define USBC_UPCON0CLR_OFFSET 0x620 /**< \brief (USBC_UPCON0CLR offset) Pipe Control Clear Register */ 6781 #define USBC_UPCON0CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON0CLR reset_value) Pipe Control Clear Register */ 6782 6783 #define USBC_UPCON0CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON0CLR) RXINE Clear */ 6784 #define USBC_UPCON0CLR_RXINEC (_U_(0x1) << USBC_UPCON0CLR_RXINEC_Pos) 6785 #define USBC_UPCON0CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON0CLR) TXOUTE Clear */ 6786 #define USBC_UPCON0CLR_TXOUTEC (_U_(0x1) << USBC_UPCON0CLR_TXOUTEC_Pos) 6787 #define USBC_UPCON0CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON0CLR) TXSTPE Clear */ 6788 #define USBC_UPCON0CLR_TXSTPEC (_U_(0x1) << USBC_UPCON0CLR_TXSTPEC_Pos) 6789 #define USBC_UPCON0CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON0CLR) PERRE Clear */ 6790 #define USBC_UPCON0CLR_PERREC (_U_(0x1) << USBC_UPCON0CLR_PERREC_Pos) 6791 #define USBC_UPCON0CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON0CLR) NAKEDE Clear */ 6792 #define USBC_UPCON0CLR_NAKEDEC (_U_(0x1) << USBC_UPCON0CLR_NAKEDEC_Pos) 6793 #define USBC_UPCON0CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON0CLR) ERRORFIE Clear */ 6794 #define USBC_UPCON0CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON0CLR_ERRORFIEC_Pos) 6795 #define USBC_UPCON0CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON0CLR) RXTALLDE Clear */ 6796 #define USBC_UPCON0CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON0CLR_RXSTALLDEC_Pos) 6797 #define USBC_UPCON0CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON0CLR) RAMACERE Clear */ 6798 #define USBC_UPCON0CLR_RAMACEREC (_U_(0x1) << USBC_UPCON0CLR_RAMACEREC_Pos) 6799 #define USBC_UPCON0CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON0CLR) NBUSYBKE Clear */ 6800 #define USBC_UPCON0CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON0CLR_NBUSYBKEC_Pos) 6801 #define USBC_UPCON0CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON0CLR) FIFOCON Clear */ 6802 #define USBC_UPCON0CLR_FIFOCONC (_U_(0x1) << USBC_UPCON0CLR_FIFOCONC_Pos) 6803 #define USBC_UPCON0CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON0CLR) PFREEZE Clear */ 6804 #define USBC_UPCON0CLR_PFREEZEC (_U_(0x1) << USBC_UPCON0CLR_PFREEZEC_Pos) 6805 #define USBC_UPCON0CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON0CLR) INITDTGL Clear */ 6806 #define USBC_UPCON0CLR_INITDTGLC (_U_(0x1) << USBC_UPCON0CLR_INITDTGLC_Pos) 6807 #define USBC_UPCON0CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON0CLR) INITBK Clear */ 6808 #define USBC_UPCON0CLR_INITBKC (_U_(0x1) << USBC_UPCON0CLR_INITBKC_Pos) 6809 #define USBC_UPCON0CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON0CLR) MASK Register */ 6810 6811 /* -------- USBC_UPCON1CLR : (USBC Offset: 0x624) ( /W 32) Pipe Control Clear Register -------- */ 6812 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6813 typedef union { 6814 struct { 6815 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 6816 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 6817 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 6818 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 6819 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 6820 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 6821 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 6822 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6823 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 6824 uint32_t :1; /*!< bit: 11 Reserved */ 6825 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 6826 uint32_t :1; /*!< bit: 13 Reserved */ 6827 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 6828 uint32_t :2; /*!< bit: 15..16 Reserved */ 6829 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 6830 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 6831 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 6832 uint32_t :12; /*!< bit: 20..31 Reserved */ 6833 } bit; /*!< Structure used for bit access */ 6834 uint32_t reg; /*!< Type used for register access */ 6835 } USBC_UPCON1CLR_Type; 6836 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6837 6838 #define USBC_UPCON1CLR_OFFSET 0x624 /**< \brief (USBC_UPCON1CLR offset) Pipe Control Clear Register */ 6839 #define USBC_UPCON1CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON1CLR reset_value) Pipe Control Clear Register */ 6840 6841 #define USBC_UPCON1CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON1CLR) RXINE Clear */ 6842 #define USBC_UPCON1CLR_RXINEC (_U_(0x1) << USBC_UPCON1CLR_RXINEC_Pos) 6843 #define USBC_UPCON1CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON1CLR) TXOUTE Clear */ 6844 #define USBC_UPCON1CLR_TXOUTEC (_U_(0x1) << USBC_UPCON1CLR_TXOUTEC_Pos) 6845 #define USBC_UPCON1CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON1CLR) TXSTPE Clear */ 6846 #define USBC_UPCON1CLR_TXSTPEC (_U_(0x1) << USBC_UPCON1CLR_TXSTPEC_Pos) 6847 #define USBC_UPCON1CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON1CLR) PERRE Clear */ 6848 #define USBC_UPCON1CLR_PERREC (_U_(0x1) << USBC_UPCON1CLR_PERREC_Pos) 6849 #define USBC_UPCON1CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON1CLR) NAKEDE Clear */ 6850 #define USBC_UPCON1CLR_NAKEDEC (_U_(0x1) << USBC_UPCON1CLR_NAKEDEC_Pos) 6851 #define USBC_UPCON1CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON1CLR) ERRORFIE Clear */ 6852 #define USBC_UPCON1CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON1CLR_ERRORFIEC_Pos) 6853 #define USBC_UPCON1CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON1CLR) RXTALLDE Clear */ 6854 #define USBC_UPCON1CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON1CLR_RXSTALLDEC_Pos) 6855 #define USBC_UPCON1CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON1CLR) RAMACERE Clear */ 6856 #define USBC_UPCON1CLR_RAMACEREC (_U_(0x1) << USBC_UPCON1CLR_RAMACEREC_Pos) 6857 #define USBC_UPCON1CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON1CLR) NBUSYBKE Clear */ 6858 #define USBC_UPCON1CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON1CLR_NBUSYBKEC_Pos) 6859 #define USBC_UPCON1CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON1CLR) FIFOCON Clear */ 6860 #define USBC_UPCON1CLR_FIFOCONC (_U_(0x1) << USBC_UPCON1CLR_FIFOCONC_Pos) 6861 #define USBC_UPCON1CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON1CLR) PFREEZE Clear */ 6862 #define USBC_UPCON1CLR_PFREEZEC (_U_(0x1) << USBC_UPCON1CLR_PFREEZEC_Pos) 6863 #define USBC_UPCON1CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON1CLR) INITDTGL Clear */ 6864 #define USBC_UPCON1CLR_INITDTGLC (_U_(0x1) << USBC_UPCON1CLR_INITDTGLC_Pos) 6865 #define USBC_UPCON1CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON1CLR) INITBK Clear */ 6866 #define USBC_UPCON1CLR_INITBKC (_U_(0x1) << USBC_UPCON1CLR_INITBKC_Pos) 6867 #define USBC_UPCON1CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON1CLR) MASK Register */ 6868 6869 /* -------- USBC_UPCON2CLR : (USBC Offset: 0x628) ( /W 32) Pipe Control Clear Register -------- */ 6870 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6871 typedef union { 6872 struct { 6873 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 6874 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 6875 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 6876 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 6877 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 6878 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 6879 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 6880 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6881 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 6882 uint32_t :1; /*!< bit: 11 Reserved */ 6883 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 6884 uint32_t :1; /*!< bit: 13 Reserved */ 6885 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 6886 uint32_t :2; /*!< bit: 15..16 Reserved */ 6887 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 6888 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 6889 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 6890 uint32_t :12; /*!< bit: 20..31 Reserved */ 6891 } bit; /*!< Structure used for bit access */ 6892 uint32_t reg; /*!< Type used for register access */ 6893 } USBC_UPCON2CLR_Type; 6894 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6895 6896 #define USBC_UPCON2CLR_OFFSET 0x628 /**< \brief (USBC_UPCON2CLR offset) Pipe Control Clear Register */ 6897 #define USBC_UPCON2CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON2CLR reset_value) Pipe Control Clear Register */ 6898 6899 #define USBC_UPCON2CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON2CLR) RXINE Clear */ 6900 #define USBC_UPCON2CLR_RXINEC (_U_(0x1) << USBC_UPCON2CLR_RXINEC_Pos) 6901 #define USBC_UPCON2CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON2CLR) TXOUTE Clear */ 6902 #define USBC_UPCON2CLR_TXOUTEC (_U_(0x1) << USBC_UPCON2CLR_TXOUTEC_Pos) 6903 #define USBC_UPCON2CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON2CLR) TXSTPE Clear */ 6904 #define USBC_UPCON2CLR_TXSTPEC (_U_(0x1) << USBC_UPCON2CLR_TXSTPEC_Pos) 6905 #define USBC_UPCON2CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON2CLR) PERRE Clear */ 6906 #define USBC_UPCON2CLR_PERREC (_U_(0x1) << USBC_UPCON2CLR_PERREC_Pos) 6907 #define USBC_UPCON2CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON2CLR) NAKEDE Clear */ 6908 #define USBC_UPCON2CLR_NAKEDEC (_U_(0x1) << USBC_UPCON2CLR_NAKEDEC_Pos) 6909 #define USBC_UPCON2CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON2CLR) ERRORFIE Clear */ 6910 #define USBC_UPCON2CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON2CLR_ERRORFIEC_Pos) 6911 #define USBC_UPCON2CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON2CLR) RXTALLDE Clear */ 6912 #define USBC_UPCON2CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON2CLR_RXSTALLDEC_Pos) 6913 #define USBC_UPCON2CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON2CLR) RAMACERE Clear */ 6914 #define USBC_UPCON2CLR_RAMACEREC (_U_(0x1) << USBC_UPCON2CLR_RAMACEREC_Pos) 6915 #define USBC_UPCON2CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON2CLR) NBUSYBKE Clear */ 6916 #define USBC_UPCON2CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON2CLR_NBUSYBKEC_Pos) 6917 #define USBC_UPCON2CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON2CLR) FIFOCON Clear */ 6918 #define USBC_UPCON2CLR_FIFOCONC (_U_(0x1) << USBC_UPCON2CLR_FIFOCONC_Pos) 6919 #define USBC_UPCON2CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON2CLR) PFREEZE Clear */ 6920 #define USBC_UPCON2CLR_PFREEZEC (_U_(0x1) << USBC_UPCON2CLR_PFREEZEC_Pos) 6921 #define USBC_UPCON2CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON2CLR) INITDTGL Clear */ 6922 #define USBC_UPCON2CLR_INITDTGLC (_U_(0x1) << USBC_UPCON2CLR_INITDTGLC_Pos) 6923 #define USBC_UPCON2CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON2CLR) INITBK Clear */ 6924 #define USBC_UPCON2CLR_INITBKC (_U_(0x1) << USBC_UPCON2CLR_INITBKC_Pos) 6925 #define USBC_UPCON2CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON2CLR) MASK Register */ 6926 6927 /* -------- USBC_UPCON3CLR : (USBC Offset: 0x62C) ( /W 32) Pipe Control Clear Register -------- */ 6928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6929 typedef union { 6930 struct { 6931 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 6932 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 6933 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 6934 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 6935 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 6936 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 6937 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 6938 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6939 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 6940 uint32_t :1; /*!< bit: 11 Reserved */ 6941 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 6942 uint32_t :1; /*!< bit: 13 Reserved */ 6943 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 6944 uint32_t :2; /*!< bit: 15..16 Reserved */ 6945 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 6946 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 6947 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 6948 uint32_t :12; /*!< bit: 20..31 Reserved */ 6949 } bit; /*!< Structure used for bit access */ 6950 uint32_t reg; /*!< Type used for register access */ 6951 } USBC_UPCON3CLR_Type; 6952 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 6953 6954 #define USBC_UPCON3CLR_OFFSET 0x62C /**< \brief (USBC_UPCON3CLR offset) Pipe Control Clear Register */ 6955 #define USBC_UPCON3CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON3CLR reset_value) Pipe Control Clear Register */ 6956 6957 #define USBC_UPCON3CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON3CLR) RXINE Clear */ 6958 #define USBC_UPCON3CLR_RXINEC (_U_(0x1) << USBC_UPCON3CLR_RXINEC_Pos) 6959 #define USBC_UPCON3CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON3CLR) TXOUTE Clear */ 6960 #define USBC_UPCON3CLR_TXOUTEC (_U_(0x1) << USBC_UPCON3CLR_TXOUTEC_Pos) 6961 #define USBC_UPCON3CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON3CLR) TXSTPE Clear */ 6962 #define USBC_UPCON3CLR_TXSTPEC (_U_(0x1) << USBC_UPCON3CLR_TXSTPEC_Pos) 6963 #define USBC_UPCON3CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON3CLR) PERRE Clear */ 6964 #define USBC_UPCON3CLR_PERREC (_U_(0x1) << USBC_UPCON3CLR_PERREC_Pos) 6965 #define USBC_UPCON3CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON3CLR) NAKEDE Clear */ 6966 #define USBC_UPCON3CLR_NAKEDEC (_U_(0x1) << USBC_UPCON3CLR_NAKEDEC_Pos) 6967 #define USBC_UPCON3CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON3CLR) ERRORFIE Clear */ 6968 #define USBC_UPCON3CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON3CLR_ERRORFIEC_Pos) 6969 #define USBC_UPCON3CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON3CLR) RXTALLDE Clear */ 6970 #define USBC_UPCON3CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON3CLR_RXSTALLDEC_Pos) 6971 #define USBC_UPCON3CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON3CLR) RAMACERE Clear */ 6972 #define USBC_UPCON3CLR_RAMACEREC (_U_(0x1) << USBC_UPCON3CLR_RAMACEREC_Pos) 6973 #define USBC_UPCON3CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON3CLR) NBUSYBKE Clear */ 6974 #define USBC_UPCON3CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON3CLR_NBUSYBKEC_Pos) 6975 #define USBC_UPCON3CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON3CLR) FIFOCON Clear */ 6976 #define USBC_UPCON3CLR_FIFOCONC (_U_(0x1) << USBC_UPCON3CLR_FIFOCONC_Pos) 6977 #define USBC_UPCON3CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON3CLR) PFREEZE Clear */ 6978 #define USBC_UPCON3CLR_PFREEZEC (_U_(0x1) << USBC_UPCON3CLR_PFREEZEC_Pos) 6979 #define USBC_UPCON3CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON3CLR) INITDTGL Clear */ 6980 #define USBC_UPCON3CLR_INITDTGLC (_U_(0x1) << USBC_UPCON3CLR_INITDTGLC_Pos) 6981 #define USBC_UPCON3CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON3CLR) INITBK Clear */ 6982 #define USBC_UPCON3CLR_INITBKC (_U_(0x1) << USBC_UPCON3CLR_INITBKC_Pos) 6983 #define USBC_UPCON3CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON3CLR) MASK Register */ 6984 6985 /* -------- USBC_UPCON4CLR : (USBC Offset: 0x630) ( /W 32) Pipe Control Clear Register -------- */ 6986 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 6987 typedef union { 6988 struct { 6989 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 6990 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 6991 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 6992 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 6993 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 6994 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 6995 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 6996 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 6997 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 6998 uint32_t :1; /*!< bit: 11 Reserved */ 6999 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 7000 uint32_t :1; /*!< bit: 13 Reserved */ 7001 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 7002 uint32_t :2; /*!< bit: 15..16 Reserved */ 7003 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 7004 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 7005 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 7006 uint32_t :12; /*!< bit: 20..31 Reserved */ 7007 } bit; /*!< Structure used for bit access */ 7008 uint32_t reg; /*!< Type used for register access */ 7009 } USBC_UPCON4CLR_Type; 7010 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7011 7012 #define USBC_UPCON4CLR_OFFSET 0x630 /**< \brief (USBC_UPCON4CLR offset) Pipe Control Clear Register */ 7013 #define USBC_UPCON4CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON4CLR reset_value) Pipe Control Clear Register */ 7014 7015 #define USBC_UPCON4CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON4CLR) RXINE Clear */ 7016 #define USBC_UPCON4CLR_RXINEC (_U_(0x1) << USBC_UPCON4CLR_RXINEC_Pos) 7017 #define USBC_UPCON4CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON4CLR) TXOUTE Clear */ 7018 #define USBC_UPCON4CLR_TXOUTEC (_U_(0x1) << USBC_UPCON4CLR_TXOUTEC_Pos) 7019 #define USBC_UPCON4CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON4CLR) TXSTPE Clear */ 7020 #define USBC_UPCON4CLR_TXSTPEC (_U_(0x1) << USBC_UPCON4CLR_TXSTPEC_Pos) 7021 #define USBC_UPCON4CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON4CLR) PERRE Clear */ 7022 #define USBC_UPCON4CLR_PERREC (_U_(0x1) << USBC_UPCON4CLR_PERREC_Pos) 7023 #define USBC_UPCON4CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON4CLR) NAKEDE Clear */ 7024 #define USBC_UPCON4CLR_NAKEDEC (_U_(0x1) << USBC_UPCON4CLR_NAKEDEC_Pos) 7025 #define USBC_UPCON4CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON4CLR) ERRORFIE Clear */ 7026 #define USBC_UPCON4CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON4CLR_ERRORFIEC_Pos) 7027 #define USBC_UPCON4CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON4CLR) RXTALLDE Clear */ 7028 #define USBC_UPCON4CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON4CLR_RXSTALLDEC_Pos) 7029 #define USBC_UPCON4CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON4CLR) RAMACERE Clear */ 7030 #define USBC_UPCON4CLR_RAMACEREC (_U_(0x1) << USBC_UPCON4CLR_RAMACEREC_Pos) 7031 #define USBC_UPCON4CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON4CLR) NBUSYBKE Clear */ 7032 #define USBC_UPCON4CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON4CLR_NBUSYBKEC_Pos) 7033 #define USBC_UPCON4CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON4CLR) FIFOCON Clear */ 7034 #define USBC_UPCON4CLR_FIFOCONC (_U_(0x1) << USBC_UPCON4CLR_FIFOCONC_Pos) 7035 #define USBC_UPCON4CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON4CLR) PFREEZE Clear */ 7036 #define USBC_UPCON4CLR_PFREEZEC (_U_(0x1) << USBC_UPCON4CLR_PFREEZEC_Pos) 7037 #define USBC_UPCON4CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON4CLR) INITDTGL Clear */ 7038 #define USBC_UPCON4CLR_INITDTGLC (_U_(0x1) << USBC_UPCON4CLR_INITDTGLC_Pos) 7039 #define USBC_UPCON4CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON4CLR) INITBK Clear */ 7040 #define USBC_UPCON4CLR_INITBKC (_U_(0x1) << USBC_UPCON4CLR_INITBKC_Pos) 7041 #define USBC_UPCON4CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON4CLR) MASK Register */ 7042 7043 /* -------- USBC_UPCON5CLR : (USBC Offset: 0x634) ( /W 32) Pipe Control Clear Register -------- */ 7044 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7045 typedef union { 7046 struct { 7047 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 7048 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 7049 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 7050 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 7051 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 7052 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 7053 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 7054 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 7055 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 7056 uint32_t :1; /*!< bit: 11 Reserved */ 7057 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 7058 uint32_t :1; /*!< bit: 13 Reserved */ 7059 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 7060 uint32_t :2; /*!< bit: 15..16 Reserved */ 7061 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 7062 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 7063 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 7064 uint32_t :12; /*!< bit: 20..31 Reserved */ 7065 } bit; /*!< Structure used for bit access */ 7066 uint32_t reg; /*!< Type used for register access */ 7067 } USBC_UPCON5CLR_Type; 7068 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7069 7070 #define USBC_UPCON5CLR_OFFSET 0x634 /**< \brief (USBC_UPCON5CLR offset) Pipe Control Clear Register */ 7071 #define USBC_UPCON5CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON5CLR reset_value) Pipe Control Clear Register */ 7072 7073 #define USBC_UPCON5CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON5CLR) RXINE Clear */ 7074 #define USBC_UPCON5CLR_RXINEC (_U_(0x1) << USBC_UPCON5CLR_RXINEC_Pos) 7075 #define USBC_UPCON5CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON5CLR) TXOUTE Clear */ 7076 #define USBC_UPCON5CLR_TXOUTEC (_U_(0x1) << USBC_UPCON5CLR_TXOUTEC_Pos) 7077 #define USBC_UPCON5CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON5CLR) TXSTPE Clear */ 7078 #define USBC_UPCON5CLR_TXSTPEC (_U_(0x1) << USBC_UPCON5CLR_TXSTPEC_Pos) 7079 #define USBC_UPCON5CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON5CLR) PERRE Clear */ 7080 #define USBC_UPCON5CLR_PERREC (_U_(0x1) << USBC_UPCON5CLR_PERREC_Pos) 7081 #define USBC_UPCON5CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON5CLR) NAKEDE Clear */ 7082 #define USBC_UPCON5CLR_NAKEDEC (_U_(0x1) << USBC_UPCON5CLR_NAKEDEC_Pos) 7083 #define USBC_UPCON5CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON5CLR) ERRORFIE Clear */ 7084 #define USBC_UPCON5CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON5CLR_ERRORFIEC_Pos) 7085 #define USBC_UPCON5CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON5CLR) RXTALLDE Clear */ 7086 #define USBC_UPCON5CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON5CLR_RXSTALLDEC_Pos) 7087 #define USBC_UPCON5CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON5CLR) RAMACERE Clear */ 7088 #define USBC_UPCON5CLR_RAMACEREC (_U_(0x1) << USBC_UPCON5CLR_RAMACEREC_Pos) 7089 #define USBC_UPCON5CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON5CLR) NBUSYBKE Clear */ 7090 #define USBC_UPCON5CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON5CLR_NBUSYBKEC_Pos) 7091 #define USBC_UPCON5CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON5CLR) FIFOCON Clear */ 7092 #define USBC_UPCON5CLR_FIFOCONC (_U_(0x1) << USBC_UPCON5CLR_FIFOCONC_Pos) 7093 #define USBC_UPCON5CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON5CLR) PFREEZE Clear */ 7094 #define USBC_UPCON5CLR_PFREEZEC (_U_(0x1) << USBC_UPCON5CLR_PFREEZEC_Pos) 7095 #define USBC_UPCON5CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON5CLR) INITDTGL Clear */ 7096 #define USBC_UPCON5CLR_INITDTGLC (_U_(0x1) << USBC_UPCON5CLR_INITDTGLC_Pos) 7097 #define USBC_UPCON5CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON5CLR) INITBK Clear */ 7098 #define USBC_UPCON5CLR_INITBKC (_U_(0x1) << USBC_UPCON5CLR_INITBKC_Pos) 7099 #define USBC_UPCON5CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON5CLR) MASK Register */ 7100 7101 /* -------- USBC_UPCON6CLR : (USBC Offset: 0x638) ( /W 32) Pipe Control Clear Register -------- */ 7102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7103 typedef union { 7104 struct { 7105 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 7106 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 7107 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 7108 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 7109 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 7110 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 7111 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 7112 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 7113 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 7114 uint32_t :1; /*!< bit: 11 Reserved */ 7115 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 7116 uint32_t :1; /*!< bit: 13 Reserved */ 7117 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 7118 uint32_t :2; /*!< bit: 15..16 Reserved */ 7119 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 7120 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 7121 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 7122 uint32_t :12; /*!< bit: 20..31 Reserved */ 7123 } bit; /*!< Structure used for bit access */ 7124 uint32_t reg; /*!< Type used for register access */ 7125 } USBC_UPCON6CLR_Type; 7126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7127 7128 #define USBC_UPCON6CLR_OFFSET 0x638 /**< \brief (USBC_UPCON6CLR offset) Pipe Control Clear Register */ 7129 #define USBC_UPCON6CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON6CLR reset_value) Pipe Control Clear Register */ 7130 7131 #define USBC_UPCON6CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON6CLR) RXINE Clear */ 7132 #define USBC_UPCON6CLR_RXINEC (_U_(0x1) << USBC_UPCON6CLR_RXINEC_Pos) 7133 #define USBC_UPCON6CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON6CLR) TXOUTE Clear */ 7134 #define USBC_UPCON6CLR_TXOUTEC (_U_(0x1) << USBC_UPCON6CLR_TXOUTEC_Pos) 7135 #define USBC_UPCON6CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON6CLR) TXSTPE Clear */ 7136 #define USBC_UPCON6CLR_TXSTPEC (_U_(0x1) << USBC_UPCON6CLR_TXSTPEC_Pos) 7137 #define USBC_UPCON6CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON6CLR) PERRE Clear */ 7138 #define USBC_UPCON6CLR_PERREC (_U_(0x1) << USBC_UPCON6CLR_PERREC_Pos) 7139 #define USBC_UPCON6CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON6CLR) NAKEDE Clear */ 7140 #define USBC_UPCON6CLR_NAKEDEC (_U_(0x1) << USBC_UPCON6CLR_NAKEDEC_Pos) 7141 #define USBC_UPCON6CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON6CLR) ERRORFIE Clear */ 7142 #define USBC_UPCON6CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON6CLR_ERRORFIEC_Pos) 7143 #define USBC_UPCON6CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON6CLR) RXTALLDE Clear */ 7144 #define USBC_UPCON6CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON6CLR_RXSTALLDEC_Pos) 7145 #define USBC_UPCON6CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON6CLR) RAMACERE Clear */ 7146 #define USBC_UPCON6CLR_RAMACEREC (_U_(0x1) << USBC_UPCON6CLR_RAMACEREC_Pos) 7147 #define USBC_UPCON6CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON6CLR) NBUSYBKE Clear */ 7148 #define USBC_UPCON6CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON6CLR_NBUSYBKEC_Pos) 7149 #define USBC_UPCON6CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON6CLR) FIFOCON Clear */ 7150 #define USBC_UPCON6CLR_FIFOCONC (_U_(0x1) << USBC_UPCON6CLR_FIFOCONC_Pos) 7151 #define USBC_UPCON6CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON6CLR) PFREEZE Clear */ 7152 #define USBC_UPCON6CLR_PFREEZEC (_U_(0x1) << USBC_UPCON6CLR_PFREEZEC_Pos) 7153 #define USBC_UPCON6CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON6CLR) INITDTGL Clear */ 7154 #define USBC_UPCON6CLR_INITDTGLC (_U_(0x1) << USBC_UPCON6CLR_INITDTGLC_Pos) 7155 #define USBC_UPCON6CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON6CLR) INITBK Clear */ 7156 #define USBC_UPCON6CLR_INITBKC (_U_(0x1) << USBC_UPCON6CLR_INITBKC_Pos) 7157 #define USBC_UPCON6CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON6CLR) MASK Register */ 7158 7159 /* -------- USBC_UPCON7CLR : (USBC Offset: 0x63C) ( /W 32) Pipe Control Clear Register -------- */ 7160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7161 typedef union { 7162 struct { 7163 uint32_t RXINEC:1; /*!< bit: 0 RXINE Clear */ 7164 uint32_t TXOUTEC:1; /*!< bit: 1 TXOUTE Clear */ 7165 uint32_t TXSTPEC:1; /*!< bit: 2 TXSTPE Clear */ 7166 uint32_t PERREC:1; /*!< bit: 3 PERRE Clear */ 7167 uint32_t NAKEDEC:1; /*!< bit: 4 NAKEDE Clear */ 7168 uint32_t ERRORFIEC:1; /*!< bit: 5 ERRORFIE Clear */ 7169 uint32_t RXSTALLDEC:1; /*!< bit: 6 RXTALLDE Clear */ 7170 uint32_t :3; /*!< bit: 7.. 9 Reserved */ 7171 uint32_t RAMACEREC:1; /*!< bit: 10 RAMACERE Clear */ 7172 uint32_t :1; /*!< bit: 11 Reserved */ 7173 uint32_t NBUSYBKEC:1; /*!< bit: 12 NBUSYBKE Clear */ 7174 uint32_t :1; /*!< bit: 13 Reserved */ 7175 uint32_t FIFOCONC:1; /*!< bit: 14 FIFOCON Clear */ 7176 uint32_t :2; /*!< bit: 15..16 Reserved */ 7177 uint32_t PFREEZEC:1; /*!< bit: 17 PFREEZE Clear */ 7178 uint32_t INITDTGLC:1; /*!< bit: 18 INITDTGL Clear */ 7179 uint32_t INITBKC:1; /*!< bit: 19 INITBK Clear */ 7180 uint32_t :12; /*!< bit: 20..31 Reserved */ 7181 } bit; /*!< Structure used for bit access */ 7182 uint32_t reg; /*!< Type used for register access */ 7183 } USBC_UPCON7CLR_Type; 7184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7185 7186 #define USBC_UPCON7CLR_OFFSET 0x63C /**< \brief (USBC_UPCON7CLR offset) Pipe Control Clear Register */ 7187 #define USBC_UPCON7CLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UPCON7CLR reset_value) Pipe Control Clear Register */ 7188 7189 #define USBC_UPCON7CLR_RXINEC_Pos 0 /**< \brief (USBC_UPCON7CLR) RXINE Clear */ 7190 #define USBC_UPCON7CLR_RXINEC (_U_(0x1) << USBC_UPCON7CLR_RXINEC_Pos) 7191 #define USBC_UPCON7CLR_TXOUTEC_Pos 1 /**< \brief (USBC_UPCON7CLR) TXOUTE Clear */ 7192 #define USBC_UPCON7CLR_TXOUTEC (_U_(0x1) << USBC_UPCON7CLR_TXOUTEC_Pos) 7193 #define USBC_UPCON7CLR_TXSTPEC_Pos 2 /**< \brief (USBC_UPCON7CLR) TXSTPE Clear */ 7194 #define USBC_UPCON7CLR_TXSTPEC (_U_(0x1) << USBC_UPCON7CLR_TXSTPEC_Pos) 7195 #define USBC_UPCON7CLR_PERREC_Pos 3 /**< \brief (USBC_UPCON7CLR) PERRE Clear */ 7196 #define USBC_UPCON7CLR_PERREC (_U_(0x1) << USBC_UPCON7CLR_PERREC_Pos) 7197 #define USBC_UPCON7CLR_NAKEDEC_Pos 4 /**< \brief (USBC_UPCON7CLR) NAKEDE Clear */ 7198 #define USBC_UPCON7CLR_NAKEDEC (_U_(0x1) << USBC_UPCON7CLR_NAKEDEC_Pos) 7199 #define USBC_UPCON7CLR_ERRORFIEC_Pos 5 /**< \brief (USBC_UPCON7CLR) ERRORFIE Clear */ 7200 #define USBC_UPCON7CLR_ERRORFIEC (_U_(0x1) << USBC_UPCON7CLR_ERRORFIEC_Pos) 7201 #define USBC_UPCON7CLR_RXSTALLDEC_Pos 6 /**< \brief (USBC_UPCON7CLR) RXTALLDE Clear */ 7202 #define USBC_UPCON7CLR_RXSTALLDEC (_U_(0x1) << USBC_UPCON7CLR_RXSTALLDEC_Pos) 7203 #define USBC_UPCON7CLR_RAMACEREC_Pos 10 /**< \brief (USBC_UPCON7CLR) RAMACERE Clear */ 7204 #define USBC_UPCON7CLR_RAMACEREC (_U_(0x1) << USBC_UPCON7CLR_RAMACEREC_Pos) 7205 #define USBC_UPCON7CLR_NBUSYBKEC_Pos 12 /**< \brief (USBC_UPCON7CLR) NBUSYBKE Clear */ 7206 #define USBC_UPCON7CLR_NBUSYBKEC (_U_(0x1) << USBC_UPCON7CLR_NBUSYBKEC_Pos) 7207 #define USBC_UPCON7CLR_FIFOCONC_Pos 14 /**< \brief (USBC_UPCON7CLR) FIFOCON Clear */ 7208 #define USBC_UPCON7CLR_FIFOCONC (_U_(0x1) << USBC_UPCON7CLR_FIFOCONC_Pos) 7209 #define USBC_UPCON7CLR_PFREEZEC_Pos 17 /**< \brief (USBC_UPCON7CLR) PFREEZE Clear */ 7210 #define USBC_UPCON7CLR_PFREEZEC (_U_(0x1) << USBC_UPCON7CLR_PFREEZEC_Pos) 7211 #define USBC_UPCON7CLR_INITDTGLC_Pos 18 /**< \brief (USBC_UPCON7CLR) INITDTGL Clear */ 7212 #define USBC_UPCON7CLR_INITDTGLC (_U_(0x1) << USBC_UPCON7CLR_INITDTGLC_Pos) 7213 #define USBC_UPCON7CLR_INITBKC_Pos 19 /**< \brief (USBC_UPCON7CLR) INITBK Clear */ 7214 #define USBC_UPCON7CLR_INITBKC (_U_(0x1) << USBC_UPCON7CLR_INITBKC_Pos) 7215 #define USBC_UPCON7CLR_MASK _U_(0x000E547F) /**< \brief (USBC_UPCON7CLR) MASK Register */ 7216 7217 /* -------- USBC_UPINRQ0 : (USBC Offset: 0x650) (R/W 32) Pipe In Request -------- */ 7218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7219 typedef union { 7220 struct { 7221 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7222 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7223 uint32_t :23; /*!< bit: 9..31 Reserved */ 7224 } bit; /*!< Structure used for bit access */ 7225 uint32_t reg; /*!< Type used for register access */ 7226 } USBC_UPINRQ0_Type; 7227 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7228 7229 #define USBC_UPINRQ0_OFFSET 0x650 /**< \brief (USBC_UPINRQ0 offset) Pipe In Request */ 7230 #define USBC_UPINRQ0_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ0 reset_value) Pipe In Request */ 7231 7232 #define USBC_UPINRQ0_INRQ_Pos 0 /**< \brief (USBC_UPINRQ0) IN Request Number before Freeze */ 7233 #define USBC_UPINRQ0_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ0_INRQ_Pos) 7234 #define USBC_UPINRQ0_INRQ(value) (USBC_UPINRQ0_INRQ_Msk & ((value) << USBC_UPINRQ0_INRQ_Pos)) 7235 #define USBC_UPINRQ0_INMODE_Pos 8 /**< \brief (USBC_UPINRQ0) IN Request Mode */ 7236 #define USBC_UPINRQ0_INMODE (_U_(0x1) << USBC_UPINRQ0_INMODE_Pos) 7237 #define USBC_UPINRQ0_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ0) MASK Register */ 7238 7239 /* -------- USBC_UPINRQ1 : (USBC Offset: 0x654) (R/W 32) Pipe In Request -------- */ 7240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7241 typedef union { 7242 struct { 7243 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7244 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7245 uint32_t :23; /*!< bit: 9..31 Reserved */ 7246 } bit; /*!< Structure used for bit access */ 7247 uint32_t reg; /*!< Type used for register access */ 7248 } USBC_UPINRQ1_Type; 7249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7250 7251 #define USBC_UPINRQ1_OFFSET 0x654 /**< \brief (USBC_UPINRQ1 offset) Pipe In Request */ 7252 #define USBC_UPINRQ1_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ1 reset_value) Pipe In Request */ 7253 7254 #define USBC_UPINRQ1_INRQ_Pos 0 /**< \brief (USBC_UPINRQ1) IN Request Number before Freeze */ 7255 #define USBC_UPINRQ1_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ1_INRQ_Pos) 7256 #define USBC_UPINRQ1_INRQ(value) (USBC_UPINRQ1_INRQ_Msk & ((value) << USBC_UPINRQ1_INRQ_Pos)) 7257 #define USBC_UPINRQ1_INMODE_Pos 8 /**< \brief (USBC_UPINRQ1) IN Request Mode */ 7258 #define USBC_UPINRQ1_INMODE (_U_(0x1) << USBC_UPINRQ1_INMODE_Pos) 7259 #define USBC_UPINRQ1_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ1) MASK Register */ 7260 7261 /* -------- USBC_UPINRQ2 : (USBC Offset: 0x658) (R/W 32) Pipe In Request -------- */ 7262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7263 typedef union { 7264 struct { 7265 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7266 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7267 uint32_t :23; /*!< bit: 9..31 Reserved */ 7268 } bit; /*!< Structure used for bit access */ 7269 uint32_t reg; /*!< Type used for register access */ 7270 } USBC_UPINRQ2_Type; 7271 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7272 7273 #define USBC_UPINRQ2_OFFSET 0x658 /**< \brief (USBC_UPINRQ2 offset) Pipe In Request */ 7274 #define USBC_UPINRQ2_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ2 reset_value) Pipe In Request */ 7275 7276 #define USBC_UPINRQ2_INRQ_Pos 0 /**< \brief (USBC_UPINRQ2) IN Request Number before Freeze */ 7277 #define USBC_UPINRQ2_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ2_INRQ_Pos) 7278 #define USBC_UPINRQ2_INRQ(value) (USBC_UPINRQ2_INRQ_Msk & ((value) << USBC_UPINRQ2_INRQ_Pos)) 7279 #define USBC_UPINRQ2_INMODE_Pos 8 /**< \brief (USBC_UPINRQ2) IN Request Mode */ 7280 #define USBC_UPINRQ2_INMODE (_U_(0x1) << USBC_UPINRQ2_INMODE_Pos) 7281 #define USBC_UPINRQ2_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ2) MASK Register */ 7282 7283 /* -------- USBC_UPINRQ3 : (USBC Offset: 0x65C) (R/W 32) Pipe In Request -------- */ 7284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7285 typedef union { 7286 struct { 7287 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7288 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7289 uint32_t :23; /*!< bit: 9..31 Reserved */ 7290 } bit; /*!< Structure used for bit access */ 7291 uint32_t reg; /*!< Type used for register access */ 7292 } USBC_UPINRQ3_Type; 7293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7294 7295 #define USBC_UPINRQ3_OFFSET 0x65C /**< \brief (USBC_UPINRQ3 offset) Pipe In Request */ 7296 #define USBC_UPINRQ3_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ3 reset_value) Pipe In Request */ 7297 7298 #define USBC_UPINRQ3_INRQ_Pos 0 /**< \brief (USBC_UPINRQ3) IN Request Number before Freeze */ 7299 #define USBC_UPINRQ3_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ3_INRQ_Pos) 7300 #define USBC_UPINRQ3_INRQ(value) (USBC_UPINRQ3_INRQ_Msk & ((value) << USBC_UPINRQ3_INRQ_Pos)) 7301 #define USBC_UPINRQ3_INMODE_Pos 8 /**< \brief (USBC_UPINRQ3) IN Request Mode */ 7302 #define USBC_UPINRQ3_INMODE (_U_(0x1) << USBC_UPINRQ3_INMODE_Pos) 7303 #define USBC_UPINRQ3_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ3) MASK Register */ 7304 7305 /* -------- USBC_UPINRQ4 : (USBC Offset: 0x660) (R/W 32) Pipe In Request -------- */ 7306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7307 typedef union { 7308 struct { 7309 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7310 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7311 uint32_t :23; /*!< bit: 9..31 Reserved */ 7312 } bit; /*!< Structure used for bit access */ 7313 uint32_t reg; /*!< Type used for register access */ 7314 } USBC_UPINRQ4_Type; 7315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7316 7317 #define USBC_UPINRQ4_OFFSET 0x660 /**< \brief (USBC_UPINRQ4 offset) Pipe In Request */ 7318 #define USBC_UPINRQ4_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ4 reset_value) Pipe In Request */ 7319 7320 #define USBC_UPINRQ4_INRQ_Pos 0 /**< \brief (USBC_UPINRQ4) IN Request Number before Freeze */ 7321 #define USBC_UPINRQ4_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ4_INRQ_Pos) 7322 #define USBC_UPINRQ4_INRQ(value) (USBC_UPINRQ4_INRQ_Msk & ((value) << USBC_UPINRQ4_INRQ_Pos)) 7323 #define USBC_UPINRQ4_INMODE_Pos 8 /**< \brief (USBC_UPINRQ4) IN Request Mode */ 7324 #define USBC_UPINRQ4_INMODE (_U_(0x1) << USBC_UPINRQ4_INMODE_Pos) 7325 #define USBC_UPINRQ4_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ4) MASK Register */ 7326 7327 /* -------- USBC_UPINRQ5 : (USBC Offset: 0x664) (R/W 32) Pipe In Request -------- */ 7328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7329 typedef union { 7330 struct { 7331 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7332 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7333 uint32_t :23; /*!< bit: 9..31 Reserved */ 7334 } bit; /*!< Structure used for bit access */ 7335 uint32_t reg; /*!< Type used for register access */ 7336 } USBC_UPINRQ5_Type; 7337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7338 7339 #define USBC_UPINRQ5_OFFSET 0x664 /**< \brief (USBC_UPINRQ5 offset) Pipe In Request */ 7340 #define USBC_UPINRQ5_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ5 reset_value) Pipe In Request */ 7341 7342 #define USBC_UPINRQ5_INRQ_Pos 0 /**< \brief (USBC_UPINRQ5) IN Request Number before Freeze */ 7343 #define USBC_UPINRQ5_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ5_INRQ_Pos) 7344 #define USBC_UPINRQ5_INRQ(value) (USBC_UPINRQ5_INRQ_Msk & ((value) << USBC_UPINRQ5_INRQ_Pos)) 7345 #define USBC_UPINRQ5_INMODE_Pos 8 /**< \brief (USBC_UPINRQ5) IN Request Mode */ 7346 #define USBC_UPINRQ5_INMODE (_U_(0x1) << USBC_UPINRQ5_INMODE_Pos) 7347 #define USBC_UPINRQ5_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ5) MASK Register */ 7348 7349 /* -------- USBC_UPINRQ6 : (USBC Offset: 0x668) (R/W 32) Pipe In Request -------- */ 7350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7351 typedef union { 7352 struct { 7353 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7354 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7355 uint32_t :23; /*!< bit: 9..31 Reserved */ 7356 } bit; /*!< Structure used for bit access */ 7357 uint32_t reg; /*!< Type used for register access */ 7358 } USBC_UPINRQ6_Type; 7359 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7360 7361 #define USBC_UPINRQ6_OFFSET 0x668 /**< \brief (USBC_UPINRQ6 offset) Pipe In Request */ 7362 #define USBC_UPINRQ6_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ6 reset_value) Pipe In Request */ 7363 7364 #define USBC_UPINRQ6_INRQ_Pos 0 /**< \brief (USBC_UPINRQ6) IN Request Number before Freeze */ 7365 #define USBC_UPINRQ6_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ6_INRQ_Pos) 7366 #define USBC_UPINRQ6_INRQ(value) (USBC_UPINRQ6_INRQ_Msk & ((value) << USBC_UPINRQ6_INRQ_Pos)) 7367 #define USBC_UPINRQ6_INMODE_Pos 8 /**< \brief (USBC_UPINRQ6) IN Request Mode */ 7368 #define USBC_UPINRQ6_INMODE (_U_(0x1) << USBC_UPINRQ6_INMODE_Pos) 7369 #define USBC_UPINRQ6_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ6) MASK Register */ 7370 7371 /* -------- USBC_UPINRQ7 : (USBC Offset: 0x66C) (R/W 32) Pipe In Request -------- */ 7372 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7373 typedef union { 7374 struct { 7375 uint32_t INRQ:8; /*!< bit: 0.. 7 IN Request Number before Freeze */ 7376 uint32_t INMODE:1; /*!< bit: 8 IN Request Mode */ 7377 uint32_t :23; /*!< bit: 9..31 Reserved */ 7378 } bit; /*!< Structure used for bit access */ 7379 uint32_t reg; /*!< Type used for register access */ 7380 } USBC_UPINRQ7_Type; 7381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7382 7383 #define USBC_UPINRQ7_OFFSET 0x66C /**< \brief (USBC_UPINRQ7 offset) Pipe In Request */ 7384 #define USBC_UPINRQ7_RESETVALUE _U_(0x00000001); /**< \brief (USBC_UPINRQ7 reset_value) Pipe In Request */ 7385 7386 #define USBC_UPINRQ7_INRQ_Pos 0 /**< \brief (USBC_UPINRQ7) IN Request Number before Freeze */ 7387 #define USBC_UPINRQ7_INRQ_Msk (_U_(0xFF) << USBC_UPINRQ7_INRQ_Pos) 7388 #define USBC_UPINRQ7_INRQ(value) (USBC_UPINRQ7_INRQ_Msk & ((value) << USBC_UPINRQ7_INRQ_Pos)) 7389 #define USBC_UPINRQ7_INMODE_Pos 8 /**< \brief (USBC_UPINRQ7) IN Request Mode */ 7390 #define USBC_UPINRQ7_INMODE (_U_(0x1) << USBC_UPINRQ7_INMODE_Pos) 7391 #define USBC_UPINRQ7_MASK _U_(0x000001FF) /**< \brief (USBC_UPINRQ7) MASK Register */ 7392 7393 /* -------- USBC_USBCON : (USBC Offset: 0x800) (R/W 32) General Control Register -------- */ 7394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7395 typedef union { 7396 struct { 7397 uint32_t :14; /*!< bit: 0..13 Reserved */ 7398 uint32_t FRZCLK:1; /*!< bit: 14 Freeze USB Clock */ 7399 uint32_t USBE:1; /*!< bit: 15 USBC Enable */ 7400 uint32_t :8; /*!< bit: 16..23 Reserved */ 7401 uint32_t UIMOD:1; /*!< bit: 24 USBC Mode */ 7402 uint32_t :7; /*!< bit: 25..31 Reserved */ 7403 } bit; /*!< Structure used for bit access */ 7404 uint32_t reg; /*!< Type used for register access */ 7405 } USBC_USBCON_Type; 7406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7407 7408 #define USBC_USBCON_OFFSET 0x800 /**< \brief (USBC_USBCON offset) General Control Register */ 7409 #define USBC_USBCON_RESETVALUE _U_(0x01004000); /**< \brief (USBC_USBCON reset_value) General Control Register */ 7410 7411 #define USBC_USBCON_FRZCLK_Pos 14 /**< \brief (USBC_USBCON) Freeze USB Clock */ 7412 #define USBC_USBCON_FRZCLK (_U_(0x1) << USBC_USBCON_FRZCLK_Pos) 7413 #define USBC_USBCON_USBE_Pos 15 /**< \brief (USBC_USBCON) USBC Enable */ 7414 #define USBC_USBCON_USBE (_U_(0x1) << USBC_USBCON_USBE_Pos) 7415 #define USBC_USBCON_UIMOD_Pos 24 /**< \brief (USBC_USBCON) USBC Mode */ 7416 #define USBC_USBCON_UIMOD (_U_(0x1) << USBC_USBCON_UIMOD_Pos) 7417 #define USBC_USBCON_MASK _U_(0x0100C000) /**< \brief (USBC_USBCON) MASK Register */ 7418 7419 /* -------- USBC_USBSTA : (USBC Offset: 0x804) (R/ 32) General Status Register -------- */ 7420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7421 typedef union { 7422 struct { 7423 uint32_t :9; /*!< bit: 0.. 8 Reserved */ 7424 uint32_t VBUSRQ:1; /*!< bit: 9 VBus Request */ 7425 uint32_t :2; /*!< bit: 10..11 Reserved */ 7426 uint32_t SPEED:2; /*!< bit: 12..13 Speed Status */ 7427 uint32_t CLKUSABLE:1; /*!< bit: 14 USB Clock Usable */ 7428 uint32_t :1; /*!< bit: 15 Reserved */ 7429 uint32_t SUSPEND:1; /*!< bit: 16 Suspend module state */ 7430 uint32_t :15; /*!< bit: 17..31 Reserved */ 7431 } bit; /*!< Structure used for bit access */ 7432 uint32_t reg; /*!< Type used for register access */ 7433 } USBC_USBSTA_Type; 7434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7435 7436 #define USBC_USBSTA_OFFSET 0x804 /**< \brief (USBC_USBSTA offset) General Status Register */ 7437 #define USBC_USBSTA_RESETVALUE _U_(0x00010000); /**< \brief (USBC_USBSTA reset_value) General Status Register */ 7438 7439 #define USBC_USBSTA_VBUSRQ_Pos 9 /**< \brief (USBC_USBSTA) VBus Request */ 7440 #define USBC_USBSTA_VBUSRQ (_U_(0x1) << USBC_USBSTA_VBUSRQ_Pos) 7441 #define USBC_USBSTA_SPEED_Pos 12 /**< \brief (USBC_USBSTA) Speed Status */ 7442 #define USBC_USBSTA_SPEED_Msk (_U_(0x3) << USBC_USBSTA_SPEED_Pos) 7443 #define USBC_USBSTA_SPEED(value) (USBC_USBSTA_SPEED_Msk & ((value) << USBC_USBSTA_SPEED_Pos)) 7444 #define USBC_USBSTA_SPEED_FULL_Val _U_(0x0) /**< \brief (USBC_USBSTA) */ 7445 #define USBC_USBSTA_SPEED_HIGH_Val _U_(0x1) /**< \brief (USBC_USBSTA) */ 7446 #define USBC_USBSTA_SPEED_LOW_Val _U_(0x2) /**< \brief (USBC_USBSTA) */ 7447 #define USBC_USBSTA_SPEED_FULL (USBC_USBSTA_SPEED_FULL_Val << USBC_USBSTA_SPEED_Pos) 7448 #define USBC_USBSTA_SPEED_HIGH (USBC_USBSTA_SPEED_HIGH_Val << USBC_USBSTA_SPEED_Pos) 7449 #define USBC_USBSTA_SPEED_LOW (USBC_USBSTA_SPEED_LOW_Val << USBC_USBSTA_SPEED_Pos) 7450 #define USBC_USBSTA_CLKUSABLE_Pos 14 /**< \brief (USBC_USBSTA) USB Clock Usable */ 7451 #define USBC_USBSTA_CLKUSABLE (_U_(0x1) << USBC_USBSTA_CLKUSABLE_Pos) 7452 #define USBC_USBSTA_SUSPEND_Pos 16 /**< \brief (USBC_USBSTA) Suspend module state */ 7453 #define USBC_USBSTA_SUSPEND (_U_(0x1) << USBC_USBSTA_SUSPEND_Pos) 7454 #define USBC_USBSTA_MASK _U_(0x00017200) /**< \brief (USBC_USBSTA) MASK Register */ 7455 7456 /* -------- USBC_USBSTACLR : (USBC Offset: 0x808) ( /W 32) General Status Clear Register -------- */ 7457 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7458 typedef union { 7459 struct { 7460 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 7461 uint32_t RAMACERIC:1; /*!< bit: 8 RAMACERI Clear */ 7462 uint32_t VBUSRQC:1; /*!< bit: 9 VBUSRQ Clear */ 7463 uint32_t :22; /*!< bit: 10..31 Reserved */ 7464 } bit; /*!< Structure used for bit access */ 7465 uint32_t reg; /*!< Type used for register access */ 7466 } USBC_USBSTACLR_Type; 7467 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7468 7469 #define USBC_USBSTACLR_OFFSET 0x808 /**< \brief (USBC_USBSTACLR offset) General Status Clear Register */ 7470 #define USBC_USBSTACLR_RESETVALUE _U_(0x00000000); /**< \brief (USBC_USBSTACLR reset_value) General Status Clear Register */ 7471 7472 #define USBC_USBSTACLR_RAMACERIC_Pos 8 /**< \brief (USBC_USBSTACLR) RAMACERI Clear */ 7473 #define USBC_USBSTACLR_RAMACERIC (_U_(0x1) << USBC_USBSTACLR_RAMACERIC_Pos) 7474 #define USBC_USBSTACLR_VBUSRQC_Pos 9 /**< \brief (USBC_USBSTACLR) VBUSRQ Clear */ 7475 #define USBC_USBSTACLR_VBUSRQC (_U_(0x1) << USBC_USBSTACLR_VBUSRQC_Pos) 7476 #define USBC_USBSTACLR_MASK _U_(0x00000300) /**< \brief (USBC_USBSTACLR) MASK Register */ 7477 7478 /* -------- USBC_USBSTASET : (USBC Offset: 0x80C) ( /W 32) General Status Set Register -------- */ 7479 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7480 typedef union { 7481 struct { 7482 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 7483 uint32_t RAMACERIS:1; /*!< bit: 8 RAMACERI Set */ 7484 uint32_t VBUSRQS:1; /*!< bit: 9 VBUSRQ Set */ 7485 uint32_t :22; /*!< bit: 10..31 Reserved */ 7486 } bit; /*!< Structure used for bit access */ 7487 uint32_t reg; /*!< Type used for register access */ 7488 } USBC_USBSTASET_Type; 7489 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7490 7491 #define USBC_USBSTASET_OFFSET 0x80C /**< \brief (USBC_USBSTASET offset) General Status Set Register */ 7492 #define USBC_USBSTASET_RESETVALUE _U_(0x00000000); /**< \brief (USBC_USBSTASET reset_value) General Status Set Register */ 7493 7494 #define USBC_USBSTASET_RAMACERIS_Pos 8 /**< \brief (USBC_USBSTASET) RAMACERI Set */ 7495 #define USBC_USBSTASET_RAMACERIS (_U_(0x1) << USBC_USBSTASET_RAMACERIS_Pos) 7496 #define USBC_USBSTASET_VBUSRQS_Pos 9 /**< \brief (USBC_USBSTASET) VBUSRQ Set */ 7497 #define USBC_USBSTASET_VBUSRQS (_U_(0x1) << USBC_USBSTASET_VBUSRQS_Pos) 7498 #define USBC_USBSTASET_MASK _U_(0x00000300) /**< \brief (USBC_USBSTASET) MASK Register */ 7499 7500 /* -------- USBC_UVERS : (USBC Offset: 0x818) (R/ 32) IP Version Register -------- */ 7501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7502 typedef union { 7503 struct { 7504 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 7505 uint32_t :4; /*!< bit: 12..15 Reserved */ 7506 uint32_t VARIANT:3; /*!< bit: 16..18 Variant Number */ 7507 uint32_t :13; /*!< bit: 19..31 Reserved */ 7508 } bit; /*!< Structure used for bit access */ 7509 uint32_t reg; /*!< Type used for register access */ 7510 } USBC_UVERS_Type; 7511 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7512 7513 #define USBC_UVERS_OFFSET 0x818 /**< \brief (USBC_UVERS offset) IP Version Register */ 7514 #define USBC_UVERS_RESETVALUE _U_(0x00000310); /**< \brief (USBC_UVERS reset_value) IP Version Register */ 7515 7516 #define USBC_UVERS_VERSION_Pos 0 /**< \brief (USBC_UVERS) Version Number */ 7517 #define USBC_UVERS_VERSION_Msk (_U_(0xFFF) << USBC_UVERS_VERSION_Pos) 7518 #define USBC_UVERS_VERSION(value) (USBC_UVERS_VERSION_Msk & ((value) << USBC_UVERS_VERSION_Pos)) 7519 #define USBC_UVERS_VARIANT_Pos 16 /**< \brief (USBC_UVERS) Variant Number */ 7520 #define USBC_UVERS_VARIANT_Msk (_U_(0x7) << USBC_UVERS_VARIANT_Pos) 7521 #define USBC_UVERS_VARIANT(value) (USBC_UVERS_VARIANT_Msk & ((value) << USBC_UVERS_VARIANT_Pos)) 7522 #define USBC_UVERS_MASK _U_(0x00070FFF) /**< \brief (USBC_UVERS) MASK Register */ 7523 7524 /* -------- USBC_UFEATURES : (USBC Offset: 0x81C) (R/ 32) IP Features Register -------- */ 7525 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7526 typedef union { 7527 struct { 7528 uint32_t EPTNBRMAX:4; /*!< bit: 0.. 3 Maximum Number of Pipes/Endpints */ 7529 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 7530 uint32_t UTMIMODE:1; /*!< bit: 8 UTMI Mode */ 7531 uint32_t :23; /*!< bit: 9..31 Reserved */ 7532 } bit; /*!< Structure used for bit access */ 7533 uint32_t reg; /*!< Type used for register access */ 7534 } USBC_UFEATURES_Type; 7535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7536 7537 #define USBC_UFEATURES_OFFSET 0x81C /**< \brief (USBC_UFEATURES offset) IP Features Register */ 7538 #define USBC_UFEATURES_RESETVALUE _U_(0x00000007); /**< \brief (USBC_UFEATURES reset_value) IP Features Register */ 7539 7540 #define USBC_UFEATURES_EPTNBRMAX_Pos 0 /**< \brief (USBC_UFEATURES) Maximum Number of Pipes/Endpints */ 7541 #define USBC_UFEATURES_EPTNBRMAX_Msk (_U_(0xF) << USBC_UFEATURES_EPTNBRMAX_Pos) 7542 #define USBC_UFEATURES_EPTNBRMAX(value) (USBC_UFEATURES_EPTNBRMAX_Msk & ((value) << USBC_UFEATURES_EPTNBRMAX_Pos)) 7543 #define USBC_UFEATURES_UTMIMODE_Pos 8 /**< \brief (USBC_UFEATURES) UTMI Mode */ 7544 #define USBC_UFEATURES_UTMIMODE (_U_(0x1) << USBC_UFEATURES_UTMIMODE_Pos) 7545 #define USBC_UFEATURES_MASK _U_(0x0000010F) /**< \brief (USBC_UFEATURES) MASK Register */ 7546 7547 /* -------- USBC_UADDRSIZE : (USBC Offset: 0x820) (R/ 32) IP PB address size Register -------- */ 7548 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7549 typedef union { 7550 struct { 7551 uint32_t UADDRSIZE:32; /*!< bit: 0..31 IP PB Address Size */ 7552 } bit; /*!< Structure used for bit access */ 7553 uint32_t reg; /*!< Type used for register access */ 7554 } USBC_UADDRSIZE_Type; 7555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7556 7557 #define USBC_UADDRSIZE_OFFSET 0x820 /**< \brief (USBC_UADDRSIZE offset) IP PB address size Register */ 7558 #define USBC_UADDRSIZE_RESETVALUE _U_(0x00001000); /**< \brief (USBC_UADDRSIZE reset_value) IP PB address size Register */ 7559 7560 #define USBC_UADDRSIZE_UADDRSIZE_Pos 0 /**< \brief (USBC_UADDRSIZE) IP PB Address Size */ 7561 #define USBC_UADDRSIZE_UADDRSIZE_Msk (_U_(0xFFFFFFFF) << USBC_UADDRSIZE_UADDRSIZE_Pos) 7562 #define USBC_UADDRSIZE_UADDRSIZE(value) (USBC_UADDRSIZE_UADDRSIZE_Msk & ((value) << USBC_UADDRSIZE_UADDRSIZE_Pos)) 7563 #define USBC_UADDRSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USBC_UADDRSIZE) MASK Register */ 7564 7565 /* -------- USBC_UNAME1 : (USBC Offset: 0x824) (R/ 32) IP Name Part One: HUSB -------- */ 7566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7567 typedef union { 7568 struct { 7569 uint32_t UNAME1:32; /*!< bit: 0..31 IP Name Part One */ 7570 } bit; /*!< Structure used for bit access */ 7571 uint32_t reg; /*!< Type used for register access */ 7572 } USBC_UNAME1_Type; 7573 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7574 7575 #define USBC_UNAME1_OFFSET 0x824 /**< \brief (USBC_UNAME1 offset) IP Name Part One: HUSB */ 7576 #define USBC_UNAME1_RESETVALUE _U_(0x48555342); /**< \brief (USBC_UNAME1 reset_value) IP Name Part One: HUSB */ 7577 7578 #define USBC_UNAME1_UNAME1_Pos 0 /**< \brief (USBC_UNAME1) IP Name Part One */ 7579 #define USBC_UNAME1_UNAME1_Msk (_U_(0xFFFFFFFF) << USBC_UNAME1_UNAME1_Pos) 7580 #define USBC_UNAME1_UNAME1(value) (USBC_UNAME1_UNAME1_Msk & ((value) << USBC_UNAME1_UNAME1_Pos)) 7581 #define USBC_UNAME1_MASK _U_(0xFFFFFFFF) /**< \brief (USBC_UNAME1) MASK Register */ 7582 7583 /* -------- USBC_UNAME2 : (USBC Offset: 0x828) (R/ 32) IP Name Part Two: HOST -------- */ 7584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7585 typedef union { 7586 struct { 7587 uint32_t UNAME2:32; /*!< bit: 0..31 IP Name Part Two */ 7588 } bit; /*!< Structure used for bit access */ 7589 uint32_t reg; /*!< Type used for register access */ 7590 } USBC_UNAME2_Type; 7591 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7592 7593 #define USBC_UNAME2_OFFSET 0x828 /**< \brief (USBC_UNAME2 offset) IP Name Part Two: HOST */ 7594 #define USBC_UNAME2_RESETVALUE _U_(0x484F5354); /**< \brief (USBC_UNAME2 reset_value) IP Name Part Two: HOST */ 7595 7596 #define USBC_UNAME2_UNAME2_Pos 0 /**< \brief (USBC_UNAME2) IP Name Part Two */ 7597 #define USBC_UNAME2_UNAME2_Msk (_U_(0xFFFFFFFF) << USBC_UNAME2_UNAME2_Pos) 7598 #define USBC_UNAME2_UNAME2(value) (USBC_UNAME2_UNAME2_Msk & ((value) << USBC_UNAME2_UNAME2_Pos)) 7599 #define USBC_UNAME2_MASK _U_(0xFFFFFFFF) /**< \brief (USBC_UNAME2) MASK Register */ 7600 7601 /* -------- USBC_USBFSM : (USBC Offset: 0x82C) (R/ 32) USB internal finite state machine -------- */ 7602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7603 typedef union { 7604 struct { 7605 uint32_t DRDSTATE:4; /*!< bit: 0.. 3 DualRoleDevice state */ 7606 uint32_t :28; /*!< bit: 4..31 Reserved */ 7607 } bit; /*!< Structure used for bit access */ 7608 uint32_t reg; /*!< Type used for register access */ 7609 } USBC_USBFSM_Type; 7610 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7611 7612 #define USBC_USBFSM_OFFSET 0x82C /**< \brief (USBC_USBFSM offset) USB internal finite state machine */ 7613 #define USBC_USBFSM_RESETVALUE _U_(0x00000009); /**< \brief (USBC_USBFSM reset_value) USB internal finite state machine */ 7614 7615 #define USBC_USBFSM_DRDSTATE_Pos 0 /**< \brief (USBC_USBFSM) DualRoleDevice state */ 7616 #define USBC_USBFSM_DRDSTATE_Msk (_U_(0xF) << USBC_USBFSM_DRDSTATE_Pos) 7617 #define USBC_USBFSM_DRDSTATE(value) (USBC_USBFSM_DRDSTATE_Msk & ((value) << USBC_USBFSM_DRDSTATE_Pos)) 7618 #define USBC_USBFSM_DRDSTATE_A_IDLE_Val _U_(0x0) /**< \brief (USBC_USBFSM) */ 7619 #define USBC_USBFSM_DRDSTATE_A_WAIT_VRISE_Val _U_(0x1) /**< \brief (USBC_USBFSM) */ 7620 #define USBC_USBFSM_DRDSTATE_A_WAIT_BCON_Val _U_(0x2) /**< \brief (USBC_USBFSM) */ 7621 #define USBC_USBFSM_DRDSTATE_A_HOST_Val _U_(0x3) /**< \brief (USBC_USBFSM) */ 7622 #define USBC_USBFSM_DRDSTATE_A_SUSPEND_Val _U_(0x4) /**< \brief (USBC_USBFSM) */ 7623 #define USBC_USBFSM_DRDSTATE_A_PERIPHERAL_Val _U_(0x5) /**< \brief (USBC_USBFSM) */ 7624 #define USBC_USBFSM_DRDSTATE_A_WAIT_VFALL_Val _U_(0x6) /**< \brief (USBC_USBFSM) */ 7625 #define USBC_USBFSM_DRDSTATE_A_VBUS_ERR_Val _U_(0x7) /**< \brief (USBC_USBFSM) */ 7626 #define USBC_USBFSM_DRDSTATE_A_WAIT_DISCHARGE_Val _U_(0x8) /**< \brief (USBC_USBFSM) */ 7627 #define USBC_USBFSM_DRDSTATE_B_IDLE_Val _U_(0x9) /**< \brief (USBC_USBFSM) */ 7628 #define USBC_USBFSM_DRDSTATE_B_PERIPHERAL_Val _U_(0xA) /**< \brief (USBC_USBFSM) */ 7629 #define USBC_USBFSM_DRDSTATE_B_WAIT_BEGIN_HNP_Val _U_(0xB) /**< \brief (USBC_USBFSM) */ 7630 #define USBC_USBFSM_DRDSTATE_B_WAIT_DISCHARGE_Val _U_(0xC) /**< \brief (USBC_USBFSM) */ 7631 #define USBC_USBFSM_DRDSTATE_B_WAIT_ACON_Val _U_(0xD) /**< \brief (USBC_USBFSM) */ 7632 #define USBC_USBFSM_DRDSTATE_B_HOST_Val _U_(0xE) /**< \brief (USBC_USBFSM) */ 7633 #define USBC_USBFSM_DRDSTATE_B_SRP_INIT_Val _U_(0xF) /**< \brief (USBC_USBFSM) */ 7634 #define USBC_USBFSM_DRDSTATE_A_IDLE (USBC_USBFSM_DRDSTATE_A_IDLE_Val << USBC_USBFSM_DRDSTATE_Pos) 7635 #define USBC_USBFSM_DRDSTATE_A_WAIT_VRISE (USBC_USBFSM_DRDSTATE_A_WAIT_VRISE_Val << USBC_USBFSM_DRDSTATE_Pos) 7636 #define USBC_USBFSM_DRDSTATE_A_WAIT_BCON (USBC_USBFSM_DRDSTATE_A_WAIT_BCON_Val << USBC_USBFSM_DRDSTATE_Pos) 7637 #define USBC_USBFSM_DRDSTATE_A_HOST (USBC_USBFSM_DRDSTATE_A_HOST_Val << USBC_USBFSM_DRDSTATE_Pos) 7638 #define USBC_USBFSM_DRDSTATE_A_SUSPEND (USBC_USBFSM_DRDSTATE_A_SUSPEND_Val << USBC_USBFSM_DRDSTATE_Pos) 7639 #define USBC_USBFSM_DRDSTATE_A_PERIPHERAL (USBC_USBFSM_DRDSTATE_A_PERIPHERAL_Val << USBC_USBFSM_DRDSTATE_Pos) 7640 #define USBC_USBFSM_DRDSTATE_A_WAIT_VFALL (USBC_USBFSM_DRDSTATE_A_WAIT_VFALL_Val << USBC_USBFSM_DRDSTATE_Pos) 7641 #define USBC_USBFSM_DRDSTATE_A_VBUS_ERR (USBC_USBFSM_DRDSTATE_A_VBUS_ERR_Val << USBC_USBFSM_DRDSTATE_Pos) 7642 #define USBC_USBFSM_DRDSTATE_A_WAIT_DISCHARGE (USBC_USBFSM_DRDSTATE_A_WAIT_DISCHARGE_Val << USBC_USBFSM_DRDSTATE_Pos) 7643 #define USBC_USBFSM_DRDSTATE_B_IDLE (USBC_USBFSM_DRDSTATE_B_IDLE_Val << USBC_USBFSM_DRDSTATE_Pos) 7644 #define USBC_USBFSM_DRDSTATE_B_PERIPHERAL (USBC_USBFSM_DRDSTATE_B_PERIPHERAL_Val << USBC_USBFSM_DRDSTATE_Pos) 7645 #define USBC_USBFSM_DRDSTATE_B_WAIT_BEGIN_HNP (USBC_USBFSM_DRDSTATE_B_WAIT_BEGIN_HNP_Val << USBC_USBFSM_DRDSTATE_Pos) 7646 #define USBC_USBFSM_DRDSTATE_B_WAIT_DISCHARGE (USBC_USBFSM_DRDSTATE_B_WAIT_DISCHARGE_Val << USBC_USBFSM_DRDSTATE_Pos) 7647 #define USBC_USBFSM_DRDSTATE_B_WAIT_ACON (USBC_USBFSM_DRDSTATE_B_WAIT_ACON_Val << USBC_USBFSM_DRDSTATE_Pos) 7648 #define USBC_USBFSM_DRDSTATE_B_HOST (USBC_USBFSM_DRDSTATE_B_HOST_Val << USBC_USBFSM_DRDSTATE_Pos) 7649 #define USBC_USBFSM_DRDSTATE_B_SRP_INIT (USBC_USBFSM_DRDSTATE_B_SRP_INIT_Val << USBC_USBFSM_DRDSTATE_Pos) 7650 #define USBC_USBFSM_MASK _U_(0x0000000F) /**< \brief (USBC_USBFSM) MASK Register */ 7651 7652 /* -------- USBC_UDESC : (USBC Offset: 0x830) (R/W 32) Endpoint descriptor table -------- */ 7653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7654 typedef union { 7655 struct { 7656 uint32_t UDESCA:32; /*!< bit: 0..31 USB Descriptor Address */ 7657 } bit; /*!< Structure used for bit access */ 7658 uint32_t reg; /*!< Type used for register access */ 7659 } USBC_UDESC_Type; 7660 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7661 7662 #define USBC_UDESC_OFFSET 0x830 /**< \brief (USBC_UDESC offset) Endpoint descriptor table */ 7663 #define USBC_UDESC_RESETVALUE _U_(0x00000000); /**< \brief (USBC_UDESC reset_value) Endpoint descriptor table */ 7664 7665 #define USBC_UDESC_UDESCA_Pos 0 /**< \brief (USBC_UDESC) USB Descriptor Address */ 7666 #define USBC_UDESC_UDESCA_Msk (_U_(0xFFFFFFFF) << USBC_UDESC_UDESCA_Pos) 7667 #define USBC_UDESC_UDESCA(value) (USBC_UDESC_UDESCA_Msk & ((value) << USBC_UDESC_UDESCA_Pos)) 7668 #define USBC_UDESC_MASK _U_(0xFFFFFFFF) /**< \brief (USBC_UDESC) MASK Register */ 7669 7670 /** \brief USBC hardware registers */ 7671 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 7672 typedef struct { 7673 __IO uint32_t UDCON; /**< \brief Offset: 0x000 (R/W 32) Device General Control Register */ 7674 __I uint32_t UDINT; /**< \brief Offset: 0x004 (R/ 32) Device Global Interupt Register */ 7675 __O uint32_t UDINTCLR; /**< \brief Offset: 0x008 ( /W 32) Device Global Interrupt Clear Register */ 7676 __O uint32_t UDINTSET; /**< \brief Offset: 0x00C ( /W 32) Device Global Interrupt Set Regsiter */ 7677 __I uint32_t UDINTE; /**< \brief Offset: 0x010 (R/ 32) Device Global Interrupt Enable Register */ 7678 __O uint32_t UDINTECLR; /**< \brief Offset: 0x014 ( /W 32) Device Global Interrupt Enable Clear Register */ 7679 __O uint32_t UDINTESET; /**< \brief Offset: 0x018 ( /W 32) Device Global Interrupt Enable Set Register */ 7680 __IO uint32_t UERST; /**< \brief Offset: 0x01C (R/W 32) Endpoint Enable/Reset Register */ 7681 __I uint32_t UDFNUM; /**< \brief Offset: 0x020 (R/ 32) Device Frame Number Register */ 7682 RoReg8 Reserved1[0xDC]; 7683 __IO uint32_t UECFG[8]; /**< \brief Offset: 0x100 (R/W 32) Endpoint Configuration Register */ 7684 RoReg8 Reserved2[0x10]; 7685 __I uint32_t UESTA[8]; /**< \brief Offset: 0x130 (R/ 32) Endpoint Status Register */ 7686 RoReg8 Reserved3[0x10]; 7687 __O uint32_t UESTACLR[8]; /**< \brief Offset: 0x160 ( /W 32) Endpoint Status Clear Register */ 7688 RoReg8 Reserved4[0x10]; 7689 __O uint32_t UESTASET[8]; /**< \brief Offset: 0x190 ( /W 32) Endpoint Status Set Register */ 7690 RoReg8 Reserved5[0x10]; 7691 __I uint32_t UECON[8]; /**< \brief Offset: 0x1C0 (R/ 32) Endpoint Control Register */ 7692 RoReg8 Reserved6[0x10]; 7693 __O uint32_t UECONSET[8]; /**< \brief Offset: 0x1F0 ( /W 32) Endpoint Control Set Register */ 7694 RoReg8 Reserved7[0x10]; 7695 __O uint32_t UECONCLR[8]; /**< \brief Offset: 0x220 ( /W 32) Endpoint Control Clear Register */ 7696 RoReg8 Reserved8[0x1C0]; 7697 __IO uint32_t UHCON; /**< \brief Offset: 0x400 (R/W 32) Host General Control Register */ 7698 __I uint32_t UHINT; /**< \brief Offset: 0x404 (R/ 32) Host Global Interrupt Register */ 7699 __O uint32_t UHINTCLR; /**< \brief Offset: 0x408 ( /W 32) Host Global Interrrupt Clear Register */ 7700 __O uint32_t UHINTSET; /**< \brief Offset: 0x40C ( /W 32) Host Global Interrupt Set Register */ 7701 __I uint32_t UHINTE; /**< \brief Offset: 0x410 (R/ 32) Host Global Interrupt Enable Register */ 7702 __O uint32_t UHINTECLR; /**< \brief Offset: 0x414 ( /W 32) Host Global Interrupt Enable Clear Register */ 7703 __O uint32_t UHINTESET; /**< \brief Offset: 0x418 ( /W 32) Host Global Interrupt Enable Set Register */ 7704 __IO uint32_t UPRST; /**< \brief Offset: 0x41C (R/W 32) Pipe Reset Register */ 7705 __IO uint32_t UHFNUM; /**< \brief Offset: 0x420 (R/W 32) Host Frame Number Register */ 7706 __IO uint32_t UHSOFC; /**< \brief Offset: 0x424 (R/W 32) Host Start of Frame Control Register */ 7707 RoReg8 Reserved9[0xD8]; 7708 __IO uint32_t UPCFG[8]; /**< \brief Offset: 0x500 (R/W 32) Pipe Configuration Register */ 7709 RoReg8 Reserved10[0x10]; 7710 __I uint32_t UPSTA[8]; /**< \brief Offset: 0x530 (R/ 32) Pipe Status Register */ 7711 RoReg8 Reserved11[0x10]; 7712 __O uint32_t UPSTACLR[8]; /**< \brief Offset: 0x560 ( /W 32) Pipe Status Clear Register */ 7713 RoReg8 Reserved12[0x10]; 7714 __O uint32_t UPSTASET[8]; /**< \brief Offset: 0x590 ( /W 32) Pipe Status Set Register */ 7715 RoReg8 Reserved13[0x10]; 7716 __I uint32_t UPCON[8]; /**< \brief Offset: 0x5C0 (R/ 32) Pipe Control Register */ 7717 RoReg8 Reserved14[0x10]; 7718 __O uint32_t UPCONSET[8]; /**< \brief Offset: 0x5F0 ( /W 32) Pipe Control Set Register */ 7719 RoReg8 Reserved15[0x10]; 7720 __O uint32_t UPCONCLR[8]; /**< \brief Offset: 0x620 ( /W 32) Pipe Control Clear Register */ 7721 RoReg8 Reserved16[0x10]; 7722 __IO uint32_t UPINRQ[8]; /**< \brief Offset: 0x650 (R/W 32) Pipe In Request */ 7723 RoReg8 Reserved17[0x190]; 7724 __IO uint32_t USBCON; /**< \brief Offset: 0x800 (R/W 32) General Control Register */ 7725 __I uint32_t USBSTA; /**< \brief Offset: 0x804 (R/ 32) General Status Register */ 7726 __O uint32_t USBSTACLR; /**< \brief Offset: 0x808 ( /W 32) General Status Clear Register */ 7727 __O uint32_t USBSTASET; /**< \brief Offset: 0x80C ( /W 32) General Status Set Register */ 7728 RoReg8 Reserved18[0x8]; 7729 __I uint32_t UVERS; /**< \brief Offset: 0x818 (R/ 32) IP Version Register */ 7730 __I uint32_t UFEATURES; /**< \brief Offset: 0x81C (R/ 32) IP Features Register */ 7731 __I uint32_t UADDRSIZE; /**< \brief Offset: 0x820 (R/ 32) IP PB address size Register */ 7732 __I uint32_t UNAME1; /**< \brief Offset: 0x824 (R/ 32) IP Name Part One: HUSB */ 7733 __I uint32_t UNAME2; /**< \brief Offset: 0x828 (R/ 32) IP Name Part Two: HOST */ 7734 __I uint32_t USBFSM; /**< \brief Offset: 0x82C (R/ 32) USB internal finite state machine */ 7735 __IO uint32_t UDESC; /**< \brief Offset: 0x830 (R/W 32) Endpoint descriptor table */ 7736 } Usbc; 7737 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 7738 7739 /*@}*/ 7740 7741 #endif /* _SAM4L_USBC_COMPONENT_ */ 7742
