1 /** 2 * \file 3 * 4 * \brief Component description for FREQM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_FREQM_COMPONENT_ 30 #define _SAM4L_FREQM_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR FREQM */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_FREQM Frequency Meter */ 36 /*@{*/ 37 38 #define FREQM_I7530 39 #define REV_FREQM 0x311 40 41 /* -------- FREQM_CTRL : (FREQM Offset: 0x000) ( /W 32) Control register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t START:1; /*!< bit: 0 Start frequency measurement */ 46 uint32_t :31; /*!< bit: 1..31 Reserved */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } FREQM_CTRL_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define FREQM_CTRL_OFFSET 0x000 /**< \brief (FREQM_CTRL offset) Control register */ 53 #define FREQM_CTRL_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_CTRL reset_value) Control register */ 54 55 #define FREQM_CTRL_START_Pos 0 /**< \brief (FREQM_CTRL) Start frequency measurement */ 56 #define FREQM_CTRL_START (_U_(0x1) << FREQM_CTRL_START_Pos) 57 #define FREQM_CTRL_MASK _U_(0x00000001) /**< \brief (FREQM_CTRL) MASK Register */ 58 59 /* -------- FREQM_MODE : (FREQM Offset: 0x004) (R/W 32) Mode register -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t REFSEL:2; /*!< bit: 0.. 1 Reference Clock Selection */ 64 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 65 uint32_t REFNUM:8; /*!< bit: 8..15 Number of Reference CLock Cycles */ 66 uint32_t CLKSEL:5; /*!< bit: 16..20 Clock Source Selection */ 67 uint32_t :10; /*!< bit: 21..30 Reserved */ 68 uint32_t REFCEN:1; /*!< bit: 31 Reference Clock Enable */ 69 } bit; /*!< Structure used for bit access */ 70 uint32_t reg; /*!< Type used for register access */ 71 } FREQM_MODE_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 #define FREQM_MODE_OFFSET 0x004 /**< \brief (FREQM_MODE offset) Mode register */ 75 #define FREQM_MODE_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_MODE reset_value) Mode register */ 76 77 #define FREQM_MODE_REFSEL_Pos 0 /**< \brief (FREQM_MODE) Reference Clock Selection */ 78 #define FREQM_MODE_REFSEL_Msk (_U_(0x3) << FREQM_MODE_REFSEL_Pos) 79 #define FREQM_MODE_REFSEL(value) (FREQM_MODE_REFSEL_Msk & ((value) << FREQM_MODE_REFSEL_Pos)) 80 #define FREQM_MODE_REFNUM_Pos 8 /**< \brief (FREQM_MODE) Number of Reference CLock Cycles */ 81 #define FREQM_MODE_REFNUM_Msk (_U_(0xFF) << FREQM_MODE_REFNUM_Pos) 82 #define FREQM_MODE_REFNUM(value) (FREQM_MODE_REFNUM_Msk & ((value) << FREQM_MODE_REFNUM_Pos)) 83 #define FREQM_MODE_CLKSEL_Pos 16 /**< \brief (FREQM_MODE) Clock Source Selection */ 84 #define FREQM_MODE_CLKSEL_Msk (_U_(0x1F) << FREQM_MODE_CLKSEL_Pos) 85 #define FREQM_MODE_CLKSEL(value) (FREQM_MODE_CLKSEL_Msk & ((value) << FREQM_MODE_CLKSEL_Pos)) 86 #define FREQM_MODE_REFCEN_Pos 31 /**< \brief (FREQM_MODE) Reference Clock Enable */ 87 #define FREQM_MODE_REFCEN (_U_(0x1) << FREQM_MODE_REFCEN_Pos) 88 #define FREQM_MODE_MASK _U_(0x801FFF03) /**< \brief (FREQM_MODE) MASK Register */ 89 90 /* -------- FREQM_STATUS : (FREQM Offset: 0x008) (R/ 32) Status register -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { 93 struct { 94 uint32_t BUSY:1; /*!< bit: 0 Frequency measurement on-going */ 95 uint32_t RCLKBUSY:1; /*!< bit: 1 Reference Clock busy */ 96 uint32_t :30; /*!< bit: 2..31 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 uint32_t reg; /*!< Type used for register access */ 99 } FREQM_STATUS_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #define FREQM_STATUS_OFFSET 0x008 /**< \brief (FREQM_STATUS offset) Status register */ 103 #define FREQM_STATUS_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_STATUS reset_value) Status register */ 104 105 #define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) Frequency measurement on-going */ 106 #define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos) 107 #define FREQM_STATUS_RCLKBUSY_Pos 1 /**< \brief (FREQM_STATUS) Reference Clock busy */ 108 #define FREQM_STATUS_RCLKBUSY (_U_(0x1) << FREQM_STATUS_RCLKBUSY_Pos) 109 #define FREQM_STATUS_MASK _U_(0x00000003) /**< \brief (FREQM_STATUS) MASK Register */ 110 111 /* -------- FREQM_VALUE : (FREQM Offset: 0x00C) (R/ 32) Value register -------- */ 112 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 113 typedef union { 114 struct { 115 uint32_t VALUE:24; /*!< bit: 0..23 Measured frequency */ 116 uint32_t :8; /*!< bit: 24..31 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } FREQM_VALUE_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 #define FREQM_VALUE_OFFSET 0x00C /**< \brief (FREQM_VALUE offset) Value register */ 123 #define FREQM_VALUE_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_VALUE reset_value) Value register */ 124 125 #define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measured frequency */ 126 #define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) 127 #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos)) 128 #define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */ 129 130 /* -------- FREQM_IER : (FREQM Offset: 0x010) ( /W 32) Interrupt Enable Register -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint32_t DONE:1; /*!< bit: 0 Frequency measurment done */ 135 uint32_t RCLKRDY:1; /*!< bit: 1 Reference Clock ready */ 136 uint32_t :30; /*!< bit: 2..31 Reserved */ 137 } bit; /*!< Structure used for bit access */ 138 uint32_t reg; /*!< Type used for register access */ 139 } FREQM_IER_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 #define FREQM_IER_OFFSET 0x010 /**< \brief (FREQM_IER offset) Interrupt Enable Register */ 143 #define FREQM_IER_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_IER reset_value) Interrupt Enable Register */ 144 145 #define FREQM_IER_DONE_Pos 0 /**< \brief (FREQM_IER) Frequency measurment done */ 146 #define FREQM_IER_DONE (_U_(0x1) << FREQM_IER_DONE_Pos) 147 #define FREQM_IER_RCLKRDY_Pos 1 /**< \brief (FREQM_IER) Reference Clock ready */ 148 #define FREQM_IER_RCLKRDY (_U_(0x1) << FREQM_IER_RCLKRDY_Pos) 149 #define FREQM_IER_MASK _U_(0x00000003) /**< \brief (FREQM_IER) MASK Register */ 150 151 /* -------- FREQM_IDR : (FREQM Offset: 0x014) ( /W 32) Interrupt Diable Register -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint32_t DONE:1; /*!< bit: 0 Frequency measurment done */ 156 uint32_t RCLKRDY:1; /*!< bit: 1 Reference Clock ready */ 157 uint32_t :30; /*!< bit: 2..31 Reserved */ 158 } bit; /*!< Structure used for bit access */ 159 uint32_t reg; /*!< Type used for register access */ 160 } FREQM_IDR_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define FREQM_IDR_OFFSET 0x014 /**< \brief (FREQM_IDR offset) Interrupt Diable Register */ 164 #define FREQM_IDR_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_IDR reset_value) Interrupt Diable Register */ 165 166 #define FREQM_IDR_DONE_Pos 0 /**< \brief (FREQM_IDR) Frequency measurment done */ 167 #define FREQM_IDR_DONE (_U_(0x1) << FREQM_IDR_DONE_Pos) 168 #define FREQM_IDR_RCLKRDY_Pos 1 /**< \brief (FREQM_IDR) Reference Clock ready */ 169 #define FREQM_IDR_RCLKRDY (_U_(0x1) << FREQM_IDR_RCLKRDY_Pos) 170 #define FREQM_IDR_MASK _U_(0x00000003) /**< \brief (FREQM_IDR) MASK Register */ 171 172 /* -------- FREQM_IMR : (FREQM Offset: 0x018) (R/ 32) Interrupt Mask Register -------- */ 173 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 174 typedef union { 175 struct { 176 uint32_t DONE:1; /*!< bit: 0 Frequency measurment done */ 177 uint32_t RCLKRDY:1; /*!< bit: 1 Reference Clock ready */ 178 uint32_t :30; /*!< bit: 2..31 Reserved */ 179 } bit; /*!< Structure used for bit access */ 180 uint32_t reg; /*!< Type used for register access */ 181 } FREQM_IMR_Type; 182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 183 184 #define FREQM_IMR_OFFSET 0x018 /**< \brief (FREQM_IMR offset) Interrupt Mask Register */ 185 #define FREQM_IMR_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_IMR reset_value) Interrupt Mask Register */ 186 187 #define FREQM_IMR_DONE_Pos 0 /**< \brief (FREQM_IMR) Frequency measurment done */ 188 #define FREQM_IMR_DONE (_U_(0x1) << FREQM_IMR_DONE_Pos) 189 #define FREQM_IMR_RCLKRDY_Pos 1 /**< \brief (FREQM_IMR) Reference Clock ready */ 190 #define FREQM_IMR_RCLKRDY (_U_(0x1) << FREQM_IMR_RCLKRDY_Pos) 191 #define FREQM_IMR_MASK _U_(0x00000003) /**< \brief (FREQM_IMR) MASK Register */ 192 193 /* -------- FREQM_ISR : (FREQM Offset: 0x01C) (R/ 32) Interrupt Status Register -------- */ 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef union { 196 struct { 197 uint32_t DONE:1; /*!< bit: 0 Frequency measurment done */ 198 uint32_t RCLKRDY:1; /*!< bit: 1 Reference Clock ready */ 199 uint32_t :30; /*!< bit: 2..31 Reserved */ 200 } bit; /*!< Structure used for bit access */ 201 uint32_t reg; /*!< Type used for register access */ 202 } FREQM_ISR_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define FREQM_ISR_OFFSET 0x01C /**< \brief (FREQM_ISR offset) Interrupt Status Register */ 206 #define FREQM_ISR_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_ISR reset_value) Interrupt Status Register */ 207 208 #define FREQM_ISR_DONE_Pos 0 /**< \brief (FREQM_ISR) Frequency measurment done */ 209 #define FREQM_ISR_DONE (_U_(0x1) << FREQM_ISR_DONE_Pos) 210 #define FREQM_ISR_RCLKRDY_Pos 1 /**< \brief (FREQM_ISR) Reference Clock ready */ 211 #define FREQM_ISR_RCLKRDY (_U_(0x1) << FREQM_ISR_RCLKRDY_Pos) 212 #define FREQM_ISR_MASK _U_(0x00000003) /**< \brief (FREQM_ISR) MASK Register */ 213 214 /* -------- FREQM_ICR : (FREQM Offset: 0x020) ( /W 32) Interrupt Clear Register -------- */ 215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 216 typedef union { 217 struct { 218 uint32_t DONE:1; /*!< bit: 0 Frequency measurment done */ 219 uint32_t RCLKRDY:1; /*!< bit: 1 Reference Clock ready */ 220 uint32_t :30; /*!< bit: 2..31 Reserved */ 221 } bit; /*!< Structure used for bit access */ 222 uint32_t reg; /*!< Type used for register access */ 223 } FREQM_ICR_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 #define FREQM_ICR_OFFSET 0x020 /**< \brief (FREQM_ICR offset) Interrupt Clear Register */ 227 #define FREQM_ICR_RESETVALUE _U_(0x00000000); /**< \brief (FREQM_ICR reset_value) Interrupt Clear Register */ 228 229 #define FREQM_ICR_DONE_Pos 0 /**< \brief (FREQM_ICR) Frequency measurment done */ 230 #define FREQM_ICR_DONE (_U_(0x1) << FREQM_ICR_DONE_Pos) 231 #define FREQM_ICR_RCLKRDY_Pos 1 /**< \brief (FREQM_ICR) Reference Clock ready */ 232 #define FREQM_ICR_RCLKRDY (_U_(0x1) << FREQM_ICR_RCLKRDY_Pos) 233 #define FREQM_ICR_MASK _U_(0x00000003) /**< \brief (FREQM_ICR) MASK Register */ 234 235 /* -------- FREQM_VERSION : (FREQM Offset: 0x3FC) (R/ 32) Version Register -------- */ 236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 237 typedef union { 238 struct { 239 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 240 uint32_t :4; /*!< bit: 12..15 Reserved */ 241 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 242 uint32_t :12; /*!< bit: 20..31 Reserved */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } FREQM_VERSION_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define FREQM_VERSION_OFFSET 0x3FC /**< \brief (FREQM_VERSION offset) Version Register */ 249 #define FREQM_VERSION_RESETVALUE _U_(0x00000311); /**< \brief (FREQM_VERSION reset_value) Version Register */ 250 251 #define FREQM_VERSION_VERSION_Pos 0 /**< \brief (FREQM_VERSION) Version number */ 252 #define FREQM_VERSION_VERSION_Msk (_U_(0xFFF) << FREQM_VERSION_VERSION_Pos) 253 #define FREQM_VERSION_VERSION(value) (FREQM_VERSION_VERSION_Msk & ((value) << FREQM_VERSION_VERSION_Pos)) 254 #define FREQM_VERSION_VARIANT_Pos 16 /**< \brief (FREQM_VERSION) Variant number */ 255 #define FREQM_VERSION_VARIANT_Msk (_U_(0xF) << FREQM_VERSION_VARIANT_Pos) 256 #define FREQM_VERSION_VARIANT(value) (FREQM_VERSION_VARIANT_Msk & ((value) << FREQM_VERSION_VARIANT_Pos)) 257 #define FREQM_VERSION_MASK _U_(0x000F0FFF) /**< \brief (FREQM_VERSION) MASK Register */ 258 259 /** \brief FREQM hardware registers */ 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 261 typedef struct { 262 __O uint32_t CTRL; /**< \brief Offset: 0x000 ( /W 32) Control register */ 263 __IO uint32_t MODE; /**< \brief Offset: 0x004 (R/W 32) Mode register */ 264 __I uint32_t STATUS; /**< \brief Offset: 0x008 (R/ 32) Status register */ 265 __I uint32_t VALUE; /**< \brief Offset: 0x00C (R/ 32) Value register */ 266 __O uint32_t IER; /**< \brief Offset: 0x010 ( /W 32) Interrupt Enable Register */ 267 __O uint32_t IDR; /**< \brief Offset: 0x014 ( /W 32) Interrupt Diable Register */ 268 __I uint32_t IMR; /**< \brief Offset: 0x018 (R/ 32) Interrupt Mask Register */ 269 __I uint32_t ISR; /**< \brief Offset: 0x01C (R/ 32) Interrupt Status Register */ 270 __O uint32_t ICR; /**< \brief Offset: 0x020 ( /W 32) Interrupt Clear Register */ 271 RoReg8 Reserved1[0x3D8]; 272 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) Version Register */ 273 } Freqm; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 /*@}*/ 277 278 #endif /* _SAM4L_FREQM_COMPONENT_ */ 279
