1 /** 2 * \file 3 * 4 * \brief Component description for DACC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_DACC_COMPONENT_ 30 #define _SAM4L_DACC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DACC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_DACC DAC Controller */ 36 /*@{*/ 37 38 #define DACC_I7645 39 #define REV_DACC 0x111 40 41 /* -------- DACC_CR : (DACC Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t :31; /*!< bit: 1..31 Reserved */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } DACC_CR_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define DACC_CR_OFFSET 0x00 /**< \brief (DACC_CR offset) Control Register */ 53 #define DACC_CR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_CR reset_value) Control Register */ 54 55 #define DACC_CR_SWRST_Pos 0 /**< \brief (DACC_CR) Software Reset */ 56 #define DACC_CR_SWRST (_U_(0x1) << DACC_CR_SWRST_Pos) 57 #define DACC_CR_MASK _U_(0x00000001) /**< \brief (DACC_CR) MASK Register */ 58 59 /* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t TRGEN:1; /*!< bit: 0 Trigger Enable */ 64 uint32_t TRGSEL:3; /*!< bit: 1.. 3 Trigger Selection */ 65 uint32_t DACEN:1; /*!< bit: 4 DAC Enable */ 66 uint32_t WORD:1; /*!< bit: 5 Word Transfer */ 67 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 68 uint32_t STARTUP:8; /*!< bit: 8..15 Startup Time Selection */ 69 uint32_t CLKDIV:16; /*!< bit: 16..31 Clock Divider for Internal Trigger */ 70 } bit; /*!< Structure used for bit access */ 71 uint32_t reg; /*!< Type used for register access */ 72 } DACC_MR_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define DACC_MR_OFFSET 0x04 /**< \brief (DACC_MR offset) Mode Register */ 76 #define DACC_MR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_MR reset_value) Mode Register */ 77 78 #define DACC_MR_TRGEN_Pos 0 /**< \brief (DACC_MR) Trigger Enable */ 79 #define DACC_MR_TRGEN (_U_(0x1) << DACC_MR_TRGEN_Pos) 80 #define DACC_MR_TRGSEL_Pos 1 /**< \brief (DACC_MR) Trigger Selection */ 81 #define DACC_MR_TRGSEL_Msk (_U_(0x7) << DACC_MR_TRGSEL_Pos) 82 #define DACC_MR_TRGSEL(value) (DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)) 83 #define DACC_MR_DACEN_Pos 4 /**< \brief (DACC_MR) DAC Enable */ 84 #define DACC_MR_DACEN (_U_(0x1) << DACC_MR_DACEN_Pos) 85 #define DACC_MR_WORD_Pos 5 /**< \brief (DACC_MR) Word Transfer */ 86 #define DACC_MR_WORD (_U_(0x1) << DACC_MR_WORD_Pos) 87 #define DACC_MR_STARTUP_Pos 8 /**< \brief (DACC_MR) Startup Time Selection */ 88 #define DACC_MR_STARTUP_Msk (_U_(0xFF) << DACC_MR_STARTUP_Pos) 89 #define DACC_MR_STARTUP(value) (DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)) 90 #define DACC_MR_CLKDIV_Pos 16 /**< \brief (DACC_MR) Clock Divider for Internal Trigger */ 91 #define DACC_MR_CLKDIV_Msk (_U_(0xFFFF) << DACC_MR_CLKDIV_Pos) 92 #define DACC_MR_CLKDIV(value) (DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)) 93 #define DACC_MR_MASK _U_(0xFFFFFF3F) /**< \brief (DACC_MR) MASK Register */ 94 95 /* -------- DACC_CDR : (DACC Offset: 0x08) ( /W 32) Conversion Data Register -------- */ 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 97 typedef union { 98 struct { 99 uint32_t DATA:32; /*!< bit: 0..31 Data to Convert */ 100 } bit; /*!< Structure used for bit access */ 101 uint32_t reg; /*!< Type used for register access */ 102 } DACC_CDR_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define DACC_CDR_OFFSET 0x08 /**< \brief (DACC_CDR offset) Conversion Data Register */ 106 #define DACC_CDR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_CDR reset_value) Conversion Data Register */ 107 108 #define DACC_CDR_DATA_Pos 0 /**< \brief (DACC_CDR) Data to Convert */ 109 #define DACC_CDR_DATA_Msk (_U_(0xFFFFFFFF) << DACC_CDR_DATA_Pos) 110 #define DACC_CDR_DATA(value) (DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)) 111 #define DACC_CDR_MASK _U_(0xFFFFFFFF) /**< \brief (DACC_CDR) MASK Register */ 112 113 /* -------- DACC_IER : (DACC Offset: 0x0C) ( /W 32) Interrupt Enable Register -------- */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef union { 116 struct { 117 uint32_t TXRDY:1; /*!< bit: 0 Transmit Ready Interrupt Enable */ 118 uint32_t :31; /*!< bit: 1..31 Reserved */ 119 } bit; /*!< Structure used for bit access */ 120 uint32_t reg; /*!< Type used for register access */ 121 } DACC_IER_Type; 122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 123 124 #define DACC_IER_OFFSET 0x0C /**< \brief (DACC_IER offset) Interrupt Enable Register */ 125 #define DACC_IER_RESETVALUE _U_(0x00000000); /**< \brief (DACC_IER reset_value) Interrupt Enable Register */ 126 127 #define DACC_IER_TXRDY_Pos 0 /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ 128 #define DACC_IER_TXRDY (_U_(0x1) << DACC_IER_TXRDY_Pos) 129 #define DACC_IER_MASK _U_(0x00000001) /**< \brief (DACC_IER) MASK Register */ 130 131 /* -------- DACC_IDR : (DACC Offset: 0x10) ( /W 32) Interrupt Disable Register -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint32_t TXRDY:1; /*!< bit: 0 Transmit Ready Interrupt Disable */ 136 uint32_t :31; /*!< bit: 1..31 Reserved */ 137 } bit; /*!< Structure used for bit access */ 138 uint32_t reg; /*!< Type used for register access */ 139 } DACC_IDR_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 #define DACC_IDR_OFFSET 0x10 /**< \brief (DACC_IDR offset) Interrupt Disable Register */ 143 144 #define DACC_IDR_TXRDY_Pos 0 /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable */ 145 #define DACC_IDR_TXRDY (_U_(0x1) << DACC_IDR_TXRDY_Pos) 146 #define DACC_IDR_MASK _U_(0x00000001) /**< \brief (DACC_IDR) MASK Register */ 147 148 /* -------- DACC_IMR : (DACC Offset: 0x14) (R/ 32) Interrupt Mask Register -------- */ 149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 150 typedef union { 151 struct { 152 uint32_t TXRDY:1; /*!< bit: 0 Transmit Ready Interrupt Mask */ 153 uint32_t :31; /*!< bit: 1..31 Reserved */ 154 } bit; /*!< Structure used for bit access */ 155 uint32_t reg; /*!< Type used for register access */ 156 } DACC_IMR_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define DACC_IMR_OFFSET 0x14 /**< \brief (DACC_IMR offset) Interrupt Mask Register */ 160 #define DACC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_IMR reset_value) Interrupt Mask Register */ 161 162 #define DACC_IMR_TXRDY_Pos 0 /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ 163 #define DACC_IMR_TXRDY (_U_(0x1) << DACC_IMR_TXRDY_Pos) 164 #define DACC_IMR_MASK _U_(0x00000001) /**< \brief (DACC_IMR) MASK Register */ 165 166 /* -------- DACC_ISR : (DACC Offset: 0x18) (R/ 32) Interrupt Status Register -------- */ 167 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 168 typedef union { 169 struct { 170 uint32_t TXRDY:1; /*!< bit: 0 Transmit Ready Interrupt Status */ 171 uint32_t :31; /*!< bit: 1..31 Reserved */ 172 } bit; /*!< Structure used for bit access */ 173 uint32_t reg; /*!< Type used for register access */ 174 } DACC_ISR_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define DACC_ISR_OFFSET 0x18 /**< \brief (DACC_ISR offset) Interrupt Status Register */ 178 #define DACC_ISR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_ISR reset_value) Interrupt Status Register */ 179 180 #define DACC_ISR_TXRDY_Pos 0 /**< \brief (DACC_ISR) Transmit Ready Interrupt Status */ 181 #define DACC_ISR_TXRDY (_U_(0x1) << DACC_ISR_TXRDY_Pos) 182 #define DACC_ISR_MASK _U_(0x00000001) /**< \brief (DACC_ISR) MASK Register */ 183 184 /* -------- DACC_WPMR : (DACC Offset: 0xE4) (R/W 32) Write Protect Mode Register -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint32_t WPEN:1; /*!< bit: 0 Write Protect Enable */ 189 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 190 uint32_t WPKEY:24; /*!< bit: 8..31 Write Protect Key */ 191 } bit; /*!< Structure used for bit access */ 192 uint32_t reg; /*!< Type used for register access */ 193 } DACC_WPMR_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define DACC_WPMR_OFFSET 0xE4 /**< \brief (DACC_WPMR offset) Write Protect Mode Register */ 197 #define DACC_WPMR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_WPMR reset_value) Write Protect Mode Register */ 198 199 #define DACC_WPMR_WPEN_Pos 0 /**< \brief (DACC_WPMR) Write Protect Enable */ 200 #define DACC_WPMR_WPEN (_U_(0x1) << DACC_WPMR_WPEN_Pos) 201 #define DACC_WPMR_WPKEY_Pos 8 /**< \brief (DACC_WPMR) Write Protect Key */ 202 #define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) 203 #define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)) 204 #define DACC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (DACC_WPMR) MASK Register */ 205 206 /* -------- DACC_WPSR : (DACC Offset: 0xE8) (R/ 32) Write Protect Status Register -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint32_t WPROTERR:1; /*!< bit: 0 Write Protection Error */ 211 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 212 uint32_t WPROTADDR:8; /*!< bit: 8..15 Write Protection Error Address */ 213 uint32_t :16; /*!< bit: 16..31 Reserved */ 214 } bit; /*!< Structure used for bit access */ 215 uint32_t reg; /*!< Type used for register access */ 216 } DACC_WPSR_Type; 217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 219 #define DACC_WPSR_OFFSET 0xE8 /**< \brief (DACC_WPSR offset) Write Protect Status Register */ 220 #define DACC_WPSR_RESETVALUE _U_(0x00000000); /**< \brief (DACC_WPSR reset_value) Write Protect Status Register */ 221 222 #define DACC_WPSR_WPROTERR_Pos 0 /**< \brief (DACC_WPSR) Write Protection Error */ 223 #define DACC_WPSR_WPROTERR (_U_(0x1) << DACC_WPSR_WPROTERR_Pos) 224 #define DACC_WPSR_WPROTADDR_Pos 8 /**< \brief (DACC_WPSR) Write Protection Error Address */ 225 #define DACC_WPSR_WPROTADDR_Msk (_U_(0xFF) << DACC_WPSR_WPROTADDR_Pos) 226 #define DACC_WPSR_WPROTADDR(value) (DACC_WPSR_WPROTADDR_Msk & ((value) << DACC_WPSR_WPROTADDR_Pos)) 227 #define DACC_WPSR_MASK _U_(0x0000FF01) /**< \brief (DACC_WPSR) MASK Register */ 228 229 /* -------- DACC_VERSION : (DACC Offset: 0xFC) (R/ 32) Version Register -------- */ 230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 231 typedef union { 232 struct { 233 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 234 uint32_t :4; /*!< bit: 12..15 Reserved */ 235 uint32_t VARIANT:3; /*!< bit: 16..18 Variant Number */ 236 uint32_t :13; /*!< bit: 19..31 Reserved */ 237 } bit; /*!< Structure used for bit access */ 238 uint32_t reg; /*!< Type used for register access */ 239 } DACC_VERSION_Type; 240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 241 242 #define DACC_VERSION_OFFSET 0xFC /**< \brief (DACC_VERSION offset) Version Register */ 243 #define DACC_VERSION_RESETVALUE _U_(0x00000111); /**< \brief (DACC_VERSION reset_value) Version Register */ 244 245 #define DACC_VERSION_VERSION_Pos 0 /**< \brief (DACC_VERSION) Version Number */ 246 #define DACC_VERSION_VERSION_Msk (_U_(0xFFF) << DACC_VERSION_VERSION_Pos) 247 #define DACC_VERSION_VERSION(value) (DACC_VERSION_VERSION_Msk & ((value) << DACC_VERSION_VERSION_Pos)) 248 #define DACC_VERSION_VARIANT_Pos 16 /**< \brief (DACC_VERSION) Variant Number */ 249 #define DACC_VERSION_VARIANT_Msk (_U_(0x7) << DACC_VERSION_VARIANT_Pos) 250 #define DACC_VERSION_VARIANT(value) (DACC_VERSION_VARIANT_Msk & ((value) << DACC_VERSION_VARIANT_Pos)) 251 #define DACC_VERSION_MASK _U_(0x00070FFF) /**< \brief (DACC_VERSION) MASK Register */ 252 253 /** \brief DACC hardware registers */ 254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 255 typedef struct { 256 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 257 __IO uint32_t MR; /**< \brief Offset: 0x04 (R/W 32) Mode Register */ 258 __O uint32_t CDR; /**< \brief Offset: 0x08 ( /W 32) Conversion Data Register */ 259 __O uint32_t IER; /**< \brief Offset: 0x0C ( /W 32) Interrupt Enable Register */ 260 __O uint32_t IDR; /**< \brief Offset: 0x10 ( /W 32) Interrupt Disable Register */ 261 __I uint32_t IMR; /**< \brief Offset: 0x14 (R/ 32) Interrupt Mask Register */ 262 __I uint32_t ISR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Status Register */ 263 RoReg8 Reserved1[0xC8]; 264 __IO uint32_t WPMR; /**< \brief Offset: 0xE4 (R/W 32) Write Protect Mode Register */ 265 __I uint32_t WPSR; /**< \brief Offset: 0xE8 (R/ 32) Write Protect Status Register */ 266 RoReg8 Reserved2[0x10]; 267 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 268 } Dacc; 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 270 271 /*@}*/ 272 273 #endif /* _SAM4L_DACC_COMPONENT_ */ 274
