1 /** 2 * \file 3 * 4 * \brief Component description for CRCCU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_CRCCU_COMPONENT_ 30 #define _SAM4L_CRCCU_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR CRCCU */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_CRCCU CRC Calculation Unit */ 36 /*@{*/ 37 38 #define CRCCU_I7644 39 #define REV_CRCCU 0x202 40 41 /* -------- CRCCU_DSCR : (CRCCU Offset: 0x00) (R/W 32) Descriptor Base Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t :9; /*!< bit: 0.. 8 Reserved */ 46 uint32_t DSCR:23; /*!< bit: 9..31 Description Base Address */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } CRCCU_DSCR_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define CRCCU_DSCR_OFFSET 0x00 /**< \brief (CRCCU_DSCR offset) Descriptor Base Register */ 53 #define CRCCU_DSCR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DSCR reset_value) Descriptor Base Register */ 54 55 #define CRCCU_DSCR_DSCR_Pos 9 /**< \brief (CRCCU_DSCR) Description Base Address */ 56 #define CRCCU_DSCR_DSCR_Msk (_U_(0x7FFFFF) << CRCCU_DSCR_DSCR_Pos) 57 #define CRCCU_DSCR_DSCR(value) (CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)) 58 #define CRCCU_DSCR_MASK _U_(0xFFFFFE00) /**< \brief (CRCCU_DSCR) MASK Register */ 59 60 /* -------- CRCCU_DMAEN : (CRCCU Offset: 0x08) ( /W 32) DMA Enable Register -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint32_t DMAEN:1; /*!< bit: 0 DMA Enable */ 65 uint32_t :31; /*!< bit: 1..31 Reserved */ 66 } bit; /*!< Structure used for bit access */ 67 uint32_t reg; /*!< Type used for register access */ 68 } CRCCU_DMAEN_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define CRCCU_DMAEN_OFFSET 0x08 /**< \brief (CRCCU_DMAEN offset) DMA Enable Register */ 72 #define CRCCU_DMAEN_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMAEN reset_value) DMA Enable Register */ 73 74 #define CRCCU_DMAEN_DMAEN_Pos 0 /**< \brief (CRCCU_DMAEN) DMA Enable */ 75 #define CRCCU_DMAEN_DMAEN (_U_(0x1) << CRCCU_DMAEN_DMAEN_Pos) 76 #define CRCCU_DMAEN_MASK _U_(0x00000001) /**< \brief (CRCCU_DMAEN) MASK Register */ 77 78 /* -------- CRCCU_DMADIS : (CRCCU Offset: 0x0C) ( /W 32) DMA Disable Register -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { 81 struct { 82 uint32_t DMADIS:1; /*!< bit: 0 DMA Disable */ 83 uint32_t :31; /*!< bit: 1..31 Reserved */ 84 } bit; /*!< Structure used for bit access */ 85 uint32_t reg; /*!< Type used for register access */ 86 } CRCCU_DMADIS_Type; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 #define CRCCU_DMADIS_OFFSET 0x0C /**< \brief (CRCCU_DMADIS offset) DMA Disable Register */ 90 #define CRCCU_DMADIS_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMADIS reset_value) DMA Disable Register */ 91 92 #define CRCCU_DMADIS_DMADIS_Pos 0 /**< \brief (CRCCU_DMADIS) DMA Disable */ 93 #define CRCCU_DMADIS_DMADIS (_U_(0x1) << CRCCU_DMADIS_DMADIS_Pos) 94 #define CRCCU_DMADIS_MASK _U_(0x00000001) /**< \brief (CRCCU_DMADIS) MASK Register */ 95 96 /* -------- CRCCU_DMASR : (CRCCU Offset: 0x10) (R/ 32) DMA Status Register -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t DMASR:1; /*!< bit: 0 DMA Channel Status */ 101 uint32_t :31; /*!< bit: 1..31 Reserved */ 102 } bit; /*!< Structure used for bit access */ 103 uint32_t reg; /*!< Type used for register access */ 104 } CRCCU_DMASR_Type; 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 #define CRCCU_DMASR_OFFSET 0x10 /**< \brief (CRCCU_DMASR offset) DMA Status Register */ 108 #define CRCCU_DMASR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMASR reset_value) DMA Status Register */ 109 110 #define CRCCU_DMASR_DMASR_Pos 0 /**< \brief (CRCCU_DMASR) DMA Channel Status */ 111 #define CRCCU_DMASR_DMASR (_U_(0x1) << CRCCU_DMASR_DMASR_Pos) 112 #define CRCCU_DMASR_MASK _U_(0x00000001) /**< \brief (CRCCU_DMASR) MASK Register */ 113 114 /* -------- CRCCU_DMAIER : (CRCCU Offset: 0x14) ( /W 32) DMA Interrupt Enable Register -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { 117 struct { 118 uint32_t DMAIER:1; /*!< bit: 0 DMA Interrupt Enable */ 119 uint32_t :31; /*!< bit: 1..31 Reserved */ 120 } bit; /*!< Structure used for bit access */ 121 uint32_t reg; /*!< Type used for register access */ 122 } CRCCU_DMAIER_Type; 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define CRCCU_DMAIER_OFFSET 0x14 /**< \brief (CRCCU_DMAIER offset) DMA Interrupt Enable Register */ 126 #define CRCCU_DMAIER_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMAIER reset_value) DMA Interrupt Enable Register */ 127 128 #define CRCCU_DMAIER_DMAIER_Pos 0 /**< \brief (CRCCU_DMAIER) DMA Interrupt Enable */ 129 #define CRCCU_DMAIER_DMAIER (_U_(0x1) << CRCCU_DMAIER_DMAIER_Pos) 130 #define CRCCU_DMAIER_MASK _U_(0x00000001) /**< \brief (CRCCU_DMAIER) MASK Register */ 131 132 /* -------- CRCCU_DMAIDR : (CRCCU Offset: 0x18) ( /W 32) DMA Interrupt Disable Register -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint32_t DMAIDR:1; /*!< bit: 0 DMA Interrupt Disable */ 137 uint32_t :31; /*!< bit: 1..31 Reserved */ 138 } bit; /*!< Structure used for bit access */ 139 uint32_t reg; /*!< Type used for register access */ 140 } CRCCU_DMAIDR_Type; 141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 142 143 #define CRCCU_DMAIDR_OFFSET 0x18 /**< \brief (CRCCU_DMAIDR offset) DMA Interrupt Disable Register */ 144 #define CRCCU_DMAIDR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMAIDR reset_value) DMA Interrupt Disable Register */ 145 146 #define CRCCU_DMAIDR_DMAIDR_Pos 0 /**< \brief (CRCCU_DMAIDR) DMA Interrupt Disable */ 147 #define CRCCU_DMAIDR_DMAIDR (_U_(0x1) << CRCCU_DMAIDR_DMAIDR_Pos) 148 #define CRCCU_DMAIDR_MASK _U_(0x00000001) /**< \brief (CRCCU_DMAIDR) MASK Register */ 149 150 /* -------- CRCCU_DMAIMR : (CRCCU Offset: 0x1C) (R/ 32) DMA Interrupt Mask Register -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t DMAIMR:1; /*!< bit: 0 DMA Interrupt Mask */ 155 uint32_t :31; /*!< bit: 1..31 Reserved */ 156 } bit; /*!< Structure used for bit access */ 157 uint32_t reg; /*!< Type used for register access */ 158 } CRCCU_DMAIMR_Type; 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 160 161 #define CRCCU_DMAIMR_OFFSET 0x1C /**< \brief (CRCCU_DMAIMR offset) DMA Interrupt Mask Register */ 162 #define CRCCU_DMAIMR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMAIMR reset_value) DMA Interrupt Mask Register */ 163 164 #define CRCCU_DMAIMR_DMAIMR_Pos 0 /**< \brief (CRCCU_DMAIMR) DMA Interrupt Mask */ 165 #define CRCCU_DMAIMR_DMAIMR (_U_(0x1) << CRCCU_DMAIMR_DMAIMR_Pos) 166 #define CRCCU_DMAIMR_MASK _U_(0x00000001) /**< \brief (CRCCU_DMAIMR) MASK Register */ 167 168 /* -------- CRCCU_DMAISR : (CRCCU Offset: 0x20) (R/ 32) DMA Interrupt Status Register -------- */ 169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 170 typedef union { 171 struct { 172 uint32_t DMAISR:1; /*!< bit: 0 DMA Interrupt Status */ 173 uint32_t :31; /*!< bit: 1..31 Reserved */ 174 } bit; /*!< Structure used for bit access */ 175 uint32_t reg; /*!< Type used for register access */ 176 } CRCCU_DMAISR_Type; 177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 178 179 #define CRCCU_DMAISR_OFFSET 0x20 /**< \brief (CRCCU_DMAISR offset) DMA Interrupt Status Register */ 180 #define CRCCU_DMAISR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_DMAISR reset_value) DMA Interrupt Status Register */ 181 182 #define CRCCU_DMAISR_DMAISR_Pos 0 /**< \brief (CRCCU_DMAISR) DMA Interrupt Status */ 183 #define CRCCU_DMAISR_DMAISR (_U_(0x1) << CRCCU_DMAISR_DMAISR_Pos) 184 #define CRCCU_DMAISR_MASK _U_(0x00000001) /**< \brief (CRCCU_DMAISR) MASK Register */ 185 186 /* -------- CRCCU_CR : (CRCCU Offset: 0x34) ( /W 32) Control Register -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { 189 struct { 190 uint32_t RESET:1; /*!< bit: 0 Reset CRCComputation */ 191 uint32_t :31; /*!< bit: 1..31 Reserved */ 192 } bit; /*!< Structure used for bit access */ 193 uint32_t reg; /*!< Type used for register access */ 194 } CRCCU_CR_Type; 195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 196 197 #define CRCCU_CR_OFFSET 0x34 /**< \brief (CRCCU_CR offset) Control Register */ 198 #define CRCCU_CR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_CR reset_value) Control Register */ 199 200 #define CRCCU_CR_RESET_Pos 0 /**< \brief (CRCCU_CR) Reset CRCComputation */ 201 #define CRCCU_CR_RESET (_U_(0x1) << CRCCU_CR_RESET_Pos) 202 #define CRCCU_CR_MASK _U_(0x00000001) /**< \brief (CRCCU_CR) MASK Register */ 203 204 /* -------- CRCCU_MR : (CRCCU Offset: 0x38) (R/W 32) Mode Register -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t ENABLE:1; /*!< bit: 0 CRC Computation Enable */ 209 uint32_t COMPARE:1; /*!< bit: 1 CRC Compare */ 210 uint32_t PTYPE:2; /*!< bit: 2.. 3 Polynomial Type */ 211 uint32_t DIVIDER:4; /*!< bit: 4.. 7 Bandwidth Divider */ 212 uint32_t :24; /*!< bit: 8..31 Reserved */ 213 } bit; /*!< Structure used for bit access */ 214 uint32_t reg; /*!< Type used for register access */ 215 } CRCCU_MR_Type; 216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 217 218 #define CRCCU_MR_OFFSET 0x38 /**< \brief (CRCCU_MR offset) Mode Register */ 219 #define CRCCU_MR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_MR reset_value) Mode Register */ 220 221 #define CRCCU_MR_ENABLE_Pos 0 /**< \brief (CRCCU_MR) CRC Computation Enable */ 222 #define CRCCU_MR_ENABLE (_U_(0x1) << CRCCU_MR_ENABLE_Pos) 223 #define CRCCU_MR_COMPARE_Pos 1 /**< \brief (CRCCU_MR) CRC Compare */ 224 #define CRCCU_MR_COMPARE (_U_(0x1) << CRCCU_MR_COMPARE_Pos) 225 #define CRCCU_MR_PTYPE_Pos 2 /**< \brief (CRCCU_MR) Polynomial Type */ 226 #define CRCCU_MR_PTYPE_Msk (_U_(0x3) << CRCCU_MR_PTYPE_Pos) 227 #define CRCCU_MR_PTYPE(value) (CRCCU_MR_PTYPE_Msk & ((value) << CRCCU_MR_PTYPE_Pos)) 228 #define CRCCU_MR_PTYPE_CCITT8023_Val _U_(0x0) /**< \brief (CRCCU_MR) */ 229 #define CRCCU_MR_PTYPE_CASTAGNOLI_Val _U_(0x1) /**< \brief (CRCCU_MR) */ 230 #define CRCCU_MR_PTYPE_CCITT16_Val _U_(0x2) /**< \brief (CRCCU_MR) */ 231 #define CRCCU_MR_PTYPE_CCITT8023 (CRCCU_MR_PTYPE_CCITT8023_Val << CRCCU_MR_PTYPE_Pos) 232 #define CRCCU_MR_PTYPE_CASTAGNOLI (CRCCU_MR_PTYPE_CASTAGNOLI_Val << CRCCU_MR_PTYPE_Pos) 233 #define CRCCU_MR_PTYPE_CCITT16 (CRCCU_MR_PTYPE_CCITT16_Val << CRCCU_MR_PTYPE_Pos) 234 #define CRCCU_MR_DIVIDER_Pos 4 /**< \brief (CRCCU_MR) Bandwidth Divider */ 235 #define CRCCU_MR_DIVIDER_Msk (_U_(0xF) << CRCCU_MR_DIVIDER_Pos) 236 #define CRCCU_MR_DIVIDER(value) (CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)) 237 #define CRCCU_MR_MASK _U_(0x000000FF) /**< \brief (CRCCU_MR) MASK Register */ 238 239 /* -------- CRCCU_SR : (CRCCU Offset: 0x3C) (R/ 32) Status Register -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { 242 struct { 243 uint32_t CRC:32; /*!< bit: 0..31 Cyclic Redundancy Check Value */ 244 } bit; /*!< Structure used for bit access */ 245 uint32_t reg; /*!< Type used for register access */ 246 } CRCCU_SR_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define CRCCU_SR_OFFSET 0x3C /**< \brief (CRCCU_SR offset) Status Register */ 250 #define CRCCU_SR_RESETVALUE _U_(0xFFFFFFFF); /**< \brief (CRCCU_SR reset_value) Status Register */ 251 252 #define CRCCU_SR_CRC_Pos 0 /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ 253 #define CRCCU_SR_CRC_Msk (_U_(0xFFFFFFFF) << CRCCU_SR_CRC_Pos) 254 #define CRCCU_SR_CRC(value) (CRCCU_SR_CRC_Msk & ((value) << CRCCU_SR_CRC_Pos)) 255 #define CRCCU_SR_MASK _U_(0xFFFFFFFF) /**< \brief (CRCCU_SR) MASK Register */ 256 257 /* -------- CRCCU_IER : (CRCCU Offset: 0x40) ( /W 32) Interrupt Enable Register -------- */ 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 259 typedef union { 260 struct { 261 uint32_t ERRIER:1; /*!< bit: 0 CRC Error Interrupt Enable */ 262 uint32_t :31; /*!< bit: 1..31 Reserved */ 263 } bit; /*!< Structure used for bit access */ 264 uint32_t reg; /*!< Type used for register access */ 265 } CRCCU_IER_Type; 266 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 267 268 #define CRCCU_IER_OFFSET 0x40 /**< \brief (CRCCU_IER offset) Interrupt Enable Register */ 269 #define CRCCU_IER_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_IER reset_value) Interrupt Enable Register */ 270 271 #define CRCCU_IER_ERRIER_Pos 0 /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ 272 #define CRCCU_IER_ERRIER (_U_(0x1) << CRCCU_IER_ERRIER_Pos) 273 #define CRCCU_IER_MASK _U_(0x00000001) /**< \brief (CRCCU_IER) MASK Register */ 274 275 /* -------- CRCCU_IDR : (CRCCU Offset: 0x44) ( /W 32) Interrupt Disable Register -------- */ 276 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 277 typedef union { 278 struct { 279 uint32_t ERRIDR:1; /*!< bit: 0 CRC Error Interrupt Disable */ 280 uint32_t :31; /*!< bit: 1..31 Reserved */ 281 } bit; /*!< Structure used for bit access */ 282 uint32_t reg; /*!< Type used for register access */ 283 } CRCCU_IDR_Type; 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 285 286 #define CRCCU_IDR_OFFSET 0x44 /**< \brief (CRCCU_IDR offset) Interrupt Disable Register */ 287 #define CRCCU_IDR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_IDR reset_value) Interrupt Disable Register */ 288 289 #define CRCCU_IDR_ERRIDR_Pos 0 /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ 290 #define CRCCU_IDR_ERRIDR (_U_(0x1) << CRCCU_IDR_ERRIDR_Pos) 291 #define CRCCU_IDR_MASK _U_(0x00000001) /**< \brief (CRCCU_IDR) MASK Register */ 292 293 /* -------- CRCCU_IMR : (CRCCU Offset: 0x48) (R/ 32) Interrupt Mask Register -------- */ 294 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 295 typedef union { 296 struct { 297 uint32_t ERRIMR:1; /*!< bit: 0 CRC Error Interrupt Mask */ 298 uint32_t :31; /*!< bit: 1..31 Reserved */ 299 } bit; /*!< Structure used for bit access */ 300 uint32_t reg; /*!< Type used for register access */ 301 } CRCCU_IMR_Type; 302 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 303 304 #define CRCCU_IMR_OFFSET 0x48 /**< \brief (CRCCU_IMR offset) Interrupt Mask Register */ 305 #define CRCCU_IMR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_IMR reset_value) Interrupt Mask Register */ 306 307 #define CRCCU_IMR_ERRIMR_Pos 0 /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ 308 #define CRCCU_IMR_ERRIMR (_U_(0x1) << CRCCU_IMR_ERRIMR_Pos) 309 #define CRCCU_IMR_MASK _U_(0x00000001) /**< \brief (CRCCU_IMR) MASK Register */ 310 311 /* -------- CRCCU_ISR : (CRCCU Offset: 0x4C) (R/ 32) Interrupt Status Register -------- */ 312 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 313 typedef union { 314 struct { 315 uint32_t ERRISR:1; /*!< bit: 0 CRC Error Interrupt Status */ 316 uint32_t :31; /*!< bit: 1..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } CRCCU_ISR_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define CRCCU_ISR_OFFSET 0x4C /**< \brief (CRCCU_ISR offset) Interrupt Status Register */ 323 #define CRCCU_ISR_RESETVALUE _U_(0x00000000); /**< \brief (CRCCU_ISR reset_value) Interrupt Status Register */ 324 325 #define CRCCU_ISR_ERRISR_Pos 0 /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ 326 #define CRCCU_ISR_ERRISR (_U_(0x1) << CRCCU_ISR_ERRISR_Pos) 327 #define CRCCU_ISR_MASK _U_(0x00000001) /**< \brief (CRCCU_ISR) MASK Register */ 328 329 /* -------- CRCCU_VERSION : (CRCCU Offset: 0xFC) (R/ 32) Version Register -------- */ 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 331 typedef union { 332 struct { 333 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 334 uint32_t :4; /*!< bit: 12..15 Reserved */ 335 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 336 uint32_t :12; /*!< bit: 20..31 Reserved */ 337 } bit; /*!< Structure used for bit access */ 338 uint32_t reg; /*!< Type used for register access */ 339 } CRCCU_VERSION_Type; 340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 341 342 #define CRCCU_VERSION_OFFSET 0xFC /**< \brief (CRCCU_VERSION offset) Version Register */ 343 #define CRCCU_VERSION_RESETVALUE _U_(0x00000202); /**< \brief (CRCCU_VERSION reset_value) Version Register */ 344 345 #define CRCCU_VERSION_VERSION_Pos 0 /**< \brief (CRCCU_VERSION) Version Number */ 346 #define CRCCU_VERSION_VERSION_Msk (_U_(0xFFF) << CRCCU_VERSION_VERSION_Pos) 347 #define CRCCU_VERSION_VERSION(value) (CRCCU_VERSION_VERSION_Msk & ((value) << CRCCU_VERSION_VERSION_Pos)) 348 #define CRCCU_VERSION_VARIANT_Pos 16 /**< \brief (CRCCU_VERSION) Variant Number */ 349 #define CRCCU_VERSION_VARIANT_Msk (_U_(0xF) << CRCCU_VERSION_VARIANT_Pos) 350 #define CRCCU_VERSION_VARIANT(value) (CRCCU_VERSION_VARIANT_Msk & ((value) << CRCCU_VERSION_VARIANT_Pos)) 351 #define CRCCU_VERSION_MASK _U_(0x000F0FFF) /**< \brief (CRCCU_VERSION) MASK Register */ 352 353 /** \brief CRCCU hardware registers */ 354 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 355 typedef struct { 356 __IO uint32_t DSCR; /**< \brief Offset: 0x00 (R/W 32) Descriptor Base Register */ 357 RoReg8 Reserved1[0x4]; 358 __O uint32_t DMAEN; /**< \brief Offset: 0x08 ( /W 32) DMA Enable Register */ 359 __O uint32_t DMADIS; /**< \brief Offset: 0x0C ( /W 32) DMA Disable Register */ 360 __I uint32_t DMASR; /**< \brief Offset: 0x10 (R/ 32) DMA Status Register */ 361 __O uint32_t DMAIER; /**< \brief Offset: 0x14 ( /W 32) DMA Interrupt Enable Register */ 362 __O uint32_t DMAIDR; /**< \brief Offset: 0x18 ( /W 32) DMA Interrupt Disable Register */ 363 __I uint32_t DMAIMR; /**< \brief Offset: 0x1C (R/ 32) DMA Interrupt Mask Register */ 364 __I uint32_t DMAISR; /**< \brief Offset: 0x20 (R/ 32) DMA Interrupt Status Register */ 365 RoReg8 Reserved2[0x10]; 366 __O uint32_t CR; /**< \brief Offset: 0x34 ( /W 32) Control Register */ 367 __IO uint32_t MR; /**< \brief Offset: 0x38 (R/W 32) Mode Register */ 368 __I uint32_t SR; /**< \brief Offset: 0x3C (R/ 32) Status Register */ 369 __O uint32_t IER; /**< \brief Offset: 0x40 ( /W 32) Interrupt Enable Register */ 370 __O uint32_t IDR; /**< \brief Offset: 0x44 ( /W 32) Interrupt Disable Register */ 371 __I uint32_t IMR; /**< \brief Offset: 0x48 (R/ 32) Interrupt Mask Register */ 372 __I uint32_t ISR; /**< \brief Offset: 0x4C (R/ 32) Interrupt Status Register */ 373 RoReg8 Reserved3[0xAC]; 374 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 375 } Crccu; 376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 /*@}*/ 379 380 #endif /* _SAM4L_CRCCU_COMPONENT_ */ 381