1 /** 2 * \file 3 * 4 * \brief Component description for CHIPID 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_CHIPID_COMPONENT_ 30 #define _SAM4L_CHIPID_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR CHIPID */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_CHIPID Chip ID Registers */ 36 /*@{*/ 37 38 #define CHIPID_ 39 #define REV_CHIPID 0x100 40 41 /* -------- CHIPID_CIDR : (CHIPID Offset: 0x340) (R/ 32) Chip ID Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 uint32_t reg; /*!< Type used for register access */ 45 } CHIPID_CIDR_Type; 46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 47 48 #define CHIPID_CIDR_OFFSET 0x340 /**< \brief (CHIPID_CIDR offset) Chip ID Register */ 49 #define CHIPID_CIDR_RESETVALUE _U_(0xAB0A09E0); /**< \brief (CHIPID_CIDR reset_value) Chip ID Register */ 50 #define CHIPID_CIDR_MASK _U_(0xFFFFFFFF) /**< \brief (CHIPID_CIDR) MASK Register */ 51 52 /* -------- CHIPID_EXID : (CHIPID Offset: 0x344) (R/ 32) Chip ID Extension Register -------- */ 53 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 54 typedef union { 55 uint32_t reg; /*!< Type used for register access */ 56 } CHIPID_EXID_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define CHIPID_EXID_OFFSET 0x344 /**< \brief (CHIPID_EXID offset) Chip ID Extension Register */ 60 #define CHIPID_EXID_RESETVALUE _U_(0x0400000F); /**< \brief (CHIPID_EXID reset_value) Chip ID Extension Register */ 61 #define CHIPID_EXID_MASK _U_(0xFFFFFFFF) /**< \brief (CHIPID_EXID) MASK Register */ 62 63 /** \brief CHIPID hardware registers */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef struct { 66 RoReg8 Reserved1[0x340]; 67 __I uint32_t CIDR; /**< \brief Offset: 0x340 (R/ 32) Chip ID Register */ 68 __I uint32_t EXID; /**< \brief Offset: 0x344 (R/ 32) Chip ID Extension Register */ 69 } Chipid; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 72 /*@}*/ 73 74 #endif /* _SAM4L_CHIPID_COMPONENT_ */ 75
