1 /** 2 * \file 3 * 4 * \brief Component description for ABDACB 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_ABDACB_COMPONENT_ 30 #define _SAM4L_ABDACB_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR ABDACB */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_ABDACB Audio Bitstream DAC */ 36 /*@{*/ 37 38 #define ABDACB_I7563 39 #define REV_ABDACB 0x100 40 41 /* -------- ABDACB_CR : (ABDACB Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 Enable */ 46 uint32_t SWAP:1; /*!< bit: 1 Swap Channels */ 47 uint32_t :1; /*!< bit: 2 Reserved */ 48 uint32_t ALTUPR:1; /*!< bit: 3 Alternative up-sampling ratio */ 49 uint32_t CMOC:1; /*!< bit: 4 Common mode offset control */ 50 uint32_t MONO:1; /*!< bit: 5 Mono mode */ 51 uint32_t :1; /*!< bit: 6 Reserved */ 52 uint32_t SWRST:1; /*!< bit: 7 Software reset */ 53 uint32_t :8; /*!< bit: 8..15 Reserved */ 54 uint32_t DATAFORMAT:3; /*!< bit: 16..18 Data word format */ 55 uint32_t :5; /*!< bit: 19..23 Reserved */ 56 uint32_t FS:4; /*!< bit: 24..27 Sampling frequency */ 57 uint32_t :4; /*!< bit: 28..31 Reserved */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } ABDACB_CR_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define ABDACB_CR_OFFSET 0x00 /**< \brief (ABDACB_CR offset) Control Register */ 64 #define ABDACB_CR_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_CR reset_value) Control Register */ 65 66 #define ABDACB_CR_EN_Pos 0 /**< \brief (ABDACB_CR) Enable */ 67 #define ABDACB_CR_EN (_U_(0x1) << ABDACB_CR_EN_Pos) 68 #define ABDACB_CR_EN_0_Val _U_(0x0) /**< \brief (ABDACB_CR) Audio DAC is disabled */ 69 #define ABDACB_CR_EN_1_Val _U_(0x1) /**< \brief (ABDACB_CR) Audio DAC is enabled */ 70 #define ABDACB_CR_EN_0 (ABDACB_CR_EN_0_Val << ABDACB_CR_EN_Pos) 71 #define ABDACB_CR_EN_1 (ABDACB_CR_EN_1_Val << ABDACB_CR_EN_Pos) 72 #define ABDACB_CR_SWAP_Pos 1 /**< \brief (ABDACB_CR) Swap Channels */ 73 #define ABDACB_CR_SWAP (_U_(0x1) << ABDACB_CR_SWAP_Pos) 74 #define ABDACB_CR_SWAP_0_Val _U_(0x0) /**< \brief (ABDACB_CR) The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR) */ 75 #define ABDACB_CR_SWAP_1_Val _U_(0x1) /**< \brief (ABDACB_CR) The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR) */ 76 #define ABDACB_CR_SWAP_0 (ABDACB_CR_SWAP_0_Val << ABDACB_CR_SWAP_Pos) 77 #define ABDACB_CR_SWAP_1 (ABDACB_CR_SWAP_1_Val << ABDACB_CR_SWAP_Pos) 78 #define ABDACB_CR_ALTUPR_Pos 3 /**< \brief (ABDACB_CR) Alternative up-sampling ratio */ 79 #define ABDACB_CR_ALTUPR (_U_(0x1) << ABDACB_CR_ALTUPR_Pos) 80 #define ABDACB_CR_CMOC_Pos 4 /**< \brief (ABDACB_CR) Common mode offset control */ 81 #define ABDACB_CR_CMOC (_U_(0x1) << ABDACB_CR_CMOC_Pos) 82 #define ABDACB_CR_MONO_Pos 5 /**< \brief (ABDACB_CR) Mono mode */ 83 #define ABDACB_CR_MONO (_U_(0x1) << ABDACB_CR_MONO_Pos) 84 #define ABDACB_CR_SWRST_Pos 7 /**< \brief (ABDACB_CR) Software reset */ 85 #define ABDACB_CR_SWRST (_U_(0x1) << ABDACB_CR_SWRST_Pos) 86 #define ABDACB_CR_DATAFORMAT_Pos 16 /**< \brief (ABDACB_CR) Data word format */ 87 #define ABDACB_CR_DATAFORMAT_Msk (_U_(0x7) << ABDACB_CR_DATAFORMAT_Pos) 88 #define ABDACB_CR_DATAFORMAT(value) (ABDACB_CR_DATAFORMAT_Msk & ((value) << ABDACB_CR_DATAFORMAT_Pos)) 89 #define ABDACB_CR_FS_Pos 24 /**< \brief (ABDACB_CR) Sampling frequency */ 90 #define ABDACB_CR_FS_Msk (_U_(0xF) << ABDACB_CR_FS_Pos) 91 #define ABDACB_CR_FS(value) (ABDACB_CR_FS_Msk & ((value) << ABDACB_CR_FS_Pos)) 92 #define ABDACB_CR_MASK _U_(0x0F0700BB) /**< \brief (ABDACB_CR) MASK Register */ 93 94 /* -------- ABDACB_SDR0 : (ABDACB Offset: 0x04) (R/W 32) Sample Data Register 0 -------- */ 95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 96 typedef union { 97 struct { 98 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ 99 } bit; /*!< Structure used for bit access */ 100 uint32_t reg; /*!< Type used for register access */ 101 } ABDACB_SDR0_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define ABDACB_SDR0_OFFSET 0x04 /**< \brief (ABDACB_SDR0 offset) Sample Data Register 0 */ 105 #define ABDACB_SDR0_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_SDR0 reset_value) Sample Data Register 0 */ 106 107 #define ABDACB_SDR0_DATA_Pos 0 /**< \brief (ABDACB_SDR0) Sample Data */ 108 #define ABDACB_SDR0_DATA_Msk (_U_(0xFFFFFFFF) << ABDACB_SDR0_DATA_Pos) 109 #define ABDACB_SDR0_DATA(value) (ABDACB_SDR0_DATA_Msk & ((value) << ABDACB_SDR0_DATA_Pos)) 110 #define ABDACB_SDR0_MASK _U_(0xFFFFFFFF) /**< \brief (ABDACB_SDR0) MASK Register */ 111 112 /* -------- ABDACB_SDR1 : (ABDACB Offset: 0x08) (R/W 32) Sample Data Register 1 -------- */ 113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 114 typedef union { 115 struct { 116 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } ABDACB_SDR1_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 #define ABDACB_SDR1_OFFSET 0x08 /**< \brief (ABDACB_SDR1 offset) Sample Data Register 1 */ 123 #define ABDACB_SDR1_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_SDR1 reset_value) Sample Data Register 1 */ 124 125 #define ABDACB_SDR1_DATA_Pos 0 /**< \brief (ABDACB_SDR1) Sample Data */ 126 #define ABDACB_SDR1_DATA_Msk (_U_(0xFFFFFFFF) << ABDACB_SDR1_DATA_Pos) 127 #define ABDACB_SDR1_DATA(value) (ABDACB_SDR1_DATA_Msk & ((value) << ABDACB_SDR1_DATA_Pos)) 128 #define ABDACB_SDR1_MASK _U_(0xFFFFFFFF) /**< \brief (ABDACB_SDR1) MASK Register */ 129 130 /* -------- ABDACB_VCR0 : (ABDACB Offset: 0x0C) (R/W 32) Volume Control Register 0 -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint32_t VOLUME:15; /*!< bit: 0..14 Volume Control */ 135 uint32_t :16; /*!< bit: 15..30 Reserved */ 136 uint32_t MUTE:1; /*!< bit: 31 Mute */ 137 } bit; /*!< Structure used for bit access */ 138 uint32_t reg; /*!< Type used for register access */ 139 } ABDACB_VCR0_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 #define ABDACB_VCR0_OFFSET 0x0C /**< \brief (ABDACB_VCR0 offset) Volume Control Register 0 */ 143 #define ABDACB_VCR0_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_VCR0 reset_value) Volume Control Register 0 */ 144 145 #define ABDACB_VCR0_VOLUME_Pos 0 /**< \brief (ABDACB_VCR0) Volume Control */ 146 #define ABDACB_VCR0_VOLUME_Msk (_U_(0x7FFF) << ABDACB_VCR0_VOLUME_Pos) 147 #define ABDACB_VCR0_VOLUME(value) (ABDACB_VCR0_VOLUME_Msk & ((value) << ABDACB_VCR0_VOLUME_Pos)) 148 #define ABDACB_VCR0_MUTE_Pos 31 /**< \brief (ABDACB_VCR0) Mute */ 149 #define ABDACB_VCR0_MUTE (_U_(0x1) << ABDACB_VCR0_MUTE_Pos) 150 #define ABDACB_VCR0_MASK _U_(0x80007FFF) /**< \brief (ABDACB_VCR0) MASK Register */ 151 152 /* -------- ABDACB_VCR1 : (ABDACB Offset: 0x10) (R/W 32) Volume Control Register 1 -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint32_t VOLUME:15; /*!< bit: 0..14 Volume Control */ 157 uint32_t :16; /*!< bit: 15..30 Reserved */ 158 uint32_t MUTE:1; /*!< bit: 31 Mute */ 159 } bit; /*!< Structure used for bit access */ 160 uint32_t reg; /*!< Type used for register access */ 161 } ABDACB_VCR1_Type; 162 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 163 164 #define ABDACB_VCR1_OFFSET 0x10 /**< \brief (ABDACB_VCR1 offset) Volume Control Register 1 */ 165 #define ABDACB_VCR1_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_VCR1 reset_value) Volume Control Register 1 */ 166 167 #define ABDACB_VCR1_VOLUME_Pos 0 /**< \brief (ABDACB_VCR1) Volume Control */ 168 #define ABDACB_VCR1_VOLUME_Msk (_U_(0x7FFF) << ABDACB_VCR1_VOLUME_Pos) 169 #define ABDACB_VCR1_VOLUME(value) (ABDACB_VCR1_VOLUME_Msk & ((value) << ABDACB_VCR1_VOLUME_Pos)) 170 #define ABDACB_VCR1_MUTE_Pos 31 /**< \brief (ABDACB_VCR1) Mute */ 171 #define ABDACB_VCR1_MUTE (_U_(0x1) << ABDACB_VCR1_MUTE_Pos) 172 #define ABDACB_VCR1_MASK _U_(0x80007FFF) /**< \brief (ABDACB_VCR1) MASK Register */ 173 174 /* -------- ABDACB_IER : (ABDACB Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef union { 177 struct { 178 uint32_t :1; /*!< bit: 0 Reserved */ 179 uint32_t TXRDY:1; /*!< bit: 1 Transmit Ready Interrupt Enable */ 180 uint32_t TXUR:1; /*!< bit: 2 Transmit Underrun Interrupt Enable */ 181 uint32_t :29; /*!< bit: 3..31 Reserved */ 182 } bit; /*!< Structure used for bit access */ 183 uint32_t reg; /*!< Type used for register access */ 184 } ABDACB_IER_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #define ABDACB_IER_OFFSET 0x14 /**< \brief (ABDACB_IER offset) Interrupt Enable Register */ 188 #define ABDACB_IER_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_IER reset_value) Interrupt Enable Register */ 189 190 #define ABDACB_IER_TXRDY_Pos 1 /**< \brief (ABDACB_IER) Transmit Ready Interrupt Enable */ 191 #define ABDACB_IER_TXRDY (_U_(0x1) << ABDACB_IER_TXRDY_Pos) 192 #define ABDACB_IER_TXRDY_0_Val _U_(0x0) /**< \brief (ABDACB_IER) No effect */ 193 #define ABDACB_IER_TXRDY_1_Val _U_(0x1) /**< \brief (ABDACB_IER) Enables the Audio DAC TX Ready interrupt */ 194 #define ABDACB_IER_TXRDY_0 (ABDACB_IER_TXRDY_0_Val << ABDACB_IER_TXRDY_Pos) 195 #define ABDACB_IER_TXRDY_1 (ABDACB_IER_TXRDY_1_Val << ABDACB_IER_TXRDY_Pos) 196 #define ABDACB_IER_TXUR_Pos 2 /**< \brief (ABDACB_IER) Transmit Underrun Interrupt Enable */ 197 #define ABDACB_IER_TXUR (_U_(0x1) << ABDACB_IER_TXUR_Pos) 198 #define ABDACB_IER_TXUR_0_Val _U_(0x0) /**< \brief (ABDACB_IER) No effect */ 199 #define ABDACB_IER_TXUR_1_Val _U_(0x1) /**< \brief (ABDACB_IER) Enables the Audio DAC Underrun interrupt */ 200 #define ABDACB_IER_TXUR_0 (ABDACB_IER_TXUR_0_Val << ABDACB_IER_TXUR_Pos) 201 #define ABDACB_IER_TXUR_1 (ABDACB_IER_TXUR_1_Val << ABDACB_IER_TXUR_Pos) 202 #define ABDACB_IER_MASK _U_(0x00000006) /**< \brief (ABDACB_IER) MASK Register */ 203 204 /* -------- ABDACB_IDR : (ABDACB Offset: 0x18) ( /W 32) Interupt Disable Register -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t :1; /*!< bit: 0 Reserved */ 209 uint32_t TXRDY:1; /*!< bit: 1 Transmit Ready Interrupt Disable */ 210 uint32_t TXUR:1; /*!< bit: 2 Transmit Underrun Interrupt Disable */ 211 uint32_t :29; /*!< bit: 3..31 Reserved */ 212 } bit; /*!< Structure used for bit access */ 213 uint32_t reg; /*!< Type used for register access */ 214 } ABDACB_IDR_Type; 215 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 #define ABDACB_IDR_OFFSET 0x18 /**< \brief (ABDACB_IDR offset) Interupt Disable Register */ 218 #define ABDACB_IDR_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_IDR reset_value) Interupt Disable Register */ 219 220 #define ABDACB_IDR_TXRDY_Pos 1 /**< \brief (ABDACB_IDR) Transmit Ready Interrupt Disable */ 221 #define ABDACB_IDR_TXRDY (_U_(0x1) << ABDACB_IDR_TXRDY_Pos) 222 #define ABDACB_IDR_TXRDY_0_Val _U_(0x0) /**< \brief (ABDACB_IDR) No effect */ 223 #define ABDACB_IDR_TXRDY_1_Val _U_(0x1) /**< \brief (ABDACB_IDR) Disable the Audio DAC TX Ready interrupt */ 224 #define ABDACB_IDR_TXRDY_0 (ABDACB_IDR_TXRDY_0_Val << ABDACB_IDR_TXRDY_Pos) 225 #define ABDACB_IDR_TXRDY_1 (ABDACB_IDR_TXRDY_1_Val << ABDACB_IDR_TXRDY_Pos) 226 #define ABDACB_IDR_TXUR_Pos 2 /**< \brief (ABDACB_IDR) Transmit Underrun Interrupt Disable */ 227 #define ABDACB_IDR_TXUR (_U_(0x1) << ABDACB_IDR_TXUR_Pos) 228 #define ABDACB_IDR_TXUR_0_Val _U_(0x0) /**< \brief (ABDACB_IDR) No effect */ 229 #define ABDACB_IDR_TXUR_1_Val _U_(0x1) /**< \brief (ABDACB_IDR) Disable the Audio DAC Underrun interrupt */ 230 #define ABDACB_IDR_TXUR_0 (ABDACB_IDR_TXUR_0_Val << ABDACB_IDR_TXUR_Pos) 231 #define ABDACB_IDR_TXUR_1 (ABDACB_IDR_TXUR_1_Val << ABDACB_IDR_TXUR_Pos) 232 #define ABDACB_IDR_MASK _U_(0x00000006) /**< \brief (ABDACB_IDR) MASK Register */ 233 234 /* -------- ABDACB_IMR : (ABDACB Offset: 0x1C) (R/ 32) Interrupt Mask Register -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 struct { 238 uint32_t :1; /*!< bit: 0 Reserved */ 239 uint32_t TXRDY:1; /*!< bit: 1 Transmit Ready Interrupt Mask */ 240 uint32_t TXUR:1; /*!< bit: 2 Transmit Underrun Interrupt Mask */ 241 uint32_t :29; /*!< bit: 3..31 Reserved */ 242 } bit; /*!< Structure used for bit access */ 243 uint32_t reg; /*!< Type used for register access */ 244 } ABDACB_IMR_Type; 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 246 247 #define ABDACB_IMR_OFFSET 0x1C /**< \brief (ABDACB_IMR offset) Interrupt Mask Register */ 248 #define ABDACB_IMR_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_IMR reset_value) Interrupt Mask Register */ 249 250 #define ABDACB_IMR_TXRDY_Pos 1 /**< \brief (ABDACB_IMR) Transmit Ready Interrupt Mask */ 251 #define ABDACB_IMR_TXRDY (_U_(0x1) << ABDACB_IMR_TXRDY_Pos) 252 #define ABDACB_IMR_TXRDY_0_Val _U_(0x0) /**< \brief (ABDACB_IMR) The Audio DAC TX Ready interrupt is disabled */ 253 #define ABDACB_IMR_TXRDY_1_Val _U_(0x1) /**< \brief (ABDACB_IMR) The Audio DAC TX Ready interrupt is enabled */ 254 #define ABDACB_IMR_TXRDY_0 (ABDACB_IMR_TXRDY_0_Val << ABDACB_IMR_TXRDY_Pos) 255 #define ABDACB_IMR_TXRDY_1 (ABDACB_IMR_TXRDY_1_Val << ABDACB_IMR_TXRDY_Pos) 256 #define ABDACB_IMR_TXUR_Pos 2 /**< \brief (ABDACB_IMR) Transmit Underrun Interrupt Mask */ 257 #define ABDACB_IMR_TXUR (_U_(0x1) << ABDACB_IMR_TXUR_Pos) 258 #define ABDACB_IMR_TXUR_0_Val _U_(0x0) /**< \brief (ABDACB_IMR) The Audio DAC Underrun interrupt is disabled */ 259 #define ABDACB_IMR_TXUR_1_Val _U_(0x1) /**< \brief (ABDACB_IMR) The Audio DAC Underrun interrupt is enabled */ 260 #define ABDACB_IMR_TXUR_0 (ABDACB_IMR_TXUR_0_Val << ABDACB_IMR_TXUR_Pos) 261 #define ABDACB_IMR_TXUR_1 (ABDACB_IMR_TXUR_1_Val << ABDACB_IMR_TXUR_Pos) 262 #define ABDACB_IMR_MASK _U_(0x00000006) /**< \brief (ABDACB_IMR) MASK Register */ 263 264 /* -------- ABDACB_SR : (ABDACB Offset: 0x20) (R/ 32) Status Register -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 struct { 268 uint32_t BUSY:1; /*!< bit: 0 ABDACB Busy */ 269 uint32_t TXRDY:1; /*!< bit: 1 Transmit Ready */ 270 uint32_t TXUR:1; /*!< bit: 2 Transmit Underrun */ 271 uint32_t :29; /*!< bit: 3..31 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 uint32_t reg; /*!< Type used for register access */ 274 } ABDACB_SR_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define ABDACB_SR_OFFSET 0x20 /**< \brief (ABDACB_SR offset) Status Register */ 278 #define ABDACB_SR_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_SR reset_value) Status Register */ 279 280 #define ABDACB_SR_BUSY_Pos 0 /**< \brief (ABDACB_SR) ABDACB Busy */ 281 #define ABDACB_SR_BUSY (_U_(0x1) << ABDACB_SR_BUSY_Pos) 282 #define ABDACB_SR_TXRDY_Pos 1 /**< \brief (ABDACB_SR) Transmit Ready */ 283 #define ABDACB_SR_TXRDY (_U_(0x1) << ABDACB_SR_TXRDY_Pos) 284 #define ABDACB_SR_TXRDY_0_Val _U_(0x0) /**< \brief (ABDACB_SR) No Audio DAC TX Ready has occured since the last time ISR was read or since reset */ 285 #define ABDACB_SR_TXRDY_1_Val _U_(0x1) /**< \brief (ABDACB_SR) At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset */ 286 #define ABDACB_SR_TXRDY_0 (ABDACB_SR_TXRDY_0_Val << ABDACB_SR_TXRDY_Pos) 287 #define ABDACB_SR_TXRDY_1 (ABDACB_SR_TXRDY_1_Val << ABDACB_SR_TXRDY_Pos) 288 #define ABDACB_SR_TXUR_Pos 2 /**< \brief (ABDACB_SR) Transmit Underrun */ 289 #define ABDACB_SR_TXUR (_U_(0x1) << ABDACB_SR_TXUR_Pos) 290 #define ABDACB_SR_TXUR_0_Val _U_(0x0) /**< \brief (ABDACB_SR) No Audio DAC Underrun has occured since the last time ISR was read or since reset */ 291 #define ABDACB_SR_TXUR_1_Val _U_(0x1) /**< \brief (ABDACB_SR) At least one Audio DAC Underrun has occured since the last time ISR was read or since reset */ 292 #define ABDACB_SR_TXUR_0 (ABDACB_SR_TXUR_0_Val << ABDACB_SR_TXUR_Pos) 293 #define ABDACB_SR_TXUR_1 (ABDACB_SR_TXUR_1_Val << ABDACB_SR_TXUR_Pos) 294 #define ABDACB_SR_MASK _U_(0x00000007) /**< \brief (ABDACB_SR) MASK Register */ 295 296 /* -------- ABDACB_SCR : (ABDACB Offset: 0x24) ( /W 32) Status Clear Register -------- */ 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 298 typedef union { 299 struct { 300 uint32_t :1; /*!< bit: 0 Reserved */ 301 uint32_t TXRDY:1; /*!< bit: 1 Transmit Ready Interrupt Clear */ 302 uint32_t TXUR:1; /*!< bit: 2 Transmit Underrun Interrupt Clear */ 303 uint32_t :29; /*!< bit: 3..31 Reserved */ 304 } bit; /*!< Structure used for bit access */ 305 uint32_t reg; /*!< Type used for register access */ 306 } ABDACB_SCR_Type; 307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 308 309 #define ABDACB_SCR_OFFSET 0x24 /**< \brief (ABDACB_SCR offset) Status Clear Register */ 310 #define ABDACB_SCR_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_SCR reset_value) Status Clear Register */ 311 312 #define ABDACB_SCR_TXRDY_Pos 1 /**< \brief (ABDACB_SCR) Transmit Ready Interrupt Clear */ 313 #define ABDACB_SCR_TXRDY (_U_(0x1) << ABDACB_SCR_TXRDY_Pos) 314 #define ABDACB_SCR_TXRDY_0_Val _U_(0x0) /**< \brief (ABDACB_SCR) No effect */ 315 #define ABDACB_SCR_TXRDY_1_Val _U_(0x1) /**< \brief (ABDACB_SCR) Clear the Audio DAC TX Ready interrupt */ 316 #define ABDACB_SCR_TXRDY_0 (ABDACB_SCR_TXRDY_0_Val << ABDACB_SCR_TXRDY_Pos) 317 #define ABDACB_SCR_TXRDY_1 (ABDACB_SCR_TXRDY_1_Val << ABDACB_SCR_TXRDY_Pos) 318 #define ABDACB_SCR_TXUR_Pos 2 /**< \brief (ABDACB_SCR) Transmit Underrun Interrupt Clear */ 319 #define ABDACB_SCR_TXUR (_U_(0x1) << ABDACB_SCR_TXUR_Pos) 320 #define ABDACB_SCR_TXUR_0_Val _U_(0x0) /**< \brief (ABDACB_SCR) No effect */ 321 #define ABDACB_SCR_TXUR_1_Val _U_(0x1) /**< \brief (ABDACB_SCR) Clear the Audio DAC Underrun interrupt */ 322 #define ABDACB_SCR_TXUR_0 (ABDACB_SCR_TXUR_0_Val << ABDACB_SCR_TXUR_Pos) 323 #define ABDACB_SCR_TXUR_1 (ABDACB_SCR_TXUR_1_Val << ABDACB_SCR_TXUR_Pos) 324 #define ABDACB_SCR_MASK _U_(0x00000006) /**< \brief (ABDACB_SCR) MASK Register */ 325 326 /* -------- ABDACB_PARAMETER : (ABDACB Offset: 0x28) (R/ 32) Parameter Register -------- */ 327 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 328 typedef union { 329 uint32_t reg; /*!< Type used for register access */ 330 } ABDACB_PARAMETER_Type; 331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 332 333 #define ABDACB_PARAMETER_OFFSET 0x28 /**< \brief (ABDACB_PARAMETER offset) Parameter Register */ 334 #define ABDACB_PARAMETER_RESETVALUE _U_(0x00000000); /**< \brief (ABDACB_PARAMETER reset_value) Parameter Register */ 335 #define ABDACB_PARAMETER_MASK _U_(0xFFFFFFFF) /**< \brief (ABDACB_PARAMETER) MASK Register */ 336 337 /* -------- ABDACB_VERSION : (ABDACB Offset: 0x2C) (R/ 32) Version Register -------- */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef union { 340 struct { 341 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 342 uint32_t :4; /*!< bit: 12..15 Reserved */ 343 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 344 uint32_t :12; /*!< bit: 20..31 Reserved */ 345 } bit; /*!< Structure used for bit access */ 346 uint32_t reg; /*!< Type used for register access */ 347 } ABDACB_VERSION_Type; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define ABDACB_VERSION_OFFSET 0x2C /**< \brief (ABDACB_VERSION offset) Version Register */ 351 #define ABDACB_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (ABDACB_VERSION reset_value) Version Register */ 352 353 #define ABDACB_VERSION_VERSION_Pos 0 /**< \brief (ABDACB_VERSION) Version Number */ 354 #define ABDACB_VERSION_VERSION_Msk (_U_(0xFFF) << ABDACB_VERSION_VERSION_Pos) 355 #define ABDACB_VERSION_VERSION(value) (ABDACB_VERSION_VERSION_Msk & ((value) << ABDACB_VERSION_VERSION_Pos)) 356 #define ABDACB_VERSION_VARIANT_Pos 16 /**< \brief (ABDACB_VERSION) Variant Number */ 357 #define ABDACB_VERSION_VARIANT_Msk (_U_(0xF) << ABDACB_VERSION_VARIANT_Pos) 358 #define ABDACB_VERSION_VARIANT(value) (ABDACB_VERSION_VARIANT_Msk & ((value) << ABDACB_VERSION_VARIANT_Pos)) 359 #define ABDACB_VERSION_MASK _U_(0x000F0FFF) /**< \brief (ABDACB_VERSION) MASK Register */ 360 361 /** \brief ABDACB hardware registers */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef struct { 364 __IO uint32_t CR; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 365 __IO uint32_t SDR0; /**< \brief Offset: 0x04 (R/W 32) Sample Data Register 0 */ 366 __IO uint32_t SDR1; /**< \brief Offset: 0x08 (R/W 32) Sample Data Register 1 */ 367 __IO uint32_t VCR0; /**< \brief Offset: 0x0C (R/W 32) Volume Control Register 0 */ 368 __IO uint32_t VCR1; /**< \brief Offset: 0x10 (R/W 32) Volume Control Register 1 */ 369 __O uint32_t IER; /**< \brief Offset: 0x14 ( /W 32) Interrupt Enable Register */ 370 __O uint32_t IDR; /**< \brief Offset: 0x18 ( /W 32) Interupt Disable Register */ 371 __I uint32_t IMR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Mask Register */ 372 __I uint32_t SR; /**< \brief Offset: 0x20 (R/ 32) Status Register */ 373 __O uint32_t SCR; /**< \brief Offset: 0x24 ( /W 32) Status Clear Register */ 374 __I uint32_t PARAMETER; /**< \brief Offset: 0x28 (R/ 32) Parameter Register */ 375 __I uint32_t VERSION; /**< \brief Offset: 0x2C (R/ 32) Version Register */ 376 } Abdacb; 377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 378 379 /*@}*/ 380 381 #endif /* _SAM4L_ABDACB_COMPONENT_ */ 382
