1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E_USART1_INSTANCE_ 31 #define _SAM4E_USART1_INSTANCE_ 32 33 /* ========== Register definition for USART1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_USART1_CR (0x400A4000U) /**< \brief (USART1) Control Register */ 36 #define REG_USART1_MR (0x400A4004U) /**< \brief (USART1) Mode Register */ 37 #define REG_USART1_IER (0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */ 38 #define REG_USART1_IDR (0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */ 39 #define REG_USART1_IMR (0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */ 40 #define REG_USART1_CSR (0x400A4014U) /**< \brief (USART1) Channel Status Register */ 41 #define REG_USART1_RHR (0x400A4018U) /**< \brief (USART1) Receiver Holding Register */ 42 #define REG_USART1_THR (0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */ 43 #define REG_USART1_BRGR (0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */ 44 #define REG_USART1_RTOR (0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */ 45 #define REG_USART1_TTGR (0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */ 46 #define REG_USART1_FIDI (0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */ 47 #define REG_USART1_NER (0x400A4044U) /**< \brief (USART1) Number of Errors Register */ 48 #define REG_USART1_IF (0x400A404CU) /**< \brief (USART1) IrDA Filter Register */ 49 #define REG_USART1_MAN (0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ 50 #define REG_USART1_WPMR (0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */ 51 #define REG_USART1_WPSR (0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */ 52 #define REG_USART1_RPR (0x400A4100U) /**< \brief (USART1) Receive Pointer Register */ 53 #define REG_USART1_RCR (0x400A4104U) /**< \brief (USART1) Receive Counter Register */ 54 #define REG_USART1_TPR (0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */ 55 #define REG_USART1_TCR (0x400A410CU) /**< \brief (USART1) Transmit Counter Register */ 56 #define REG_USART1_RNPR (0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */ 57 #define REG_USART1_RNCR (0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */ 58 #define REG_USART1_TNPR (0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */ 59 #define REG_USART1_TNCR (0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */ 60 #define REG_USART1_PTCR (0x400A4120U) /**< \brief (USART1) Transfer Control Register */ 61 #define REG_USART1_PTSR (0x400A4124U) /**< \brief (USART1) Transfer Status Register */ 62 #else 63 #define REG_USART1_CR (*(WoReg*)0x400A4000U) /**< \brief (USART1) Control Register */ 64 #define REG_USART1_MR (*(RwReg*)0x400A4004U) /**< \brief (USART1) Mode Register */ 65 #define REG_USART1_IER (*(WoReg*)0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */ 66 #define REG_USART1_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */ 67 #define REG_USART1_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */ 68 #define REG_USART1_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART1) Channel Status Register */ 69 #define REG_USART1_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART1) Receiver Holding Register */ 70 #define REG_USART1_THR (*(WoReg*)0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */ 71 #define REG_USART1_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */ 72 #define REG_USART1_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */ 73 #define REG_USART1_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */ 74 #define REG_USART1_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */ 75 #define REG_USART1_NER (*(RoReg*)0x400A4044U) /**< \brief (USART1) Number of Errors Register */ 76 #define REG_USART1_IF (*(RwReg*)0x400A404CU) /**< \brief (USART1) IrDA Filter Register */ 77 #define REG_USART1_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ 78 #define REG_USART1_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */ 79 #define REG_USART1_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */ 80 #define REG_USART1_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART1) Receive Pointer Register */ 81 #define REG_USART1_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART1) Receive Counter Register */ 82 #define REG_USART1_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */ 83 #define REG_USART1_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART1) Transmit Counter Register */ 84 #define REG_USART1_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */ 85 #define REG_USART1_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */ 86 #define REG_USART1_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */ 87 #define REG_USART1_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */ 88 #define REG_USART1_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART1) Transfer Control Register */ 89 #define REG_USART1_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART1) Transfer Status Register */ 90 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 #endif /* _SAM4E_USART1_INSTANCE_ */ 93
