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2 /*                  Atmel Microcontroller Software Support                      */
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29 
30 #ifndef _SAM3X4C_
31 #define _SAM3X4C_
32 
33 /** \addtogroup SAM3X4C_definitions SAM3X4C definitions
34   This file defines all structures and symbols for SAM3X4C:
35     - registers and bitfields
36     - peripheral base address
37     - peripheral ID
38     - PIO definitions
39 */
40 /*@{*/
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47 #include <stdint.h>
48 #endif
49 
50 /* ************************************************************************** */
51 /*   CMSIS DEFINITIONS FOR SAM3X4C */
52 /* ************************************************************************** */
53 /** \addtogroup SAM3X4C_cmsis CMSIS Definitions */
54 /*@{*/
55 
56 /**< Interrupt Number Definition */
57 typedef enum IRQn
58 {
59 /******  Cortex-M3 Processor Exceptions Numbers ******************************/
60   NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61   MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
62   BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
63   UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
64   SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
65   DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
66   PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
67   SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
68 /******  SAM3X4C specific Interrupt Numbers *********************************/
69 
70   SUPC_IRQn            =  0, /**<  0 SAM3X4C Supply Controller (SUPC) */
71   RSTC_IRQn            =  1, /**<  1 SAM3X4C Reset Controller (RSTC) */
72   RTC_IRQn             =  2, /**<  2 SAM3X4C Real Time Clock (RTC) */
73   RTT_IRQn             =  3, /**<  3 SAM3X4C Real Time Timer (RTT) */
74   WDT_IRQn             =  4, /**<  4 SAM3X4C Watchdog Timer (WDT) */
75   PMC_IRQn             =  5, /**<  5 SAM3X4C Power Management Controller (PMC) */
76   EFC0_IRQn            =  6, /**<  6 SAM3X4C Enhanced Flash Controller 0 (EFC0) */
77   EFC1_IRQn            =  7, /**<  7 SAM3X4C Enhanced Flash Controller 1 (EFC1) */
78   UART_IRQn            =  8, /**<  8 SAM3X4C Universal Asynchronous Receiver Transceiver (UART) */
79   PIOA_IRQn            = 11, /**< 11 SAM3X4C Parallel I/O Controller A, (PIOA) */
80   PIOB_IRQn            = 12, /**< 12 SAM3X4C Parallel I/O Controller B (PIOB) */
81   USART0_IRQn          = 17, /**< 17 SAM3X4C USART 0 (USART0) */
82   USART1_IRQn          = 18, /**< 18 SAM3X4C USART 1 (USART1) */
83   USART2_IRQn          = 19, /**< 19 SAM3X4C USART 2 (USART2) */
84   HSMCI_IRQn           = 21, /**< 21 SAM3X4C Multimedia Card Interface (HSMCI) */
85   TWI0_IRQn            = 22, /**< 22 SAM3X4C Two-Wire Interface 0 (TWI0) */
86   TWI1_IRQn            = 23, /**< 23 SAM3X4C Two-Wire Interface 1 (TWI1) */
87   SPI0_IRQn            = 24, /**< 24 SAM3X4C Serial Peripheral Interface (SPI0) */
88   SSC_IRQn             = 26, /**< 26 SAM3X4C Synchronous Serial Controller (SSC) */
89   TC0_IRQn             = 27, /**< 27 SAM3X4C Timer Counter 0 (TC0) */
90   TC1_IRQn             = 28, /**< 28 SAM3X4C Timer Counter 1 (TC1) */
91   TC2_IRQn             = 29, /**< 29 SAM3X4C Timer Counter 2 (TC2) */
92   TC3_IRQn             = 30, /**< 30 SAM3X4C Timer Counter 3 (TC3) */
93   TC4_IRQn             = 31, /**< 31 SAM3X4C Timer Counter 4 (TC4) */
94   TC5_IRQn             = 32, /**< 32 SAM3X4C Timer Counter 5 (TC5) */
95   PWM_IRQn             = 36, /**< 36 SAM3X4C Pulse Width Modulation Controller (PWM) */
96   ADC_IRQn             = 37, /**< 37 SAM3X4C ADC Controller (ADC) */
97   DACC_IRQn            = 38, /**< 38 SAM3X4C DAC Controller (DACC) */
98   DMAC_IRQn            = 39, /**< 39 SAM3X4C DMA Controller (DMAC) */
99   UOTGHS_IRQn          = 40, /**< 40 SAM3X4C USB OTG High Speed (UOTGHS) */
100   TRNG_IRQn            = 41, /**< 41 SAM3X4C True Random Number Generator (TRNG) */
101   EMAC_IRQn            = 42, /**< 42 SAM3X4C Ethernet MAC (EMAC) */
102   CAN0_IRQn            = 43, /**< 43 SAM3X4C CAN Controller 0 (CAN0) */
103   CAN1_IRQn            = 44, /**< 44 SAM3X4C CAN Controller 1 (CAN1) */
104 
105   PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
106 } IRQn_Type;
107 
108 typedef struct _DeviceVectors
109 {
110   /* Stack pointer */
111   void* pvStack;
112 
113   /* Cortex-M handlers */
114   void* pfnReset_Handler;
115   void* pfnNMI_Handler;
116   void* pfnHardFault_Handler;
117   void* pfnMemManage_Handler;
118   void* pfnBusFault_Handler;
119   void* pfnUsageFault_Handler;
120   void* pfnReserved1_Handler;
121   void* pfnReserved2_Handler;
122   void* pfnReserved3_Handler;
123   void* pfnReserved4_Handler;
124   void* pfnSVC_Handler;
125   void* pfnDebugMon_Handler;
126   void* pfnReserved5_Handler;
127   void* pfnPendSV_Handler;
128   void* pfnSysTick_Handler;
129 
130   /* Peripheral handlers */
131   void* pfnSUPC_Handler;   /*  0 Supply Controller */
132   void* pfnRSTC_Handler;   /*  1 Reset Controller */
133   void* pfnRTC_Handler;    /*  2 Real Time Clock */
134   void* pfnRTT_Handler;    /*  3 Real Time Timer */
135   void* pfnWDT_Handler;    /*  4 Watchdog Timer */
136   void* pfnPMC_Handler;    /*  5 Power Management Controller */
137   void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
138   void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
139   void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
140   void* pvReserved9;
141   void* pvReserved10;
142   void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
143   void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
144   void* pvReserved13;
145   void* pvReserved14;
146   void* pvReserved15;
147   void* pvReserved16;
148   void* pfnUSART0_Handler; /* 17 USART 0 */
149   void* pfnUSART1_Handler; /* 18 USART 1 */
150   void* pfnUSART2_Handler; /* 19 USART 2 */
151   void* pvReserved20;
152   void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
153   void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
154   void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
155   void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
156   void* pvReserved25;
157   void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
158   void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
159   void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
160   void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
161   void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
162   void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
163   void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
164   void* pvReserved33;
165   void* pvReserved34;
166   void* pvReserved35;
167   void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
168   void* pfnADC_Handler;    /* 37 ADC Controller */
169   void* pfnDACC_Handler;   /* 38 DAC Controller */
170   void* pfnDMAC_Handler;   /* 39 DMA Controller */
171   void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
172   void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
173   void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
174   void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
175   void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
176 } DeviceVectors;
177 
178 /* Cortex-M3 core handlers */
179 void Reset_Handler      ( void );
180 void NMI_Handler        ( void );
181 void HardFault_Handler  ( void );
182 void MemManage_Handler  ( void );
183 void BusFault_Handler   ( void );
184 void UsageFault_Handler ( void );
185 void SVC_Handler        ( void );
186 void DebugMon_Handler   ( void );
187 void PendSV_Handler     ( void );
188 void SysTick_Handler    ( void );
189 
190 /* Peripherals handlers */
191 void ADC_Handler        ( void );
192 void CAN0_Handler       ( void );
193 void CAN1_Handler       ( void );
194 void DACC_Handler       ( void );
195 void DMAC_Handler       ( void );
196 void EFC0_Handler       ( void );
197 void EFC1_Handler       ( void );
198 void EMAC_Handler       ( void );
199 void HSMCI_Handler      ( void );
200 void PIOA_Handler       ( void );
201 void PIOB_Handler       ( void );
202 void PMC_Handler        ( void );
203 void PWM_Handler        ( void );
204 void RSTC_Handler       ( void );
205 void RTC_Handler        ( void );
206 void RTT_Handler        ( void );
207 void SPI0_Handler       ( void );
208 void SSC_Handler        ( void );
209 void SUPC_Handler       ( void );
210 void TC0_Handler        ( void );
211 void TC1_Handler        ( void );
212 void TC2_Handler        ( void );
213 void TC3_Handler        ( void );
214 void TC4_Handler        ( void );
215 void TC5_Handler        ( void );
216 void TRNG_Handler       ( void );
217 void TWI0_Handler       ( void );
218 void TWI1_Handler       ( void );
219 void UART_Handler       ( void );
220 void UOTGHS_Handler     ( void );
221 void USART0_Handler     ( void );
222 void USART1_Handler     ( void );
223 void USART2_Handler     ( void );
224 void WDT_Handler        ( void );
225 
226 /**
227  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
228  */
229 
230 #define __CM3_REV              0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */
231 #define __MPU_PRESENT          1      /**< SAM3X4C does provide a MPU */
232 #define __NVIC_PRIO_BITS       4      /**< SAM3X4C uses 4 Bits for the Priority Levels */
233 #define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
234 
235 /*
236  * \brief CMSIS includes
237  */
238 
239 #include <core_cm3.h>
240 #if !defined DONT_USE_CMSIS_INIT
241 #include "system_sam3xa.h"
242 #endif /* DONT_USE_CMSIS_INIT */
243 
244 /*@}*/
245 
246 /* ************************************************************************** */
247 /**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4C */
248 /* ************************************************************************** */
249 /** \addtogroup SAM3X4C_api Peripheral Software API */
250 /*@{*/
251 
252 #include "component/adc.h"
253 #include "component/can.h"
254 #include "component/chipid.h"
255 #include "component/dacc.h"
256 #include "component/dmac.h"
257 #include "component/efc.h"
258 #include "component/emac.h"
259 #include "component/gpbr.h"
260 #include "component/hsmci.h"
261 #include "component/matrix.h"
262 #include "component/pdc.h"
263 #include "component/pio.h"
264 #include "component/pmc.h"
265 #include "component/pwm.h"
266 #include "component/rstc.h"
267 #include "component/rtc.h"
268 #include "component/rtt.h"
269 #include "component/spi.h"
270 #include "component/ssc.h"
271 #include "component/supc.h"
272 #include "component/tc.h"
273 #include "component/trng.h"
274 #include "component/twi.h"
275 #include "component/uart.h"
276 #include "component/uotghs.h"
277 #include "component/usart.h"
278 #include "component/wdt.h"
279 /*@}*/
280 
281 /* ************************************************************************** */
282 /*   REGISTER ACCESS DEFINITIONS FOR SAM3X4C */
283 /* ************************************************************************** */
284 /** \addtogroup SAM3X4C_reg Registers Access Definitions */
285 /*@{*/
286 
287 #include "instance/hsmci.h"
288 #include "instance/ssc.h"
289 #include "instance/spi0.h"
290 #include "instance/tc0.h"
291 #include "instance/tc1.h"
292 #include "instance/twi0.h"
293 #include "instance/twi1.h"
294 #include "instance/pwm.h"
295 #include "instance/usart0.h"
296 #include "instance/usart1.h"
297 #include "instance/usart2.h"
298 #include "instance/uotghs.h"
299 #include "instance/emac.h"
300 #include "instance/can0.h"
301 #include "instance/can1.h"
302 #include "instance/trng.h"
303 #include "instance/adc.h"
304 #include "instance/dmac.h"
305 #include "instance/dacc.h"
306 #include "instance/matrix.h"
307 #include "instance/pmc.h"
308 #include "instance/uart.h"
309 #include "instance/chipid.h"
310 #include "instance/efc0.h"
311 #include "instance/efc1.h"
312 #include "instance/pioa.h"
313 #include "instance/piob.h"
314 #include "instance/rstc.h"
315 #include "instance/supc.h"
316 #include "instance/rtt.h"
317 #include "instance/wdt.h"
318 #include "instance/rtc.h"
319 #include "instance/gpbr.h"
320 /*@}*/
321 
322 /* ************************************************************************** */
323 /*   PERIPHERAL ID DEFINITIONS FOR SAM3X4C */
324 /* ************************************************************************** */
325 /** \addtogroup SAM3X4C_id Peripheral Ids Definitions */
326 /*@{*/
327 
328 #define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
329 #define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
330 #define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
331 #define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
332 #define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
333 #define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
334 #define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
335 #define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
336 #define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
337 #define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
338 #define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
339 #define ID_USART0 (17) /**< \brief USART 0 (USART0) */
340 #define ID_USART1 (18) /**< \brief USART 1 (USART1) */
341 #define ID_USART2 (19) /**< \brief USART 2 (USART2) */
342 #define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
343 #define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
344 #define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
345 #define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
346 #define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
347 #define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
348 #define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
349 #define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
350 #define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
351 #define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
352 #define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
353 #define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
354 #define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
355 #define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
356 #define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
357 #define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
358 #define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
359 #define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
360 #define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
361 #define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
362 
363 #define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
364 /*@}*/
365 
366 /* ************************************************************************** */
367 /*   BASE ADDRESS DEFINITIONS FOR SAM3X4C */
368 /* ************************************************************************** */
369 /** \addtogroup SAM3X4C_base Peripheral Base Address Definitions */
370 /*@{*/
371 
372 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
373 #define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
374 #define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
375 #define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
376 #define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
377 #define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
378 #define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
379 #define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
380 #define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
381 #define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
382 #define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
383 #define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
384 #define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
385 #define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
386 #define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
387 #define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
388 #define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
389 #define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
390 #define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
391 #define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
392 #define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
393 #define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
394 #define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
395 #define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
396 #define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
397 #define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
398 #define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
399 #define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
400 #define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
401 #define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
402 #define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
403 #define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
404 #define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
405 #define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
406 #define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
407 #define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
408 #define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
409 #define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
410 #define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
411 #define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
412 #define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
413 #define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
414 #define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
415 #else
416 #define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
417 #define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
418 #define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
419 #define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
420 #define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
421 #define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
422 #define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
423 #define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
424 #define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
425 #define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
426 #define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
427 #define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
428 #define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
429 #define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
430 #define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
431 #define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
432 #define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
433 #define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
434 #define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
435 #define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
436 #define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
437 #define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
438 #define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
439 #define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
440 #define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
441 #define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
442 #define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
443 #define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
444 #define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
445 #define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
446 #define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
447 #define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
448 #define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
449 #define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
450 #define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
451 #define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
452 #define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
453 #define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
454 #define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
455 #define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
456 #define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
457 #define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
458 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
459 /*@}*/
460 
461 /* ************************************************************************** */
462 /*   PIO DEFINITIONS FOR SAM3X4C */
463 /* ************************************************************************** */
464 /** \addtogroup SAM3X4C_pio Peripheral Pio Definitions */
465 /*@{*/
466 
467 #include "pio/sam3x4c.h"
468 /*@}*/
469 
470 /* ************************************************************************** */
471 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X4C */
472 /* ************************************************************************** */
473 
474 #define IFLASH0_SIZE             (0x20000u)
475 #define IFLASH0_PAGE_SIZE        (256u)
476 #define IFLASH0_LOCK_REGION_SIZE (16384u)
477 #define IFLASH0_NB_OF_PAGES      (512u)
478 #define IFLASH0_NB_OF_LOCK_BITS  (16u)
479 #define IFLASH1_SIZE             (0x20000u)
480 #define IFLASH1_PAGE_SIZE        (256u)
481 #define IFLASH1_LOCK_REGION_SIZE (16384u)
482 #define IFLASH1_NB_OF_PAGES      (512u)
483 #define IFLASH1_NB_OF_LOCK_BITS  (16u)
484 #define IRAM0_SIZE               (0x8000u)
485 #define IRAM1_SIZE               (0x8000u)
486 #define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
487 #define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
488 
489 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
490 #if defined IFLASH0_SIZE
491 #define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
492 #endif
493 #define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
494 #define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
495 #define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
496 #define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
497 #define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
498 #define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
499 #define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
500 #define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
501 #define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
502 #define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
503 #define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
504 #define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
505 #define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
506 
507 /* ************************************************************************** */
508 /*   MISCELLANEOUS DEFINITIONS FOR SAM3X4C */
509 /* ************************************************************************** */
510 
511 #define CHIP_JTAGID       (0x05B2B03FUL)
512 #define CHIP_CIDR         (0x284B0930UL)
513 #define CHIP_EXID         (0x0UL)
514 #define NB_CH_ADC         (15UL)
515 #define NB_CH_DAC         (2UL)
516 #define USB_DEVICE_MAX_EP (10UL)
517 #define USB_HOST_MAX_PIPE (10UL)
518 
519 /* ************************************************************************** */
520 /*   ELECTRICAL DEFINITIONS FOR SAM3X4C */
521 /* ************************************************************************** */
522 
523 /* Device characteristics */
524 #define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
525 #define CHIP_FREQ_SLCK_RC               (32000UL)
526 #define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
527 #define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
528 #define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
529 #define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
530 #define CHIP_FREQ_CPU_MAX               (84000000UL)
531 #define CHIP_FREQ_XTAL_32K              (32768UL)
532 #define CHIP_FREQ_XTAL_12M              (12000000UL)
533 #define CHIP_FREQ_UTMIPLL               (480000000UL) /* UTMI PLL frequency */
534 
535 /* Embedded Flash Write Wait State */
536 #define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
537 
538 /* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
539 #define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
540 #define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
541 #define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
542 #define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
543 
544 #ifdef __cplusplus
545 }
546 #endif
547 
548 /*@}*/
549 
550 #endif /* _SAM3X4C_ */
551