1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_USART3_INSTANCE_ 31 #define _SAM3XA_USART3_INSTANCE_ 32 33 /* ========== Register definition for USART3 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_USART3_CR (0x400A4000U) /**< \brief (USART3) Control Register */ 36 #define REG_USART3_MR (0x400A4004U) /**< \brief (USART3) Mode Register */ 37 #define REG_USART3_IER (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ 38 #define REG_USART3_IDR (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ 39 #define REG_USART3_IMR (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ 40 #define REG_USART3_CSR (0x400A4014U) /**< \brief (USART3) Channel Status Register */ 41 #define REG_USART3_RHR (0x400A4018U) /**< \brief (USART3) Receive Holding Register */ 42 #define REG_USART3_THR (0x400A401CU) /**< \brief (USART3) Transmit Holding Register */ 43 #define REG_USART3_BRGR (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ 44 #define REG_USART3_RTOR (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ 45 #define REG_USART3_TTGR (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ 46 #define REG_USART3_FIDI (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ 47 #define REG_USART3_NER (0x400A4044U) /**< \brief (USART3) Number of Errors Register */ 48 #define REG_USART3_IF (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ 49 #define REG_USART3_MAN (0x400A4050U) /**< \brief (USART3) Manchester Configuration Register */ 50 #define REG_USART3_LINMR (0x400A4054U) /**< \brief (USART3) LIN Mode Register */ 51 #define REG_USART3_LINIR (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ 52 #define REG_USART3_LINBRR (0x400A405CU) /**< \brief (USART3) LIN Baud Rate Register */ 53 #define REG_USART3_WPMR (0x400A40E4U) /**< \brief (USART3) Write Protection Mode Register */ 54 #define REG_USART3_WPSR (0x400A40E8U) /**< \brief (USART3) Write Protection Status Register */ 55 #define REG_USART3_RPR (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ 56 #define REG_USART3_RCR (0x400A4104U) /**< \brief (USART3) Receive Counter Register */ 57 #define REG_USART3_TPR (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ 58 #define REG_USART3_TCR (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ 59 #define REG_USART3_RNPR (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ 60 #define REG_USART3_RNCR (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ 61 #define REG_USART3_TNPR (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ 62 #define REG_USART3_TNCR (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ 63 #define REG_USART3_PTCR (0x400A4120U) /**< \brief (USART3) Transfer Control Register */ 64 #define REG_USART3_PTSR (0x400A4124U) /**< \brief (USART3) Transfer Status Register */ 65 #else 66 #define REG_USART3_CR (*(__O uint32_t*)0x400A4000U) /**< \brief (USART3) Control Register */ 67 #define REG_USART3_MR (*(__IO uint32_t*)0x400A4004U) /**< \brief (USART3) Mode Register */ 68 #define REG_USART3_IER (*(__O uint32_t*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ 69 #define REG_USART3_IDR (*(__O uint32_t*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ 70 #define REG_USART3_IMR (*(__I uint32_t*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ 71 #define REG_USART3_CSR (*(__I uint32_t*)0x400A4014U) /**< \brief (USART3) Channel Status Register */ 72 #define REG_USART3_RHR (*(__I uint32_t*)0x400A4018U) /**< \brief (USART3) Receive Holding Register */ 73 #define REG_USART3_THR (*(__O uint32_t*)0x400A401CU) /**< \brief (USART3) Transmit Holding Register */ 74 #define REG_USART3_BRGR (*(__IO uint32_t*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ 75 #define REG_USART3_RTOR (*(__IO uint32_t*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ 76 #define REG_USART3_TTGR (*(__IO uint32_t*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ 77 #define REG_USART3_FIDI (*(__IO uint32_t*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ 78 #define REG_USART3_NER (*(__I uint32_t*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */ 79 #define REG_USART3_IF (*(__IO uint32_t*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ 80 #define REG_USART3_MAN (*(__IO uint32_t*)0x400A4050U) /**< \brief (USART3) Manchester Configuration Register */ 81 #define REG_USART3_LINMR (*(__IO uint32_t*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */ 82 #define REG_USART3_LINIR (*(__IO uint32_t*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ 83 #define REG_USART3_LINBRR (*(__I uint32_t*)0x400A405CU) /**< \brief (USART3) LIN Baud Rate Register */ 84 #define REG_USART3_WPMR (*(__IO uint32_t*)0x400A40E4U) /**< \brief (USART3) Write Protection Mode Register */ 85 #define REG_USART3_WPSR (*(__I uint32_t*)0x400A40E8U) /**< \brief (USART3) Write Protection Status Register */ 86 #define REG_USART3_RPR (*(__IO uint32_t*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ 87 #define REG_USART3_RCR (*(__IO uint32_t*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */ 88 #define REG_USART3_TPR (*(__IO uint32_t*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ 89 #define REG_USART3_TCR (*(__IO uint32_t*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ 90 #define REG_USART3_RNPR (*(__IO uint32_t*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ 91 #define REG_USART3_RNCR (*(__IO uint32_t*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ 92 #define REG_USART3_TNPR (*(__IO uint32_t*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ 93 #define REG_USART3_TNCR (*(__IO uint32_t*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ 94 #define REG_USART3_PTCR (*(__O uint32_t*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */ 95 #define REG_USART3_PTSR (*(__I uint32_t*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */ 96 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 98 #endif /* _SAM3XA_USART3_INSTANCE_ */ 99
