1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_USART2_INSTANCE_ 31 #define _SAM3XA_USART2_INSTANCE_ 32 33 /* ========== Register definition for USART2 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_USART2_CR (0x400A0000U) /**< \brief (USART2) Control Register */ 36 #define REG_USART2_MR (0x400A0004U) /**< \brief (USART2) Mode Register */ 37 #define REG_USART2_IER (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ 38 #define REG_USART2_IDR (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ 39 #define REG_USART2_IMR (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ 40 #define REG_USART2_CSR (0x400A0014U) /**< \brief (USART2) Channel Status Register */ 41 #define REG_USART2_RHR (0x400A0018U) /**< \brief (USART2) Receive Holding Register */ 42 #define REG_USART2_THR (0x400A001CU) /**< \brief (USART2) Transmit Holding Register */ 43 #define REG_USART2_BRGR (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ 44 #define REG_USART2_RTOR (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ 45 #define REG_USART2_TTGR (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ 46 #define REG_USART2_FIDI (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ 47 #define REG_USART2_NER (0x400A0044U) /**< \brief (USART2) Number of Errors Register */ 48 #define REG_USART2_IF (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ 49 #define REG_USART2_MAN (0x400A0050U) /**< \brief (USART2) Manchester Configuration Register */ 50 #define REG_USART2_LINMR (0x400A0054U) /**< \brief (USART2) LIN Mode Register */ 51 #define REG_USART2_LINIR (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ 52 #define REG_USART2_LINBRR (0x400A005CU) /**< \brief (USART2) LIN Baud Rate Register */ 53 #define REG_USART2_WPMR (0x400A00E4U) /**< \brief (USART2) Write Protection Mode Register */ 54 #define REG_USART2_WPSR (0x400A00E8U) /**< \brief (USART2) Write Protection Status Register */ 55 #define REG_USART2_RPR (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ 56 #define REG_USART2_RCR (0x400A0104U) /**< \brief (USART2) Receive Counter Register */ 57 #define REG_USART2_TPR (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ 58 #define REG_USART2_TCR (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ 59 #define REG_USART2_RNPR (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ 60 #define REG_USART2_RNCR (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ 61 #define REG_USART2_TNPR (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ 62 #define REG_USART2_TNCR (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ 63 #define REG_USART2_PTCR (0x400A0120U) /**< \brief (USART2) Transfer Control Register */ 64 #define REG_USART2_PTSR (0x400A0124U) /**< \brief (USART2) Transfer Status Register */ 65 #else 66 #define REG_USART2_CR (*(__O uint32_t*)0x400A0000U) /**< \brief (USART2) Control Register */ 67 #define REG_USART2_MR (*(__IO uint32_t*)0x400A0004U) /**< \brief (USART2) Mode Register */ 68 #define REG_USART2_IER (*(__O uint32_t*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ 69 #define REG_USART2_IDR (*(__O uint32_t*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ 70 #define REG_USART2_IMR (*(__I uint32_t*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ 71 #define REG_USART2_CSR (*(__I uint32_t*)0x400A0014U) /**< \brief (USART2) Channel Status Register */ 72 #define REG_USART2_RHR (*(__I uint32_t*)0x400A0018U) /**< \brief (USART2) Receive Holding Register */ 73 #define REG_USART2_THR (*(__O uint32_t*)0x400A001CU) /**< \brief (USART2) Transmit Holding Register */ 74 #define REG_USART2_BRGR (*(__IO uint32_t*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ 75 #define REG_USART2_RTOR (*(__IO uint32_t*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ 76 #define REG_USART2_TTGR (*(__IO uint32_t*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ 77 #define REG_USART2_FIDI (*(__IO uint32_t*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ 78 #define REG_USART2_NER (*(__I uint32_t*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */ 79 #define REG_USART2_IF (*(__IO uint32_t*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ 80 #define REG_USART2_MAN (*(__IO uint32_t*)0x400A0050U) /**< \brief (USART2) Manchester Configuration Register */ 81 #define REG_USART2_LINMR (*(__IO uint32_t*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */ 82 #define REG_USART2_LINIR (*(__IO uint32_t*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ 83 #define REG_USART2_LINBRR (*(__I uint32_t*)0x400A005CU) /**< \brief (USART2) LIN Baud Rate Register */ 84 #define REG_USART2_WPMR (*(__IO uint32_t*)0x400A00E4U) /**< \brief (USART2) Write Protection Mode Register */ 85 #define REG_USART2_WPSR (*(__I uint32_t*)0x400A00E8U) /**< \brief (USART2) Write Protection Status Register */ 86 #define REG_USART2_RPR (*(__IO uint32_t*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ 87 #define REG_USART2_RCR (*(__IO uint32_t*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */ 88 #define REG_USART2_TPR (*(__IO uint32_t*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ 89 #define REG_USART2_TCR (*(__IO uint32_t*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ 90 #define REG_USART2_RNPR (*(__IO uint32_t*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ 91 #define REG_USART2_RNCR (*(__IO uint32_t*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ 92 #define REG_USART2_TNPR (*(__IO uint32_t*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ 93 #define REG_USART2_TNCR (*(__IO uint32_t*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ 94 #define REG_USART2_PTCR (*(__O uint32_t*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */ 95 #define REG_USART2_PTSR (*(__I uint32_t*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */ 96 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 98 #endif /* _SAM3XA_USART2_INSTANCE_ */ 99
