1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_TWI1_INSTANCE_ 31 #define _SAM3XA_TWI1_INSTANCE_ 32 33 /* ========== Register definition for TWI1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TWI1_CR (0x40090000U) /**< \brief (TWI1) Control Register */ 36 #define REG_TWI1_MMR (0x40090004U) /**< \brief (TWI1) Master Mode Register */ 37 #define REG_TWI1_SMR (0x40090008U) /**< \brief (TWI1) Slave Mode Register */ 38 #define REG_TWI1_IADR (0x4009000CU) /**< \brief (TWI1) Internal Address Register */ 39 #define REG_TWI1_CWGR (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ 40 #define REG_TWI1_SR (0x40090020U) /**< \brief (TWI1) Status Register */ 41 #define REG_TWI1_IER (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ 42 #define REG_TWI1_IDR (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ 43 #define REG_TWI1_IMR (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ 44 #define REG_TWI1_RHR (0x40090030U) /**< \brief (TWI1) Receive Holding Register */ 45 #define REG_TWI1_THR (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ 46 #define REG_TWI1_RPR (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ 47 #define REG_TWI1_RCR (0x40090104U) /**< \brief (TWI1) Receive Counter Register */ 48 #define REG_TWI1_TPR (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ 49 #define REG_TWI1_TCR (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ 50 #define REG_TWI1_RNPR (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ 51 #define REG_TWI1_RNCR (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ 52 #define REG_TWI1_TNPR (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ 53 #define REG_TWI1_TNCR (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ 54 #define REG_TWI1_PTCR (0x40090120U) /**< \brief (TWI1) Transfer Control Register */ 55 #define REG_TWI1_PTSR (0x40090124U) /**< \brief (TWI1) Transfer Status Register */ 56 #else 57 #define REG_TWI1_CR (*(__O uint32_t*)0x40090000U) /**< \brief (TWI1) Control Register */ 58 #define REG_TWI1_MMR (*(__IO uint32_t*)0x40090004U) /**< \brief (TWI1) Master Mode Register */ 59 #define REG_TWI1_SMR (*(__IO uint32_t*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */ 60 #define REG_TWI1_IADR (*(__IO uint32_t*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */ 61 #define REG_TWI1_CWGR (*(__IO uint32_t*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ 62 #define REG_TWI1_SR (*(__I uint32_t*)0x40090020U) /**< \brief (TWI1) Status Register */ 63 #define REG_TWI1_IER (*(__O uint32_t*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ 64 #define REG_TWI1_IDR (*(__O uint32_t*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ 65 #define REG_TWI1_IMR (*(__I uint32_t*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ 66 #define REG_TWI1_RHR (*(__I uint32_t*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */ 67 #define REG_TWI1_THR (*(__O uint32_t*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ 68 #define REG_TWI1_RPR (*(__IO uint32_t*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ 69 #define REG_TWI1_RCR (*(__IO uint32_t*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */ 70 #define REG_TWI1_TPR (*(__IO uint32_t*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ 71 #define REG_TWI1_TCR (*(__IO uint32_t*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ 72 #define REG_TWI1_RNPR (*(__IO uint32_t*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ 73 #define REG_TWI1_RNCR (*(__IO uint32_t*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ 74 #define REG_TWI1_TNPR (*(__IO uint32_t*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ 75 #define REG_TWI1_TNCR (*(__IO uint32_t*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ 76 #define REG_TWI1_PTCR (*(__O uint32_t*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */ 77 #define REG_TWI1_PTSR (*(__I uint32_t*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */ 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 #endif /* _SAM3XA_TWI1_INSTANCE_ */ 81
