1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_SPI1_INSTANCE_ 31 #define _SAM3XA_SPI1_INSTANCE_ 32 33 /* ========== Register definition for SPI1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SPI1_CR (0x4000C000U) /**< \brief (SPI1) Control Register */ 36 #define REG_SPI1_MR (0x4000C004U) /**< \brief (SPI1) Mode Register */ 37 #define REG_SPI1_RDR (0x4000C008U) /**< \brief (SPI1) Receive Data Register */ 38 #define REG_SPI1_TDR (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ 39 #define REG_SPI1_SR (0x4000C010U) /**< \brief (SPI1) Status Register */ 40 #define REG_SPI1_IER (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ 41 #define REG_SPI1_IDR (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ 42 #define REG_SPI1_IMR (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ 43 #define REG_SPI1_CSR (0x4000C030U) /**< \brief (SPI1) Chip Select Register */ 44 #define REG_SPI1_WPMR (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ 45 #define REG_SPI1_WPSR (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ 46 #else 47 #define REG_SPI1_CR (*(__O uint32_t*)0x4000C000U) /**< \brief (SPI1) Control Register */ 48 #define REG_SPI1_MR (*(__IO uint32_t*)0x4000C004U) /**< \brief (SPI1) Mode Register */ 49 #define REG_SPI1_RDR (*(__I uint32_t*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */ 50 #define REG_SPI1_TDR (*(__O uint32_t*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ 51 #define REG_SPI1_SR (*(__I uint32_t*)0x4000C010U) /**< \brief (SPI1) Status Register */ 52 #define REG_SPI1_IER (*(__O uint32_t*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ 53 #define REG_SPI1_IDR (*(__O uint32_t*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ 54 #define REG_SPI1_IMR (*(__I uint32_t*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ 55 #define REG_SPI1_CSR (*(__IO uint32_t*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */ 56 #define REG_SPI1_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ 57 #define REG_SPI1_WPSR (*(__I uint32_t*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ 58 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #endif /* _SAM3XA_SPI1_INSTANCE_ */ 61
