1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_SDRAMC_INSTANCE_ 31 #define _SAM3XA_SDRAMC_INSTANCE_ 32 33 /* ========== Register definition for SDRAMC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ 36 #define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ 37 #define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ 38 #define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ 39 #define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ 40 #define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ 41 #define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ 42 #define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ 43 #define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ 44 #define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ 45 #define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ 46 #else 47 #define REG_SDRAMC_MR (*(__IO uint32_t*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ 48 #define REG_SDRAMC_TR (*(__IO uint32_t*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ 49 #define REG_SDRAMC_CR (*(__IO uint32_t*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ 50 #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ 51 #define REG_SDRAMC_IER (*(__O uint32_t*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ 52 #define REG_SDRAMC_IDR (*(__O uint32_t*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ 53 #define REG_SDRAMC_IMR (*(__I uint32_t*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ 54 #define REG_SDRAMC_ISR (*(__I uint32_t*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ 55 #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ 56 #define REG_SDRAMC_CR1 (*(__IO uint32_t*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ 57 #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ 58 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #endif /* _SAM3XA_SDRAMC_INSTANCE_ */ 61
