1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_HSMCI_INSTANCE_ 31 #define _SAM3XA_HSMCI_INSTANCE_ 32 33 /* ========== Register definition for HSMCI peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ 36 #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ 37 #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ 38 #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ 39 #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ 40 #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ 41 #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ 42 #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ 43 #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ 44 #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ 45 #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ 46 #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ 47 #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ 48 #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ 49 #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ 50 #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ 51 #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ 52 #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ 53 #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ 54 #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ 55 #else 56 #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ 57 #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ 58 #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ 59 #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ 60 #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ 61 #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ 62 #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ 63 #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ 64 #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ 65 #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ 66 #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ 67 #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ 68 #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ 69 #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ 70 #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ 71 #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ 72 #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ 73 #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ 74 #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ 75 #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ 76 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 #endif /* _SAM3XA_HSMCI_INSTANCE_ */ 79
